1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_CORE_SHARED_TYPES_H__ 6 #define __DML2_CORE_SHARED_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 #include "dml_top_display_cfg_types.h" 10 #include "dml_top_types.h" 11 #include "lib_frl_cap_check.h" 12 13 #define __DML_VBA_DEBUG__ 14 #define __DML2_CALCS_MAX_VRATIO_PRE_OTO__ 4.0 //<brief max vratio for one-to-one prefetch bw scheduling 15 #define __DML2_CALCS_MAX_VRATIO_PRE_EQU__ 6.0 //<brief max vratio for equalized prefetch bw scheduling 16 #define __DML2_CALCS_MAX_VRATIO_PRE__ 8.0 //<brief max prefetch vratio register limit 17 #define __DML2_CALCS_MAX_VSTARTUP__ 1023.0 // <brief max vstartup lines supported by hardware 18 19 #define __DML2_CALCS_DPP_INVALID__ 0 20 #define __DML2_CALCS_DCFCLK_FACTOR__ 1.15 //<brief fudge factor for min dcfclk calclation 21 #define __DML2_CALCS_PIPE_NO_PLANE__ 99 22 23 struct dml2_core_ip_params { 24 unsigned int vblank_nom_default_us; 25 unsigned int remote_iommu_outstanding_translations; 26 unsigned int rob_buffer_size_kbytes; 27 unsigned int config_return_buffer_size_in_kbytes; 28 unsigned int config_return_buffer_segment_size_in_kbytes; 29 unsigned int compressed_buffer_segment_size_in_kbytes; 30 unsigned int meta_fifo_size_in_kentries; 31 unsigned int dpte_buffer_size_in_pte_reqs_luma; 32 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 33 unsigned int pixel_chunk_size_kbytes; 34 unsigned int alpha_pixel_chunk_size_kbytes; 35 unsigned int min_pixel_chunk_size_bytes; 36 unsigned int writeback_chunk_size_kbytes; 37 unsigned int line_buffer_size_bits; 38 unsigned int max_line_buffer_lines; 39 unsigned int writeback_interface_buffer_size_kbytes; 40 unsigned int max_num_dpp; 41 unsigned int max_num_opp; 42 unsigned int max_num_otg; 43 unsigned int TDLUT_33cube_count; 44 unsigned int max_num_wb; 45 unsigned int max_dchub_pscl_bw_pix_per_clk; 46 unsigned int max_pscl_lb_bw_pix_per_clk; 47 unsigned int max_lb_vscl_bw_pix_per_clk; 48 unsigned int max_vscl_hscl_bw_pix_per_clk; 49 double max_hscl_ratio; 50 double max_vscl_ratio; 51 unsigned int max_hscl_taps; 52 unsigned int max_vscl_taps; 53 unsigned int odm_combine_support_mask; 54 unsigned int num_dsc; 55 unsigned int maximum_dsc_slices_per_pipe; 56 unsigned int maximum_dsc_bits_per_component; 57 unsigned int maximum_pixels_per_line_per_dsc_unit; 58 bool dsc422_native_support; 59 bool cursor_64bpp_support; 60 double dispclk_ramp_margin_percent; 61 unsigned int dppclk_delay_subtotal; 62 unsigned int dppclk_delay_scl; 63 unsigned int dppclk_delay_scl_lb_only; 64 unsigned int dppclk_delay_cnvc_formatter; 65 unsigned int dppclk_delay_cnvc_cursor; 66 unsigned int cursor_buffer_size; 67 unsigned int cursor_chunk_size; 68 unsigned int dispclk_delay_subtotal; 69 bool dynamic_metadata_vm_enabled; 70 unsigned int max_inter_dcn_tile_repeaters; 71 unsigned int max_num_hdmi_frl_outputs; 72 unsigned int max_num_dp2p0_outputs; 73 unsigned int max_num_dp2p0_streams; 74 bool dcc_supported; 75 bool ptoi_supported; 76 double writeback_max_hscl_ratio; 77 double writeback_max_vscl_ratio; 78 double writeback_min_hscl_ratio; 79 double writeback_min_vscl_ratio; 80 unsigned int writeback_max_hscl_taps; 81 unsigned int writeback_max_vscl_taps; 82 unsigned int writeback_line_buffer_buffer_size; 83 84 unsigned int words_per_channel; 85 bool imall_supported; 86 unsigned int max_flip_time_us; 87 unsigned int max_flip_time_lines; 88 unsigned int subvp_swath_height_margin_lines; 89 unsigned int subvp_fw_processing_delay_us; 90 unsigned int subvp_pstate_allow_width_us; 91 unsigned int alt_chan_fw_delay_us; // FW delay value required in mode support calculation 92 // MRQ 93 bool dcn_mrq_present; 94 unsigned int zero_size_buffer_entries; 95 unsigned int compbuf_reserved_space_zs; 96 unsigned int dcc_meta_buffer_size_bytes; 97 unsigned int meta_chunk_size_kbytes; 98 unsigned int min_meta_chunk_size_bytes; 99 100 unsigned int dchub_arb_to_ret_delay; // num of dcfclk 101 unsigned int hostvm_mode; 102 unsigned int fams2_max_allow_delay_us; 103 unsigned int fams2_min_allow_width_us; 104 unsigned int ppt_max_allow_delay_us; 105 unsigned int temp_read_max_allow_delay_us; 106 bool use_legacy_dsc_delay_formula; 107 }; 108 109 struct dml2_core_internal_DmlPipe { 110 double Dppclk; 111 double Dispclk; 112 double PixelClock; 113 double DCFClkDeepSleep; 114 unsigned int DPPPerSurface; 115 bool ScalerEnabled; 116 bool UPSPEnabled; 117 unsigned int UPSPVTaps; 118 enum dml2_sample_positioning UPSPSamplePositioning; 119 enum dml2_rotation_angle RotationAngle; 120 bool mirrored; 121 unsigned int ViewportHeight; 122 unsigned int ViewportHeightC; 123 unsigned int BlockWidth256BytesY; 124 unsigned int BlockHeight256BytesY; 125 unsigned int BlockWidth256BytesC; 126 unsigned int BlockHeight256BytesC; 127 unsigned int BlockWidthY; 128 unsigned int BlockHeightY; 129 unsigned int BlockWidthC; 130 unsigned int BlockHeightC; 131 unsigned int InterlaceEnable; 132 unsigned int NumberOfCursors; 133 unsigned int VBlank; 134 unsigned int HTotal; 135 unsigned int HActive; 136 bool DCCEnable; 137 enum dml2_odm_mode ODMMode; 138 enum dml2_source_format_class SourcePixelFormat; 139 enum dml2_swizzle_mode SurfaceTiling; 140 unsigned int BytePerPixelY; 141 unsigned int BytePerPixelC; 142 bool ProgressiveToInterlaceUnitInOPP; 143 double VRatio; 144 double VRatioChroma; 145 unsigned int VTaps; 146 unsigned int VTapsChroma; 147 unsigned int PitchY; 148 unsigned int PitchC; 149 bool ViewportStationary; 150 unsigned int ViewportXStart; 151 unsigned int ViewportYStart; 152 unsigned int ViewportXStartC; 153 unsigned int ViewportYStartC; 154 bool FORCE_ONE_ROW_FOR_FRAME; 155 unsigned int SwathHeightY; 156 unsigned int SwathHeightC; 157 158 unsigned int DCCMetaPitchY; 159 unsigned int DCCMetaPitchC; 160 }; 161 162 enum dml2_core_internal_request_type { 163 dml2_core_internal_request_type_256_bytes = 0, 164 dml2_core_internal_request_type_128_bytes_non_contiguous = 1, 165 dml2_core_internal_request_type_128_bytes_contiguous = 2, 166 dml2_core_internal_request_type_na = 3 167 }; 168 enum dml2_core_internal_bw_type { 169 dml2_core_internal_bw_sdp = 0, 170 dml2_core_internal_bw_dram = 1, 171 dml2_core_internal_bw_max 172 }; 173 174 enum dml2_core_internal_soc_state_type { 175 dml2_core_internal_soc_state_sys_active = 0, 176 dml2_core_internal_soc_state_svp_prefetch = 1, 177 dml2_core_internal_soc_state_sys_idle = 2, 178 dml2_core_internal_soc_state_max 179 }; 180 181 enum dml2_core_internal_output_type { 182 dml2_core_internal_output_type_unknown = 0, 183 dml2_core_internal_output_type_dp = 1, 184 dml2_core_internal_output_type_edp = 2, 185 dml2_core_internal_output_type_dp2p0 = 3, 186 dml2_core_internal_output_type_hdmi = 4, 187 dml2_core_internal_output_type_hdmifrl = 5 188 }; 189 190 enum dml2_core_internal_output_type_rate { 191 dml2_core_internal_output_rate_unknown = 0, 192 dml2_core_internal_output_rate_dp_rate_hbr = 1, 193 dml2_core_internal_output_rate_dp_rate_hbr2 = 2, 194 dml2_core_internal_output_rate_dp_rate_hbr3 = 3, 195 dml2_core_internal_output_rate_dp_rate_uhbr10 = 4, 196 dml2_core_internal_output_rate_dp_rate_uhbr13p5 = 5, 197 dml2_core_internal_output_rate_dp_rate_uhbr20 = 6, 198 dml2_core_internal_output_rate_hdmi_rate_3x3 = 7, 199 dml2_core_internal_output_rate_hdmi_rate_6x3 = 8, 200 dml2_core_internal_output_rate_hdmi_rate_6x4 = 9, 201 dml2_core_internal_output_rate_hdmi_rate_8x4 = 10, 202 dml2_core_internal_output_rate_hdmi_rate_10x4 = 11, 203 dml2_core_internal_output_rate_hdmi_rate_12x4 = 12, 204 dml2_core_internal_output_rate_hdmi_rate_16x4 = 13, 205 dml2_core_internal_output_rate_hdmi_rate_20x4 = 14 206 }; 207 208 struct dml2_core_internal_watermarks { 209 double UrgentWatermark; 210 double WritebackUrgentWatermark; 211 double DRAMClockChangeWatermark; 212 double FCLKChangeWatermark; 213 double WritebackDRAMClockChangeWatermark; 214 double WritebackFCLKChangeWatermark; 215 double StutterExitWatermark; 216 double StutterEnterPlusExitWatermark; 217 double LowPowerStutterExitWatermark; 218 double LowPowerStutterEnterPlusExitWatermark; 219 double Z8StutterExitWatermark; 220 double Z8StutterEnterPlusExitWatermark; 221 double USRRetrainingWatermark; 222 double temp_read_or_ppt_watermark_us; 223 double writeback_temp_read_or_ppt_watermark_us; 224 }; 225 226 struct dml2_core_internal_mode_support_info { 227 //----------------- 228 // Mode Support Information 229 //----------------- 230 bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming 231 232 // Mode Support Reason/ 233 bool WritebackLatencySupport; 234 bool ScaleRatioAndTapsSupport; 235 bool SourceFormatPixelAndScanSupport; 236 bool P2IWith420; 237 bool DSCSlicesODMModeSupported; 238 bool DSCOnlyIfNecessaryWithBPP; 239 bool DSC422NativeNotSupported; 240 bool LinkRateDoesNotMatchDPVersion; 241 bool LinkRateForMultistreamNotIndicated; 242 bool BPPForMultistreamNotIndicated; 243 bool MultistreamWithHDMIOreDP; 244 bool MSOOrODMSplitWithNonDPLink; 245 bool NotEnoughLanesForMSO; 246 bool NumberOfOTGSupport; 247 bool NumberOfTDLUT33cubeSupport; 248 bool NumberOfHDMIFRLSupport; 249 bool NumberOfDP2p0Support; 250 bool WritebackScaleRatioAndTapsSupport; 251 bool CursorSupport; 252 bool PitchSupport; 253 bool ViewportExceedsSurface; 254 //bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; 255 bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; 256 bool InvalidCombinationOfMALLUseForPStateAndStaticScreen; 257 bool InvalidCombinationOfMALLUseForPState; 258 bool ExceededMALLSize; 259 bool EnoughWritebackUnits; 260 261 bool ExceededMultistreamSlots; 262 bool NotEnoughDSCUnits; 263 bool NotEnoughDSCSlices; 264 bool PixelsPerLinePerDSCUnitSupport; 265 bool DSCCLKRequiredMoreThanSupported; 266 bool DTBCLKRequiredMoreThanSupported; 267 bool LinkCapacitySupport; 268 269 bool ROBSupport; 270 bool OutstandingRequestsSupport; 271 bool OutstandingRequestsUrgencyAvoidance; 272 273 bool PTEBufferSizeNotExceeded; 274 bool DCCMetaBufferSizeNotExceeded; 275 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 276 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 277 enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES]; 278 bool global_dram_clock_change_support_required; 279 bool global_dram_clock_change_supported; 280 bool global_fclk_change_supported; 281 bool global_temp_read_or_ppt_supported; 282 bool fclk_pstate_schedule_admissible; 283 bool temp_read_pstate_schedule_admissible; 284 bool ppt_pstate_schedule_admissible; 285 bool USRRetrainingSupport; 286 bool AvgBandwidthSupport; 287 bool UrgVactiveBandwidthSupport; 288 bool EnoughUrgentLatencyHidingSupport; 289 bool PrefetchScheduleSupported; 290 bool PrefetchSupported; 291 bool PrefetchBandwidthSupported; 292 bool DynamicMetadataSupported; 293 bool VRatioInPrefetchSupported; 294 bool DISPCLK_DPPCLK_Support; 295 bool TotalAvailablePipesSupport; 296 bool ODMSupport; 297 bool ModeSupport; 298 bool ViewportSizeSupport; 299 300 bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting 301 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 302 unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 303 bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming 304 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required 305 unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode 306 307 double OutputBpp[DML2_MAX_PLANES]; 308 enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES]; 309 enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES]; 310 311 unsigned int AlignedYPitch[DML2_MAX_PLANES]; 312 unsigned int AlignedCPitch[DML2_MAX_PLANES]; 313 314 unsigned int AlignedDCCMetaPitchY[DML2_MAX_PLANES]; 315 unsigned int AlignedDCCMetaPitchC[DML2_MAX_PLANES]; 316 317 unsigned int request_size_bytes_luma[DML2_MAX_PLANES]; 318 unsigned int request_size_bytes_chroma[DML2_MAX_PLANES]; 319 enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES]; 320 enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES]; 321 322 unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES]; 323 unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES]; 324 unsigned int DCCYIndependentBlock[DML2_MAX_PLANES]; 325 unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES]; 326 unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES]; 327 unsigned int DCCCIndependentBlock[DML2_MAX_PLANES]; 328 329 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max]; 330 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 331 double urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_max]; // min between SDP and DRAM, for latency evaluation 332 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM 333 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 334 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm etc. 335 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc. 336 337 double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 338 double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor 339 double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor 340 double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw 341 double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip 342 343 double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor 344 double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 345 bool avg_bandwidth_support_ok[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 346 struct dml2_memory_path_bandwidth bandwidth_upper_bound; 347 double max_urgent_latency_us; 348 double max_non_urgent_latency_us; 349 double avg_non_urgent_latency_us; 350 double avg_urgent_latency_us; 351 double df_response_time_us; 352 353 bool incorrect_imall_usage; 354 355 bool g6_temp_read_support; 356 357 struct dml2_core_internal_watermarks watermarks; 358 bool dcfclk_support; 359 bool qos_bandwidth_support; 360 bool alternate_channel_size_support; 361 }; 362 363 struct dml2_core_internal_mode_support { 364 // Physical info; only using for programming 365 unsigned int state_idx; // <brief min clk state table index for mode support call 366 unsigned int qos_param_index; // to access the uclk dependent qos_parameters table 367 unsigned int active_min_uclk_dpm_index; // to access the min_clk table 368 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 369 370 // Calculated Clocks 371 double RequiredDISPCLK; /// <brief Required DISPCLK; depends on pixel rate; odm mode etc. 372 double RequiredDPPCLK[DML2_MAX_PLANES]; 373 double RequiredDISPCLKPerSurface[DML2_MAX_PLANES]; 374 double RequiredDTBCLK[DML2_MAX_PLANES]; 375 376 double required_dscclk_freq_mhz[DML2_MAX_PLANES]; 377 378 double FabricClock; /// <brief Basically just the clock freq at the min (or given) state 379 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 380 double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 381 double GlobalDPPCLK; /// <brief the Max DPPCLK freq out of all pipes 382 double GlobalDTBCLK; /// <brief the Max DTBCLK freq out of all pipes 383 double uclk_freq_mhz; 384 double dram_bw_mbps; 385 double max_dram_bw_mbps; 386 double min_available_urgent_bandwidth_MBps; /// <brief Minimum guaranteed available urgent return bandwidth in MBps 387 388 double MaxFabricClock; /// <brief Basically just the clock freq at the min (or given) state 389 double MaxDCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 390 double max_dispclk_freq_mhz; 391 double max_dppclk_freq_mhz; 392 double max_dscclk_freq_mhz; 393 394 bool NoTimeForPrefetch[DML2_MAX_PLANES]; 395 bool NoTimeForDynamicMetadata[DML2_MAX_PLANES]; 396 397 // ---------------------------------- 398 // Mode Support Info and fail reason 399 // ---------------------------------- 400 struct dml2_core_internal_mode_support_info support; 401 402 // These are calculated before the ModeSupport and ModeProgram step 403 // They represent the bound for the return buffer sizing 404 unsigned int MaxTotalDETInKByte; 405 unsigned int NomDETInKByte; 406 unsigned int MinCompressedBufferSizeInKByte; 407 408 // Info obtained at the end of mode support calculations 409 // The reported info is at the "optimal" state and combine setting 410 unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 411 unsigned int DETBufferSizeY[DML2_MAX_PLANES]; 412 unsigned int DETBufferSizeC[DML2_MAX_PLANES]; 413 unsigned int SwathHeightY[DML2_MAX_PLANES]; 414 unsigned int SwathHeightC[DML2_MAX_PLANES]; 415 unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe 416 unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe 417 418 // ---------------------------------- 419 // Intermediates/Informational 420 // ---------------------------------- 421 unsigned int TotImmediateFlipBytes; 422 bool DCCEnabledInAnySurface; 423 double WritebackRequiredDISPCLK; 424 double TimeCalc; 425 double TWait[DML2_MAX_PLANES]; 426 427 bool UnboundedRequestEnabled; 428 unsigned int compbuf_reserved_space_64b; 429 bool hw_debug5; 430 unsigned int CompressedBufferSizeInkByte; 431 double VRatioPreY[DML2_MAX_PLANES]; 432 double VRatioPreC[DML2_MAX_PLANES]; 433 unsigned int req_per_swath_ub_l[DML2_MAX_PLANES]; 434 unsigned int req_per_swath_ub_c[DML2_MAX_PLANES]; 435 unsigned int swath_width_luma_ub[DML2_MAX_PLANES]; 436 unsigned int swath_width_chroma_ub[DML2_MAX_PLANES]; 437 unsigned int RequiredSlots[DML2_MAX_PLANES]; 438 unsigned int vm_bytes[DML2_MAX_PLANES]; 439 unsigned int DPTEBytesPerRow[DML2_MAX_PLANES]; 440 unsigned int PrefetchLinesY[DML2_MAX_PLANES]; 441 unsigned int PrefetchLinesC[DML2_MAX_PLANES]; 442 unsigned int MaxNumSwathY[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch 443 unsigned int MaxNumSwathC[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch 444 unsigned int PrefillY[DML2_MAX_PLANES]; 445 unsigned int PrefillC[DML2_MAX_PLANES]; 446 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 447 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 448 449 bool use_one_row_for_frame[DML2_MAX_PLANES]; 450 bool use_one_row_for_frame_flip[DML2_MAX_PLANES]; 451 452 double dst_y_prefetch[DML2_MAX_PLANES]; 453 double LinesForVM[DML2_MAX_PLANES]; 454 double LinesForDPTERow[DML2_MAX_PLANES]; 455 unsigned int SwathWidthYSingleDPP[DML2_MAX_PLANES]; 456 unsigned int SwathWidthCSingleDPP[DML2_MAX_PLANES]; 457 unsigned int BytePerPixelY[DML2_MAX_PLANES]; 458 unsigned int BytePerPixelC[DML2_MAX_PLANES]; 459 double BytePerPixelInDETY[DML2_MAX_PLANES]; 460 double BytePerPixelInDETC[DML2_MAX_PLANES]; 461 462 unsigned int Read256BlockHeightY[DML2_MAX_PLANES]; 463 unsigned int Read256BlockWidthY[DML2_MAX_PLANES]; 464 unsigned int Read256BlockHeightC[DML2_MAX_PLANES]; 465 unsigned int Read256BlockWidthC[DML2_MAX_PLANES]; 466 unsigned int MacroTileHeightY[DML2_MAX_PLANES]; 467 unsigned int MacroTileHeightC[DML2_MAX_PLANES]; 468 unsigned int MacroTileWidthY[DML2_MAX_PLANES]; 469 unsigned int MacroTileWidthC[DML2_MAX_PLANES]; 470 471 bool surf_linear128_l[DML2_MAX_PLANES]; 472 bool surf_linear128_c[DML2_MAX_PLANES]; 473 474 double PSCL_FACTOR[DML2_MAX_PLANES]; 475 double PSCL_FACTOR_CHROMA[DML2_MAX_PLANES]; 476 double MaximumSwathWidthLuma[DML2_MAX_PLANES]; 477 double MaximumSwathWidthChroma[DML2_MAX_PLANES]; 478 double Tno_bw[DML2_MAX_PLANES]; 479 double Tno_bw_flip[DML2_MAX_PLANES]; 480 double dst_y_per_vm_flip[DML2_MAX_PLANES]; 481 double dst_y_per_row_flip[DML2_MAX_PLANES]; 482 double WritebackDelayTime[DML2_MAX_PLANES]; 483 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 484 unsigned int dpte_row_height[DML2_MAX_PLANES]; 485 unsigned int dpte_row_height_chroma[DML2_MAX_PLANES]; 486 double UrgLatency; 487 double TripToMemory; 488 double UrgentBurstFactorCursor[DML2_MAX_PLANES]; 489 double UrgentBurstFactorCursorPre[DML2_MAX_PLANES]; 490 double UrgentBurstFactorLuma[DML2_MAX_PLANES]; 491 double UrgentBurstFactorLumaPre[DML2_MAX_PLANES]; 492 double UrgentBurstFactorChroma[DML2_MAX_PLANES]; 493 double UrgentBurstFactorChromaPre[DML2_MAX_PLANES]; 494 double MaximumSwathWidthInLineBufferLuma; 495 double MaximumSwathWidthInLineBufferChroma; 496 double ExtraLatency; 497 double ExtraLatency_sr; 498 double ExtraLatencyPrefetch; 499 500 double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta 501 double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES]; 502 double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta 503 double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES]; 504 double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; // overhead to the imall or phantom pipe 505 double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES]; 506 507 bool is_using_mall_for_ss[DML2_MAX_PLANES]; 508 unsigned int meta_row_width_chroma[DML2_MAX_PLANES]; 509 unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES]; 510 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 511 unsigned int meta_req_height_chroma[DML2_MAX_PLANES]; 512 unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 513 unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 514 unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES]; 515 unsigned int meta_req_width[DML2_MAX_PLANES]; 516 unsigned int meta_row_width[DML2_MAX_PLANES]; 517 unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES]; 518 unsigned int dpte_row_height_linear[DML2_MAX_PLANES]; 519 unsigned int PTERequestSizeY[DML2_MAX_PLANES]; 520 unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES]; 521 unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES]; 522 unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 523 unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES]; 524 unsigned int PTERequestSizeC[DML2_MAX_PLANES]; 525 unsigned int meta_req_height[DML2_MAX_PLANES]; 526 unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 527 unsigned int meta_req_width_chroma[DML2_MAX_PLANES]; 528 unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES]; 529 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 530 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 531 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 532 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 533 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 534 double TSetup[DML2_MAX_PLANES]; 535 double Tdmdl_vm_raw[DML2_MAX_PLANES]; 536 double Tdmdl_raw[DML2_MAX_PLANES]; 537 unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos. 538 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 539 double MaxActiveFCLKChangeLatencySupported; 540 541 // Backend 542 bool RequiresDSC[DML2_MAX_PLANES]; 543 bool RequiresFEC[DML2_MAX_PLANES]; 544 double OutputBpp[DML2_MAX_PLANES]; 545 double DesiredOutputBpp[DML2_MAX_PLANES]; 546 double PixelClockBackEnd[DML2_MAX_PLANES]; 547 unsigned int DSCDelay[DML2_MAX_PLANES]; 548 bool use_legacy_dsc_delay_formula; 549 enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES]; 550 enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES]; 551 bool TotalAvailablePipesSupportNoDSC; 552 bool TotalAvailablePipesSupportDSC; 553 unsigned int NumberOfDPPNoDSC; 554 unsigned int NumberOfDPPDSC; 555 enum dml2_odm_mode ODMModeNoDSC; 556 enum dml2_odm_mode ODMModeDSC; 557 double RequiredDISPCLKPerSurfaceNoDSC; 558 double RequiredDISPCLKPerSurfaceDSC; 559 unsigned int EstimatedNumberOfDSCSlices[DML2_MAX_PLANES]; 560 561 // Bandwidth Related Info 562 double BandwidthAvailableForImmediateFlip; 563 double vactive_sw_bw_l[DML2_MAX_PLANES]; // no dcc overhead, for the plane 564 double vactive_sw_bw_c[DML2_MAX_PLANES]; 565 double WriteBandwidth[DML2_MAX_PLANES][DML2_MAX_WRITEBACK]; 566 double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES]; 567 double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES]; 568 /* Max bandwidth calculated from prefetch schedule should be considered in addition to the pixel data bw to avoid ms/mp mismatches. 569 * 1. oto bw should also be considered when calculating peak urgent bw to avoid situations oto/equ mismatches between ms and mp 570 * 571 * 2. equ bandwidth needs to be considered for calculating peak urgent bw when equ schedule is used in mode support. 572 * Some slight difference in variables may cause the pixel data bandwidth to be higher 573 * even though overall equ prefetch bandwidths can be lower going from ms to mp 574 */ 575 double RequiredPrefetchBWMax[DML2_MAX_PLANES]; 576 double cursor_bw[DML2_MAX_PLANES]; 577 double prefetch_cursor_bw[DML2_MAX_PLANES]; 578 double prefetch_vmrow_bw[DML2_MAX_PLANES]; 579 double final_flip_bw[DML2_MAX_PLANES]; 580 double meta_row_bw[DML2_MAX_PLANES]; 581 unsigned int meta_row_bytes[DML2_MAX_PLANES]; 582 double dpte_row_bw[DML2_MAX_PLANES]; 583 double excess_vactive_fill_bw_l[DML2_MAX_PLANES]; 584 double excess_vactive_fill_bw_c[DML2_MAX_PLANES]; 585 double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 586 double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 587 588 // Something that should be feedback to caller 589 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; 590 unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES]; 591 unsigned int NoOfDPP[DML2_MAX_PLANES]; 592 unsigned int NoOfOPP[DML2_MAX_PLANES]; 593 bool MPCCombine[DML2_MAX_PLANES]; 594 double dcfclk_deepsleep; 595 double MinDPPCLKUsingSingleDPP[DML2_MAX_PLANES]; 596 bool SingleDPPViewportSizeSupportPerSurface[DML2_MAX_PLANES]; 597 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 598 bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES]; 599 bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES]; 600 bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES]; 601 bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES]; 602 unsigned int TotalNumberOfActiveDPP; 603 unsigned int TotalNumberOfActiveOPP; 604 unsigned int TotalNumberOfSingleDPPSurfaces; 605 unsigned int TotalNumberOfDCCActiveDPP; 606 unsigned int Total3dlutActive; 607 608 unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES]; 609 double VActiveLatencyHidingMargin[DML2_MAX_PLANES]; 610 double VActiveLatencyHidingUs[DML2_MAX_PLANES]; 611 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; 612 double pstate_vactive_det_fill_delay_us[dml2_pstate_type_count][DML2_MAX_PLANES]; 613 614 unsigned int num_mcaches_l[DML2_MAX_PLANES]; 615 unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; 616 unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES]; 617 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 618 unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES]; 619 620 unsigned int num_mcaches_c[DML2_MAX_PLANES]; 621 unsigned int mcache_row_bytes_c[DML2_MAX_PLANES]; 622 unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES]; 623 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 624 unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES]; 625 626 bool mall_comb_mcache_l[DML2_MAX_PLANES]; 627 bool mall_comb_mcache_c[DML2_MAX_PLANES]; 628 bool lc_comb_mcache[DML2_MAX_PLANES]; 629 630 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 631 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 632 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 633 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 634 635 unsigned int meta_row_height_luma[DML2_MAX_PLANES]; 636 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 637 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 638 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 639 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 640 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 641 642 unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 643 unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 644 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 645 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 646 647 unsigned int MaximumVStartup[DML2_MAX_PLANES]; 648 649 double HostVMInefficiencyFactor; 650 double HostVMInefficiencyFactorPrefetch; 651 652 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 653 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 654 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 655 double tdlut_opt_time[DML2_MAX_PLANES]; 656 double tdlut_drain_time[DML2_MAX_PLANES]; 657 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 658 659 double Tvm_trips_flip[DML2_MAX_PLANES]; 660 double Tr0_trips_flip[DML2_MAX_PLANES]; 661 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 662 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 663 664 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 665 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 666 667 enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES]; 668 unsigned int svp0_max_bytes; 669 unsigned int svp1_max_bytes; 670 unsigned int svp0_max_bytes_per_dpp[DML2_MAX_PLANES]; // max bytes for any DPP under a given plane 671 unsigned int svp0_max_bytes_per_dpp_c[DML2_MAX_PLANES]; // max bytes for any DPP under a given plane 672 unsigned int svp1_max_bytes_per_dpp[DML2_MAX_PLANES]; // max bytes for any DPP under a given plane 673 unsigned int svp1_max_bytes_per_dpp_c[DML2_MAX_PLANES]; // max bytes for any DPP under a given plane 674 unsigned int svp0_dst_lines[DML2_MAX_PLANES]; // per stream 675 unsigned int svp1_dst_lines[DML2_MAX_PLANES]; // per stream 676 unsigned int svp_req_limit[DML2_MAX_PLANES]; // per stream, should be the same value in time between all streams max(2 swaths, dst_y_pre) over all planes 677 unsigned int nom_req_limit_alt[DML2_MAX_PLANES]; 678 unsigned int min_lead_dst_lines[DML2_MAX_PLANES]; 679 unsigned int total_swaths[DML2_MAX_PLANES]; 680 unsigned int total_swaths_c[DML2_MAX_PLANES]; 681 unsigned int prefetch_swaths[DML2_MAX_PLANES]; 682 unsigned int prefetch_swaths_c[DML2_MAX_PLANES]; 683 double prefetch_hdl_delta[DML2_MAX_PLANES]; // in dst 684 double recout_hdl_delta[DML2_MAX_PLANES]; // in dst 685 double prefetch_hdl_delta_c[DML2_MAX_PLANES]; // in dst 686 double recout_hdl_delta_c[DML2_MAX_PLANES]; // in dst 687 unsigned int max_prefetch_in_lines[DML2_MAX_PLANES]; // max prefetch time over all planes converted to lines for the given stream 688 double lsdma_bw_req_for_alt_kbps; 689 690 // Synchronized timing group assignement 691 unsigned int timing_group_id[DML2_MAX_PLANES]; // timing group id for the given plane 692 unsigned int timing_group_count; 693 694 bool fclk_pstate_required; 695 bool ppt_pstate_required; 696 bool temp_read_pstate_required; 697 // P-state schedule windows 698 double fclk_pstate_allow_start_us[DML2_MAX_PLANES]; 699 double fclk_pstate_allow_end_us[DML2_MAX_PLANES]; 700 double ppt_pstate_allow_start_us[DML2_MAX_PLANES]; 701 double ppt_pstate_allow_end_us[DML2_MAX_PLANES]; 702 double temp_read_pstate_allow_start_us[DML2_MAX_PLANES]; 703 double temp_read_pstate_allow_end_us[DML2_MAX_PLANES]; 704 }; 705 706 /// @brief A mega structure that houses various info for model programming step. 707 struct dml2_core_internal_mode_program { 708 unsigned int qos_param_index; // to access the uclk dependent dpm table 709 unsigned int active_min_uclk_dpm_index; // to access the min_clk table 710 double FabricClock; /// <brief Basically just the clock freq at the min (or given) state 711 //double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 712 double dram_bw_mbps; 713 double min_available_urgent_bandwidth_MBps; /// <brief Minimum guaranteed available urgent return bandwidth in MBps 714 double uclk_freq_mhz; 715 unsigned int NoOfDPP[DML2_MAX_PLANES]; 716 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; 717 718 //------------- 719 // Intermediate/Informational 720 //------------- 721 double UrgentLatency; 722 double TripToMemory; 723 double MetaTripToMemory; 724 unsigned int VInitPreFillY[DML2_MAX_PLANES]; 725 unsigned int VInitPreFillC[DML2_MAX_PLANES]; 726 unsigned int MaxNumSwathY[DML2_MAX_PLANES]; 727 unsigned int MaxNumSwathC[DML2_MAX_PLANES]; 728 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 729 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 730 731 double BytePerPixelInDETY[DML2_MAX_PLANES]; 732 double BytePerPixelInDETC[DML2_MAX_PLANES]; 733 unsigned int BytePerPixelY[DML2_MAX_PLANES]; 734 unsigned int BytePerPixelC[DML2_MAX_PLANES]; 735 unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe 736 unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe 737 unsigned int req_per_swath_ub_l[DML2_MAX_PLANES]; 738 unsigned int req_per_swath_ub_c[DML2_MAX_PLANES]; 739 unsigned int SwathWidthSingleDPPY[DML2_MAX_PLANES]; 740 unsigned int SwathWidthSingleDPPC[DML2_MAX_PLANES]; 741 double vactive_sw_bw_l[DML2_MAX_PLANES]; 742 double vactive_sw_bw_c[DML2_MAX_PLANES]; 743 double excess_vactive_fill_bw_l[DML2_MAX_PLANES]; 744 double excess_vactive_fill_bw_c[DML2_MAX_PLANES]; 745 746 unsigned int PixelPTEBytesPerRow[DML2_MAX_PLANES]; 747 unsigned int vm_bytes[DML2_MAX_PLANES]; 748 unsigned int PrefetchSourceLinesY[DML2_MAX_PLANES]; 749 double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES]; 750 double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES]; 751 unsigned int PrefetchSourceLinesC[DML2_MAX_PLANES]; 752 double PSCL_THROUGHPUT[DML2_MAX_PLANES]; 753 double PSCL_THROUGHPUT_CHROMA[DML2_MAX_PLANES]; 754 unsigned int DSCDelay[DML2_MAX_PLANES]; 755 bool use_legacy_dsc_delay_formula; 756 double DPPCLKUsingSingleDPP[DML2_MAX_PLANES]; 757 758 unsigned int Read256BlockHeightY[DML2_MAX_PLANES]; 759 unsigned int Read256BlockWidthY[DML2_MAX_PLANES]; 760 unsigned int Read256BlockHeightC[DML2_MAX_PLANES]; 761 unsigned int Read256BlockWidthC[DML2_MAX_PLANES]; 762 unsigned int MacroTileHeightY[DML2_MAX_PLANES]; 763 unsigned int MacroTileHeightC[DML2_MAX_PLANES]; 764 unsigned int MacroTileWidthY[DML2_MAX_PLANES]; 765 unsigned int MacroTileWidthC[DML2_MAX_PLANES]; 766 double MaximumSwathWidthLuma[DML2_MAX_PLANES]; 767 double MaximumSwathWidthChroma[DML2_MAX_PLANES]; 768 769 bool surf_linear128_l[DML2_MAX_PLANES]; 770 bool surf_linear128_c[DML2_MAX_PLANES]; 771 772 unsigned int SurfaceSizeInTheMALL[DML2_MAX_PLANES]; 773 double VRatioPrefetchY[DML2_MAX_PLANES]; 774 double VRatioPrefetchC[DML2_MAX_PLANES]; 775 double Tno_bw[DML2_MAX_PLANES]; 776 double Tno_bw_flip[DML2_MAX_PLANES]; 777 double final_flip_bw[DML2_MAX_PLANES]; 778 double prefetch_vmrow_bw[DML2_MAX_PLANES]; 779 double cursor_bw[DML2_MAX_PLANES]; 780 double prefetch_cursor_bw[DML2_MAX_PLANES]; 781 double WritebackDelay[DML2_MAX_PLANES]; 782 unsigned int dpte_row_height[DML2_MAX_PLANES]; 783 unsigned int dpte_row_height_linear[DML2_MAX_PLANES]; 784 unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES]; 785 unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES]; 786 unsigned int dpte_row_height_chroma[DML2_MAX_PLANES]; 787 unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES]; 788 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 789 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 790 791 double dpte_row_bw[DML2_MAX_PLANES]; 792 double time_per_tdlut_group[DML2_MAX_PLANES]; 793 double UrgentBurstFactorCursor[DML2_MAX_PLANES]; 794 double UrgentBurstFactorCursorPre[DML2_MAX_PLANES]; 795 double UrgentBurstFactorLuma[DML2_MAX_PLANES]; 796 double UrgentBurstFactorLumaPre[DML2_MAX_PLANES]; 797 double UrgentBurstFactorChroma[DML2_MAX_PLANES]; 798 double UrgentBurstFactorChromaPre[DML2_MAX_PLANES]; 799 800 double MaximumSwathWidthInLineBufferLuma; 801 double MaximumSwathWidthInLineBufferChroma; 802 803 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 804 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 805 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 806 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 807 808 double meta_row_bw[DML2_MAX_PLANES]; 809 unsigned int meta_row_bytes[DML2_MAX_PLANES]; 810 unsigned int meta_req_width[DML2_MAX_PLANES]; 811 unsigned int meta_req_height[DML2_MAX_PLANES]; 812 unsigned int meta_row_width[DML2_MAX_PLANES]; 813 unsigned int meta_row_height[DML2_MAX_PLANES]; 814 unsigned int meta_req_width_chroma[DML2_MAX_PLANES]; 815 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 816 unsigned int meta_row_width_chroma[DML2_MAX_PLANES]; 817 unsigned int meta_req_height_chroma[DML2_MAX_PLANES]; 818 819 unsigned int swath_width_luma_ub[DML2_MAX_PLANES]; 820 unsigned int swath_width_chroma_ub[DML2_MAX_PLANES]; 821 unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES]; 822 unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES]; 823 unsigned int PTERequestSizeY[DML2_MAX_PLANES]; 824 unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES]; 825 unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES]; 826 unsigned int PTERequestSizeC[DML2_MAX_PLANES]; 827 828 double TWait[DML2_MAX_PLANES]; 829 double Tdmdl_vm_raw[DML2_MAX_PLANES]; 830 double Tdmdl_vm[DML2_MAX_PLANES]; 831 double Tdmdl_raw[DML2_MAX_PLANES]; 832 double Tdmdl[DML2_MAX_PLANES]; 833 double TSetup[DML2_MAX_PLANES]; 834 unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 835 unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 836 837 unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 838 unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 839 840 bool UnboundedRequestEnabled; 841 unsigned int CompressedBufferSizeInkByte; 842 unsigned int compbuf_reserved_space_64b; 843 bool hw_debug5; 844 unsigned int dcfclk_deep_sleep_hysteresis; 845 unsigned int min_return_latency_in_dcfclk; 846 847 bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES]; 848 bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES]; 849 double ExtraLatency; 850 double ExtraLatency_sr; 851 double ExtraLatencyPrefetch; 852 bool PrefetchAndImmediateFlipSupported; 853 double TotalDataReadBandwidth; 854 double BandwidthAvailableForImmediateFlip; 855 bool NotEnoughTimeForDynamicMetadata[DML2_MAX_PLANES]; 856 857 bool use_one_row_for_frame[DML2_MAX_PLANES]; 858 bool use_one_row_for_frame_flip[DML2_MAX_PLANES]; 859 860 double TCalc; 861 unsigned int TotImmediateFlipBytes; 862 863 unsigned int MaxTotalDETInKByte; 864 unsigned int NomDETInKByte; 865 unsigned int MinCompressedBufferSizeInKByte; 866 double PixelClockBackEnd[DML2_MAX_PLANES]; 867 double OutputBpp[DML2_MAX_PLANES]; 868 bool dsc_enable[DML2_MAX_PLANES]; 869 unsigned int num_dsc_slices[DML2_MAX_PLANES]; 870 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 871 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 872 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 873 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 874 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 875 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 876 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG 877 double HostVMInefficiencyFactor; 878 double HostVMInefficiencyFactorPrefetch; 879 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 880 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 881 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 882 double tdlut_opt_time[DML2_MAX_PLANES]; 883 double tdlut_drain_time[DML2_MAX_PLANES]; 884 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 885 double Tvm_trips_flip[DML2_MAX_PLANES]; 886 double Tr0_trips_flip[DML2_MAX_PLANES]; 887 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 888 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 889 bool immediate_flip_required; // any pipes need immediate flip 890 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 891 double TotalWRBandwidth; 892 double max_urgent_latency_us; 893 double df_response_time_us; 894 895 enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES]; 896 unsigned int svp0_max_bytes; 897 unsigned int svp1_max_bytes; 898 unsigned int svp0_max_bytes_per_dpp[DML2_MAX_PLANES]; // max bytes for any DPP under a given plane 899 unsigned int svp0_max_bytes_per_dpp_c[DML2_MAX_PLANES]; // max bytes for any DPP under a given plane 900 unsigned int svp1_max_bytes_per_dpp[DML2_MAX_PLANES]; // max bytes for any DPP under a given plane 901 unsigned int svp1_max_bytes_per_dpp_c[DML2_MAX_PLANES]; // max bytes for any DPP under a given plane 902 unsigned int svp0_dst_lines[DML2_MAX_PLANES]; // per stream 903 unsigned int svp1_dst_lines[DML2_MAX_PLANES]; // per stream 904 unsigned int min_lead_dst_lines[DML2_MAX_PLANES]; // per stream, should be max(nominal_req_limit, vstartup_to_vactive). Does not have to be maxed over all planes 905 unsigned int svp_req_limit[DML2_MAX_PLANES]; // per stream, should be the same value in time between all streams max(2 swaths, dst_y_pre) over all planes 906 unsigned int nom_req_limit_alt[DML2_MAX_PLANES]; // per stream 907 unsigned int total_swaths[DML2_MAX_PLANES]; 908 unsigned int total_swaths_c[DML2_MAX_PLANES]; 909 unsigned int prefetch_swaths[DML2_MAX_PLANES]; 910 unsigned int prefetch_swaths_c[DML2_MAX_PLANES]; 911 double prefetch_hdl_delta[DML2_MAX_PLANES]; // in dst 912 double recout_hdl_delta[DML2_MAX_PLANES]; // in dst 913 double prefetch_hdl_delta_c[DML2_MAX_PLANES]; // in dst 914 double recout_hdl_delta_c[DML2_MAX_PLANES]; // in dst 915 unsigned int max_prefetch_in_lines[DML2_MAX_PLANES]; // max prefetch time over all planes converted to lines for the given stream 916 // ------------------- 917 // Output 918 // ------------------- 919 unsigned int pipe_plane[DML2_MAX_PLANES]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe 920 unsigned int num_active_pipes; 921 922 bool NoTimeToPrefetch[DML2_MAX_PLANES]; // <brief Prefetch schedule calculation result 923 924 // Support 925 bool UrgVactiveBandwidthSupport; 926 bool PrefetchScheduleSupported; 927 bool UrgentBandwidthSupport; 928 bool PrefetchModeSupported; // <brief Is the prefetch mode (bandwidth and latency) supported 929 bool ImmediateFlipSupported; 930 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 931 bool dcfclk_support; 932 933 // Clock 934 double Dcfclk; 935 double Dispclk; // <brief dispclk being used in mode programming 936 double Dppclk[DML2_MAX_PLANES]; // <brief dppclk being used in mode programming 937 double GlobalDPPCLK; 938 939 double DSCCLK[DML2_MAX_PLANES]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now 940 double DCFCLKDeepSleep; 941 942 // ARB reg 943 bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 944 struct dml2_core_internal_watermarks Watermark; 945 946 // DCC compression control 947 unsigned int request_size_bytes_luma[DML2_MAX_PLANES]; 948 unsigned int request_size_bytes_chroma[DML2_MAX_PLANES]; 949 enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES]; 950 enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES]; 951 unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES]; 952 unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES]; 953 unsigned int DCCYIndependentBlock[DML2_MAX_PLANES]; 954 unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES]; 955 unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES]; 956 unsigned int DCCCIndependentBlock[DML2_MAX_PLANES]; 957 958 // Stutter Efficiency 959 double StutterEfficiency; 960 double StutterEfficiencyNotIncludingVBlank; 961 unsigned int NumberOfStutterBurstsPerFrame; 962 double Z8StutterEfficiency; 963 unsigned int Z8NumberOfStutterBurstsPerFrame; 964 double Z8StutterEfficiencyNotIncludingVBlank; 965 double LowPowerStutterEfficiency; 966 double LowPowerStutterEfficiencyNotIncludingVBlank; 967 unsigned int LowPowerNumberOfStutterBurstsPerFrame; 968 double StutterPeriod; 969 double Z8StutterEfficiencyBestCase; 970 unsigned int Z8NumberOfStutterBurstsPerFrameBestCase; 971 double Z8StutterEfficiencyNotIncludingVBlankBestCase; 972 double StutterPeriodBestCase; 973 974 // DLG TTU reg 975 double MIN_DST_Y_NEXT_START[DML2_MAX_PLANES]; 976 bool VREADY_AT_OR_AFTER_VSYNC[DML2_MAX_PLANES]; 977 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 978 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 979 double dst_y_prefetch[DML2_MAX_PLANES]; 980 double dst_y_per_vm_vblank[DML2_MAX_PLANES]; 981 double dst_y_per_row_vblank[DML2_MAX_PLANES]; 982 double dst_y_per_vm_flip[DML2_MAX_PLANES]; 983 double dst_y_per_row_flip[DML2_MAX_PLANES]; 984 double MinTTUVBlank[DML2_MAX_PLANES]; 985 double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES]; 986 double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES]; 987 double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 988 double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 989 double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES]; 990 double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES]; 991 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 992 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 993 unsigned int CursorDstXOffset[DML2_MAX_PLANES]; 994 unsigned int CursorDstYOffset[DML2_MAX_PLANES]; 995 unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES]; 996 997 double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES]; 998 double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES]; 999 double time_per_pte_group_nom_luma[DML2_MAX_PLANES]; 1000 double time_per_pte_group_nom_chroma[DML2_MAX_PLANES]; 1001 double time_per_pte_group_vblank_luma[DML2_MAX_PLANES]; 1002 double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES]; 1003 double time_per_pte_group_flip_luma[DML2_MAX_PLANES]; 1004 double time_per_pte_group_flip_chroma[DML2_MAX_PLANES]; 1005 double TimePerVMGroupVBlank[DML2_MAX_PLANES]; 1006 double TimePerVMGroupFlip[DML2_MAX_PLANES]; 1007 double TimePerVMRequestVBlank[DML2_MAX_PLANES]; 1008 double TimePerVMRequestFlip[DML2_MAX_PLANES]; 1009 1010 double DST_Y_PER_META_ROW_NOM_L[DML2_MAX_PLANES]; 1011 double DST_Y_PER_META_ROW_NOM_C[DML2_MAX_PLANES]; 1012 double TimePerMetaChunkNominal[DML2_MAX_PLANES]; 1013 double TimePerChromaMetaChunkNominal[DML2_MAX_PLANES]; 1014 double TimePerMetaChunkVBlank[DML2_MAX_PLANES]; 1015 double TimePerChromaMetaChunkVBlank[DML2_MAX_PLANES]; 1016 double TimePerMetaChunkFlip[DML2_MAX_PLANES]; 1017 double TimePerChromaMetaChunkFlip[DML2_MAX_PLANES]; 1018 1019 double FractionOfUrgentBandwidth; 1020 double FractionOfUrgentBandwidthImmediateFlip; 1021 double FractionOfUrgentBandwidthMALL; 1022 1023 // RQ registers 1024 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 1025 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 1026 double VActiveLatencyHidingUs[DML2_MAX_PLANES]; 1027 unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES]; 1028 bool is_using_mall_for_ss[DML2_MAX_PLANES]; 1029 1030 // OTG 1031 unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos. 1032 unsigned int VStartup[DML2_MAX_PLANES]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank)) 1033 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 1034 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 1035 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 1036 unsigned int pstate_keepout_dst_lines[DML2_MAX_PLANES]; 1037 1038 // Latency and Support 1039 double MaxActiveFCLKChangeLatencySupported; 1040 bool USRRetrainingSupport; 1041 bool g6_temp_read_support; 1042 bool global_z8_stutter_supported; 1043 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 1044 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 1045 enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES]; 1046 bool global_dram_clock_change_supported; 1047 bool global_fclk_change_supported; 1048 bool global_temp_read_or_ppt_supported; 1049 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 1050 double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES]; 1051 double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES]; 1052 1053 // buffer sizing 1054 unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 1055 unsigned int DETBufferSizeY[DML2_MAX_PLANES]; 1056 unsigned int DETBufferSizeC[DML2_MAX_PLANES]; 1057 unsigned int SwathHeightY[DML2_MAX_PLANES]; 1058 unsigned int SwathHeightC[DML2_MAX_PLANES]; 1059 1060 double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor 1061 double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor 1062 double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw 1063 double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip 1064 double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor 1065 double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1066 1067 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max]; 1068 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1069 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM 1070 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1071 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm traffic etc. 1072 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc. 1073 double non_urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1074 1075 double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; 1076 double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES]; 1077 double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; 1078 double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES]; 1079 double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; 1080 double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES]; 1081 1082 unsigned int num_mcaches_l[DML2_MAX_PLANES]; 1083 unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; 1084 unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES]; 1085 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 1086 unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES]; 1087 1088 unsigned int num_mcaches_c[DML2_MAX_PLANES]; 1089 unsigned int mcache_row_bytes_c[DML2_MAX_PLANES]; 1090 unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES]; 1091 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 1092 unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES]; 1093 1094 bool mall_comb_mcache_l[DML2_MAX_PLANES]; 1095 bool mall_comb_mcache_c[DML2_MAX_PLANES]; 1096 bool lc_comb_mcache[DML2_MAX_PLANES]; 1097 1098 double impacted_prefetch_margin_us[DML2_MAX_PLANES]; 1099 }; 1100 1101 struct dml2_core_internal_SOCParametersList { 1102 double UrgentLatency; 1103 double ExtraLatency_sr; 1104 double ExtraLatency; 1105 double WritebackLatency; 1106 double DRAMClockChangeLatency; 1107 double FCLKChangeLatency; 1108 double SRExitTime; 1109 double SREnterPlusExitTime; 1110 double SRExitTimeLowPower; 1111 double SREnterPlusExitTimeLowPower; 1112 double SRExitZ8Time; 1113 double SREnterPlusExitZ8Time; 1114 double USRRetrainingLatency; 1115 double SMNLatency; 1116 double g6_temp_read_blackout_us; 1117 double temp_read_or_ppt_blackout_us; 1118 double max_urgent_latency_us; 1119 double df_response_time_us; 1120 enum dml2_qos_param_type qos_type; 1121 }; 1122 1123 struct dml2_core_calcs_mode_support_locals { 1124 double PixelClockBackEnd[DML2_MAX_PLANES]; 1125 double OutputBpp[DML2_MAX_PLANES]; 1126 1127 unsigned int meta_row_height_luma[DML2_MAX_PLANES]; 1128 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 1129 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1130 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1131 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 1132 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 1133 1134 bool dummy_boolean[3]; 1135 unsigned int dummy_integer[3]; 1136 unsigned int dummy_integer_array[36][DML2_MAX_PLANES]; 1137 enum dml2_odm_mode dummy_odm_mode[DML2_MAX_PLANES]; 1138 bool dummy_boolean_array[2][DML2_MAX_PLANES]; 1139 double dummy_single[3]; 1140 double dummy_single_array[DML2_MAX_PLANES]; 1141 double dummy_double_array[3][DML2_MAX_PLANES]; 1142 enum dml2_pstate_method dummy_pstate_method_array[DML2_MAX_PLANES]; 1143 struct dml2_core_internal_watermarks dummy_watermark; 1144 double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1145 double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1146 1147 unsigned int MaximumVStartup[DML2_MAX_PLANES]; 1148 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 1149 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 1150 struct dml2_core_internal_SOCParametersList mSOCParameters; 1151 struct dml2_core_internal_DmlPipe myPipe; 1152 struct dml2_core_internal_DmlPipe SurfParameters[DML2_MAX_PLANES]; 1153 unsigned int TotalNumberOfActiveWriteback; 1154 unsigned int MaximumSwathWidthSupportLuma; 1155 unsigned int MaximumSwathWidthSupportChroma; 1156 bool MPCCombineMethodAsNeededForPStateChangeAndVoltage; 1157 bool MPCCombineMethodAsPossible; 1158 bool TotalAvailablePipesSupportNoDSC; 1159 unsigned int NumberOfDPPNoDSC; 1160 enum dml2_odm_mode ODMModeNoDSC; 1161 double RequiredDISPCLKPerSurfaceNoDSC; 1162 bool TotalAvailablePipesSupportDSC; 1163 unsigned int NumberOfDPPDSC; 1164 enum dml2_odm_mode ODMModeDSC; 1165 double RequiredDISPCLKPerSurfaceDSC; 1166 double BWOfNonCombinedSurfaceOfMaximumBandwidth; 1167 unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth; 1168 unsigned int TotalNumberOfActiveOTG; 1169 unsigned int TotalNumberOfActiveHDMIFRL; 1170 unsigned int TotalNumberOfActiveDP2p0; 1171 unsigned int TotalNumberOfActiveDP2p0Outputs; 1172 unsigned int TotalSlots; 1173 unsigned int DSCFormatFactor; 1174 unsigned int TotalDSCUnitsRequired; 1175 unsigned int ReorderingBytes; 1176 bool ImmediateFlipRequired; 1177 bool FullFrameMALLPStateMethod; 1178 bool SubViewportMALLPStateMethod; 1179 bool PhantomPipeMALLPStateMethod; 1180 bool SubViewportMALLRefreshGreaterThan120Hz; 1181 1182 double HostVMInefficiencyFactor; 1183 double HostVMInefficiencyFactorPrefetch; 1184 unsigned int MaxVStartup; 1185 double PixelClockBackEndFactor; 1186 unsigned int NumDSCUnitRequired; 1187 1188 double Tvm_trips[DML2_MAX_PLANES]; 1189 double Tr0_trips[DML2_MAX_PLANES]; 1190 double Tvm_trips_flip[DML2_MAX_PLANES]; 1191 double Tr0_trips_flip[DML2_MAX_PLANES]; 1192 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 1193 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 1194 unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; 1195 1196 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 1197 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 1198 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 1199 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 1200 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 1201 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 1202 1203 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 1204 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 1205 unsigned int tdlut_row_bytes[DML2_MAX_PLANES]; 1206 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 1207 double tdlut_opt_time[DML2_MAX_PLANES]; 1208 double tdlut_drain_time[DML2_MAX_PLANES]; 1209 unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES]; 1210 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 1211 1212 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 1213 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 1214 unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES]; 1215 unsigned int cursor_bytes[DML2_MAX_PLANES]; 1216 bool stream_visited[DML2_MAX_PLANES]; 1217 1218 unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 1219 unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 1220 1221 double prefetch_sw_bytes[DML2_MAX_PLANES]; 1222 double Tpre_rounded[DML2_MAX_PLANES]; 1223 double Tpre_oto[DML2_MAX_PLANES]; 1224 bool recalc_prefetch_schedule; 1225 bool recalc_prefetch_done; 1226 double impacted_dst_y_pre[DML2_MAX_PLANES]; 1227 double line_times[DML2_MAX_PLANES]; 1228 enum dml2_source_format_class pixel_format[DML2_MAX_PLANES]; 1229 unsigned int lb_source_lines_l[DML2_MAX_PLANES]; 1230 unsigned int lb_source_lines_c[DML2_MAX_PLANES]; 1231 double prefetch_swath_time_us[DML2_MAX_PLANES]; 1232 }; 1233 1234 struct dml2_core_calcs_mode_programming_locals { 1235 double PixelClockBackEnd[DML2_MAX_PLANES]; 1236 double OutputBpp[DML2_MAX_PLANES]; 1237 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 1238 unsigned int MaxTotalDETInKByte; 1239 unsigned int NomDETInKByte; 1240 unsigned int MinCompressedBufferSizeInKByte; 1241 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 1242 1243 double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1244 double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1245 double surface_dummy_bw0[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1246 unsigned int dummy_integer_array[4][DML2_MAX_PLANES]; 1247 enum dml2_output_encoder_class dummy_output_encoder_array[DML2_MAX_PLANES]; 1248 double dummy_single_array[2][DML2_MAX_PLANES]; 1249 unsigned int dummy_long_array[8][DML2_MAX_PLANES]; 1250 bool dummy_boolean_array[2][DML2_MAX_PLANES]; 1251 bool dummy_boolean[2]; 1252 double dummy_single[2]; 1253 struct dml2_core_internal_watermarks dummy_watermark; 1254 1255 unsigned int DSCFormatFactor; 1256 struct dml2_core_internal_DmlPipe SurfaceParameters[DML2_MAX_PLANES]; 1257 unsigned int ReorderingBytes; 1258 double HostVMInefficiencyFactor; 1259 double HostVMInefficiencyFactorPrefetch; 1260 unsigned int TotalDCCActiveDPP; 1261 unsigned int TotalActiveDPP; 1262 unsigned int Total3dlutActive; 1263 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG 1264 bool immediate_flip_required; // any pipes need immediate flip 1265 bool DestinationLineTimesForPrefetchLessThan2; 1266 bool VRatioPrefetchMoreThanMax; 1267 double MaxTotalRDBandwidthNotIncludingMALLPrefetch; 1268 struct dml2_core_internal_SOCParametersList mmSOCParameters; 1269 double Tvstartup_margin; 1270 double dlg_vblank_start; 1271 double LSetup; 1272 double blank_lines_remaining; 1273 double WRBandwidth; 1274 struct dml2_core_internal_DmlPipe myPipe; 1275 double PixelClockBackEndFactor; 1276 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 1277 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 1278 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 1279 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 1280 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 1281 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 1282 1283 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1284 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1285 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 1286 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 1287 1288 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 1289 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 1290 unsigned int tdlut_row_bytes[DML2_MAX_PLANES]; 1291 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 1292 double tdlut_opt_time[DML2_MAX_PLANES]; 1293 double tdlut_drain_time[DML2_MAX_PLANES]; 1294 unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES]; 1295 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 1296 1297 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 1298 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 1299 unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES]; 1300 unsigned int cursor_bytes[DML2_MAX_PLANES]; 1301 1302 double Tvm_trips[DML2_MAX_PLANES]; 1303 double Tr0_trips[DML2_MAX_PLANES]; 1304 double Tvm_trips_flip[DML2_MAX_PLANES]; 1305 double Tr0_trips_flip[DML2_MAX_PLANES]; 1306 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 1307 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 1308 unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; 1309 1310 unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 1311 unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 1312 1313 double prefetch_sw_bytes[DML2_MAX_PLANES]; 1314 double Tpre_rounded[DML2_MAX_PLANES]; 1315 double Tpre_oto[DML2_MAX_PLANES]; 1316 bool recalc_prefetch_schedule; 1317 double impacted_dst_y_pre[DML2_MAX_PLANES]; 1318 double line_times[DML2_MAX_PLANES]; 1319 enum dml2_source_format_class pixel_format[DML2_MAX_PLANES]; 1320 unsigned int lb_source_lines_l[DML2_MAX_PLANES]; 1321 unsigned int lb_source_lines_c[DML2_MAX_PLANES]; 1322 unsigned int num_dsc_slices[DML2_MAX_PLANES]; 1323 bool dsc_enable[DML2_MAX_PLANES]; 1324 }; 1325 1326 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals { 1327 double ActiveDRAMClockChangeLatencyMargin[DML2_MAX_PLANES]; 1328 double ActiveFCLKChangeLatencyMargin[DML2_MAX_PLANES]; 1329 double USRRetrainingLatencyMargin[DML2_MAX_PLANES]; 1330 double g6_temp_read_latency_margin[DML2_MAX_PLANES]; 1331 double temp_read_or_ppt_latency_margin[DML2_MAX_PLANES]; 1332 1333 double EffectiveLBLatencyHidingY; 1334 double EffectiveLBLatencyHidingC; 1335 double LinesInDETY[DML2_MAX_PLANES]; 1336 double LinesInDETC[DML2_MAX_PLANES]; 1337 unsigned int LinesInDETYRoundedDownToSwath[DML2_MAX_PLANES]; 1338 unsigned int LinesInDETCRoundedDownToSwath[DML2_MAX_PLANES]; 1339 double FullDETBufferingTimeY; 1340 double FullDETBufferingTimeC; 1341 double WritebackDRAMClockChangeLatencyMargin; 1342 double WritebackFCLKChangeLatencyMargin; 1343 double WritebackTempReadOrPptLatencyMargin; 1344 double WritebackLatencyHiding; 1345 1346 unsigned int TotalActiveWriteback; 1347 unsigned int LBLatencyHidingSourceLinesY[DML2_MAX_PLANES]; 1348 unsigned int LBLatencyHidingSourceLinesC[DML2_MAX_PLANES]; 1349 double TotalPixelBW; 1350 double EffectiveDETBufferSizeY; 1351 double ActiveClockChangeLatencyHidingY; 1352 double ActiveClockChangeLatencyHidingC; 1353 double ActiveClockChangeLatencyHiding; 1354 double peak_vactive_p_vblank_latency_hiding_us; 1355 unsigned int dst_y_pstate; 1356 unsigned int src_y_pstate_l; 1357 unsigned int src_y_pstate_c; 1358 unsigned int src_y_ahead_l; 1359 unsigned int src_y_ahead_c; 1360 unsigned int sub_vp_lines_l; 1361 unsigned int sub_vp_lines_c; 1362 1363 }; 1364 1365 struct dml2_core_calcs_CalculateVMRowAndSwath_locals { 1366 unsigned int PTEBufferSizeInRequestsForLuma[DML2_MAX_PLANES]; 1367 unsigned int PTEBufferSizeInRequestsForChroma[DML2_MAX_PLANES]; 1368 unsigned int vm_bytes_l; 1369 unsigned int vm_bytes_c; 1370 unsigned int PixelPTEBytesPerRowY[DML2_MAX_PLANES]; 1371 unsigned int PixelPTEBytesPerRowC[DML2_MAX_PLANES]; 1372 unsigned int PixelPTEBytesPerRowStorageY[DML2_MAX_PLANES]; 1373 unsigned int PixelPTEBytesPerRowStorageC[DML2_MAX_PLANES]; 1374 unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DML2_MAX_PLANES]; 1375 unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DML2_MAX_PLANES]; 1376 unsigned int dpte_row_width_luma_ub_one_row_per_frame[DML2_MAX_PLANES]; 1377 unsigned int dpte_row_height_luma_one_row_per_frame[DML2_MAX_PLANES]; 1378 unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DML2_MAX_PLANES]; 1379 unsigned int dpte_row_height_chroma_one_row_per_frame[DML2_MAX_PLANES]; 1380 bool one_row_per_frame_fits_in_buffer[DML2_MAX_PLANES]; 1381 unsigned int HostVMDynamicLevels; 1382 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1383 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1384 }; 1385 1386 struct dml2_core_calcs_CalculateVMRowAndSwath_params { 1387 const struct dml2_display_cfg *display_cfg; 1388 unsigned int NumberOfActiveSurfaces; 1389 struct dml2_core_internal_DmlPipe *myPipe; 1390 unsigned int *SurfaceSizeInMALL; 1391 unsigned int PTEBufferSizeInRequestsLuma; 1392 unsigned int PTEBufferSizeInRequestsChroma; 1393 unsigned int MALLAllocatedForDCN; 1394 unsigned int *SwathWidthY; 1395 unsigned int *SwathWidthC; 1396 unsigned int HostVMMinPageSize; 1397 unsigned int DCCMetaBufferSizeBytes; 1398 bool mrq_present; 1399 enum dml2_pstate_method *uclk_pstate_switch_modes; 1400 1401 // Output 1402 bool *PTEBufferSizeNotExceeded; 1403 bool *DCCMetaBufferSizeNotExceeded; 1404 1405 unsigned int *dpte_row_width_luma_ub; 1406 unsigned int *dpte_row_width_chroma_ub; 1407 unsigned int *dpte_row_height_luma; 1408 unsigned int *dpte_row_height_chroma; 1409 unsigned int *dpte_row_height_linear_luma; // VBA_DELTA 1410 unsigned int *dpte_row_height_linear_chroma; // VBA_DELTA 1411 1412 unsigned int *vm_group_bytes; 1413 unsigned int *dpte_group_bytes; 1414 unsigned int *PixelPTEReqWidthY; 1415 unsigned int *PixelPTEReqHeightY; 1416 unsigned int *PTERequestSizeY; 1417 unsigned int *vmpg_width_y; 1418 unsigned int *vmpg_height_y; 1419 1420 unsigned int *PixelPTEReqWidthC; 1421 unsigned int *PixelPTEReqHeightC; 1422 unsigned int *PTERequestSizeC; 1423 unsigned int *vmpg_width_c; 1424 unsigned int *vmpg_height_c; 1425 1426 unsigned int *dpde0_bytes_per_frame_ub_l; 1427 unsigned int *dpde0_bytes_per_frame_ub_c; 1428 1429 unsigned int *PrefetchSourceLinesY; 1430 unsigned int *PrefetchSourceLinesC; 1431 unsigned int *VInitPreFillY; 1432 unsigned int *VInitPreFillC; 1433 unsigned int *MaxNumSwathY; 1434 unsigned int *MaxNumSwathC; 1435 double *dpte_row_bw; 1436 unsigned int *PixelPTEBytesPerRow; 1437 unsigned int *dpte_row_bytes_per_row_l; 1438 unsigned int *dpte_row_bytes_per_row_c; 1439 unsigned int *vm_bytes; 1440 bool *use_one_row_for_frame; 1441 bool *use_one_row_for_frame_flip; 1442 bool *is_using_mall_for_ss; 1443 bool *PTE_BUFFER_MODE; 1444 unsigned int *BIGK_FRAGMENT_SIZE; 1445 1446 // MRQ 1447 unsigned int *meta_req_width_luma; 1448 unsigned int *meta_req_height_luma; 1449 unsigned int *meta_row_width_luma; 1450 unsigned int *meta_row_height_luma; 1451 unsigned int *meta_pte_bytes_per_frame_ub_l; 1452 1453 unsigned int *meta_req_width_chroma; 1454 unsigned int *meta_req_height_chroma; 1455 unsigned int *meta_row_width_chroma; 1456 unsigned int *meta_row_height_chroma; 1457 unsigned int *meta_pte_bytes_per_frame_ub_c; 1458 double *meta_row_bw; 1459 unsigned int *meta_row_bytes; 1460 unsigned int *meta_row_bytes_per_row_ub_l; 1461 unsigned int *meta_row_bytes_per_row_ub_c; 1462 }; 1463 1464 struct dml2_core_calcs_CalculatePrefetchSchedule_locals { 1465 bool NoTimeToPrefetch; 1466 unsigned int DPPCycles; 1467 unsigned int DISPCLKCycles; 1468 double DSTTotalPixelsAfterScaler; 1469 double LineTime; 1470 double dst_y_prefetch_equ; 1471 double prefetch_bw_oto; 1472 double per_pipe_vactive_sw_bw; 1473 double Tvm_oto; 1474 double Tr0_oto; 1475 double Tvm_oto_lines; 1476 double Tr0_oto_lines; 1477 double dst_y_prefetch_oto; 1478 double TimeForFetchingVM; 1479 double TimeForFetchingRowInVBlank; 1480 double LinesToRequestPrefetchPixelData; 1481 unsigned int HostVMDynamicLevelsTrips; 1482 double trip_to_mem; 1483 double Tvm_trips_rounded; 1484 double Tr0_trips_rounded; 1485 double max_Tsw; 1486 double Lsw_oto; 1487 double prefetch_bw_equ; 1488 double Tvm_equ; 1489 double Tr0_equ; 1490 double Tdmbf; 1491 double Tdmec; 1492 double Tdmsks; 1493 double total_row_bytes; 1494 double prefetch_bw_pr; 1495 double bytes_pp; 1496 double dep_bytes; 1497 double min_Lsw_oto; 1498 double min_Lsw_equ; 1499 double Tsw_est1; 1500 double Tsw_est2; 1501 double Tsw_est3; 1502 double prefetch_bw1; 1503 double prefetch_bw2; 1504 double prefetch_bw3; 1505 double prefetch_bw4; 1506 double dst_y_prefetch_equ_impacted; 1507 1508 double TWait_p; 1509 unsigned int cursor_prefetch_bytes; 1510 }; 1511 1512 struct dml2_core_shared_calculate_det_buffer_size_params { 1513 const struct dml2_display_cfg *display_cfg; 1514 bool ForceSingleDPP; 1515 unsigned int NumberOfActiveSurfaces; 1516 bool UnboundedRequestEnabled; 1517 unsigned int nomDETInKByte; 1518 unsigned int MaxTotalDETInKByte; 1519 unsigned int ConfigReturnBufferSizeInKByte; 1520 unsigned int MinCompressedBufferSizeInKByte; 1521 unsigned int ConfigReturnBufferSegmentSizeInkByte; 1522 unsigned int CompressedBufferSegmentSizeInkByte; 1523 double *ReadBandwidthLuma; 1524 double *ReadBandwidthChroma; 1525 unsigned int *full_swath_bytes_l; 1526 unsigned int *full_swath_bytes_c; 1527 unsigned int *swath_time_value_us; 1528 unsigned int *DPPPerSurface; 1529 bool TryToAllocateForWriteLatency; 1530 unsigned int bestEffortMinActiveLatencyHidingUs; 1531 1532 // Output 1533 unsigned int *DETBufferSizeInKByte; 1534 unsigned int *CompressedBufferSizeInkByte; 1535 }; 1536 1537 struct dml2_core_shared_calculate_vm_and_row_bytes_params { 1538 bool ViewportStationary; 1539 bool DCCEnable; 1540 unsigned int NumberOfDPPs; 1541 unsigned int BlockHeight256Bytes; 1542 unsigned int BlockWidth256Bytes; 1543 enum dml2_source_format_class SourcePixelFormat; 1544 unsigned int SurfaceTiling; 1545 unsigned int BytePerPixel; 1546 enum dml2_rotation_angle RotationAngle; 1547 unsigned int SwathWidth; // per pipe 1548 unsigned int ViewportHeight; 1549 unsigned int ViewportXStart; 1550 unsigned int ViewportYStart; 1551 bool GPUVMEnable; 1552 unsigned int GPUVMMaxPageTableLevels; 1553 unsigned int GPUVMMinPageSizeKBytes; 1554 unsigned int PTEBufferSizeInRequests; 1555 unsigned int Pitch; 1556 unsigned int MacroTileWidth; 1557 unsigned int MacroTileHeight; 1558 bool is_phantom; 1559 unsigned int DCCMetaPitch; 1560 bool mrq_present; 1561 1562 // Output 1563 unsigned int *PixelPTEBytesPerRow; // for bandwidth calculation 1564 unsigned int *PixelPTEBytesPerRowStorage; // for PTE buffer size check 1565 unsigned int *dpte_row_width_ub; 1566 unsigned int *dpte_row_height; 1567 unsigned int *dpte_row_height_linear; 1568 unsigned int *PixelPTEBytesPerRow_one_row_per_frame; 1569 unsigned int *dpte_row_width_ub_one_row_per_frame; 1570 unsigned int *dpte_row_height_one_row_per_frame; 1571 unsigned int *vmpg_width; 1572 unsigned int *vmpg_height; 1573 unsigned int *PixelPTEReqWidth; 1574 unsigned int *PixelPTEReqHeight; 1575 unsigned int *PTERequestSize; 1576 unsigned int *dpde0_bytes_per_frame_ub; 1577 1578 unsigned int *meta_row_bytes; 1579 unsigned int *MetaRequestWidth; 1580 unsigned int *MetaRequestHeight; 1581 unsigned int *meta_row_width; 1582 unsigned int *meta_row_height; 1583 unsigned int *meta_pte_bytes_per_frame_ub; 1584 }; 1585 1586 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals { 1587 unsigned int MaximumSwathHeightY[DML2_MAX_PLANES]; 1588 unsigned int MaximumSwathHeightC[DML2_MAX_PLANES]; 1589 unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES]; 1590 unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES]; 1591 unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES]; 1592 unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES]; 1593 unsigned int SwathTimeValueUs[DML2_MAX_PLANES]; 1594 1595 struct dml2_core_shared_calculate_det_buffer_size_params calculate_det_buffer_size_params; 1596 }; 1597 1598 struct dml2_core_shared_TruncToValidBPP_locals { 1599 struct lib_frl_cap_check_params hdmifrlparams; 1600 struct lib_frl_cap_check_intermediates hdmifrlinter; 1601 }; 1602 1603 struct dml2_core_shared_CalculateDETBufferSize_locals { 1604 unsigned int DETBufferSizePoolInKByte; 1605 unsigned int NextDETBufferPieceInKByte; 1606 unsigned int NextSurfaceToAssignDETPiece; 1607 double TotalBandwidth; 1608 double BandwidthOfSurfacesNotAssignedDETPiece; 1609 unsigned int max_minDET; 1610 unsigned int minDET; 1611 unsigned int minDET_pipe; 1612 unsigned int TotalBandwidthPerStream[DML2_MAX_PLANES]; 1613 unsigned int TotalPixelRate; 1614 unsigned int DETBudgetPerStream[DML2_MAX_PLANES]; 1615 unsigned int RemainingDETBudgetPerStream[DML2_MAX_PLANES]; 1616 unsigned int IdealDETBudget, DeltaDETBudget; 1617 unsigned int ResidualDETAfterRounding; 1618 }; 1619 1620 struct dml2_core_shared_get_urgent_bandwidth_required_locals { 1621 double required_bandwidth_mbps; 1622 double required_bandwidth_mbps_this_surface; 1623 double adj_factor_p0; 1624 double adj_factor_p1; 1625 double adj_factor_cur; 1626 double adj_factor_p0_pre; 1627 double adj_factor_p1_pre; 1628 double adj_factor_cur_pre; 1629 double per_plane_flip_bw[DML2_MAX_PLANES]; 1630 double mall_svp_prefetch_factor; 1631 double tmp_nom_adj_factor_p0; 1632 double tmp_nom_adj_factor_p1; 1633 double tmp_pref_adj_factor_p0; 1634 double tmp_pref_adj_factor_p1; 1635 double vm_row_bw; 1636 double flip_and_active_bw; 1637 double flip_and_prefetch_bw; 1638 double flip_and_prefetch_bw_max; 1639 double active_and_excess_bw; 1640 }; 1641 1642 struct dml2_core_shared_calculate_peak_bandwidth_required_locals { 1643 double unity_array[DML2_MAX_PLANES]; 1644 double zero_array[DML2_MAX_PLANES]; 1645 double surface_dummy_bw[DML2_MAX_PLANES]; 1646 }; 1647 1648 struct dml2_core_shared_CalculateFlipSchedule_locals { 1649 double min_row_time; 1650 double Tvm_flip; 1651 double Tr0_flip; 1652 double ImmediateFlipBW; 1653 double dpte_row_bytes; 1654 double min_row_height; 1655 double min_row_height_chroma; 1656 double max_flip_time; 1657 double lb_flip_bw; 1658 double hvm_scaled_vm_bytes; 1659 double num_rows; 1660 double hvm_scaled_row_bytes; 1661 double hvm_scaled_vm_row_bytes; 1662 double vm_time_budget; 1663 double row_time_budget; 1664 double vm_and_row_time_budget; 1665 bool dual_plane; 1666 }; 1667 1668 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals { 1669 unsigned int plane_idx; 1670 unsigned int stream_idx; 1671 enum dml2_source_format_class source_format; 1672 const struct dml2_timing_cfg *timing; 1673 bool dual_plane; 1674 enum dml2_odm_mode odm_mode; 1675 1676 unsigned int htotal; 1677 unsigned int hactive; 1678 unsigned int hblank_end; 1679 unsigned int vblank_end; 1680 bool interlaced; 1681 double pclk_freq_in_mhz; 1682 double refclk_freq_in_mhz; 1683 double ref_freq_to_pix_freq; 1684 1685 unsigned int num_active_pipes; 1686 unsigned int first_pipe_idx_in_plane; 1687 unsigned int pipe_idx_in_combine; 1688 unsigned int odm_combine_factor; 1689 1690 double min_ttu_vblank; 1691 unsigned int min_dst_y_next_start; 1692 1693 unsigned int vready_after_vcount0; 1694 1695 unsigned int dst_x_after_scaler; 1696 unsigned int dst_y_after_scaler; 1697 1698 double dst_y_prefetch; 1699 double dst_y_per_vm_vblank; 1700 double dst_y_per_row_vblank; 1701 double dst_y_per_vm_flip; 1702 double dst_y_per_row_flip; 1703 1704 double max_dst_y_per_vm_vblank; 1705 double max_dst_y_per_row_vblank; 1706 1707 double vratio_pre_l; 1708 double vratio_pre_c; 1709 1710 double refcyc_per_line_delivery_pre_l; 1711 double refcyc_per_line_delivery_l; 1712 1713 double refcyc_per_line_delivery_pre_c; 1714 double refcyc_per_line_delivery_c; 1715 1716 double refcyc_per_req_delivery_pre_l; 1717 double refcyc_per_req_delivery_l; 1718 1719 double refcyc_per_req_delivery_pre_c; 1720 double refcyc_per_req_delivery_c; 1721 1722 double dst_y_per_pte_row_nom_l; 1723 double dst_y_per_pte_row_nom_c; 1724 double refcyc_per_pte_group_nom_l; 1725 double refcyc_per_pte_group_nom_c; 1726 double refcyc_per_pte_group_vblank_l; 1727 double refcyc_per_pte_group_vblank_c; 1728 double refcyc_per_pte_group_flip_l; 1729 double refcyc_per_pte_group_flip_c; 1730 double refcyc_per_tdlut_group; 1731 1732 double dst_y_per_meta_row_nom_l; 1733 double dst_y_per_meta_row_nom_c; 1734 double refcyc_per_meta_chunk_nom_l; 1735 double refcyc_per_meta_chunk_nom_c; 1736 double refcyc_per_meta_chunk_vblank_l; 1737 double refcyc_per_meta_chunk_vblank_c; 1738 double refcyc_per_meta_chunk_flip_l; 1739 double refcyc_per_meta_chunk_flip_c; 1740 }; 1741 1742 struct dml2_core_shared_CalculateMetaAndPTETimes_params { 1743 struct dml2_core_internal_scratch *scratch; 1744 const struct dml2_display_cfg *display_cfg; 1745 unsigned int NumberOfActiveSurfaces; 1746 bool *use_one_row_for_frame; 1747 double *dst_y_per_row_vblank; 1748 double *dst_y_per_row_flip; 1749 unsigned int *BytePerPixelY; 1750 unsigned int *BytePerPixelC; 1751 unsigned int *dpte_row_height; 1752 unsigned int *dpte_row_height_chroma; 1753 unsigned int *dpte_group_bytes; 1754 unsigned int *PTERequestSizeY; 1755 unsigned int *PTERequestSizeC; 1756 unsigned int *PixelPTEReqWidthY; 1757 unsigned int *PixelPTEReqHeightY; 1758 unsigned int *PixelPTEReqWidthC; 1759 unsigned int *PixelPTEReqHeightC; 1760 unsigned int *dpte_row_width_luma_ub; 1761 unsigned int *dpte_row_width_chroma_ub; 1762 unsigned int *tdlut_groups_per_2row_ub; 1763 bool mrq_present; 1764 unsigned int MetaChunkSize; 1765 unsigned int MinMetaChunkSizeBytes; 1766 unsigned int *meta_row_width; 1767 unsigned int *meta_row_width_chroma; 1768 unsigned int *meta_row_height; 1769 unsigned int *meta_row_height_chroma; 1770 unsigned int *meta_req_width; 1771 unsigned int *meta_req_width_chroma; 1772 unsigned int *meta_req_height; 1773 unsigned int *meta_req_height_chroma; 1774 1775 // Output 1776 double *time_per_tdlut_group; 1777 double *DST_Y_PER_PTE_ROW_NOM_L; 1778 double *DST_Y_PER_PTE_ROW_NOM_C; 1779 double *time_per_pte_group_nom_luma; 1780 double *time_per_pte_group_vblank_luma; 1781 double *time_per_pte_group_flip_luma; 1782 double *time_per_pte_group_nom_chroma; 1783 double *time_per_pte_group_vblank_chroma; 1784 double *time_per_pte_group_flip_chroma; 1785 1786 double *DST_Y_PER_META_ROW_NOM_L; 1787 double *DST_Y_PER_META_ROW_NOM_C; 1788 1789 double *TimePerMetaChunkNominal; 1790 double *TimePerChromaMetaChunkNominal; 1791 double *TimePerMetaChunkVBlank; 1792 double *TimePerChromaMetaChunkVBlank; 1793 double *TimePerMetaChunkFlip; 1794 double *TimePerChromaMetaChunkFlip; 1795 }; 1796 1797 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params { 1798 const struct dml2_display_cfg *display_cfg; 1799 bool USRRetrainingRequired; 1800 unsigned int NumberOfActiveSurfaces; 1801 unsigned int MaxLineBufferLines; 1802 unsigned int LineBufferSize; 1803 unsigned int WritebackInterfaceBufferSize; 1804 double DCFCLK; 1805 double ReturnBW; 1806 bool SynchronizeTimings; 1807 bool SynchronizeDRRDisplaysForUCLKPStateChange; 1808 const unsigned int *dpte_group_bytes; 1809 struct dml2_core_internal_SOCParametersList mmSOCParameters; 1810 unsigned int WritebackChunkSize; 1811 double SOCCLK; 1812 double DCFClkDeepSleep; 1813 const unsigned int *DETBufferSizeY; 1814 const unsigned int *DETBufferSizeC; 1815 const unsigned int *SwathHeightY; 1816 const unsigned int *SwathHeightC; 1817 const unsigned int *SwathWidthY; 1818 const unsigned int *SwathWidthC; 1819 const unsigned int *DPPPerSurface; 1820 const double *BytePerPixelDETY; 1821 const double *BytePerPixelDETC; 1822 const unsigned int *DSTXAfterScaler; 1823 const unsigned int *DSTYAfterScaler; 1824 bool UnboundedRequestEnabled; 1825 unsigned int CompressedBufferSizeInkByte; 1826 bool max_outstanding_when_urgent_expected; 1827 unsigned int max_outstanding_requests; 1828 unsigned int max_request_size_bytes; 1829 const unsigned int *meta_row_height_l; 1830 const unsigned int *meta_row_height_c; 1831 const enum dml2_pstate_method *uclk_pstate_switch_modes; 1832 1833 // Output 1834 struct dml2_core_internal_watermarks *Watermark; 1835 enum dml2_pstate_change_support *DRAMClockChangeSupport; 1836 bool *global_dram_clock_change_support_required; 1837 bool *global_dram_clock_change_supported; 1838 double *MaxActiveDRAMClockChangeLatencySupported; 1839 unsigned int *SubViewportLinesNeededInMALL; 1840 enum dml2_pstate_change_support *FCLKChangeSupport; 1841 bool *global_fclk_change_supported; 1842 double *MaxActiveFCLKChangeLatencySupported; 1843 bool *USRRetrainingSupport; 1844 double *VActiveLatencyHidingMargin; 1845 double *VActiveLatencyHidingUs; 1846 bool *g6_temp_read_support; 1847 enum dml2_pstate_change_support *temp_read_or_ppt_support; 1848 bool *global_temp_read_or_ppt_supported; 1849 bool *global_z8_stutter_supported; 1850 }; 1851 1852 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params { 1853 const struct dml2_display_cfg *display_cfg; 1854 unsigned int ConfigReturnBufferSizeInKByte; 1855 unsigned int MaxTotalDETInKByte; 1856 unsigned int MinCompressedBufferSizeInKByte; 1857 unsigned int rob_buffer_size_kbytes; 1858 unsigned int pixel_chunk_size_kbytes; 1859 bool ForceSingleDPP; 1860 unsigned int NumberOfActiveSurfaces; 1861 unsigned int nomDETInKByte; 1862 unsigned int ConfigReturnBufferSegmentSizeInkByte; 1863 unsigned int CompressedBufferSegmentSizeInkByte; 1864 double *ReadBandwidthLuma; 1865 double *ReadBandwidthChroma; 1866 double *MaximumSwathWidthLuma; 1867 double *MaximumSwathWidthChroma; 1868 unsigned int *Read256BytesBlockHeightY; 1869 unsigned int *Read256BytesBlockHeightC; 1870 unsigned int *Read256BytesBlockWidthY; 1871 unsigned int *Read256BytesBlockWidthC; 1872 bool *surf_linear128_l; 1873 bool *surf_linear128_c; 1874 enum dml2_odm_mode *ODMMode; 1875 unsigned int *BytePerPixY; 1876 unsigned int *BytePerPixC; 1877 double *BytePerPixDETY; 1878 double *BytePerPixDETC; 1879 unsigned int *DPPPerSurface; 1880 bool mrq_present; 1881 unsigned int dummy[2][DML2_MAX_PLANES]; 1882 unsigned int swath_width_luma_ub_single_dpp[DML2_MAX_PLANES]; 1883 unsigned int swath_width_chroma_ub_single_dpp[DML2_MAX_PLANES]; 1884 1885 // output 1886 unsigned int *req_per_swath_ub_l; 1887 unsigned int *req_per_swath_ub_c; 1888 unsigned int *swath_width_luma_ub; 1889 unsigned int *swath_width_chroma_ub; 1890 unsigned int *SwathWidth; 1891 unsigned int *SwathWidthChroma; 1892 unsigned int *SwathHeightY; 1893 unsigned int *SwathHeightC; 1894 unsigned int *request_size_bytes_luma; 1895 unsigned int *request_size_bytes_chroma; 1896 unsigned int *DETBufferSizeInKByte; 1897 unsigned int *DETBufferSizeY; 1898 unsigned int *DETBufferSizeC; 1899 unsigned int *full_swath_bytes_l; 1900 unsigned int *full_swath_bytes_c; 1901 unsigned int *full_swath_bytes_single_dpp_l; 1902 unsigned int *full_swath_bytes_single_dpp_c; 1903 bool *UnboundedRequestEnabled; 1904 unsigned int *compbuf_reserved_space_64b; 1905 unsigned int *CompressedBufferSizeInkByte; 1906 bool *ViewportSizeSupportPerSurface; 1907 bool *ViewportSizeSupport; 1908 bool *hw_debug5; 1909 1910 struct dml2_core_shared_calculation_funcs *funcs; 1911 }; 1912 1913 struct dml2_core_calcs_CalculateStutterEfficiency_locals { 1914 double DETBufferingTimeY; 1915 double SwathWidthYCriticalSurface; 1916 double SwathHeightYCriticalSurface; 1917 double VActiveTimeCriticalSurface; 1918 double FrameTimeCriticalSurface; 1919 unsigned int BytePerPixelYCriticalSurface; 1920 unsigned int DETBufferSizeYCriticalSurface; 1921 double MinTTUVBlankCriticalSurface; 1922 unsigned int BlockWidth256BytesYCriticalSurface; 1923 bool SinglePlaneCriticalSurface; 1924 bool SinglePipeCriticalSurface; 1925 double TotalCompressedReadBandwidth; 1926 double TotalRowReadBandwidth; 1927 double AverageDCCCompressionRate; 1928 double EffectiveCompressedBufferSize; 1929 double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer; 1930 double StutterBurstTime; 1931 unsigned int TotalActiveWriteback; 1932 double LinesInDETY; 1933 double LinesInDETYRoundedDownToSwath; 1934 double MaximumEffectiveCompressionLuma; 1935 double MaximumEffectiveCompressionChroma; 1936 double TotalZeroSizeRequestReadBandwidth; 1937 double TotalZeroSizeCompressedReadBandwidth; 1938 double AverageDCCZeroSizeFraction; 1939 double AverageZeroSizeCompressionRate; 1940 bool stream_visited[DML2_MAX_PLANES]; 1941 }; 1942 1943 struct dml2_core_calcs_CalculateStutterEfficiency_params { 1944 const struct dml2_display_cfg *display_cfg; 1945 unsigned int CompressedBufferSizeInkByte; 1946 bool UnboundedRequestEnabled; 1947 unsigned int MetaFIFOSizeInKEntries; 1948 unsigned int ZeroSizeBufferEntries; 1949 unsigned int PixelChunkSizeInKByte; 1950 unsigned int NumberOfActiveSurfaces; 1951 unsigned int ROBBufferSizeInKByte; 1952 double TotalDataReadBandwidth; 1953 double DCFCLK; 1954 double ReturnBW; 1955 unsigned int CompbufReservedSpace64B; 1956 unsigned int CompbufReservedSpaceZs; 1957 bool hw_debug5; 1958 double SRExitTime; 1959 double SRExitTimeLowPower; 1960 double SRExitZ8Time; 1961 bool SynchronizeTimings; 1962 double StutterEnterPlusExitWatermark; 1963 double LowPowerStutterEnterPlusExitWatermark; 1964 double Z8StutterEnterPlusExitWatermark; 1965 bool ProgressiveToInterlaceUnitInOPP; 1966 double *MinTTUVBlank; 1967 unsigned int *DPPPerSurface; 1968 unsigned int *DETBufferSizeY; 1969 unsigned int *BytePerPixelY; 1970 double *BytePerPixelDETY; 1971 unsigned int *SwathWidthY; 1972 unsigned int *SwathHeightY; 1973 unsigned int *SwathHeightC; 1974 unsigned int *BlockHeight256BytesY; 1975 unsigned int *BlockWidth256BytesY; 1976 unsigned int *BlockHeight256BytesC; 1977 unsigned int *BlockWidth256BytesC; 1978 unsigned int *DCCYMaxUncompressedBlock; 1979 unsigned int *DCCCMaxUncompressedBlock; 1980 double *ReadBandwidthSurfaceLuma; 1981 double *ReadBandwidthSurfaceChroma; 1982 double *meta_row_bw; 1983 double *dpte_row_bw; 1984 bool rob_alloc_compressed; 1985 1986 // output 1987 double *StutterEfficiencyNotIncludingVBlank; 1988 double *StutterEfficiency; 1989 double *LowPowerStutterEfficiencyNotIncludingVBlank; 1990 double *LowPowerStutterEfficiency; 1991 unsigned int *NumberOfStutterBurstsPerFrame; 1992 unsigned int *LowPowerNumberOfStutterBurstsPerFrame; 1993 double *Z8StutterEfficiencyNotIncludingVBlank; 1994 double *Z8StutterEfficiency; 1995 unsigned int *Z8NumberOfStutterBurstsPerFrame; 1996 double *StutterPeriod; 1997 bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 1998 }; 1999 2000 struct dml2_core_calcs_CalculatePrefetchSchedule_params { 2001 const struct dml2_display_cfg *display_cfg; 2002 double HostVMInefficiencyFactor; 2003 struct dml2_core_internal_DmlPipe *myPipe; 2004 unsigned int DSCDelay; 2005 double DPPCLKDelaySubtotalPlusCNVCFormater; 2006 double DPPCLKDelaySCL; 2007 double DPPCLKDelaySCLLBOnly; 2008 double DPPCLKDelayCNVCCursor; 2009 double DISPCLKDelaySubtotal; 2010 unsigned int DPP_RECOUT_WIDTH; 2011 enum dml2_output_format_class OutputFormat; 2012 unsigned int MaxInterDCNTileRepeaters; 2013 unsigned int VStartup; 2014 unsigned int HostVMMinPageSize; 2015 bool DynamicMetadataEnable; 2016 bool DynamicMetadataVMEnabled; 2017 unsigned int DynamicMetadataLinesBeforeActiveRequired; 2018 unsigned int DynamicMetadataTransmittedBytes; 2019 double ExtraLatencyPrefetch; 2020 double TCalc; 2021 unsigned int vm_bytes; 2022 unsigned int PixelPTEBytesPerRow; 2023 double PrefetchSourceLinesY; 2024 unsigned int VInitPreFillY; 2025 unsigned int MaxNumSwathY; 2026 double PrefetchSourceLinesC; 2027 unsigned int VInitPreFillC; 2028 unsigned int MaxNumSwathC; 2029 unsigned int swath_width_luma_ub; // per-pipe 2030 unsigned int swath_width_chroma_ub; // per-pipe 2031 unsigned int SwathHeightY; 2032 unsigned int SwathHeightC; 2033 double TWait; 2034 double Ttrip; 2035 double Turg; 2036 bool setup_for_tdlut; 2037 bool use_max_lsw; 2038 unsigned int tdlut_pte_bytes_per_frame; 2039 unsigned int tdlut_bytes_per_frame; 2040 double tdlut_opt_time; 2041 double tdlut_drain_time; 2042 2043 unsigned int num_cursors; 2044 unsigned int cursor_bytes_per_chunk; 2045 unsigned int cursor_bytes_per_line; 2046 2047 // MRQ 2048 bool dcc_enable; 2049 bool mrq_present; 2050 unsigned int meta_row_bytes; 2051 double mall_prefetch_sdp_overhead_factor; 2052 2053 double impacted_dst_y_pre; 2054 double vactive_sw_bw_l; // per surface bw 2055 double vactive_sw_bw_c; // per surface bw 2056 2057 // output 2058 unsigned int *DSTXAfterScaler; 2059 unsigned int *DSTYAfterScaler; 2060 double *dst_y_prefetch; 2061 double *dst_y_per_vm_vblank; 2062 double *dst_y_per_row_vblank; 2063 double *VRatioPrefetchY; 2064 double *VRatioPrefetchC; 2065 double *RequiredPrefetchPixelDataBWLuma; 2066 double *RequiredPrefetchPixelDataBWChroma; 2067 double *RequiredPrefetchBWMax; 2068 bool *NotEnoughTimeForDynamicMetadata; 2069 double *Tno_bw; 2070 double *Tno_bw_flip; 2071 double *prefetch_vmrow_bw; 2072 double *Tdmdl_vm; 2073 double *Tdmdl; 2074 double *TSetup; 2075 double *Tpre_rounded; 2076 double *Tpre_oto; 2077 double *Tvm_trips; 2078 double *Tr0_trips; 2079 double *Tvm_trips_flip; 2080 double *Tr0_trips_flip; 2081 double *Tvm_trips_flip_rounded; 2082 double *Tr0_trips_flip_rounded; 2083 unsigned int *VUpdateOffsetPix; 2084 unsigned int *VUpdateWidthPix; 2085 unsigned int *VReadyOffsetPix; 2086 double *prefetch_cursor_bw; 2087 double *prefetch_sw_bytes; 2088 double *prefetch_swath_time_us; 2089 }; 2090 2091 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params { 2092 unsigned int num_active_planes; 2093 enum dml2_source_format_class *pixel_format; 2094 unsigned int rob_buffer_size_kbytes; 2095 unsigned int compressed_buffer_size_kbytes; 2096 unsigned int chunk_bytes_l; // same for all planes 2097 unsigned int chunk_bytes_c; 2098 unsigned int *detile_buffer_size_bytes_l; 2099 unsigned int *detile_buffer_size_bytes_c; 2100 unsigned int *full_swath_bytes_l; 2101 unsigned int *full_swath_bytes_c; 2102 unsigned int *lb_source_lines_l; 2103 unsigned int *lb_source_lines_c; 2104 unsigned int *swath_height_l; 2105 unsigned int *swath_height_c; 2106 double *prefetch_sw_bytes; 2107 double *Tpre_rounded; 2108 double *Tpre_oto; 2109 double estimated_dcfclk_mhz; 2110 double estimated_urg_bandwidth_required_mbps; 2111 double *line_time; 2112 double *dst_y_prefetch; 2113 2114 // output 2115 bool *recalc_prefetch_schedule; 2116 double *impacted_dst_y_pre; 2117 }; 2118 2119 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals { 2120 unsigned int max_Trpd_dcfclk_cycles; 2121 unsigned int burst_bytes_to_fill_det; 2122 double time_to_fill_det_us; 2123 unsigned int accumulated_return_path_dcfclk_cycles[DML2_MAX_PLANES]; 2124 bool prefetch_global_check_passed; 2125 unsigned int src_swath_bytes_l[DML2_MAX_PLANES]; 2126 unsigned int src_swath_bytes_c[DML2_MAX_PLANES]; 2127 unsigned int src_detile_buf_size_bytes_l[DML2_MAX_PLANES]; 2128 unsigned int src_detile_buf_size_bytes_c[DML2_MAX_PLANES]; 2129 }; 2130 2131 struct dml2_core_calcs_calculate_mcache_row_bytes_params { 2132 unsigned int num_chans; 2133 unsigned int mem_word_bytes; 2134 unsigned int mcache_size_bytes; 2135 unsigned int mcache_line_size_bytes; 2136 unsigned int gpuvm_enable; 2137 unsigned int gpuvm_page_size_kbytes; 2138 2139 //enum dml_rotation_angle rotation_angle; 2140 bool surf_vert; 2141 unsigned int vp_stationary; 2142 unsigned int tiling_mode; 2143 bool imall_enable; 2144 2145 unsigned int vp_start_x; 2146 unsigned int vp_start_y; 2147 unsigned int full_vp_width; 2148 unsigned int full_vp_height; 2149 unsigned int blk_width; 2150 unsigned int blk_height; 2151 unsigned int vmpg_width; 2152 unsigned int vmpg_height; 2153 unsigned int full_swath_bytes; 2154 unsigned int bytes_per_pixel; 2155 2156 // output 2157 unsigned int *num_mcaches; 2158 unsigned int *mcache_row_bytes; 2159 unsigned int *mcache_row_bytes_per_channel; 2160 unsigned int *meta_row_width_ub; 2161 double *dcc_dram_bw_nom_overhead_factor; 2162 double *dcc_dram_bw_pref_overhead_factor; 2163 unsigned int *mvmpg_width; 2164 unsigned int *mvmpg_height; 2165 unsigned int *full_vp_access_width_mvmpg_aligned; 2166 unsigned int *mvmpg_per_mcache_lb; 2167 }; 2168 2169 struct dml2_core_shared_calculate_mcache_setting_locals { 2170 struct dml2_core_calcs_calculate_mcache_row_bytes_params l_p; 2171 struct dml2_core_calcs_calculate_mcache_row_bytes_params c_p; 2172 2173 bool is_dual_plane; 2174 unsigned int mvmpg_width_l; 2175 unsigned int mvmpg_height_l; 2176 unsigned int full_vp_access_width_mvmpg_aligned_l; 2177 unsigned int mvmpg_per_mcache_lb_l; 2178 unsigned int meta_row_width_l; 2179 2180 unsigned int mvmpg_width_c; 2181 unsigned int mvmpg_height_c; 2182 unsigned int full_vp_access_width_mvmpg_aligned_c; 2183 unsigned int mvmpg_per_mcache_lb_c; 2184 unsigned int meta_row_width_c; 2185 2186 unsigned int lc_comb_last_mcache_size; 2187 double luma_time_factor; 2188 double mcache_remainder_l; 2189 double mcache_remainder_c; 2190 unsigned int mvmpg_access_width_l; 2191 unsigned int mvmpg_access_width_c; 2192 unsigned int avg_mcache_element_size_l; 2193 unsigned int avg_mcache_element_size_c; 2194 2195 unsigned int full_vp_access_width_l; 2196 unsigned int full_vp_access_width_c; 2197 }; 2198 2199 struct dml2_core_calcs_calculate_mcache_setting_params { 2200 bool dcc_enable; 2201 unsigned int num_chans; 2202 unsigned int mem_word_bytes; 2203 unsigned int mcache_size_bytes; 2204 unsigned int mcache_line_size_bytes; 2205 unsigned int gpuvm_enable; 2206 unsigned int gpuvm_page_size_kbytes; 2207 2208 enum dml2_source_format_class source_format; 2209 bool surf_vert; 2210 unsigned int vp_stationary; 2211 unsigned int tiling_mode; 2212 bool imall_enable; 2213 2214 unsigned int vp_start_x_l; 2215 unsigned int vp_start_y_l; 2216 unsigned int full_vp_width_l; 2217 unsigned int full_vp_height_l; 2218 unsigned int blk_width_l; 2219 unsigned int blk_height_l; 2220 unsigned int vmpg_width_l; 2221 unsigned int vmpg_height_l; 2222 unsigned int full_swath_bytes_l; 2223 unsigned int bytes_per_pixel_l; 2224 2225 unsigned int vp_start_x_c; 2226 unsigned int vp_start_y_c; 2227 unsigned int full_vp_width_c; 2228 unsigned int full_vp_height_c; 2229 unsigned int blk_width_c; 2230 unsigned int blk_height_c; 2231 unsigned int vmpg_width_c; 2232 unsigned int vmpg_height_c; 2233 unsigned int full_swath_bytes_c; 2234 unsigned int bytes_per_pixel_c; 2235 2236 // output 2237 unsigned int *num_mcaches_l; 2238 unsigned int *mcache_row_bytes_l; 2239 unsigned int *mcache_row_bytes_per_channel_l; 2240 unsigned int *mcache_offsets_l; 2241 unsigned int *mcache_shift_granularity_l; 2242 double *dcc_dram_bw_nom_overhead_factor_l; 2243 double *dcc_dram_bw_pref_overhead_factor_l; 2244 2245 unsigned int *num_mcaches_c; 2246 unsigned int *mcache_row_bytes_c; 2247 unsigned int *mcache_row_bytes_per_channel_c; 2248 unsigned int *mcache_offsets_c; 2249 unsigned int *mcache_shift_granularity_c; 2250 double *dcc_dram_bw_nom_overhead_factor_c; 2251 double *dcc_dram_bw_pref_overhead_factor_c; 2252 2253 bool *mall_comb_mcache_l; 2254 bool *mall_comb_mcache_c; 2255 bool *lc_comb_mcache; 2256 }; 2257 2258 2259 struct dml2_core_calcs_calculate_alternate_lead_lines { 2260 /* input params */ 2261 const struct dml2_display_cfg *display_cfg; 2262 unsigned int *VStartup; 2263 double *VActiveLatencyHidingUs; 2264 2265 /* output params */ 2266 unsigned int *min_lead_dst_lines; 2267 }; 2268 2269 struct dml2_core_calcs_calculate_alternate_svp_lines { 2270 /* input params */ 2271 const struct dml2_display_cfg *display_cfg; 2272 unsigned int *SwathHeightY; 2273 unsigned int *SwathHeightC; 2274 unsigned int *DETBufferSizeY; 2275 double *BytePerPixelInDETC; 2276 double dram_blackout_us; 2277 2278 /* output params */ 2279 unsigned int *svp0_dst_lines; 2280 unsigned int *svp1_dst_lines; 2281 unsigned int *svp_req_limit; 2282 }; 2283 2284 struct dml2_core_calcs_calculate_alternate_params { 2285 /* input params */ 2286 const struct dml2_display_cfg *display_cfg; 2287 double *dst_y_prefetch; 2288 unsigned int *SwathHeightY; 2289 unsigned int *SwathHeightC; 2290 unsigned int *SwathWidthY; 2291 unsigned int *SwathWidthC; 2292 unsigned int *DETBufferSizeY; 2293 unsigned int *DETBufferSizeC; 2294 unsigned int *BytePerPixelY; 2295 unsigned int *BytePerPixelC; 2296 double *BytePerPixelInDETY; 2297 double *BytePerPixelInDETC; 2298 unsigned int *Read256BlockWidthY; 2299 unsigned int *Read256BlockHeightY; 2300 unsigned int *Read256BlockWidthC; 2301 unsigned int *Read256BlockHeightC; 2302 unsigned int *MacroTileWidthY; 2303 unsigned int *MacroTileWidthC; 2304 unsigned int *MacroTileHeightY; 2305 unsigned int *MacroTileHeightC; 2306 unsigned int *VInitPrefillY; 2307 unsigned int *VInitPrefillC; 2308 double *VRatioPrefetchY; 2309 double *VRatioPrefetchC; 2310 unsigned int *NoOfDPP; 2311 unsigned int max_num_dpp; 2312 double dram_blackout_us; 2313 unsigned int *svp0_dst_lines; 2314 unsigned int *svp1_dst_lines; 2315 unsigned int *svp_req_limit; 2316 double dcn_non_urgent_bandwidth_kbps; 2317 double max_lsdma_bandwidth_kbps; 2318 unsigned int alt_chan_fw_delay_us; 2319 double *dst_y_per_vm_vblank; 2320 double *dst_y_per_row_vblank; 2321 unsigned int *DSTYAfterScaler; 2322 enum dml2_odm_mode *ODMMode; 2323 bool alt_chan_in_use; 2324 2325 /* output params */ 2326 unsigned int *svp0_max_bytes; 2327 unsigned int *svp1_max_bytes; 2328 unsigned int *svp0_max_bytes_per_dpp; 2329 unsigned int *svp0_max_bytes_per_dpp_c; 2330 unsigned int *svp1_max_bytes_per_dpp; 2331 unsigned int *svp1_max_bytes_per_dpp_c; 2332 unsigned int *nom_req_limit_alt; 2333 unsigned int *min_lead_dst_lines; 2334 unsigned int *total_swaths; 2335 unsigned int *total_swaths_c; 2336 unsigned int *prefetch_swaths; 2337 unsigned int *prefetch_swaths_c; 2338 double *prefetch_hdl_delta; 2339 double *recout_hdl_delta; 2340 double *prefetch_hdl_delta_c; 2341 double *recout_hdl_delta_c; 2342 unsigned int *max_prefetch_in_lines; 2343 double *lsdma_bw_req_for_alt_kbps; 2344 }; 2345 struct dml2_core_calcs_calculate_tdlut_setting_params { 2346 // input params 2347 double dispclk_mhz; 2348 bool setup_for_tdlut; 2349 enum dml2_tdlut_width_mode tdlut_width_mode; 2350 enum dml2_tdlut_addressing_mode tdlut_addressing_mode; 2351 unsigned int cursor_buffer_size; 2352 bool gpuvm_enable; 2353 unsigned int gpuvm_page_size_kbytes; 2354 bool is_gfx11; 2355 bool tdlut_mpc_width_flag; 2356 2357 // output param 2358 unsigned int *tdlut_pte_bytes_per_frame; 2359 unsigned int *tdlut_bytes_per_frame; 2360 unsigned int *tdlut_groups_per_2row_ub; 2361 double *tdlut_opt_time; 2362 double *tdlut_drain_time; 2363 unsigned int *tdlut_bytes_to_deliver; 2364 unsigned int *tdlut_bytes_per_group; 2365 }; 2366 2367 struct dml2_core_calcs_calculate_peak_bandwidth_required_params { 2368 // output 2369 double (*urg_vactive_bandwidth_required)[dml2_core_internal_bw_max]; 2370 double (*urg_bandwidth_required)[dml2_core_internal_bw_max]; 2371 double (*urg_bandwidth_required_qual)[dml2_core_internal_bw_max]; 2372 double (*non_urg_bandwidth_required)[dml2_core_internal_bw_max]; 2373 double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES]; 2374 double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES]; 2375 2376 // input 2377 const struct dml2_display_cfg *display_cfg; 2378 bool inc_flip_bw; 2379 unsigned int num_active_planes; 2380 unsigned int *num_of_dpp; 2381 double *dcc_dram_bw_nom_overhead_factor_p0; 2382 double *dcc_dram_bw_nom_overhead_factor_p1; 2383 double *dcc_dram_bw_pref_overhead_factor_p0; 2384 double *dcc_dram_bw_pref_overhead_factor_p1; 2385 double *mall_prefetch_sdp_overhead_factor; 2386 double *mall_prefetch_dram_overhead_factor; 2387 double *surface_read_bandwidth_l; 2388 double *surface_read_bandwidth_c; 2389 double *prefetch_bandwidth_l; 2390 double *prefetch_bandwidth_c; 2391 double *prefetch_bandwidth_max; 2392 double *excess_vactive_fill_bw_l; 2393 double *excess_vactive_fill_bw_c; 2394 double *cursor_bw; 2395 double *dpte_row_bw; 2396 double *meta_row_bw; 2397 double *prefetch_cursor_bw; 2398 double *prefetch_vmrow_bw; 2399 double *flip_bw; 2400 double *urgent_burst_factor_l; 2401 double *urgent_burst_factor_c; 2402 double *urgent_burst_factor_cursor; 2403 double *urgent_burst_factor_prefetch_l; 2404 double *urgent_burst_factor_prefetch_c; 2405 double *urgent_burst_factor_prefetch_cursor; 2406 }; 2407 2408 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params { 2409 /* inputs */ 2410 const struct dml2_display_cfg *display_cfg; 2411 bool mrq_present; 2412 unsigned int num_active_planes; 2413 unsigned int *num_of_dpp; 2414 unsigned int *meta_row_height_l; 2415 unsigned int *meta_row_height_c; 2416 unsigned int *meta_row_bytes_per_row_ub_l; 2417 unsigned int *meta_row_bytes_per_row_ub_c; 2418 unsigned int *dpte_row_height_l; 2419 unsigned int *dpte_row_height_c; 2420 unsigned int *dpte_bytes_per_row_l; 2421 unsigned int *dpte_bytes_per_row_c; 2422 unsigned int *byte_per_pix_l; 2423 unsigned int *byte_per_pix_c; 2424 unsigned int *swath_width_l; 2425 unsigned int *swath_width_c; 2426 unsigned int *swath_height_l; 2427 unsigned int *swath_height_c; 2428 double latency_to_hide_us[DML2_MAX_PLANES]; 2429 2430 /* outputs */ 2431 unsigned int *bytes_required_l; 2432 unsigned int *bytes_required_c; 2433 }; 2434 2435 // A list of overridable function pointers in the core 2436 // shared calculation library. 2437 struct dml2_core_shared_calculation_funcs { 2438 void (*calculate_det_buffer_size)(struct dml2_core_shared_calculate_det_buffer_size_params *p); 2439 }; 2440 2441 struct dml2_core_internal_scratch { 2442 // Scratch space for function locals 2443 struct dml2_core_calcs_mode_support_locals dml_core_mode_support_locals; 2444 struct dml2_core_calcs_mode_programming_locals dml_core_mode_programming_locals; 2445 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals; 2446 struct dml2_core_calcs_CalculateVMRowAndSwath_locals CalculateVMRowAndSwath_locals; 2447 struct dml2_core_calcs_CalculatePrefetchSchedule_locals CalculatePrefetchSchedule_locals; 2448 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals CheckGlobalPrefetchAdmissibility_locals; 2449 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals CalculateSwathAndDETConfiguration_locals; 2450 struct dml2_core_shared_TruncToValidBPP_locals TruncToValidBPP_locals; 2451 struct dml2_core_shared_CalculateDETBufferSize_locals CalculateDETBufferSize_locals; 2452 struct dml2_core_shared_get_urgent_bandwidth_required_locals get_urgent_bandwidth_required_locals; 2453 struct dml2_core_shared_calculate_peak_bandwidth_required_locals calculate_peak_bandwidth_required_locals; 2454 struct dml2_core_shared_CalculateFlipSchedule_locals CalculateFlipSchedule_locals; 2455 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals rq_dlg_get_dlg_reg_locals; 2456 struct dml2_core_calcs_CalculateStutterEfficiency_locals CalculateStutterEfficiency_locals; 2457 2458 // Scratch space for function params 2459 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params; 2460 struct dml2_core_calcs_CalculateVMRowAndSwath_params CalculateVMRowAndSwath_params; 2461 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params CalculateSwathAndDETConfiguration_params; 2462 struct dml2_core_calcs_CalculateStutterEfficiency_params CalculateStutterEfficiency_params; 2463 struct dml2_core_calcs_CalculatePrefetchSchedule_params CalculatePrefetchSchedule_params; 2464 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params CheckGlobalPrefetchAdmissibility_params; 2465 struct dml2_core_calcs_calculate_mcache_setting_params calculate_mcache_setting_params; 2466 struct dml2_core_calcs_calculate_tdlut_setting_params calculate_tdlut_setting_params; 2467 struct dml2_core_shared_calculate_vm_and_row_bytes_params calculate_vm_and_row_bytes_params; 2468 struct dml2_core_shared_calculate_mcache_setting_locals calculate_mcache_setting_locals; 2469 struct dml2_core_shared_CalculateMetaAndPTETimes_params CalculateMetaAndPTETimes_params; 2470 struct dml2_core_calcs_calculate_peak_bandwidth_required_params calculate_peak_bandwidth_params; 2471 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params calculate_bytes_to_fetch_required_to_hide_latency_params; 2472 struct dml2_core_calcs_calculate_alternate_params calculate_alternate_params; 2473 struct dml2_core_calcs_calculate_alternate_svp_lines calculate_alternate_svp_lines; 2474 struct dml2_core_calcs_calculate_alternate_lead_lines calculate_alternate_lead_lines; 2475 }; 2476 2477 //struct dml2_svp_mode_override; 2478 struct dml2_core_internal_display_mode_lib { 2479 struct dml2_core_ip_params ip; 2480 struct dml2_soc_bb soc; 2481 struct dml2_ip_capabilities ip_caps; 2482 2483 //@brief Mode Support and Mode programming struct 2484 // Used to hold input; intermediate and output of the calculations 2485 struct dml2_core_internal_mode_support ms; // struct for mode support 2486 struct dml2_core_internal_mode_program mp; // struct for mode programming 2487 // Available overridable calculators for core_shared. 2488 // if null, core_shared will use default calculators. 2489 struct dml2_core_shared_calculation_funcs funcs; 2490 2491 struct dml2_core_internal_scratch scratch; 2492 }; 2493 2494 struct dml2_core_calcs_mode_support_ex { 2495 struct dml2_core_internal_display_mode_lib *mode_lib; 2496 const struct dml2_display_cfg *in_display_cfg; 2497 const struct dml2_mcg_min_clock_table *min_clk_table; 2498 int min_clk_index; 2499 const struct dml2_utm_soc_bb *utm_soc_bb; 2500 //unsigned int in_state_index; 2501 struct dml2_core_internal_mode_support_info *out_evaluation_info; 2502 const enum dml2_pstate_method *uclk_pstate_switch_modes; 2503 }; 2504 2505 struct core_display_cfg_support_info; 2506 2507 struct dml2_core_calcs_mode_programming_ex { 2508 struct dml2_core_internal_display_mode_lib *mode_lib; 2509 const struct dml2_display_cfg *in_display_cfg; 2510 const struct dml2_mcg_min_clock_table *min_clk_table; 2511 const struct core_display_cfg_support_info *cfg_support_info; 2512 int min_clk_index; 2513 const struct dml2_uclk_pstate_params *uclk_params; 2514 const struct dml2_display_solution *solution; 2515 const struct dml2_utm_soc_bb *utm_soc_bb; 2516 struct dml2_display_cfg_programming *programming; 2517 }; 2518 2519 #endif 2520