1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare XPCS helpers
5 *
6 * Author: Jose Abreu <Jose.Abreu@synopsys.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/pcs/pcs-xpcs.h>
12 #include <linux/mdio.h>
13 #include <linux/phy.h>
14 #include <linux/phylink.h>
15 #include <linux/property.h>
16
17 #include "pcs-xpcs.h"
18
19 #define phylink_pcs_to_xpcs(pl_pcs) \
20 container_of((pl_pcs), struct dw_xpcs, pcs)
21
22 static const int xpcs_usxgmii_features[] = {
23 ETHTOOL_LINK_MODE_Pause_BIT,
24 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
25 ETHTOOL_LINK_MODE_Autoneg_BIT,
26 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
27 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
28 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
29 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
30 __ETHTOOL_LINK_MODE_MASK_NBITS,
31 };
32
33 static const int xpcs_10gkr_features[] = {
34 ETHTOOL_LINK_MODE_Pause_BIT,
35 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
36 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
37 __ETHTOOL_LINK_MODE_MASK_NBITS,
38 };
39
40 static const int xpcs_xlgmii_features[] = {
41 ETHTOOL_LINK_MODE_Pause_BIT,
42 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
43 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
44 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
45 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
46 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
47 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
48 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
49 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
50 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
51 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
52 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
53 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
54 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
55 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
56 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
57 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
58 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
59 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
60 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
61 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
62 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
63 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
64 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
65 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
66 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
67 __ETHTOOL_LINK_MODE_MASK_NBITS,
68 };
69
70 static const int xpcs_10gbaser_features[] = {
71 ETHTOOL_LINK_MODE_Pause_BIT,
72 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
73 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
74 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
75 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
76 ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
77 __ETHTOOL_LINK_MODE_MASK_NBITS,
78 };
79
80 static const int xpcs_sgmii_features[] = {
81 ETHTOOL_LINK_MODE_Pause_BIT,
82 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
83 ETHTOOL_LINK_MODE_Autoneg_BIT,
84 ETHTOOL_LINK_MODE_10baseT_Half_BIT,
85 ETHTOOL_LINK_MODE_10baseT_Full_BIT,
86 ETHTOOL_LINK_MODE_100baseT_Half_BIT,
87 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
88 ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
89 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
90 __ETHTOOL_LINK_MODE_MASK_NBITS,
91 };
92
93 static const int xpcs_1000basex_features[] = {
94 ETHTOOL_LINK_MODE_Pause_BIT,
95 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
96 ETHTOOL_LINK_MODE_Autoneg_BIT,
97 ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
98 __ETHTOOL_LINK_MODE_MASK_NBITS,
99 };
100
101 static const int xpcs_2500basex_features[] = {
102 ETHTOOL_LINK_MODE_Pause_BIT,
103 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
104 ETHTOOL_LINK_MODE_Autoneg_BIT,
105 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
106 ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
107 __ETHTOOL_LINK_MODE_MASK_NBITS,
108 };
109
110 struct dw_xpcs_compat {
111 phy_interface_t interface;
112 const int *supported;
113 int an_mode;
114 int (*pma_config)(struct dw_xpcs *xpcs);
115 };
116
117 struct dw_xpcs_desc {
118 u32 id;
119 u32 mask;
120 const struct dw_xpcs_compat *compat;
121 };
122
123 static const struct dw_xpcs_compat *
xpcs_find_compat(struct dw_xpcs * xpcs,phy_interface_t interface)124 xpcs_find_compat(struct dw_xpcs *xpcs, phy_interface_t interface)
125 {
126 const struct dw_xpcs_compat *compat;
127
128 for (compat = xpcs->desc->compat; compat->supported; compat++)
129 if (compat->interface == interface)
130 return compat;
131
132 return NULL;
133 }
134
xpcs_to_phylink_pcs(struct dw_xpcs * xpcs)135 struct phylink_pcs *xpcs_to_phylink_pcs(struct dw_xpcs *xpcs)
136 {
137 return &xpcs->pcs;
138 }
139 EXPORT_SYMBOL_GPL(xpcs_to_phylink_pcs);
140
xpcs_get_an_mode(struct dw_xpcs * xpcs,phy_interface_t interface)141 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
142 {
143 const struct dw_xpcs_compat *compat;
144
145 compat = xpcs_find_compat(xpcs, interface);
146 if (!compat)
147 return -ENODEV;
148
149 return compat->an_mode;
150 }
151 EXPORT_SYMBOL_GPL(xpcs_get_an_mode);
152
__xpcs_linkmode_supported(const struct dw_xpcs_compat * compat,enum ethtool_link_mode_bit_indices linkmode)153 static bool __xpcs_linkmode_supported(const struct dw_xpcs_compat *compat,
154 enum ethtool_link_mode_bit_indices linkmode)
155 {
156 int i;
157
158 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
159 if (compat->supported[i] == linkmode)
160 return true;
161
162 return false;
163 }
164
165 #define xpcs_linkmode_supported(compat, mode) \
166 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT)
167
xpcs_read(struct dw_xpcs * xpcs,int dev,u32 reg)168 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
169 {
170 return mdiodev_c45_read(xpcs->mdiodev, dev, reg);
171 }
172
xpcs_write(struct dw_xpcs * xpcs,int dev,u32 reg,u16 val)173 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
174 {
175 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val);
176 }
177
xpcs_modify(struct dw_xpcs * xpcs,int dev,u32 reg,u16 mask,u16 set)178 int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set)
179 {
180 return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set);
181 }
182
xpcs_modify_changed(struct dw_xpcs * xpcs,int dev,u32 reg,u16 mask,u16 set)183 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg,
184 u16 mask, u16 set)
185 {
186 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set);
187 }
188
xpcs_read_vendor(struct dw_xpcs * xpcs,int dev,u32 reg)189 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
190 {
191 return xpcs_read(xpcs, dev, DW_VENDOR | reg);
192 }
193
xpcs_write_vendor(struct dw_xpcs * xpcs,int dev,int reg,u16 val)194 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg,
195 u16 val)
196 {
197 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);
198 }
199
xpcs_modify_vendor(struct dw_xpcs * xpcs,int dev,int reg,u16 mask,u16 set)200 static int xpcs_modify_vendor(struct dw_xpcs *xpcs, int dev, int reg, u16 mask,
201 u16 set)
202 {
203 return xpcs_modify(xpcs, dev, DW_VENDOR | reg, mask, set);
204 }
205
xpcs_read_vpcs(struct dw_xpcs * xpcs,int reg)206 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg)
207 {
208 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg);
209 }
210
xpcs_write_vpcs(struct dw_xpcs * xpcs,int reg,u16 val)211 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val)
212 {
213 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val);
214 }
215
xpcs_modify_vpcs(struct dw_xpcs * xpcs,int reg,u16 mask,u16 val)216 static int xpcs_modify_vpcs(struct dw_xpcs *xpcs, int reg, u16 mask, u16 val)
217 {
218 return xpcs_modify_vendor(xpcs, MDIO_MMD_PCS, reg, mask, val);
219 }
220
xpcs_poll_reset(struct dw_xpcs * xpcs,int dev)221 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
222 {
223 int ret, val;
224
225 ret = read_poll_timeout(xpcs_read, val,
226 val < 0 || !(val & BMCR_RESET),
227 50000, 600000, true, xpcs, dev, MII_BMCR);
228 if (val < 0)
229 ret = val;
230
231 return ret;
232 }
233
xpcs_soft_reset(struct dw_xpcs * xpcs,const struct dw_xpcs_compat * compat)234 static int xpcs_soft_reset(struct dw_xpcs *xpcs,
235 const struct dw_xpcs_compat *compat)
236 {
237 int ret, dev;
238
239 switch (compat->an_mode) {
240 case DW_AN_C73:
241 case DW_10GBASER:
242 dev = MDIO_MMD_PCS;
243 break;
244 case DW_AN_C37_SGMII:
245 case DW_2500BASEX:
246 case DW_AN_C37_1000BASEX:
247 dev = MDIO_MMD_VEND2;
248 break;
249 default:
250 return -EINVAL;
251 }
252
253 ret = xpcs_write(xpcs, dev, MII_BMCR, BMCR_RESET);
254 if (ret < 0)
255 return ret;
256
257 return xpcs_poll_reset(xpcs, dev);
258 }
259
260 #define xpcs_warn(__xpcs, __state, __args...) \
261 ({ \
262 if ((__state)->link) \
263 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \
264 })
265
xpcs_read_fault_c73(struct dw_xpcs * xpcs,struct phylink_link_state * state,u16 pcs_stat1)266 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
267 struct phylink_link_state *state,
268 u16 pcs_stat1)
269 {
270 int ret;
271
272 if (pcs_stat1 & MDIO_STAT1_FAULT) {
273 xpcs_warn(xpcs, state, "Link fault condition detected!\n");
274 return -EFAULT;
275 }
276
277 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2);
278 if (ret < 0)
279 return ret;
280
281 if (ret & MDIO_STAT2_RXFAULT)
282 xpcs_warn(xpcs, state, "Receiver fault detected!\n");
283 if (ret & MDIO_STAT2_TXFAULT)
284 xpcs_warn(xpcs, state, "Transmitter fault detected!\n");
285
286 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS);
287 if (ret < 0)
288 return ret;
289
290 if (ret & DW_RXFIFO_ERR) {
291 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n");
292 return -EFAULT;
293 }
294
295 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
296 if (ret < 0)
297 return ret;
298
299 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK))
300 xpcs_warn(xpcs, state, "Link is not locked!\n");
301
302 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2);
303 if (ret < 0)
304 return ret;
305
306 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) {
307 xpcs_warn(xpcs, state, "Link has errors!\n");
308 return -EFAULT;
309 }
310
311 return 0;
312 }
313
xpcs_link_up_usxgmii(struct dw_xpcs * xpcs,int speed)314 static void xpcs_link_up_usxgmii(struct dw_xpcs *xpcs, int speed)
315 {
316 int ret, speed_sel;
317
318 switch (speed) {
319 case SPEED_10:
320 speed_sel = DW_USXGMII_10;
321 break;
322 case SPEED_100:
323 speed_sel = DW_USXGMII_100;
324 break;
325 case SPEED_1000:
326 speed_sel = DW_USXGMII_1000;
327 break;
328 case SPEED_2500:
329 speed_sel = DW_USXGMII_2500;
330 break;
331 case SPEED_5000:
332 speed_sel = DW_USXGMII_5000;
333 break;
334 case SPEED_10000:
335 speed_sel = DW_USXGMII_10000;
336 break;
337 default:
338 /* Nothing to do here */
339 return;
340 }
341
342 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN);
343 if (ret < 0)
344 goto out;
345
346 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, DW_USXGMII_SS_MASK,
347 speed_sel | DW_USXGMII_FULL);
348 if (ret < 0)
349 goto out;
350
351 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST,
352 DW_USXGMII_RST);
353 if (ret < 0)
354 goto out;
355
356 return;
357
358 out:
359 dev_err(&xpcs->mdiodev->dev, "%s: XPCS access returned %pe\n",
360 __func__, ERR_PTR(ret));
361 }
362
_xpcs_config_aneg_c73(struct dw_xpcs * xpcs,const struct dw_xpcs_compat * compat)363 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
364 const struct dw_xpcs_compat *compat)
365 {
366 int ret, adv;
367
368 /* By default, in USXGMII mode XPCS operates at 10G baud and
369 * replicates data to achieve lower speeds. Hereby, in this
370 * default configuration we need to advertise all supported
371 * modes and not only the ones we want to use.
372 */
373
374 /* SR_AN_ADV3 */
375 adv = 0;
376 if (xpcs_linkmode_supported(compat, 2500baseX_Full))
377 adv |= DW_C73_2500KX;
378
379 /* TODO: 5000baseKR */
380
381 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
382 if (ret < 0)
383 return ret;
384
385 /* SR_AN_ADV2 */
386 adv = 0;
387 if (xpcs_linkmode_supported(compat, 1000baseKX_Full))
388 adv |= DW_C73_1000KX;
389 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full))
390 adv |= DW_C73_10000KX4;
391 if (xpcs_linkmode_supported(compat, 10000baseKR_Full))
392 adv |= DW_C73_10000KR;
393
394 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
395 if (ret < 0)
396 return ret;
397
398 /* SR_AN_ADV1 */
399 adv = DW_C73_AN_ADV_SF;
400 if (xpcs_linkmode_supported(compat, Pause))
401 adv |= DW_C73_PAUSE;
402 if (xpcs_linkmode_supported(compat, Asym_Pause))
403 adv |= DW_C73_ASYM_PAUSE;
404
405 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
406 }
407
xpcs_config_aneg_c73(struct dw_xpcs * xpcs,const struct dw_xpcs_compat * compat)408 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
409 const struct dw_xpcs_compat *compat)
410 {
411 int ret;
412
413 ret = _xpcs_config_aneg_c73(xpcs, compat);
414 if (ret < 0)
415 return ret;
416
417 return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1,
418 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART,
419 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
420 }
421
xpcs_aneg_done_c73(struct dw_xpcs * xpcs,struct phylink_link_state * state,const struct dw_xpcs_compat * compat,u16 an_stat1)422 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
423 struct phylink_link_state *state,
424 const struct dw_xpcs_compat *compat, u16 an_stat1)
425 {
426 int ret;
427
428 if (an_stat1 & MDIO_AN_STAT1_COMPLETE) {
429 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA);
430 if (ret < 0)
431 return ret;
432
433 /* Check if Aneg outcome is valid */
434 if (!(ret & DW_C73_AN_ADV_SF)) {
435 xpcs_config_aneg_c73(xpcs, compat);
436 return 0;
437 }
438
439 return 1;
440 }
441
442 return 0;
443 }
444
xpcs_read_lpa_c73(struct dw_xpcs * xpcs,struct phylink_link_state * state,u16 an_stat1)445 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
446 struct phylink_link_state *state, u16 an_stat1)
447 {
448 u16 lpa[3];
449 int i, ret;
450
451 if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) {
452 phylink_clear(state->lp_advertising, Autoneg);
453 return 0;
454 }
455
456 phylink_set(state->lp_advertising, Autoneg);
457
458 /* Read Clause 73 link partner advertisement */
459 for (i = ARRAY_SIZE(lpa); --i >= 0; ) {
460 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i);
461 if (ret < 0)
462 return ret;
463
464 lpa[i] = ret;
465 }
466
467 mii_c73_mod_linkmode(state->lp_advertising, lpa);
468
469 return 0;
470 }
471
xpcs_get_max_xlgmii_speed(struct dw_xpcs * xpcs,struct phylink_link_state * state)472 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
473 struct phylink_link_state *state)
474 {
475 unsigned long *adv = state->advertising;
476 int speed = SPEED_UNKNOWN;
477 int bit;
478
479 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) {
480 int new_speed = SPEED_UNKNOWN;
481
482 switch (bit) {
483 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
484 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
485 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
486 new_speed = SPEED_25000;
487 break;
488 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
489 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
490 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
491 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
492 new_speed = SPEED_40000;
493 break;
494 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT:
495 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT:
496 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT:
497 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
498 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
499 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
500 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
501 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT:
502 new_speed = SPEED_50000;
503 break;
504 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
505 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
506 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
507 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
508 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT:
509 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT:
510 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT:
511 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT:
512 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT:
513 new_speed = SPEED_100000;
514 break;
515 default:
516 continue;
517 }
518
519 if (new_speed > speed)
520 speed = new_speed;
521 }
522
523 return speed;
524 }
525
xpcs_resolve_pma(struct dw_xpcs * xpcs,struct phylink_link_state * state)526 static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
527 struct phylink_link_state *state)
528 {
529 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
530 state->duplex = DUPLEX_FULL;
531
532 switch (state->interface) {
533 case PHY_INTERFACE_MODE_10GKR:
534 state->speed = SPEED_10000;
535 break;
536 case PHY_INTERFACE_MODE_XLGMII:
537 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
538 break;
539 default:
540 state->speed = SPEED_UNKNOWN;
541 break;
542 }
543 }
544
xpcs_validate(struct phylink_pcs * pcs,unsigned long * supported,const struct phylink_link_state * state)545 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported,
546 const struct phylink_link_state *state)
547 {
548 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, };
549 const struct dw_xpcs_compat *compat;
550 struct dw_xpcs *xpcs;
551 int i;
552
553 xpcs = phylink_pcs_to_xpcs(pcs);
554 compat = xpcs_find_compat(xpcs, state->interface);
555 if (!compat)
556 return -EINVAL;
557
558 /* Populate the supported link modes for this PHY interface type.
559 * FIXME: what about the port modes and autoneg bit? This masks
560 * all those away.
561 */
562 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
563 set_bit(compat->supported[i], xpcs_supported);
564
565 linkmode_and(supported, supported, xpcs_supported);
566
567 return 0;
568 }
569
xpcs_inband_caps(struct phylink_pcs * pcs,phy_interface_t interface)570 static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs,
571 phy_interface_t interface)
572 {
573 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
574 const struct dw_xpcs_compat *compat;
575
576 compat = xpcs_find_compat(xpcs, interface);
577 if (!compat)
578 return 0;
579
580 switch (compat->an_mode) {
581 case DW_AN_C73:
582 return LINK_INBAND_ENABLE;
583
584 case DW_AN_C37_SGMII:
585 case DW_AN_C37_1000BASEX:
586 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
587
588 case DW_10GBASER:
589 case DW_2500BASEX:
590 return LINK_INBAND_DISABLE;
591
592 default:
593 return 0;
594 }
595 }
596
xpcs_get_interfaces(struct dw_xpcs * xpcs,unsigned long * interfaces)597 static void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces)
598 {
599 const struct dw_xpcs_compat *compat;
600
601 for (compat = xpcs->desc->compat; compat->supported; compat++)
602 __set_bit(compat->interface, interfaces);
603 }
604
xpcs_config_eee(struct dw_xpcs * xpcs,int mult_fact_100ns,int enable)605 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
606 {
607 u16 mask, val;
608 int ret;
609
610 mask = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
611 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
612 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
613 DW_VR_MII_EEE_MULT_FACT_100NS;
614
615 if (enable)
616 val = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
617 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
618 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
619 FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS,
620 mult_fact_100ns);
621 else
622 val = 0;
623
624 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, mask,
625 val);
626 if (ret < 0)
627 return ret;
628
629 return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1,
630 DW_VR_MII_EEE_TRN_LPI,
631 enable ? DW_VR_MII_EEE_TRN_LPI : 0);
632 }
633 EXPORT_SYMBOL_GPL(xpcs_config_eee);
634
xpcs_pre_config(struct phylink_pcs * pcs,phy_interface_t interface)635 static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface)
636 {
637 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
638 const struct dw_xpcs_compat *compat;
639 int ret;
640
641 if (!xpcs->need_reset)
642 return;
643
644 compat = xpcs_find_compat(xpcs, interface);
645 if (!compat) {
646 dev_err(&xpcs->mdiodev->dev, "unsupported interface %s\n",
647 phy_modes(interface));
648 return;
649 }
650
651 ret = xpcs_soft_reset(xpcs, compat);
652 if (ret)
653 dev_err(&xpcs->mdiodev->dev, "soft reset failed: %pe\n",
654 ERR_PTR(ret));
655
656 xpcs->need_reset = false;
657 }
658
xpcs_config_aneg_c37_sgmii(struct dw_xpcs * xpcs,unsigned int neg_mode)659 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
660 unsigned int neg_mode)
661 {
662 int ret, mdio_ctrl, tx_conf;
663 u16 mask, val;
664
665 /* For AN for C37 SGMII mode, the settings are :-
666 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case
667 it is already enabled)
668 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN)
669 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII)
670 * DW xPCS used with DW EQoS MAC is always MAC side SGMII.
671 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic
672 * speed/duplex mode change by HW after SGMII AN complete)
673 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN)
674 *
675 * Note that VR_MII_MMD_CTRL is MII_BMCR.
676 *
677 * Note: Since it is MAC side SGMII, there is no need to set
678 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from
679 * PHY about the link state change after C28 AN is completed
680 * between PHY and Link Partner. There is also no need to
681 * trigger AN restart for MAC-side SGMII.
682 */
683 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR);
684 if (mdio_ctrl < 0)
685 return mdio_ctrl;
686
687 if (mdio_ctrl & BMCR_ANENABLE) {
688 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
689 mdio_ctrl & ~BMCR_ANENABLE);
690 if (ret < 0)
691 return ret;
692 }
693
694 mask = DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK;
695 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK,
696 DW_VR_MII_PCS_MODE_C37_SGMII);
697
698 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
699 mask |= DW_VR_MII_AN_CTRL_8BIT;
700 val |= DW_VR_MII_AN_CTRL_8BIT;
701 /* Hardware requires it to be PHY side SGMII */
702 tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII;
703 } else {
704 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII;
705 }
706
707 val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf);
708
709 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val);
710 if (ret < 0)
711 return ret;
712
713 val = 0;
714 mask = DW_VR_MII_DIG_CTRL1_2G5_EN | DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
715
716 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
717 val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
718
719 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
720 mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
721 val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
722 }
723
724 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val);
725 if (ret < 0)
726 return ret;
727
728 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
729 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
730 mdio_ctrl | BMCR_ANENABLE);
731
732 return ret;
733 }
734
xpcs_config_aneg_c37_1000basex(struct dw_xpcs * xpcs,unsigned int neg_mode,const unsigned long * advertising)735 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs,
736 unsigned int neg_mode,
737 const unsigned long *advertising)
738 {
739 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX;
740 int ret, mdio_ctrl, adv;
741 bool changed = 0;
742 u16 mask, val;
743
744 /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must
745 * be disabled first:-
746 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b
747 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37)
748 *
749 * Note that VR_MII_MMD_CTRL is MII_BMCR.
750 */
751 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR);
752 if (mdio_ctrl < 0)
753 return mdio_ctrl;
754
755 if (mdio_ctrl & BMCR_ANENABLE) {
756 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
757 mdio_ctrl & ~BMCR_ANENABLE);
758 if (ret < 0)
759 return ret;
760 }
761
762 mask = DW_VR_MII_PCS_MODE_MASK;
763 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK,
764 DW_VR_MII_PCS_MODE_C37_1000BASEX);
765
766 if (!xpcs->pcs.poll) {
767 mask |= DW_VR_MII_AN_INTR_EN;
768 val |= DW_VR_MII_AN_INTR_EN;
769 }
770
771 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val);
772 if (ret < 0)
773 return ret;
774
775 /* Check for advertising changes and update the C45 MII ADV
776 * register accordingly.
777 */
778 adv = phylink_mii_c22_pcs_encode_advertisement(interface,
779 advertising);
780 if (adv >= 0) {
781 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2,
782 MII_ADVERTISE, 0xffff, adv);
783 if (ret < 0)
784 return ret;
785
786 changed = ret;
787 }
788
789 /* Clear CL37 AN complete status */
790 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
791 if (ret < 0)
792 return ret;
793
794 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
795 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
796 mdio_ctrl | BMCR_ANENABLE);
797 if (ret < 0)
798 return ret;
799 }
800
801 return changed;
802 }
803
xpcs_config_2500basex(struct dw_xpcs * xpcs)804 static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
805 {
806 int ret;
807
808 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1,
809 DW_VR_MII_DIG_CTRL1_2G5_EN |
810 DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW,
811 DW_VR_MII_DIG_CTRL1_2G5_EN);
812 if (ret < 0)
813 return ret;
814
815 return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR,
816 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_SPEED100,
817 BMCR_SPEED1000);
818 }
819
xpcs_do_config(struct dw_xpcs * xpcs,phy_interface_t interface,const unsigned long * advertising,unsigned int neg_mode)820 static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
821 const unsigned long *advertising,
822 unsigned int neg_mode)
823 {
824 const struct dw_xpcs_compat *compat;
825 int ret;
826
827 compat = xpcs_find_compat(xpcs, interface);
828 if (!compat)
829 return -ENODEV;
830
831 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) {
832 ret = txgbe_xpcs_switch_mode(xpcs, interface);
833 if (ret)
834 return ret;
835
836 /* Wangxun devices need backplane CL37 AN enabled for
837 * SGMII and 1000base-X
838 */
839 if (interface == PHY_INTERFACE_MODE_SGMII ||
840 interface == PHY_INTERFACE_MODE_1000BASEX)
841 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1,
842 DW_CL37_BP | DW_EN_VSMMD1);
843 }
844
845 switch (compat->an_mode) {
846 case DW_10GBASER:
847 break;
848 case DW_AN_C73:
849 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
850 ret = xpcs_config_aneg_c73(xpcs, compat);
851 if (ret)
852 return ret;
853 }
854 break;
855 case DW_AN_C37_SGMII:
856 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode);
857 if (ret)
858 return ret;
859 break;
860 case DW_AN_C37_1000BASEX:
861 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode,
862 advertising);
863 if (ret)
864 return ret;
865 break;
866 case DW_2500BASEX:
867 ret = xpcs_config_2500basex(xpcs);
868 if (ret)
869 return ret;
870 break;
871 default:
872 return -EINVAL;
873 }
874
875 if (compat->pma_config) {
876 ret = compat->pma_config(xpcs);
877 if (ret)
878 return ret;
879 }
880
881 return 0;
882 }
883
xpcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)884 static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
885 phy_interface_t interface,
886 const unsigned long *advertising,
887 bool permit_pause_to_mac)
888 {
889 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
890
891 return xpcs_do_config(xpcs, interface, advertising, neg_mode);
892 }
893
xpcs_get_state_c73(struct dw_xpcs * xpcs,struct phylink_link_state * state,const struct dw_xpcs_compat * compat)894 static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
895 struct phylink_link_state *state,
896 const struct dw_xpcs_compat *compat)
897 {
898 bool an_enabled;
899 int pcs_stat1;
900 int an_stat1;
901 int ret;
902
903 /* The link status bit is latching-low, so it is important to
904 * avoid unnecessary re-reads of this register to avoid missing
905 * a link-down event.
906 */
907 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
908 if (pcs_stat1 < 0) {
909 state->link = false;
910 return pcs_stat1;
911 }
912
913 /* Link needs to be read first ... */
914 state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS);
915
916 /* ... and then we check the faults. */
917 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1);
918 if (ret) {
919 ret = xpcs_soft_reset(xpcs, compat);
920 if (ret)
921 return ret;
922
923 state->link = 0;
924
925 return xpcs_do_config(xpcs, state->interface, NULL,
926 PHYLINK_PCS_NEG_INBAND_ENABLED);
927 }
928
929 /* There is no point doing anything else if the link is down. */
930 if (!state->link)
931 return 0;
932
933 an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
934 state->advertising);
935 if (an_enabled) {
936 /* The link status bit is latching-low, so it is important to
937 * avoid unnecessary re-reads of this register to avoid missing
938 * a link-down event.
939 */
940 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
941 if (an_stat1 < 0) {
942 state->link = false;
943 return an_stat1;
944 }
945
946 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat,
947 an_stat1);
948 if (!state->an_complete) {
949 state->link = false;
950 return 0;
951 }
952
953 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1);
954 if (ret < 0) {
955 state->link = false;
956 return ret;
957 }
958
959 phylink_resolve_c73(state);
960 } else {
961 xpcs_resolve_pma(xpcs, state);
962 }
963
964 return 0;
965 }
966
xpcs_get_state_c37_sgmii(struct dw_xpcs * xpcs,struct phylink_link_state * state)967 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
968 struct phylink_link_state *state)
969 {
970 int ret;
971
972 /* Reset link_state */
973 state->link = false;
974 state->speed = SPEED_UNKNOWN;
975 state->duplex = DUPLEX_UNKNOWN;
976 state->pause = 0;
977
978 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link
979 * status, speed and duplex.
980 */
981 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
982 if (ret < 0)
983 return ret;
984
985 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) {
986 int speed_value;
987
988 state->link = true;
989
990 speed_value = FIELD_GET(DW_VR_MII_AN_STS_C37_ANSGM_SP, ret);
991 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000)
992 state->speed = SPEED_1000;
993 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)
994 state->speed = SPEED_100;
995 else
996 state->speed = SPEED_10;
997
998 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD)
999 state->duplex = DUPLEX_FULL;
1000 else
1001 state->duplex = DUPLEX_HALF;
1002 } else if (ret == DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) {
1003 int speed, duplex;
1004
1005 state->link = true;
1006
1007 speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR);
1008 if (speed < 0)
1009 return speed;
1010
1011 speed &= BMCR_SPEED100 | BMCR_SPEED1000;
1012 if (speed == BMCR_SPEED1000)
1013 state->speed = SPEED_1000;
1014 else if (speed == BMCR_SPEED100)
1015 state->speed = SPEED_100;
1016 else if (speed == 0)
1017 state->speed = SPEED_10;
1018
1019 duplex = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
1020 if (duplex < 0)
1021 return duplex;
1022
1023 if (duplex & ADVERTISE_1000XFULL)
1024 state->duplex = DUPLEX_FULL;
1025 else if (duplex & ADVERTISE_1000XHALF)
1026 state->duplex = DUPLEX_HALF;
1027
1028 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
1029 }
1030
1031 return 0;
1032 }
1033
xpcs_get_state_c37_1000basex(struct dw_xpcs * xpcs,unsigned int neg_mode,struct phylink_link_state * state)1034 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
1035 unsigned int neg_mode,
1036 struct phylink_link_state *state)
1037 {
1038 int lpa, bmsr;
1039
1040 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
1041 state->advertising)) {
1042 /* Reset link state */
1043 state->link = false;
1044
1045 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
1046 if (lpa < 0 || lpa & LPA_RFAULT)
1047 return lpa;
1048
1049 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR);
1050 if (bmsr < 0)
1051 return bmsr;
1052
1053 /* Clear AN complete interrupt */
1054 if (!xpcs->pcs.poll) {
1055 int an_intr;
1056
1057 an_intr = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
1058 if (an_intr & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) {
1059 an_intr &= ~DW_VR_MII_AN_STS_C37_ANCMPLT_INTR;
1060 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, an_intr);
1061 }
1062 }
1063
1064 phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);
1065 }
1066
1067 return 0;
1068 }
1069
xpcs_get_state_2500basex(struct dw_xpcs * xpcs,struct phylink_link_state * state)1070 static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs,
1071 struct phylink_link_state *state)
1072 {
1073 int ret;
1074
1075 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR);
1076 if (ret < 0) {
1077 state->link = 0;
1078 return ret;
1079 }
1080
1081 state->link = !!(ret & BMSR_LSTATUS);
1082 if (!state->link)
1083 return 0;
1084
1085 state->speed = SPEED_2500;
1086 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX;
1087 state->duplex = DUPLEX_FULL;
1088
1089 return 0;
1090 }
1091
xpcs_get_state(struct phylink_pcs * pcs,unsigned int neg_mode,struct phylink_link_state * state)1092 static void xpcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,
1093 struct phylink_link_state *state)
1094 {
1095 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1096 const struct dw_xpcs_compat *compat;
1097 int ret;
1098
1099 compat = xpcs_find_compat(xpcs, state->interface);
1100 if (!compat)
1101 return;
1102
1103 switch (compat->an_mode) {
1104 case DW_10GBASER:
1105 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state);
1106 break;
1107 case DW_AN_C73:
1108 ret = xpcs_get_state_c73(xpcs, state, compat);
1109 if (ret)
1110 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n",
1111 "xpcs_get_state_c73", ERR_PTR(ret));
1112 break;
1113 case DW_AN_C37_SGMII:
1114 ret = xpcs_get_state_c37_sgmii(xpcs, state);
1115 if (ret)
1116 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n",
1117 "xpcs_get_state_c37_sgmii", ERR_PTR(ret));
1118 break;
1119 case DW_AN_C37_1000BASEX:
1120 ret = xpcs_get_state_c37_1000basex(xpcs, neg_mode, state);
1121 if (ret)
1122 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n",
1123 "xpcs_get_state_c37_1000basex", ERR_PTR(ret));
1124 break;
1125 case DW_2500BASEX:
1126 ret = xpcs_get_state_2500basex(xpcs, state);
1127 if (ret)
1128 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n",
1129 "xpcs_get_state_2500basex", ERR_PTR(ret));
1130 break;
1131 default:
1132 return;
1133 }
1134 }
1135
xpcs_link_up_sgmii_1000basex(struct dw_xpcs * xpcs,unsigned int neg_mode,phy_interface_t interface,int speed,int duplex)1136 static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs,
1137 unsigned int neg_mode,
1138 phy_interface_t interface,
1139 int speed, int duplex)
1140 {
1141 int ret;
1142
1143 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
1144 return;
1145
1146 if (interface == PHY_INTERFACE_MODE_1000BASEX) {
1147 if (speed != SPEED_1000) {
1148 dev_err(&xpcs->mdiodev->dev,
1149 "%s: speed %dMbps not supported\n",
1150 __func__, speed);
1151 return;
1152 }
1153
1154 if (duplex != DUPLEX_FULL)
1155 dev_err(&xpcs->mdiodev->dev,
1156 "%s: half duplex not supported\n",
1157 __func__);
1158 }
1159
1160 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
1161 mii_bmcr_encode_fixed(speed, duplex));
1162 if (ret)
1163 dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n",
1164 __func__, ERR_PTR(ret));
1165 }
1166
xpcs_link_up(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,int speed,int duplex)1167 static void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
1168 phy_interface_t interface, int speed, int duplex)
1169 {
1170 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1171
1172 switch (interface) {
1173 case PHY_INTERFACE_MODE_USXGMII:
1174 xpcs_link_up_usxgmii(xpcs, speed);
1175 break;
1176
1177 case PHY_INTERFACE_MODE_SGMII:
1178 case PHY_INTERFACE_MODE_1000BASEX:
1179 xpcs_link_up_sgmii_1000basex(xpcs, neg_mode, interface, speed,
1180 duplex);
1181 break;
1182
1183 default:
1184 break;
1185 }
1186 }
1187
xpcs_an_restart(struct phylink_pcs * pcs)1188 static void xpcs_an_restart(struct phylink_pcs *pcs)
1189 {
1190 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1191
1192 xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART,
1193 BMCR_ANRESTART);
1194 }
1195
xpcs_read_ids(struct dw_xpcs * xpcs)1196 static int xpcs_read_ids(struct dw_xpcs *xpcs)
1197 {
1198 int ret;
1199 u32 id;
1200
1201 /* First, search C73 PCS using PCS MMD 3. Return ENODEV if communication
1202 * failed indicating that device couldn't be reached.
1203 */
1204 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1);
1205 if (ret < 0)
1206 return -ENODEV;
1207
1208 id = ret << 16;
1209
1210 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2);
1211 if (ret < 0)
1212 return ret;
1213
1214 id |= ret;
1215
1216 /* If Device IDs are not all zeros or ones, then 10GBase-X/R or C73
1217 * KR/KX4 PCS found. Otherwise fallback to detecting 1000Base-X or C37
1218 * PCS in MII MMD 31.
1219 */
1220 if (!id || id == 0xffffffff) {
1221 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1);
1222 if (ret < 0)
1223 return ret;
1224
1225 id = ret << 16;
1226
1227 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2);
1228 if (ret < 0)
1229 return ret;
1230
1231 id |= ret;
1232 }
1233
1234 /* Set the PCS ID if it hasn't been pre-initialized */
1235 if (xpcs->info.pcs == DW_XPCS_ID_NATIVE)
1236 xpcs->info.pcs = id;
1237
1238 /* Find out PMA/PMD ID from MMD 1 device ID registers */
1239 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1);
1240 if (ret < 0)
1241 return ret;
1242
1243 id = ret;
1244
1245 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2);
1246 if (ret < 0)
1247 return ret;
1248
1249 /* Note the inverted dword order and masked out Model/Revision numbers
1250 * with respect to what is done with the PCS ID...
1251 */
1252 ret = (ret >> 10) & 0x3F;
1253 id |= ret << 16;
1254
1255 /* Set the PMA ID if it hasn't been pre-initialized */
1256 if (xpcs->info.pma == DW_XPCS_PMA_ID_NATIVE)
1257 xpcs->info.pma = id;
1258
1259 return 0;
1260 }
1261
1262 static const struct dw_xpcs_compat synopsys_xpcs_compat[] = {
1263 {
1264 .interface = PHY_INTERFACE_MODE_USXGMII,
1265 .supported = xpcs_usxgmii_features,
1266 .an_mode = DW_AN_C73,
1267 }, {
1268 .interface = PHY_INTERFACE_MODE_10GKR,
1269 .supported = xpcs_10gkr_features,
1270 .an_mode = DW_AN_C73,
1271 }, {
1272 .interface = PHY_INTERFACE_MODE_XLGMII,
1273 .supported = xpcs_xlgmii_features,
1274 .an_mode = DW_AN_C73,
1275 }, {
1276 .interface = PHY_INTERFACE_MODE_10GBASER,
1277 .supported = xpcs_10gbaser_features,
1278 .an_mode = DW_10GBASER,
1279 }, {
1280 .interface = PHY_INTERFACE_MODE_SGMII,
1281 .supported = xpcs_sgmii_features,
1282 .an_mode = DW_AN_C37_SGMII,
1283 }, {
1284 .interface = PHY_INTERFACE_MODE_1000BASEX,
1285 .supported = xpcs_1000basex_features,
1286 .an_mode = DW_AN_C37_1000BASEX,
1287 }, {
1288 .interface = PHY_INTERFACE_MODE_2500BASEX,
1289 .supported = xpcs_2500basex_features,
1290 .an_mode = DW_2500BASEX,
1291 }, {
1292 }
1293 };
1294
1295 static const struct dw_xpcs_compat nxp_sja1105_xpcs_compat[] = {
1296 {
1297 .interface = PHY_INTERFACE_MODE_SGMII,
1298 .supported = xpcs_sgmii_features,
1299 .an_mode = DW_AN_C37_SGMII,
1300 .pma_config = nxp_sja1105_sgmii_pma_config,
1301 }, {
1302 }
1303 };
1304
1305 static const struct dw_xpcs_compat nxp_sja1110_xpcs_compat[] = {
1306 {
1307 .interface = PHY_INTERFACE_MODE_SGMII,
1308 .supported = xpcs_sgmii_features,
1309 .an_mode = DW_AN_C37_SGMII,
1310 .pma_config = nxp_sja1110_sgmii_pma_config,
1311 }, {
1312 .interface = PHY_INTERFACE_MODE_2500BASEX,
1313 .supported = xpcs_2500basex_features,
1314 .an_mode = DW_2500BASEX,
1315 .pma_config = nxp_sja1110_2500basex_pma_config,
1316 }, {
1317 }
1318 };
1319
1320 static const struct dw_xpcs_desc xpcs_desc_list[] = {
1321 {
1322 .id = DW_XPCS_ID,
1323 .mask = DW_XPCS_ID_MASK,
1324 .compat = synopsys_xpcs_compat,
1325 }, {
1326 .id = NXP_SJA1105_XPCS_ID,
1327 .mask = DW_XPCS_ID_MASK,
1328 .compat = nxp_sja1105_xpcs_compat,
1329 }, {
1330 .id = NXP_SJA1110_XPCS_ID,
1331 .mask = DW_XPCS_ID_MASK,
1332 .compat = nxp_sja1110_xpcs_compat,
1333 },
1334 };
1335
1336 static const struct phylink_pcs_ops xpcs_phylink_ops = {
1337 .pcs_validate = xpcs_validate,
1338 .pcs_inband_caps = xpcs_inband_caps,
1339 .pcs_pre_config = xpcs_pre_config,
1340 .pcs_config = xpcs_config,
1341 .pcs_get_state = xpcs_get_state,
1342 .pcs_an_restart = xpcs_an_restart,
1343 .pcs_link_up = xpcs_link_up,
1344 };
1345
xpcs_identify(struct dw_xpcs * xpcs)1346 static int xpcs_identify(struct dw_xpcs *xpcs)
1347 {
1348 int i, ret;
1349
1350 ret = xpcs_read_ids(xpcs);
1351 if (ret < 0)
1352 return ret;
1353
1354 for (i = 0; i < ARRAY_SIZE(xpcs_desc_list); i++) {
1355 const struct dw_xpcs_desc *entry = &xpcs_desc_list[i];
1356
1357 if ((xpcs->info.pcs & entry->mask) == entry->id) {
1358 xpcs->desc = entry;
1359 return 0;
1360 }
1361 }
1362
1363 return -ENODEV;
1364 }
1365
xpcs_create_data(struct mdio_device * mdiodev)1366 static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev)
1367 {
1368 struct dw_xpcs *xpcs;
1369
1370 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL);
1371 if (!xpcs)
1372 return ERR_PTR(-ENOMEM);
1373
1374 mdio_device_get(mdiodev);
1375 xpcs->mdiodev = mdiodev;
1376 xpcs->pcs.ops = &xpcs_phylink_ops;
1377 xpcs->pcs.neg_mode = true;
1378 xpcs->pcs.poll = true;
1379
1380 return xpcs;
1381 }
1382
xpcs_free_data(struct dw_xpcs * xpcs)1383 static void xpcs_free_data(struct dw_xpcs *xpcs)
1384 {
1385 mdio_device_put(xpcs->mdiodev);
1386 kfree(xpcs);
1387 }
1388
xpcs_init_clks(struct dw_xpcs * xpcs)1389 static int xpcs_init_clks(struct dw_xpcs *xpcs)
1390 {
1391 static const char *ids[DW_XPCS_NUM_CLKS] = {
1392 [DW_XPCS_CORE_CLK] = "core",
1393 [DW_XPCS_PAD_CLK] = "pad",
1394 };
1395 struct device *dev = &xpcs->mdiodev->dev;
1396 int ret, i;
1397
1398 for (i = 0; i < DW_XPCS_NUM_CLKS; ++i)
1399 xpcs->clks[i].id = ids[i];
1400
1401 ret = clk_bulk_get_optional(dev, DW_XPCS_NUM_CLKS, xpcs->clks);
1402 if (ret)
1403 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1404
1405 ret = clk_bulk_prepare_enable(DW_XPCS_NUM_CLKS, xpcs->clks);
1406 if (ret)
1407 return dev_err_probe(dev, ret, "Failed to enable clocks\n");
1408
1409 return 0;
1410 }
1411
xpcs_clear_clks(struct dw_xpcs * xpcs)1412 static void xpcs_clear_clks(struct dw_xpcs *xpcs)
1413 {
1414 clk_bulk_disable_unprepare(DW_XPCS_NUM_CLKS, xpcs->clks);
1415
1416 clk_bulk_put(DW_XPCS_NUM_CLKS, xpcs->clks);
1417 }
1418
xpcs_init_id(struct dw_xpcs * xpcs)1419 static int xpcs_init_id(struct dw_xpcs *xpcs)
1420 {
1421 const struct dw_xpcs_info *info;
1422
1423 info = dev_get_platdata(&xpcs->mdiodev->dev);
1424 if (!info) {
1425 xpcs->info.pcs = DW_XPCS_ID_NATIVE;
1426 xpcs->info.pma = DW_XPCS_PMA_ID_NATIVE;
1427 } else {
1428 xpcs->info = *info;
1429 }
1430
1431 return xpcs_identify(xpcs);
1432 }
1433
xpcs_create(struct mdio_device * mdiodev)1434 static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev)
1435 {
1436 struct dw_xpcs *xpcs;
1437 int ret;
1438
1439 xpcs = xpcs_create_data(mdiodev);
1440 if (IS_ERR(xpcs))
1441 return xpcs;
1442
1443 ret = xpcs_init_clks(xpcs);
1444 if (ret)
1445 goto out_free_data;
1446
1447 ret = xpcs_init_id(xpcs);
1448 if (ret)
1449 goto out_clear_clks;
1450
1451 xpcs_get_interfaces(xpcs, xpcs->pcs.supported_interfaces);
1452
1453 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID)
1454 xpcs->pcs.poll = false;
1455 else
1456 xpcs->need_reset = true;
1457
1458 return xpcs;
1459
1460 out_clear_clks:
1461 xpcs_clear_clks(xpcs);
1462
1463 out_free_data:
1464 xpcs_free_data(xpcs);
1465
1466 return ERR_PTR(ret);
1467 }
1468
1469 /**
1470 * xpcs_create_mdiodev() - create a DW xPCS instance with the MDIO @addr
1471 * @bus: pointer to the MDIO-bus descriptor for the device to be looked at
1472 * @addr: device MDIO-bus ID
1473 *
1474 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if
1475 * the PCS device couldn't be found on the bus and other negative errno related
1476 * to the data allocation and MDIO-bus communications.
1477 */
xpcs_create_mdiodev(struct mii_bus * bus,int addr)1478 struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr)
1479 {
1480 struct mdio_device *mdiodev;
1481 struct dw_xpcs *xpcs;
1482
1483 mdiodev = mdio_device_create(bus, addr);
1484 if (IS_ERR(mdiodev))
1485 return ERR_CAST(mdiodev);
1486
1487 xpcs = xpcs_create(mdiodev);
1488
1489 /* xpcs_create() has taken a refcount on the mdiodev if it was
1490 * successful. If xpcs_create() fails, this will free the mdio
1491 * device here. In any case, we don't need to hold our reference
1492 * anymore, and putting it here will allow mdio_device_put() in
1493 * xpcs_destroy() to automatically free the mdio device.
1494 */
1495 mdio_device_put(mdiodev);
1496
1497 return xpcs;
1498 }
1499 EXPORT_SYMBOL_GPL(xpcs_create_mdiodev);
1500
xpcs_create_pcs_mdiodev(struct mii_bus * bus,int addr)1501 struct phylink_pcs *xpcs_create_pcs_mdiodev(struct mii_bus *bus, int addr)
1502 {
1503 struct dw_xpcs *xpcs;
1504
1505 xpcs = xpcs_create_mdiodev(bus, addr);
1506 if (IS_ERR(xpcs))
1507 return ERR_CAST(xpcs);
1508
1509 return &xpcs->pcs;
1510 }
1511 EXPORT_SYMBOL_GPL(xpcs_create_pcs_mdiodev);
1512
1513 /**
1514 * xpcs_create_fwnode() - Create a DW xPCS instance from @fwnode
1515 * @fwnode: fwnode handle poining to the DW XPCS device
1516 *
1517 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if
1518 * the fwnode device is unavailable or the PCS device couldn't be found on the
1519 * bus, -EPROBE_DEFER if the respective MDIO-device instance couldn't be found,
1520 * other negative errno related to the data allocations and MDIO-bus
1521 * communications.
1522 */
xpcs_create_fwnode(struct fwnode_handle * fwnode)1523 struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode)
1524 {
1525 struct mdio_device *mdiodev;
1526 struct dw_xpcs *xpcs;
1527
1528 if (!fwnode_device_is_available(fwnode))
1529 return ERR_PTR(-ENODEV);
1530
1531 mdiodev = fwnode_mdio_find_device(fwnode);
1532 if (!mdiodev)
1533 return ERR_PTR(-EPROBE_DEFER);
1534
1535 xpcs = xpcs_create(mdiodev);
1536
1537 /* xpcs_create() has taken a refcount on the mdiodev if it was
1538 * successful. If xpcs_create() fails, this will free the mdio
1539 * device here. In any case, we don't need to hold our reference
1540 * anymore, and putting it here will allow mdio_device_put() in
1541 * xpcs_destroy() to automatically free the mdio device.
1542 */
1543 mdio_device_put(mdiodev);
1544
1545 return xpcs;
1546 }
1547 EXPORT_SYMBOL_GPL(xpcs_create_fwnode);
1548
xpcs_destroy(struct dw_xpcs * xpcs)1549 void xpcs_destroy(struct dw_xpcs *xpcs)
1550 {
1551 if (!xpcs)
1552 return;
1553
1554 xpcs_clear_clks(xpcs);
1555
1556 xpcs_free_data(xpcs);
1557 }
1558 EXPORT_SYMBOL_GPL(xpcs_destroy);
1559
xpcs_destroy_pcs(struct phylink_pcs * pcs)1560 void xpcs_destroy_pcs(struct phylink_pcs *pcs)
1561 {
1562 xpcs_destroy(phylink_pcs_to_xpcs(pcs));
1563 }
1564 EXPORT_SYMBOL_GPL(xpcs_destroy_pcs);
1565
1566 MODULE_DESCRIPTION("Synopsys DesignWare XPCS library");
1567 MODULE_LICENSE("GPL v2");
1568