1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Core of Xen paravirt_ops implementation. 4 * 5 * This file contains the xen_paravirt_ops structure itself, and the 6 * implementations for: 7 * - privileged instructions 8 * - interrupt flags 9 * - segment operations 10 * - booting and setup 11 * 12 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 13 */ 14 15 #include <linux/cpu.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/smp.h> 19 #include <linux/preempt.h> 20 #include <linux/hardirq.h> 21 #include <linux/percpu.h> 22 #include <linux/delay.h> 23 #include <linux/start_kernel.h> 24 #include <linux/sched.h> 25 #include <linux/kprobes.h> 26 #include <linux/kstrtox.h> 27 #include <linux/memblock.h> 28 #include <linux/export.h> 29 #include <linux/mm.h> 30 #include <linux/page-flags.h> 31 #include <linux/pci.h> 32 #include <linux/gfp.h> 33 #include <linux/edd.h> 34 #include <linux/reboot.h> 35 #include <linux/virtio_anchor.h> 36 #include <linux/stackprotector.h> 37 38 #include <xen/xen.h> 39 #include <xen/events.h> 40 #include <xen/interface/xen.h> 41 #include <xen/interface/version.h> 42 #include <xen/interface/physdev.h> 43 #include <xen/interface/vcpu.h> 44 #include <xen/interface/memory.h> 45 #include <xen/interface/nmi.h> 46 #include <xen/interface/xen-mca.h> 47 #include <xen/features.h> 48 #include <xen/page.h> 49 #include <xen/hvc-console.h> 50 #include <xen/acpi.h> 51 52 #include <asm/cpuid/api.h> 53 #include <asm/paravirt.h> 54 #include <asm/apic.h> 55 #include <asm/page.h> 56 #include <asm/xen/pci.h> 57 #include <asm/xen/hypercall.h> 58 #include <asm/xen/hypervisor.h> 59 #include <asm/xen/cpuid.h> 60 #include <asm/fixmap.h> 61 #include <asm/processor.h> 62 #include <asm/proto.h> 63 #include <asm/msr-index.h> 64 #include <asm/msr.h> 65 #include <asm/traps.h> 66 #include <asm/setup.h> 67 #include <asm/desc.h> 68 #include <asm/pgalloc.h> 69 #include <asm/tlbflush.h> 70 #include <asm/reboot.h> 71 #include <asm/hypervisor.h> 72 #include <asm/mach_traps.h> 73 #include <asm/mtrr.h> 74 #include <asm/mwait.h> 75 #include <asm/pci_x86.h> 76 #include <asm/cpu.h> 77 #include <asm/irq_stack.h> 78 #ifdef CONFIG_X86_IOPL_IOPERM 79 #include <asm/io_bitmap.h> 80 #endif 81 82 #ifdef CONFIG_ACPI 83 #include <linux/acpi.h> 84 #include <asm/acpi.h> 85 #include <acpi/proc_cap_intel.h> 86 #include <acpi/processor.h> 87 #include <xen/interface/platform.h> 88 #endif 89 90 #include "xen-ops.h" 91 92 #include "../kernel/cpu/cpu.h" /* get_cpu_cap() */ 93 94 void *xen_initial_gdt; 95 96 static int xen_cpu_up_prepare_pv(unsigned int cpu); 97 static int xen_cpu_dead_pv(unsigned int cpu); 98 99 #ifndef CONFIG_PREEMPTION 100 /* 101 * Some hypercalls issued by the toolstack can take many 10s of 102 * seconds. Allow tasks running hypercalls via the privcmd driver to 103 * be voluntarily preempted even if full kernel preemption is 104 * disabled. 105 * 106 * Such preemptible hypercalls are bracketed by 107 * xen_preemptible_hcall_begin() and xen_preemptible_hcall_end() 108 * calls. 109 */ 110 DEFINE_PER_CPU(bool, xen_in_preemptible_hcall); 111 EXPORT_PER_CPU_SYMBOL_GPL(xen_in_preemptible_hcall); 112 113 /* 114 * In case of scheduling the flag must be cleared and restored after 115 * returning from schedule as the task might move to a different CPU. 116 */ 117 static __always_inline bool get_and_clear_inhcall(void) 118 { 119 bool inhcall = __this_cpu_read(xen_in_preemptible_hcall); 120 121 __this_cpu_write(xen_in_preemptible_hcall, false); 122 return inhcall; 123 } 124 125 static __always_inline void restore_inhcall(bool inhcall) 126 { 127 __this_cpu_write(xen_in_preemptible_hcall, inhcall); 128 } 129 130 #else 131 132 static __always_inline bool get_and_clear_inhcall(void) { return false; } 133 static __always_inline void restore_inhcall(bool inhcall) { } 134 135 #endif 136 137 struct tls_descs { 138 struct desc_struct desc[3]; 139 }; 140 141 static DEFINE_PER_CPU(bool, xen_cpu_lazy_mode); 142 143 bool xen_is_cpu_lazy_mode(void) 144 { 145 return !in_interrupt() && this_cpu_read(xen_cpu_lazy_mode); 146 } 147 148 /* 149 * Updating the 3 TLS descriptors in the GDT on every task switch is 150 * surprisingly expensive so we avoid updating them if they haven't 151 * changed. Since Xen writes different descriptors than the one 152 * passed in the update_descriptor hypercall we keep shadow copies to 153 * compare against. 154 */ 155 static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc); 156 157 static __read_mostly bool xen_msr_safe = IS_ENABLED(CONFIG_XEN_PV_MSR_SAFE); 158 159 static int __init parse_xen_msr_safe(char *str) 160 { 161 if (str) 162 return kstrtobool(str, &xen_msr_safe); 163 return -EINVAL; 164 } 165 early_param("xen_msr_safe", parse_xen_msr_safe); 166 167 /* Get MTRR settings from Xen and put them into mtrr_state. */ 168 static void __init xen_set_mtrr_data(void) 169 { 170 #ifdef CONFIG_MTRR 171 struct xen_platform_op op = { 172 .cmd = XENPF_read_memtype, 173 .interface_version = XENPF_INTERFACE_VERSION, 174 }; 175 unsigned int reg; 176 unsigned long mask; 177 uint32_t eax, width; 178 static struct mtrr_var_range var[MTRR_MAX_VAR_RANGES] __initdata; 179 180 /* Get physical address width (only 64-bit cpus supported). */ 181 width = 36; 182 eax = cpuid_eax(0x80000000); 183 if ((eax >> 16) == 0x8000 && eax >= 0x80000008) { 184 eax = cpuid_eax(0x80000008); 185 width = eax & 0xff; 186 } 187 188 for (reg = 0; reg < MTRR_MAX_VAR_RANGES; reg++) { 189 op.u.read_memtype.reg = reg; 190 if (HYPERVISOR_platform_op(&op)) 191 break; 192 193 /* 194 * Only called in dom0, which has all RAM PFNs mapped at 195 * RAM MFNs, and all PCI space etc. is identity mapped. 196 * This means we can treat MFN == PFN regarding MTRR settings. 197 */ 198 var[reg].base_lo = op.u.read_memtype.type; 199 var[reg].base_lo |= op.u.read_memtype.mfn << PAGE_SHIFT; 200 var[reg].base_hi = op.u.read_memtype.mfn >> (32 - PAGE_SHIFT); 201 mask = ~((op.u.read_memtype.nr_mfns << PAGE_SHIFT) - 1); 202 mask &= (1UL << width) - 1; 203 if (mask) 204 mask |= MTRR_PHYSMASK_V; 205 var[reg].mask_lo = mask; 206 var[reg].mask_hi = mask >> 32; 207 } 208 209 /* Only overwrite MTRR state if any MTRR could be got from Xen. */ 210 if (reg) 211 guest_force_mtrr_state(var, reg, MTRR_TYPE_UNCACHABLE); 212 #endif 213 } 214 215 static void __init xen_pv_init_platform(void) 216 { 217 /* PV guests can't operate virtio devices without grants. */ 218 if (IS_ENABLED(CONFIG_XEN_VIRTIO)) 219 virtio_set_mem_acc_cb(xen_virtio_restricted_mem_acc); 220 221 populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP)); 222 223 set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info); 224 HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP); 225 226 /* xen clock uses per-cpu vcpu_info, need to init it for boot cpu */ 227 xen_vcpu_info_reset(0); 228 229 /* pvclock is in shared info area */ 230 xen_init_time_ops(); 231 232 if (xen_initial_domain()) 233 xen_set_mtrr_data(); 234 else 235 guest_force_mtrr_state(NULL, 0, MTRR_TYPE_WRBACK); 236 237 /* Adjust nr_cpu_ids before "enumeration" happens */ 238 xen_smp_count_cpus(); 239 } 240 241 static void __init xen_pv_guest_late_init(void) 242 { 243 #ifndef CONFIG_SMP 244 /* Setup shared vcpu info for non-smp configurations */ 245 xen_setup_vcpu_info_placement(); 246 #endif 247 } 248 249 static __read_mostly unsigned int cpuid_leaf5_ecx_val; 250 static __read_mostly unsigned int cpuid_leaf5_edx_val; 251 252 static void xen_cpuid(unsigned int *ax, unsigned int *bx, 253 unsigned int *cx, unsigned int *dx) 254 { 255 unsigned int maskebx = ~0; 256 unsigned int or_ebx = 0; 257 258 /* 259 * Mask out inconvenient features, to try and disable as many 260 * unsupported kernel subsystems as possible. 261 */ 262 switch (*ax) { 263 case 0x1: 264 /* Replace initial APIC ID in bits 24-31 of EBX. */ 265 /* See xen_pv_smp_config() for related topology preparations. */ 266 maskebx = 0x00ffffff; 267 or_ebx = smp_processor_id() << 24; 268 break; 269 270 case CPUID_LEAF_MWAIT: 271 /* Synthesize the values.. */ 272 *ax = 0; 273 *bx = 0; 274 *cx = cpuid_leaf5_ecx_val; 275 *dx = cpuid_leaf5_edx_val; 276 return; 277 278 case 0xb: 279 /* Suppress extended topology stuff */ 280 maskebx = 0; 281 break; 282 } 283 284 asm(XEN_EMULATE_PREFIX "cpuid" 285 : "=a" (*ax), 286 "=b" (*bx), 287 "=c" (*cx), 288 "=d" (*dx) 289 : "0" (*ax), "2" (*cx)); 290 291 *bx &= maskebx; 292 *bx |= or_ebx; 293 } 294 295 static bool __init xen_check_mwait(void) 296 { 297 #ifdef CONFIG_ACPI 298 struct xen_platform_op op = { 299 .cmd = XENPF_set_processor_pminfo, 300 .u.set_pminfo.id = -1, 301 .u.set_pminfo.type = XEN_PM_PDC, 302 }; 303 uint32_t buf[3]; 304 unsigned int ax, bx, cx, dx; 305 unsigned int mwait_mask; 306 307 /* We need to determine whether it is OK to expose the MWAIT 308 * capability to the kernel to harvest deeper than C3 states from ACPI 309 * _CST using the processor_harvest_xen.c module. For this to work, we 310 * need to gather the MWAIT_LEAF values (which the cstate.c code 311 * checks against). The hypervisor won't expose the MWAIT flag because 312 * it would break backwards compatibility; so we will find out directly 313 * from the hardware and hypercall. 314 */ 315 if (!xen_initial_domain()) 316 return false; 317 318 /* 319 * When running under platform earlier than Xen4.2, do not expose 320 * mwait, to avoid the risk of loading native acpi pad driver 321 */ 322 if (!xen_running_on_version_or_later(4, 2)) 323 return false; 324 325 ax = 1; 326 cx = 0; 327 328 native_cpuid(&ax, &bx, &cx, &dx); 329 330 mwait_mask = (1 << (X86_FEATURE_EST % 32)) | 331 (1 << (X86_FEATURE_MWAIT % 32)); 332 333 if ((cx & mwait_mask) != mwait_mask) 334 return false; 335 336 /* We need to emulate the MWAIT_LEAF and for that we need both 337 * ecx and edx. The hypercall provides only partial information. 338 */ 339 340 ax = CPUID_LEAF_MWAIT; 341 bx = 0; 342 cx = 0; 343 dx = 0; 344 345 native_cpuid(&ax, &bx, &cx, &dx); 346 347 /* Ask the Hypervisor whether to clear ACPI_PROC_CAP_C_C2C3_FFH. If so, 348 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3. 349 */ 350 buf[0] = ACPI_PDC_REVISION_ID; 351 buf[1] = 1; 352 buf[2] = (ACPI_PROC_CAP_C_CAPABILITY_SMP | ACPI_PROC_CAP_EST_CAPABILITY_SWSMP); 353 354 set_xen_guest_handle(op.u.set_pminfo.pdc, buf); 355 356 if ((HYPERVISOR_platform_op(&op) == 0) && 357 (buf[2] & (ACPI_PROC_CAP_C_C1_FFH | ACPI_PROC_CAP_C_C2C3_FFH))) { 358 cpuid_leaf5_ecx_val = cx; 359 cpuid_leaf5_edx_val = dx; 360 } 361 return true; 362 #else 363 return false; 364 #endif 365 } 366 367 static bool __init xen_check_xsave(void) 368 { 369 unsigned int cx, xsave_mask; 370 371 cx = cpuid_ecx(1); 372 373 xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) | 374 (1 << (X86_FEATURE_OSXSAVE % 32)); 375 376 /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ 377 return (cx & xsave_mask) == xsave_mask; 378 } 379 380 static void __init xen_init_capabilities(void) 381 { 382 setup_clear_cpu_cap(X86_FEATURE_DCA); 383 setup_clear_cpu_cap(X86_FEATURE_APERFMPERF); 384 setup_clear_cpu_cap(X86_FEATURE_MTRR); 385 setup_clear_cpu_cap(X86_FEATURE_ACC); 386 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 387 setup_clear_cpu_cap(X86_FEATURE_SME); 388 setup_clear_cpu_cap(X86_FEATURE_LKGS); 389 390 /* 391 * Xen PV would need some work to support PCID: CR3 handling as well 392 * as xen_flush_tlb_multi() would need updating. 393 */ 394 setup_clear_cpu_cap(X86_FEATURE_PCID); 395 396 if (!xen_initial_domain()) 397 setup_clear_cpu_cap(X86_FEATURE_ACPI); 398 399 if (xen_check_mwait()) 400 setup_force_cpu_cap(X86_FEATURE_MWAIT); 401 else 402 setup_clear_cpu_cap(X86_FEATURE_MWAIT); 403 404 if (!xen_check_xsave()) { 405 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 406 setup_clear_cpu_cap(X86_FEATURE_OSXSAVE); 407 } 408 } 409 410 static noinstr void xen_set_debugreg(int reg, unsigned long val) 411 { 412 HYPERVISOR_set_debugreg(reg, val); 413 } 414 415 static noinstr unsigned long xen_get_debugreg(int reg) 416 { 417 return HYPERVISOR_get_debugreg(reg); 418 } 419 420 static void xen_start_context_switch(struct task_struct *prev) 421 { 422 BUG_ON(preemptible()); 423 424 __task_lazy_mmu_mode_pause(prev); 425 this_cpu_write(xen_cpu_lazy_mode, true); 426 } 427 428 static void xen_end_context_switch(struct task_struct *next) 429 { 430 BUG_ON(preemptible()); 431 432 xen_mc_flush(); 433 this_cpu_write(xen_cpu_lazy_mode, false); 434 __task_lazy_mmu_mode_resume(next); 435 } 436 437 static unsigned long xen_store_tr(void) 438 { 439 return 0; 440 } 441 442 /* 443 * Set the page permissions for a particular virtual address. If the 444 * address is a vmalloc mapping (or other non-linear mapping), then 445 * find the linear mapping of the page and also set its protections to 446 * match. 447 */ 448 static void set_aliased_prot(void *v, pgprot_t prot) 449 { 450 int level; 451 pte_t *ptep; 452 pte_t pte; 453 unsigned long pfn; 454 unsigned char dummy; 455 void *va; 456 457 ptep = lookup_address((unsigned long)v, &level); 458 BUG_ON(ptep == NULL); 459 460 pfn = pte_pfn(*ptep); 461 pte = pfn_pte(pfn, prot); 462 463 /* 464 * Careful: update_va_mapping() will fail if the virtual address 465 * we're poking isn't populated in the page tables. We don't 466 * need to worry about the direct map (that's always in the page 467 * tables), but we need to be careful about vmap space. In 468 * particular, the top level page table can lazily propagate 469 * entries between processes, so if we've switched mms since we 470 * vmapped the target in the first place, we might not have the 471 * top-level page table entry populated. 472 * 473 * We disable preemption because we want the same mm active when 474 * we probe the target and when we issue the hypercall. We'll 475 * have the same nominal mm, but if we're a kernel thread, lazy 476 * mm dropping could change our pgd. 477 * 478 * Out of an abundance of caution, this uses __get_user() to fault 479 * in the target address just in case there's some obscure case 480 * in which the target address isn't readable. 481 */ 482 483 preempt_disable(); 484 485 copy_from_kernel_nofault(&dummy, v, 1); 486 487 if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0)) 488 BUG(); 489 490 va = __va(PFN_PHYS(pfn)); 491 492 if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 493 BUG(); 494 495 preempt_enable(); 496 } 497 498 static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries) 499 { 500 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 501 int i; 502 503 /* 504 * We need to mark the all aliases of the LDT pages RO. We 505 * don't need to call vm_flush_aliases(), though, since that's 506 * only responsible for flushing aliases out the TLBs, not the 507 * page tables, and Xen will flush the TLB for us if needed. 508 * 509 * To avoid confusing future readers: none of this is necessary 510 * to load the LDT. The hypervisor only checks this when the 511 * LDT is faulted in due to subsequent descriptor access. 512 */ 513 514 for (i = 0; i < entries; i += entries_per_page) 515 set_aliased_prot(ldt + i, PAGE_KERNEL_RO); 516 } 517 518 static void xen_free_ldt(struct desc_struct *ldt, unsigned entries) 519 { 520 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 521 int i; 522 523 for (i = 0; i < entries; i += entries_per_page) 524 set_aliased_prot(ldt + i, PAGE_KERNEL); 525 } 526 527 static void xen_set_ldt(const void *addr, unsigned entries) 528 { 529 struct mmuext_op *op; 530 struct multicall_space mcs = xen_mc_entry(sizeof(*op)); 531 532 trace_xen_cpu_set_ldt(addr, entries); 533 534 op = mcs.args; 535 op->cmd = MMUEXT_SET_LDT; 536 op->arg1.linear_addr = (unsigned long)addr; 537 op->arg2.nr_ents = entries; 538 539 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF); 540 541 xen_mc_issue(!xen_is_cpu_lazy_mode()); 542 } 543 544 static void xen_load_gdt(const struct desc_ptr *dtr) 545 { 546 unsigned long va = dtr->address; 547 unsigned int size = dtr->size + 1; 548 unsigned long pfn, mfn; 549 int level; 550 pte_t *ptep; 551 void *virt; 552 553 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 554 BUG_ON(size > PAGE_SIZE); 555 BUG_ON(va & ~PAGE_MASK); 556 557 /* 558 * The GDT is per-cpu and is in the percpu data area. 559 * That can be virtually mapped, so we need to do a 560 * page-walk to get the underlying MFN for the 561 * hypercall. The page can also be in the kernel's 562 * linear range, so we need to RO that mapping too. 563 */ 564 ptep = lookup_address(va, &level); 565 BUG_ON(ptep == NULL); 566 567 pfn = pte_pfn(*ptep); 568 mfn = pfn_to_mfn(pfn); 569 virt = __va(PFN_PHYS(pfn)); 570 571 make_lowmem_page_readonly((void *)va); 572 make_lowmem_page_readonly(virt); 573 574 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 575 BUG(); 576 } 577 578 /* 579 * load_gdt for early boot, when the gdt is only mapped once 580 */ 581 static void __init xen_load_gdt_boot(const struct desc_ptr *dtr) 582 { 583 unsigned long va = dtr->address; 584 unsigned int size = dtr->size + 1; 585 unsigned long pfn, mfn; 586 pte_t pte; 587 588 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 589 BUG_ON(size > PAGE_SIZE); 590 BUG_ON(va & ~PAGE_MASK); 591 592 pfn = virt_to_pfn((void *)va); 593 mfn = pfn_to_mfn(pfn); 594 595 pte = pfn_pte(pfn, PAGE_KERNEL_RO); 596 597 if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 598 BUG(); 599 600 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 601 BUG(); 602 } 603 604 static inline bool desc_equal(const struct desc_struct *d1, 605 const struct desc_struct *d2) 606 { 607 return !memcmp(d1, d2, sizeof(*d1)); 608 } 609 610 static void load_TLS_descriptor(struct thread_struct *t, 611 unsigned int cpu, unsigned int i) 612 { 613 struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i]; 614 struct desc_struct *gdt; 615 xmaddr_t maddr; 616 struct multicall_space mc; 617 618 if (desc_equal(shadow, &t->tls_array[i])) 619 return; 620 621 *shadow = t->tls_array[i]; 622 623 gdt = get_cpu_gdt_rw(cpu); 624 maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]); 625 mc = __xen_mc_entry(0); 626 627 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]); 628 } 629 630 static void xen_load_tls(struct thread_struct *t, unsigned int cpu) 631 { 632 /* 633 * In lazy mode we need to zero %fs, otherwise we may get an 634 * exception between the new %fs descriptor being loaded and 635 * %fs being effectively cleared at __switch_to(). 636 */ 637 if (xen_is_cpu_lazy_mode()) 638 loadsegment(fs, 0); 639 640 xen_mc_batch(); 641 642 load_TLS_descriptor(t, cpu, 0); 643 load_TLS_descriptor(t, cpu, 1); 644 load_TLS_descriptor(t, cpu, 2); 645 646 xen_mc_issue(!xen_is_cpu_lazy_mode()); 647 } 648 649 static void xen_load_gs_index(unsigned int idx) 650 { 651 if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx)) 652 BUG(); 653 } 654 655 static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum, 656 const void *ptr) 657 { 658 xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]); 659 u64 entry = *(u64 *)ptr; 660 661 trace_xen_cpu_write_ldt_entry(dt, entrynum, entry); 662 663 preempt_disable(); 664 665 xen_mc_flush(); 666 if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry)) 667 BUG(); 668 669 preempt_enable(); 670 } 671 672 void noist_exc_debug(struct pt_regs *regs); 673 674 DEFINE_IDTENTRY_RAW(xenpv_exc_nmi) 675 { 676 /* On Xen PV, NMI doesn't use IST. The C part is the same as native. */ 677 exc_nmi(regs); 678 } 679 680 DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault) 681 { 682 /* On Xen PV, DF doesn't use IST. The C part is the same as native. */ 683 exc_double_fault(regs, error_code); 684 } 685 686 DEFINE_IDTENTRY_RAW(xenpv_exc_debug) 687 { 688 /* 689 * There's no IST on Xen PV, but we still need to dispatch 690 * to the correct handler. 691 */ 692 if (user_mode(regs)) 693 noist_exc_debug(regs); 694 else 695 exc_debug(regs); 696 } 697 698 DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap) 699 { 700 /* This should never happen and there is no way to handle it. */ 701 instrumentation_begin(); 702 pr_err("Unknown trap in Xen PV mode."); 703 BUG(); 704 instrumentation_end(); 705 } 706 707 #ifdef CONFIG_X86_MCE 708 DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check) 709 { 710 /* 711 * There's no IST on Xen PV, but we still need to dispatch 712 * to the correct handler. 713 */ 714 if (user_mode(regs)) 715 noist_exc_machine_check(regs); 716 else 717 exc_machine_check(regs); 718 } 719 #endif 720 721 static void __xen_pv_evtchn_do_upcall(struct pt_regs *regs) 722 { 723 struct pt_regs *old_regs = set_irq_regs(regs); 724 725 inc_irq_stat(HYPERVISOR_CALLBACK); 726 727 xen_evtchn_do_upcall(); 728 729 set_irq_regs(old_regs); 730 } 731 732 __visible noinstr void xen_pv_evtchn_do_upcall(struct pt_regs *regs) 733 { 734 irqentry_state_t state = irqentry_enter(regs); 735 bool inhcall; 736 737 instrumentation_begin(); 738 run_sysvec_on_irqstack_cond(__xen_pv_evtchn_do_upcall, regs); 739 740 inhcall = get_and_clear_inhcall(); 741 if (inhcall && !WARN_ON_ONCE(state.exit_rcu)) { 742 irqentry_exit_cond_resched(); 743 instrumentation_end(); 744 restore_inhcall(inhcall); 745 } else { 746 instrumentation_end(); 747 irqentry_exit(regs, state); 748 } 749 } 750 751 struct trap_array_entry { 752 void (*orig)(void); 753 void (*xen)(void); 754 bool ist_okay; 755 }; 756 757 #define TRAP_ENTRY(func, ist_ok) { \ 758 .orig = asm_##func, \ 759 .xen = xen_asm_##func, \ 760 .ist_okay = ist_ok } 761 762 #define TRAP_ENTRY_REDIR(func, ist_ok) { \ 763 .orig = asm_##func, \ 764 .xen = xen_asm_xenpv_##func, \ 765 .ist_okay = ist_ok } 766 767 static struct trap_array_entry trap_array[] = { 768 TRAP_ENTRY_REDIR(exc_debug, true ), 769 TRAP_ENTRY_REDIR(exc_double_fault, true ), 770 #ifdef CONFIG_X86_MCE 771 TRAP_ENTRY_REDIR(exc_machine_check, true ), 772 #endif 773 TRAP_ENTRY_REDIR(exc_nmi, true ), 774 TRAP_ENTRY(exc_int3, false ), 775 TRAP_ENTRY(exc_overflow, false ), 776 #ifdef CONFIG_IA32_EMULATION 777 TRAP_ENTRY(int80_emulation, false ), 778 #endif 779 TRAP_ENTRY(exc_page_fault, false ), 780 TRAP_ENTRY(exc_divide_error, false ), 781 TRAP_ENTRY(exc_bounds, false ), 782 TRAP_ENTRY(exc_invalid_op, false ), 783 TRAP_ENTRY(exc_device_not_available, false ), 784 TRAP_ENTRY(exc_coproc_segment_overrun, false ), 785 TRAP_ENTRY(exc_invalid_tss, false ), 786 TRAP_ENTRY(exc_segment_not_present, false ), 787 TRAP_ENTRY(exc_stack_segment, false ), 788 TRAP_ENTRY(exc_general_protection, false ), 789 TRAP_ENTRY(exc_spurious_interrupt_bug, false ), 790 TRAP_ENTRY(exc_coprocessor_error, false ), 791 TRAP_ENTRY(exc_alignment_check, false ), 792 TRAP_ENTRY(exc_simd_coprocessor_error, false ), 793 #ifdef CONFIG_X86_CET 794 TRAP_ENTRY(exc_control_protection, false ), 795 #endif 796 }; 797 798 static bool __ref get_trap_addr(void **addr, unsigned int ist) 799 { 800 unsigned int nr; 801 bool ist_okay = false; 802 bool found = false; 803 804 /* 805 * Replace trap handler addresses by Xen specific ones. 806 * Check for known traps using IST and whitelist them. 807 * The debugger ones are the only ones we care about. 808 * Xen will handle faults like double_fault, so we should never see 809 * them. Warn if there's an unexpected IST-using fault handler. 810 */ 811 for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) { 812 struct trap_array_entry *entry = trap_array + nr; 813 814 if (*addr == entry->orig) { 815 *addr = entry->xen; 816 ist_okay = entry->ist_okay; 817 found = true; 818 break; 819 } 820 } 821 822 if (nr == ARRAY_SIZE(trap_array) && 823 *addr >= (void *)early_idt_handler_array[0] && 824 *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) { 825 nr = (*addr - (void *)early_idt_handler_array[0]) / 826 EARLY_IDT_HANDLER_SIZE; 827 *addr = (void *)xen_early_idt_handler_array[nr]; 828 found = true; 829 } 830 831 if (!found) 832 *addr = (void *)xen_asm_exc_xen_unknown_trap; 833 834 if (WARN_ON(found && ist != 0 && !ist_okay)) 835 return false; 836 837 return true; 838 } 839 840 static int cvt_gate_to_trap(int vector, const gate_desc *val, 841 struct trap_info *info) 842 { 843 unsigned long addr; 844 845 if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT) 846 return 0; 847 848 info->vector = vector; 849 850 addr = gate_offset(val); 851 if (!get_trap_addr((void **)&addr, val->bits.ist)) 852 return 0; 853 info->address = addr; 854 855 info->cs = gate_segment(val); 856 info->flags = val->bits.dpl; 857 /* interrupt gates clear IF */ 858 if (val->bits.type == GATE_INTERRUPT) 859 info->flags |= 1 << 2; 860 861 return 1; 862 } 863 864 /* Locations of each CPU's IDT */ 865 static DEFINE_PER_CPU(struct desc_ptr, idt_desc); 866 867 /* Set an IDT entry. If the entry is part of the current IDT, then 868 also update Xen. */ 869 static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) 870 { 871 unsigned long p = (unsigned long)&dt[entrynum]; 872 unsigned long start, end; 873 874 trace_xen_cpu_write_idt_entry(dt, entrynum, g); 875 876 preempt_disable(); 877 878 start = __this_cpu_read(idt_desc.address); 879 end = start + __this_cpu_read(idt_desc.size) + 1; 880 881 xen_mc_flush(); 882 883 native_write_idt_entry(dt, entrynum, g); 884 885 if (p >= start && (p + 8) <= end) { 886 struct trap_info info[2]; 887 888 info[1].address = 0; 889 890 if (cvt_gate_to_trap(entrynum, g, &info[0])) 891 if (HYPERVISOR_set_trap_table(info)) 892 BUG(); 893 } 894 895 preempt_enable(); 896 } 897 898 static unsigned xen_convert_trap_info(const struct desc_ptr *desc, 899 struct trap_info *traps, bool full) 900 { 901 unsigned in, out, count; 902 903 count = (desc->size+1) / sizeof(gate_desc); 904 BUG_ON(count > 256); 905 906 for (in = out = 0; in < count; in++) { 907 gate_desc *entry = (gate_desc *)(desc->address) + in; 908 909 if (cvt_gate_to_trap(in, entry, &traps[out]) || full) 910 out++; 911 } 912 913 return out; 914 } 915 916 void xen_copy_trap_info(struct trap_info *traps) 917 { 918 const struct desc_ptr *desc = this_cpu_ptr(&idt_desc); 919 920 xen_convert_trap_info(desc, traps, true); 921 } 922 923 /* Load a new IDT into Xen. In principle this can be per-CPU, so we 924 hold a spinlock to protect the static traps[] array (static because 925 it avoids allocation, and saves stack space). */ 926 static void xen_load_idt(const struct desc_ptr *desc) 927 { 928 static DEFINE_SPINLOCK(lock); 929 static struct trap_info traps[257]; 930 static const struct trap_info zero = { }; 931 unsigned out; 932 933 trace_xen_cpu_load_idt(desc); 934 935 spin_lock(&lock); 936 937 memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc)); 938 939 out = xen_convert_trap_info(desc, traps, false); 940 traps[out] = zero; 941 942 xen_mc_flush(); 943 if (HYPERVISOR_set_trap_table(traps)) 944 BUG(); 945 946 spin_unlock(&lock); 947 } 948 949 /* Write a GDT descriptor entry. Ignore LDT descriptors, since 950 they're handled differently. */ 951 static void xen_write_gdt_entry(struct desc_struct *dt, int entry, 952 const void *desc, int type) 953 { 954 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 955 956 preempt_disable(); 957 958 switch (type) { 959 case DESC_LDT: 960 case DESC_TSS: 961 /* ignore */ 962 break; 963 964 default: { 965 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]); 966 967 xen_mc_flush(); 968 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 969 BUG(); 970 } 971 972 } 973 974 preempt_enable(); 975 } 976 977 /* 978 * Version of write_gdt_entry for use at early boot-time needed to 979 * update an entry as simply as possible. 980 */ 981 static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry, 982 const void *desc, int type) 983 { 984 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 985 986 switch (type) { 987 case DESC_LDT: 988 case DESC_TSS: 989 /* ignore */ 990 break; 991 992 default: { 993 xmaddr_t maddr = virt_to_machine(&dt[entry]); 994 995 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 996 dt[entry] = *(struct desc_struct *)desc; 997 } 998 999 } 1000 } 1001 1002 static void xen_load_sp0(unsigned long sp0) 1003 { 1004 struct multicall_space mcs; 1005 1006 mcs = xen_mc_entry(0); 1007 MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0); 1008 xen_mc_issue(!xen_is_cpu_lazy_mode()); 1009 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 1010 } 1011 1012 #ifdef CONFIG_X86_IOPL_IOPERM 1013 static void xen_invalidate_io_bitmap(void) 1014 { 1015 struct physdev_set_iobitmap iobitmap = { 1016 .bitmap = NULL, 1017 .nr_ports = 0, 1018 }; 1019 1020 native_tss_invalidate_io_bitmap(); 1021 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 1022 } 1023 1024 static void xen_update_io_bitmap(void) 1025 { 1026 struct physdev_set_iobitmap iobitmap; 1027 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 1028 1029 native_tss_update_io_bitmap(); 1030 1031 iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) + 1032 tss->x86_tss.io_bitmap_base; 1033 if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID) 1034 iobitmap.nr_ports = 0; 1035 else 1036 iobitmap.nr_ports = IO_BITMAP_BITS; 1037 1038 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 1039 } 1040 #endif 1041 1042 static DEFINE_PER_CPU(unsigned long, xen_cr0_value); 1043 1044 static unsigned long xen_read_cr0(void) 1045 { 1046 unsigned long cr0 = this_cpu_read(xen_cr0_value); 1047 1048 if (unlikely(cr0 == 0)) { 1049 cr0 = native_read_cr0(); 1050 this_cpu_write(xen_cr0_value, cr0); 1051 } 1052 1053 return cr0; 1054 } 1055 1056 static void xen_write_cr0(unsigned long cr0) 1057 { 1058 struct multicall_space mcs; 1059 1060 this_cpu_write(xen_cr0_value, cr0); 1061 1062 /* Only pay attention to cr0.TS; everything else is 1063 ignored. */ 1064 mcs = xen_mc_entry(0); 1065 1066 MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0); 1067 1068 xen_mc_issue(!xen_is_cpu_lazy_mode()); 1069 } 1070 1071 static void xen_write_cr4(unsigned long cr4) 1072 { 1073 cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE); 1074 1075 native_write_cr4(cr4); 1076 } 1077 1078 static u64 xen_do_read_msr(u32 msr, int *err) 1079 { 1080 u64 val = 0; /* Avoid uninitialized value for safe variant. */ 1081 1082 if (pmu_msr_chk_emulated(msr, &val, true)) 1083 return val; 1084 1085 if (err) 1086 *err = native_read_msr_safe(msr, &val); 1087 else 1088 val = native_read_msr(msr); 1089 1090 switch (msr) { 1091 case MSR_IA32_APICBASE: 1092 val &= ~X2APIC_ENABLE; 1093 if (smp_processor_id() == 0) 1094 val |= MSR_IA32_APICBASE_BSP; 1095 else 1096 val &= ~MSR_IA32_APICBASE_BSP; 1097 break; 1098 } 1099 return val; 1100 } 1101 1102 static void set_seg(u32 which, u64 base) 1103 { 1104 if (HYPERVISOR_set_segment_base(which, base)) 1105 WARN(1, "Xen set_segment_base(%u, %llx) failed\n", which, base); 1106 } 1107 1108 /* 1109 * Support write_msr_safe() and write_msr() semantics. 1110 * With err == NULL write_msr() semantics are selected. 1111 * Supplying an err pointer requires err to be pre-initialized with 0. 1112 */ 1113 static void xen_do_write_msr(u32 msr, u64 val, int *err) 1114 { 1115 switch (msr) { 1116 case MSR_FS_BASE: 1117 set_seg(SEGBASE_FS, val); 1118 break; 1119 1120 case MSR_KERNEL_GS_BASE: 1121 set_seg(SEGBASE_GS_USER, val); 1122 break; 1123 1124 case MSR_GS_BASE: 1125 set_seg(SEGBASE_GS_KERNEL, val); 1126 break; 1127 1128 case MSR_STAR: 1129 case MSR_CSTAR: 1130 case MSR_LSTAR: 1131 case MSR_SYSCALL_MASK: 1132 case MSR_IA32_SYSENTER_CS: 1133 case MSR_IA32_SYSENTER_ESP: 1134 case MSR_IA32_SYSENTER_EIP: 1135 /* Fast syscall setup is all done in hypercalls, so 1136 these are all ignored. Stub them out here to stop 1137 Xen console noise. */ 1138 break; 1139 1140 default: 1141 if (pmu_msr_chk_emulated(msr, &val, false)) 1142 return; 1143 1144 if (err) 1145 *err = native_write_msr_safe(msr, val); 1146 else 1147 native_write_msr(msr, val); 1148 } 1149 } 1150 1151 static int xen_read_msr_safe(u32 msr, u64 *val) 1152 { 1153 int err = 0; 1154 1155 *val = xen_do_read_msr(msr, &err); 1156 return err; 1157 } 1158 1159 static int xen_write_msr_safe(u32 msr, u64 val) 1160 { 1161 int err = 0; 1162 1163 xen_do_write_msr(msr, val, &err); 1164 1165 return err; 1166 } 1167 1168 static u64 xen_read_msr(u32 msr) 1169 { 1170 int err = 0; 1171 1172 return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); 1173 } 1174 1175 static void xen_write_msr(u32 msr, u64 val) 1176 { 1177 int err; 1178 1179 xen_do_write_msr(msr, val, xen_msr_safe ? &err : NULL); 1180 } 1181 1182 /* This is called once we have the cpu_possible_mask */ 1183 void __init xen_setup_vcpu_info_placement(void) 1184 { 1185 int cpu; 1186 1187 for_each_possible_cpu(cpu) { 1188 /* Set up direct vCPU id mapping for PV guests. */ 1189 per_cpu(xen_vcpu_id, cpu) = cpu; 1190 xen_vcpu_setup(cpu); 1191 } 1192 1193 pv_ops.irq.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct); 1194 pv_ops.irq.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct); 1195 pv_ops.irq.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct); 1196 pv_ops.mmu.read_cr2 = __PV_IS_CALLEE_SAVE(xen_read_cr2_direct); 1197 } 1198 1199 static const struct pv_info xen_info __initconst = { 1200 .extra_user_64bit_cs = FLAT_USER_CS64, 1201 .io_delay = false, 1202 .name = "Xen", 1203 }; 1204 1205 static void xen_restart(char *msg) 1206 { 1207 xen_reboot(SHUTDOWN_reboot); 1208 } 1209 1210 static void xen_machine_halt(void) 1211 { 1212 xen_reboot(SHUTDOWN_poweroff); 1213 } 1214 1215 static void xen_machine_power_off(void) 1216 { 1217 do_kernel_power_off(); 1218 xen_reboot(SHUTDOWN_poweroff); 1219 } 1220 1221 static void xen_crash_shutdown(struct pt_regs *regs) 1222 { 1223 xen_reboot(SHUTDOWN_crash); 1224 } 1225 1226 static const struct machine_ops xen_machine_ops __initconst = { 1227 .restart = xen_restart, 1228 .halt = xen_machine_halt, 1229 .power_off = xen_machine_power_off, 1230 .shutdown = xen_machine_halt, 1231 .crash_shutdown = xen_crash_shutdown, 1232 .emergency_restart = xen_emergency_restart, 1233 }; 1234 1235 static unsigned char xen_get_nmi_reason(void) 1236 { 1237 unsigned char reason = 0; 1238 1239 /* Construct a value which looks like it came from port 0x61. */ 1240 if (test_bit(_XEN_NMIREASON_io_error, 1241 &HYPERVISOR_shared_info->arch.nmi_reason)) 1242 reason |= NMI_REASON_IOCHK; 1243 if (test_bit(_XEN_NMIREASON_pci_serr, 1244 &HYPERVISOR_shared_info->arch.nmi_reason)) 1245 reason |= NMI_REASON_SERR; 1246 1247 return reason; 1248 } 1249 1250 static void __init xen_boot_params_init_edd(void) 1251 { 1252 #if IS_ENABLED(CONFIG_EDD) 1253 struct xen_platform_op op; 1254 struct edd_info *edd_info; 1255 u32 *mbr_signature; 1256 unsigned nr; 1257 int ret; 1258 1259 edd_info = boot_params.eddbuf; 1260 mbr_signature = boot_params.edd_mbr_sig_buffer; 1261 1262 op.cmd = XENPF_firmware_info; 1263 1264 op.u.firmware_info.type = XEN_FW_DISK_INFO; 1265 for (nr = 0; nr < EDDMAXNR; nr++) { 1266 struct edd_info *info = edd_info + nr; 1267 1268 op.u.firmware_info.index = nr; 1269 info->params.length = sizeof(info->params); 1270 set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params, 1271 &info->params); 1272 ret = HYPERVISOR_platform_op(&op); 1273 if (ret) 1274 break; 1275 1276 #define C(x) info->x = op.u.firmware_info.u.disk_info.x 1277 C(device); 1278 C(version); 1279 C(interface_support); 1280 C(legacy_max_cylinder); 1281 C(legacy_max_head); 1282 C(legacy_sectors_per_track); 1283 #undef C 1284 } 1285 boot_params.eddbuf_entries = nr; 1286 1287 op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE; 1288 for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) { 1289 op.u.firmware_info.index = nr; 1290 ret = HYPERVISOR_platform_op(&op); 1291 if (ret) 1292 break; 1293 mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature; 1294 } 1295 boot_params.edd_mbr_sig_buf_entries = nr; 1296 #endif 1297 } 1298 1299 /* 1300 * Set up the GDT and segment registers for -fstack-protector. Until 1301 * we do this, we have to be careful not to call any stack-protected 1302 * function, which is most of the kernel. 1303 */ 1304 static void __init xen_setup_gdt(int cpu) 1305 { 1306 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry_boot; 1307 pv_ops.cpu.load_gdt = xen_load_gdt_boot; 1308 1309 switch_gdt_and_percpu_base(cpu); 1310 1311 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry; 1312 pv_ops.cpu.load_gdt = xen_load_gdt; 1313 } 1314 1315 static void __init xen_dom0_set_legacy_features(void) 1316 { 1317 x86_platform.legacy.rtc = 1; 1318 } 1319 1320 static void __init xen_domu_set_legacy_features(void) 1321 { 1322 x86_platform.legacy.rtc = 0; 1323 } 1324 1325 extern void early_xen_iret_patch(void); 1326 1327 /* First C function to be called on Xen boot */ 1328 asmlinkage __visible void __init xen_start_kernel(struct start_info *si) 1329 { 1330 struct physdev_set_iopl set_iopl; 1331 unsigned long initrd_start = 0; 1332 int rc; 1333 1334 if (!si) 1335 return; 1336 1337 clear_bss(); 1338 1339 xen_start_info = si; 1340 1341 __text_gen_insn(&early_xen_iret_patch, 1342 JMP32_INSN_OPCODE, &early_xen_iret_patch, &xen_iret, 1343 JMP32_INSN_SIZE); 1344 1345 xen_domain_type = XEN_PV_DOMAIN; 1346 setup_force_cpu_cap(X86_FEATURE_XENPV); 1347 xen_start_flags = xen_start_info->flags; 1348 /* Interrupts are guaranteed to be off initially. */ 1349 early_boot_irqs_disabled = true; 1350 static_call_update_early(xen_hypercall, xen_hypercall_pv); 1351 1352 xen_setup_features(); 1353 1354 /* Install Xen paravirt ops */ 1355 pv_info = xen_info; 1356 1357 pv_ops.cpu.cpuid = xen_cpuid; 1358 pv_ops.cpu.set_debugreg = xen_set_debugreg; 1359 pv_ops.cpu.get_debugreg = xen_get_debugreg; 1360 pv_ops.cpu.read_cr0 = xen_read_cr0; 1361 pv_ops.cpu.write_cr0 = xen_write_cr0; 1362 pv_ops.cpu.write_cr4 = xen_write_cr4; 1363 pv_ops.cpu.read_msr = xen_read_msr; 1364 pv_ops.cpu.write_msr = xen_write_msr; 1365 pv_ops.cpu.read_msr_safe = xen_read_msr_safe; 1366 pv_ops.cpu.write_msr_safe = xen_write_msr_safe; 1367 pv_ops.cpu.read_pmc = xen_read_pmc; 1368 pv_ops.cpu.load_tr_desc = paravirt_nop; 1369 pv_ops.cpu.set_ldt = xen_set_ldt; 1370 pv_ops.cpu.load_gdt = xen_load_gdt; 1371 pv_ops.cpu.load_idt = xen_load_idt; 1372 pv_ops.cpu.load_tls = xen_load_tls; 1373 pv_ops.cpu.load_gs_index = xen_load_gs_index; 1374 pv_ops.cpu.alloc_ldt = xen_alloc_ldt; 1375 pv_ops.cpu.free_ldt = xen_free_ldt; 1376 pv_ops.cpu.store_tr = xen_store_tr; 1377 pv_ops.cpu.write_ldt_entry = xen_write_ldt_entry; 1378 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry; 1379 pv_ops.cpu.write_idt_entry = xen_write_idt_entry; 1380 pv_ops.cpu.load_sp0 = xen_load_sp0; 1381 #ifdef CONFIG_X86_IOPL_IOPERM 1382 pv_ops.cpu.invalidate_io_bitmap = xen_invalidate_io_bitmap; 1383 pv_ops.cpu.update_io_bitmap = xen_update_io_bitmap; 1384 #endif 1385 pv_ops.cpu.start_context_switch = xen_start_context_switch; 1386 pv_ops.cpu.end_context_switch = xen_end_context_switch; 1387 1388 xen_init_irq_ops(); 1389 1390 /* 1391 * Setup xen_vcpu early because it is needed for 1392 * local_irq_disable(), irqs_disabled(), e.g. in printk(). 1393 * 1394 * Don't do the full vcpu_info placement stuff until we have 1395 * the cpu_possible_mask and a non-dummy shared_info. 1396 */ 1397 xen_vcpu_info_reset(0); 1398 1399 x86_platform.get_nmi_reason = xen_get_nmi_reason; 1400 x86_platform.realmode_reserve = x86_init_noop; 1401 x86_platform.realmode_init = x86_init_noop; 1402 1403 x86_init.resources.memory_setup = xen_memory_setup; 1404 x86_init.irqs.intr_mode_select = x86_init_noop; 1405 x86_init.irqs.intr_mode_init = x86_64_probe_apic; 1406 x86_init.oem.arch_setup = xen_arch_setup; 1407 x86_init.oem.banner = xen_banner; 1408 x86_init.hyper.init_platform = xen_pv_init_platform; 1409 x86_init.hyper.guest_late_init = xen_pv_guest_late_init; 1410 1411 /* 1412 * Set up some pagetable state before starting to set any ptes. 1413 */ 1414 1415 xen_setup_machphys_mapping(); 1416 xen_init_mmu_ops(); 1417 1418 /* Prevent unwanted bits from being set in PTEs. */ 1419 __supported_pte_mask &= ~_PAGE_GLOBAL; 1420 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 1421 1422 /* Get mfn list */ 1423 xen_build_dynamic_phys_to_machine(); 1424 1425 /* Work out if we support NX */ 1426 cpuid_scan_cpu(&boot_cpu_data); 1427 get_cpu_cap(&boot_cpu_data); 1428 x86_configure_nx(); 1429 1430 /* 1431 * Set up kernel GDT and segment registers, mainly so that 1432 * -fstack-protector code can be executed. 1433 */ 1434 xen_setup_gdt(0); 1435 1436 /* Determine virtual and physical address sizes */ 1437 get_cpu_address_sizes(&boot_cpu_data); 1438 1439 /* Let's presume PV guests always boot on vCPU with id 0. */ 1440 per_cpu(xen_vcpu_id, 0) = 0; 1441 1442 idt_setup_early_handler(); 1443 1444 xen_init_capabilities(); 1445 1446 /* 1447 * set up the basic apic ops. 1448 */ 1449 xen_init_apic(); 1450 1451 machine_ops = xen_machine_ops; 1452 1453 /* 1454 * The only reliable way to retain the initial address of the 1455 * percpu gdt_page is to remember it here, so we can go and 1456 * mark it RW later, when the initial percpu area is freed. 1457 */ 1458 xen_initial_gdt = &per_cpu(gdt_page, 0); 1459 1460 xen_smp_init(); 1461 1462 #ifdef CONFIG_ACPI_NUMA 1463 /* 1464 * The pages we from Xen are not related to machine pages, so 1465 * any NUMA information the kernel tries to get from ACPI will 1466 * be meaningless. Prevent it from trying. 1467 */ 1468 disable_srat(); 1469 #endif 1470 WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv)); 1471 1472 local_irq_disable(); 1473 1474 xen_raw_console_write("mapping kernel into physical memory\n"); 1475 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, 1476 xen_start_info->nr_pages); 1477 xen_reserve_special_pages(); 1478 1479 /* 1480 * We used to do this in xen_arch_setup, but that is too late 1481 * on AMD were early_cpu_init (run before ->arch_setup()) calls 1482 * early_amd_init which pokes 0xcf8 port. 1483 */ 1484 set_iopl.iopl = 1; 1485 rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl); 1486 if (rc != 0) 1487 xen_raw_printk("physdev_op failed %d\n", rc); 1488 1489 1490 if (xen_start_info->mod_start) { 1491 if (xen_start_info->flags & SIF_MOD_START_PFN) 1492 initrd_start = PFN_PHYS(xen_start_info->mod_start); 1493 else 1494 initrd_start = __pa(xen_start_info->mod_start); 1495 } 1496 1497 /* Poke various useful things into boot_params */ 1498 boot_params.hdr.type_of_loader = (9 << 4) | 0; 1499 boot_params.hdr.ramdisk_image = initrd_start; 1500 boot_params.hdr.ramdisk_size = xen_start_info->mod_len; 1501 boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line); 1502 boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN; 1503 1504 if (!xen_initial_domain()) { 1505 if (pci_xen) 1506 x86_init.pci.arch_init = pci_xen_init; 1507 x86_platform.set_legacy_features = 1508 xen_domu_set_legacy_features; 1509 } else { 1510 const struct dom0_vga_console_info *info = 1511 (void *)((char *)xen_start_info + 1512 xen_start_info->console.dom0.info_off); 1513 struct xen_platform_op op = { 1514 .cmd = XENPF_firmware_info, 1515 .interface_version = XENPF_INTERFACE_VERSION, 1516 .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS, 1517 }; 1518 1519 x86_platform.set_legacy_features = 1520 xen_dom0_set_legacy_features; 1521 xen_init_vga(info, xen_start_info->console.dom0.info_size, 1522 &boot_params.screen_info); 1523 xen_start_info->console.domU.mfn = 0; 1524 xen_start_info->console.domU.evtchn = 0; 1525 1526 if (HYPERVISOR_platform_op(&op) == 0) 1527 boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags; 1528 1529 /* Make sure ACS will be enabled */ 1530 pci_request_acs(); 1531 1532 xen_acpi_sleep_register(); 1533 1534 xen_boot_params_init_edd(); 1535 1536 #ifdef CONFIG_ACPI 1537 /* 1538 * Disable selecting "Firmware First mode" for correctable 1539 * memory errors, as this is the duty of the hypervisor to 1540 * decide. 1541 */ 1542 acpi_disable_cmcff = 1; 1543 #endif 1544 } 1545 1546 xen_add_preferred_consoles(); 1547 1548 #ifdef CONFIG_PCI 1549 /* PCI BIOS service won't work from a PV guest. */ 1550 pci_probe &= ~PCI_PROBE_BIOS; 1551 #endif 1552 xen_raw_console_write("about to get started...\n"); 1553 1554 /* We need this for printk timestamps */ 1555 xen_setup_runstate_info(0); 1556 1557 xen_efi_init(&boot_params); 1558 1559 /* Start the world */ 1560 cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */ 1561 x86_64_start_reservations((char *)__pa_symbol(&boot_params)); 1562 } 1563 1564 static int xen_cpu_up_prepare_pv(unsigned int cpu) 1565 { 1566 int rc; 1567 1568 if (per_cpu(xen_vcpu, cpu) == NULL) 1569 return -ENODEV; 1570 1571 xen_setup_timer(cpu); 1572 1573 rc = xen_smp_intr_init(cpu); 1574 if (rc) { 1575 WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n", 1576 cpu, rc); 1577 return rc; 1578 } 1579 1580 rc = xen_smp_intr_init_pv(cpu); 1581 if (rc) { 1582 WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n", 1583 cpu, rc); 1584 return rc; 1585 } 1586 1587 return 0; 1588 } 1589 1590 static int xen_cpu_dead_pv(unsigned int cpu) 1591 { 1592 xen_smp_intr_free(cpu); 1593 xen_smp_intr_free_pv(cpu); 1594 1595 xen_teardown_timer(cpu); 1596 1597 return 0; 1598 } 1599 1600 static uint32_t __init xen_platform_pv(void) 1601 { 1602 if (xen_pv_domain()) 1603 return xen_cpuid_base(); 1604 1605 return 0; 1606 } 1607 1608 const __initconst struct hypervisor_x86 x86_hyper_xen_pv = { 1609 .name = "Xen PV", 1610 .detect = xen_platform_pv, 1611 .type = X86_HYPER_XEN_PV, 1612 .runtime.pin_vcpu = xen_pin_vcpu, 1613 .ignore_nopv = true, 1614 }; 1615