1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board. 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 12#include "rzg3s-smarc-switches.h" 13 14/ { 15 compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; 16 17 aliases { 18 i2c1 = &i2c1; 19 mmc0 = &sdhi0; 20#if SW_CONFIG3 == SW_OFF 21 mmc2 = &sdhi2; 22#else 23 ethernet0 = ð0; 24 ethernet1 = ð1; 25#endif 26 }; 27 28 memory@48000000 { 29 device_type = "memory"; 30 /* First 128MB is reserved for secure area. */ 31 reg = <0x0 0x48000000 0x0 0x38000000>; 32 }; 33 34 vcc_sdhi0: regulator0 { 35 compatible = "regulator-fixed"; 36 regulator-name = "SDHI0 Vcc"; 37 regulator-min-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>; 39 gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>; 40 enable-active-high; 41 }; 42 43 vccq_sdhi0: regulator1 { 44 compatible = "regulator-gpio"; 45 regulator-name = "SDHI0 VccQ"; 46 regulator-min-microvolt = <1800000>; 47 regulator-max-microvolt = <3300000>; 48 gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>; 49 gpios-states = <1>; 50 states = <3300000 1>, <1800000 0>; 51 }; 52 53 reg_1p8v: regulator2 { 54 compatible = "regulator-fixed"; 55 regulator-name = "fixed-1.8V"; 56 regulator-min-microvolt = <1800000>; 57 regulator-max-microvolt = <1800000>; 58 regulator-boot-on; 59 regulator-always-on; 60 }; 61 62 reg_3p3v: regulator3 { 63 compatible = "regulator-fixed"; 64 regulator-name = "fixed-3.3V"; 65 regulator-min-microvolt = <3300000>; 66 regulator-max-microvolt = <3300000>; 67 regulator-boot-on; 68 regulator-always-on; 69 }; 70 71 vcc_sdhi2: regulator4 { 72 compatible = "regulator-fixed"; 73 regulator-name = "SDHI2 Vcc"; 74 regulator-min-microvolt = <3300000>; 75 regulator-max-microvolt = <3300000>; 76 gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>; 77 enable-active-high; 78 }; 79 80 x3_clk: x3-clock { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <24000000>; 84 }; 85}; 86 87#if SW_CONFIG3 == SW_ON 88ð0 { 89 pinctrl-0 = <ð0_pins>; 90 pinctrl-names = "default"; 91 phy-handle = <&phy0>; 92 phy-mode = "rgmii-id"; 93 status = "okay"; 94 95 phy0: ethernet-phy@7 { 96 reg = <7>; 97 interrupts-extended = <&pinctrl RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>; 98 rxc-skew-psec = <0>; 99 txc-skew-psec = <0>; 100 rxdv-skew-psec = <0>; 101 txen-skew-psec = <0>; 102 rxd0-skew-psec = <0>; 103 rxd1-skew-psec = <0>; 104 rxd2-skew-psec = <0>; 105 rxd3-skew-psec = <0>; 106 txd0-skew-psec = <0>; 107 txd1-skew-psec = <0>; 108 txd2-skew-psec = <0>; 109 txd3-skew-psec = <0>; 110 }; 111}; 112 113ð1 { 114 pinctrl-0 = <ð1_pins>; 115 pinctrl-names = "default"; 116 phy-handle = <&phy1>; 117 phy-mode = "rgmii-id"; 118 status = "okay"; 119 120 phy1: ethernet-phy@7 { 121 reg = <7>; 122 interrupts-extended = <&pinctrl RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>; 123 rxc-skew-psec = <0>; 124 txc-skew-psec = <0>; 125 rxdv-skew-psec = <0>; 126 txen-skew-psec = <0>; 127 rxd0-skew-psec = <0>; 128 rxd1-skew-psec = <0>; 129 rxd2-skew-psec = <0>; 130 rxd3-skew-psec = <0>; 131 txd0-skew-psec = <0>; 132 txd1-skew-psec = <0>; 133 txd2-skew-psec = <0>; 134 txd3-skew-psec = <0>; 135 }; 136}; 137#endif 138 139&extal_clk { 140 clock-frequency = <24000000>; 141}; 142 143&i2c1 { 144 status = "okay"; 145 146 versa3: clock-generator@68 { 147 compatible = "renesas,5l35023"; 148 reg = <0x68>; 149 clocks = <&x3_clk>; 150 #clock-cells = <1>; 151 assigned-clocks = <&versa3 0>, 152 <&versa3 1>, 153 <&versa3 2>, 154 <&versa3 3>, 155 <&versa3 4>, 156 <&versa3 5>; 157 assigned-clock-rates = <24000000>, 158 <12288000>, 159 <11289600>, 160 <25000000>, 161 <100000000>, 162 <100000000>; 163 renesas,settings = [ 164 80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27 165 00 40 00 00 00 00 00 00 06 0c 19 02 3b f0 90 86 166 a0 80 30 30 9c 167 ]; 168 }; 169}; 170 171&pcie_port0 { 172 clocks = <&versa3 5>; 173 clock-names = "ref"; 174}; 175 176#if SW_CONFIG2 == SW_ON 177/* SD0 slot */ 178&sdhi0 { 179 pinctrl-0 = <&sdhi0_pins>; 180 pinctrl-1 = <&sdhi0_uhs_pins>; 181 pinctrl-names = "default", "state_uhs"; 182 vmmc-supply = <&vcc_sdhi0>; 183 vqmmc-supply = <&vccq_sdhi0>; 184 bus-width = <4>; 185 sd-uhs-sdr50; 186 sd-uhs-sdr104; 187 max-frequency = <125000000>; 188 status = "okay"; 189}; 190#else 191/* eMMC */ 192&sdhi0 { 193 pinctrl-0 = <&sdhi0_emmc_pins>; 194 pinctrl-1 = <&sdhi0_emmc_pins>; 195 pinctrl-names = "default", "state_uhs"; 196 vmmc-supply = <&vcc_sdhi0>; 197 vqmmc-supply = <®_1p8v>; 198 bus-width = <8>; 199 mmc-hs200-1_8v; 200 non-removable; 201 fixed-emmc-driver-type = <1>; 202 max-frequency = <125000000>; 203 status = "okay"; 204}; 205#endif 206 207#if SW_CONFIG3 == SW_OFF 208&sdhi2 { 209 pinctrl-0 = <&sdhi2_pins>; 210 pinctrl-names = "default"; 211 vmmc-supply = <&vcc_sdhi2>; 212 bus-width = <4>; 213 max-frequency = <50000000>; 214 status = "okay"; 215}; 216#endif 217 218&pinctrl { 219#if SW_CONFIG3 == SW_ON 220 eth0-phy-irq-hog { 221 gpio-hog; 222 gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>; 223 input; 224 line-name = "eth0-phy-irq"; 225 }; 226#endif 227 228 eth0_pins: eth0 { 229 txc { 230 pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */ 231 power-source = <1800>; 232 output-enable; 233 input-enable; 234 drive-strength-microamp = <5200>; 235 }; 236 237 tx_ctl { 238 pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* ET0_TX_CTL */ 239 power-source = <1800>; 240 output-enable; 241 drive-strength-microamp = <5200>; 242 }; 243 244 mux { 245 pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */ 246 <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */ 247 <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */ 248 <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */ 249 <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */ 250 <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */ 251 <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */ 252 <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */ 253 <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */ 254 <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */ 255 <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */ 256 <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */ 257 <RZG2L_PORT_PINMUX(4, 5, 1)>; /* ET0_LINKSTA */ 258 power-source = <1800>; 259 }; 260 }; 261 262#if SW_CONFIG3 == SW_ON 263 eth1-phy-irq-hog { 264 gpio-hog; 265 gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>; 266 input; 267 line-name = "eth1-phy-irq"; 268 }; 269#endif 270 271 eth1_pins: eth1 { 272 txc { 273 pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */ 274 power-source = <1800>; 275 output-enable; 276 input-enable; 277 drive-strength-microamp = <5200>; 278 }; 279 280 tx_ctl { 281 pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>; /* ET1_TX_CTL */ 282 power-source = <1800>; 283 output-enable; 284 drive-strength-microamp = <5200>; 285 }; 286 287 mux { 288 pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */ 289 <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */ 290 <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */ 291 <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */ 292 <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */ 293 <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */ 294 <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */ 295 <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */ 296 <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */ 297 <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */ 298 <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */ 299 <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */ 300 <RZG2L_PORT_PINMUX(10, 4, 1)>; /* ET1_LINKSTA */ 301 power-source = <1800>; 302 }; 303 }; 304 305 sdhi0_pins: sd0 { 306 data { 307 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 308 power-source = <3300>; 309 }; 310 311 ctrl { 312 pins = "SD0_CLK", "SD0_CMD"; 313 power-source = <3300>; 314 }; 315 316 cd { 317 pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ 318 }; 319 }; 320 321 sdhi0_uhs_pins: sd0-uhs { 322 data { 323 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 324 power-source = <1800>; 325 }; 326 327 ctrl { 328 pins = "SD0_CLK", "SD0_CMD"; 329 power-source = <1800>; 330 }; 331 332 cd { 333 pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ 334 }; 335 }; 336 337 sdhi0_emmc_pins: sd0-emmc { 338 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", 339 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7", 340 "SD0_CLK", "SD0_CMD", "SD0_RST#"; 341 power-source = <1800>; 342 }; 343 344 sdhi2_pins: sd2 { 345 data { 346 pins = "P11_2", "P11_3", "P12_0", "P12_1"; 347 input-enable; 348 }; 349 350 ctrl { 351 pins = "P11_1"; 352 input-enable; 353 }; 354 355 mux { 356 pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */ 357 <RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */ 358 <RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */ 359 <RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */ 360 <RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */ 361 <RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */ 362 <RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */ 363 }; 364 }; 365}; 366 367&rtc { 368 status = "okay"; 369}; 370 371&vbattb { 372 assigned-clocks = <&vbattb VBATTB_MUX>; 373 assigned-clock-parents = <&vbattb VBATTB_XC>; 374 quartz-load-femtofarads = <12500>; 375 status = "okay"; 376}; 377 378&vbattb_xtal { 379 clock-frequency = <32768>; 380}; 381 382&wdt0 { 383 timeout-sec = <60>; 384 status = "okay"; 385}; 386