1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7
8 #include <linux/bitfield.h>
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <linux/refcount.h>
17 #include <linux/crash_dump.h>
18 #include <linux/trace_events.h>
19 #include <linux/trace.h>
20 #include <linux/irq.h>
21
22 #include <scsi/scsi_tcq.h>
23 #include <scsi/scsicam.h>
24 #include <scsi/scsi_transport.h>
25 #include <scsi/scsi_transport_fc.h>
26
27 #include "qla_target.h"
28
29 /*
30 * Driver version
31 */
32 char qla2x00_version_str[40];
33
34 static int apidev_major;
35
36 /*
37 * SRB allocation cache
38 */
39 struct kmem_cache *srb_cachep;
40
41 static struct trace_array *qla_trc_array;
42
43 int ql2xfulldump_on_mpifail;
44 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
46 "Set this to take full dump on MPI hang.");
47
48 int ql2xenforce_iocb_limit = 2;
49 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
50 MODULE_PARM_DESC(ql2xenforce_iocb_limit,
51 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) "
52 "1: track usage per queue, 2: track usage per adapter");
53
54 /*
55 * CT6 CTX allocation cache
56 */
57 static struct kmem_cache *ctx_cachep;
58 /*
59 * error level for logging
60 */
61 uint ql_errlev = 0x8001;
62
63 int ql2xsecenable;
64 module_param(ql2xsecenable, int, S_IRUGO);
65 MODULE_PARM_DESC(ql2xsecenable,
66 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
67
68 static int ql2xenableclass2;
69 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
70 MODULE_PARM_DESC(ql2xenableclass2,
71 "Specify if Class 2 operations are supported from the very "
72 "beginning. Default is 0 - class 2 not supported.");
73
74
75 int ql2xlogintimeout = 20;
76 module_param(ql2xlogintimeout, int, S_IRUGO);
77 MODULE_PARM_DESC(ql2xlogintimeout,
78 "Login timeout value in seconds.");
79
80 int qlport_down_retry;
81 module_param(qlport_down_retry, int, S_IRUGO);
82 MODULE_PARM_DESC(qlport_down_retry,
83 "Maximum number of command retries to a port that returns "
84 "a PORT-DOWN status.");
85
86 int ql2xplogiabsentdevice;
87 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
88 MODULE_PARM_DESC(ql2xplogiabsentdevice,
89 "Option to enable PLOGI to devices that are not present after "
90 "a Fabric scan. This is needed for several broken switches. "
91 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
92
93 int ql2xloginretrycount;
94 module_param(ql2xloginretrycount, int, S_IRUGO);
95 MODULE_PARM_DESC(ql2xloginretrycount,
96 "Specify an alternate value for the NVRAM login retry count.");
97
98 int ql2xallocfwdump = 1;
99 module_param(ql2xallocfwdump, int, S_IRUGO);
100 MODULE_PARM_DESC(ql2xallocfwdump,
101 "Option to enable allocation of memory for a firmware dump "
102 "during HBA initialization. Memory allocation requirements "
103 "vary by ISP type. Default is 1 - allocate memory.");
104
105 int ql2xextended_error_logging;
106 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
107 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
108 MODULE_PARM_DESC(ql2xextended_error_logging,
109 "Option to enable extended error logging,\n"
110 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
111 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
112 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
113 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
114 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
115 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
116 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
117 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
118 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
119 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
120 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
121 "\t\t0x1e400000 - Preferred value for capturing essential "
122 "debug information (equivalent to old "
123 "ql2xextended_error_logging=1).\n"
124 "\t\tDo LOGICAL OR of the value to enable more than one level");
125
126 int ql2xextended_error_logging_ktrace = 1;
127 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR);
128 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace,
129 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n");
130
131 int ql2xshiftctondsd = 6;
132 module_param(ql2xshiftctondsd, int, S_IRUGO);
133 MODULE_PARM_DESC(ql2xshiftctondsd,
134 "Set to control shifting of command type processing "
135 "based on total number of SG elements.");
136
137 int ql2xfdmienable = 1;
138 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
139 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
140 MODULE_PARM_DESC(ql2xfdmienable,
141 "Enables FDMI registrations. "
142 "0 - no FDMI registrations. "
143 "1 - provide FDMI registrations (default).");
144
145 #define MAX_Q_DEPTH 64
146 static int ql2xmaxqdepth = MAX_Q_DEPTH;
147 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
148 MODULE_PARM_DESC(ql2xmaxqdepth,
149 "Maximum queue depth to set for each LUN. "
150 "Default is 64.");
151
152 int ql2xenabledif = 2;
153 module_param(ql2xenabledif, int, S_IRUGO);
154 MODULE_PARM_DESC(ql2xenabledif,
155 " Enable T10-CRC-DIF:\n"
156 " Default is 2.\n"
157 " 0 -- No DIF Support\n"
158 " 1 -- Enable DIF for all types\n"
159 " 2 -- Enable DIF for all types, except Type 0.\n");
160
161 #if (IS_ENABLED(CONFIG_NVME_FC))
162 int ql2xnvmeenable = 1;
163 #else
164 int ql2xnvmeenable;
165 #endif
166 module_param(ql2xnvmeenable, int, 0644);
167 MODULE_PARM_DESC(ql2xnvmeenable,
168 "Enables NVME support. "
169 "0 - no NVMe. Default is Y");
170
171 int ql2xenablehba_err_chk = 2;
172 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
173 MODULE_PARM_DESC(ql2xenablehba_err_chk,
174 " Enable T10-CRC-DIF Error isolation by HBA:\n"
175 " Default is 2.\n"
176 " 0 -- Error isolation disabled\n"
177 " 1 -- Error isolation enabled only for DIX Type 0\n"
178 " 2 -- Error isolation enabled for all Types\n");
179
180 int ql2xmqsupport = 1;
181 module_param(ql2xmqsupport, int, S_IRUGO);
182 MODULE_PARM_DESC(ql2xmqsupport,
183 "Enable on demand multiple queue pairs support "
184 "Default is 1 for supported. "
185 "Set it to 0 to turn off mq qpair support.");
186
187 int ql2xfwloadbin;
188 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
189 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
190 MODULE_PARM_DESC(ql2xfwloadbin,
191 "Option to specify location from which to load ISP firmware:.\n"
192 " 2 -- load firmware via the request_firmware() (hotplug).\n"
193 " interface.\n"
194 " 1 -- load firmware from flash.\n"
195 " 0 -- use default semantics.\n");
196
197 int ql2xdbwr = 1;
198 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
199 MODULE_PARM_DESC(ql2xdbwr,
200 "Option to specify scheme for request queue posting.\n"
201 " 0 -- Regular doorbell.\n"
202 " 1 -- CAMRAM doorbell (faster).\n");
203
204 int ql2xgffidenable;
205 module_param(ql2xgffidenable, int, S_IRUGO);
206 MODULE_PARM_DESC(ql2xgffidenable,
207 "Enables GFF_ID checks of port type. "
208 "Default is 0 - Do not use GFF_ID information.");
209
210 int ql2xasynctmfenable = 1;
211 module_param(ql2xasynctmfenable, int, S_IRUGO);
212 MODULE_PARM_DESC(ql2xasynctmfenable,
213 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
214 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
215
216 int ql2xdontresethba;
217 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
218 MODULE_PARM_DESC(ql2xdontresethba,
219 "Option to specify reset behaviour.\n"
220 " 0 (Default) -- Reset on failure.\n"
221 " 1 -- Do not reset on failure.\n");
222
223 uint64_t ql2xmaxlun = MAX_LUNS;
224 module_param(ql2xmaxlun, ullong, S_IRUGO);
225 MODULE_PARM_DESC(ql2xmaxlun,
226 "Defines the maximum LU number to register with the SCSI "
227 "midlayer. Default is 65535.");
228
229 int ql2xmdcapmask = 0x1F;
230 module_param(ql2xmdcapmask, int, S_IRUGO);
231 MODULE_PARM_DESC(ql2xmdcapmask,
232 "Set the Minidump driver capture mask level. "
233 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
234
235 int ql2xmdenable = 1;
236 module_param(ql2xmdenable, int, S_IRUGO);
237 MODULE_PARM_DESC(ql2xmdenable,
238 "Enable/disable MiniDump. "
239 "0 - MiniDump disabled. "
240 "1 (Default) - MiniDump enabled.");
241
242 int ql2xexlogins;
243 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
244 MODULE_PARM_DESC(ql2xexlogins,
245 "Number of extended Logins. "
246 "0 (Default)- Disabled.");
247
248 int ql2xexchoffld = 1024;
249 module_param(ql2xexchoffld, uint, 0644);
250 MODULE_PARM_DESC(ql2xexchoffld,
251 "Number of target exchanges.");
252
253 int ql2xiniexchg = 1024;
254 module_param(ql2xiniexchg, uint, 0644);
255 MODULE_PARM_DESC(ql2xiniexchg,
256 "Number of initiator exchanges.");
257
258 int ql2xfwholdabts;
259 module_param(ql2xfwholdabts, int, S_IRUGO);
260 MODULE_PARM_DESC(ql2xfwholdabts,
261 "Allow FW to hold status IOCB until ABTS rsp received. "
262 "0 (Default) Do not set fw option. "
263 "1 - Set fw option to hold ABTS.");
264
265 int ql2xmvasynctoatio = 1;
266 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
267 MODULE_PARM_DESC(ql2xmvasynctoatio,
268 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
269 "0 (Default). Do not move IOCBs"
270 "1 - Move IOCBs.");
271
272 int ql2xautodetectsfp = 1;
273 module_param(ql2xautodetectsfp, int, 0444);
274 MODULE_PARM_DESC(ql2xautodetectsfp,
275 "Detect SFP range and set appropriate distance.\n"
276 "1 (Default): Enable\n");
277
278 int ql2xenablemsix = 1;
279 module_param(ql2xenablemsix, int, 0444);
280 MODULE_PARM_DESC(ql2xenablemsix,
281 "Set to enable MSI or MSI-X interrupt mechanism.\n"
282 " Default is 1, enable MSI-X interrupt mechanism.\n"
283 " 0 -- enable traditional pin-based mechanism.\n"
284 " 1 -- enable MSI-X interrupt mechanism.\n"
285 " 2 -- enable MSI interrupt mechanism.\n");
286
287 int qla2xuseresexchforels;
288 module_param(qla2xuseresexchforels, int, 0444);
289 MODULE_PARM_DESC(qla2xuseresexchforels,
290 "Reserve 1/2 of emergency exchanges for ELS.\n"
291 " 0 (default): disabled");
292
293 static int ql2xprotmask;
294 module_param(ql2xprotmask, int, 0644);
295 MODULE_PARM_DESC(ql2xprotmask,
296 "Override DIF/DIX protection capabilities mask\n"
297 "Default is 0 which sets protection mask based on "
298 "capabilities reported by HBA firmware.\n");
299
300 static int ql2xprotguard;
301 module_param(ql2xprotguard, int, 0644);
302 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
303 " 0 -- Let HBA firmware decide\n"
304 " 1 -- Force T10 CRC\n"
305 " 2 -- Force IP checksum\n");
306
307 int ql2xdifbundlinginternalbuffers;
308 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
309 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
310 "Force using internal buffers for DIF information\n"
311 "0 (Default). Based on check.\n"
312 "1 Force using internal buffers\n");
313
314 int ql2xsmartsan;
315 module_param(ql2xsmartsan, int, 0444);
316 module_param_named(smartsan, ql2xsmartsan, int, 0444);
317 MODULE_PARM_DESC(ql2xsmartsan,
318 "Send SmartSAN Management Attributes for FDMI Registration."
319 " Default is 0 - No SmartSAN registration,"
320 " 1 - Register SmartSAN Management Attributes.");
321
322 int ql2xrdpenable;
323 module_param(ql2xrdpenable, int, 0444);
324 module_param_named(rdpenable, ql2xrdpenable, int, 0444);
325 MODULE_PARM_DESC(ql2xrdpenable,
326 "Enables RDP responses. "
327 "0 - no RDP responses (default). "
328 "1 - provide RDP responses.");
329 int ql2xabts_wait_nvme = 1;
330 module_param(ql2xabts_wait_nvme, int, 0444);
331 MODULE_PARM_DESC(ql2xabts_wait_nvme,
332 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)");
333
334
335 static u32 ql2xdelay_before_pci_error_handling = 5;
336 module_param(ql2xdelay_before_pci_error_handling, uint, 0644);
337 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling,
338 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");
339
340 static void qla2x00_clear_drv_active(struct qla_hw_data *);
341 static void qla2x00_free_device(scsi_qla_host_t *);
342 static void qla2xxx_map_queues(struct Scsi_Host *shost);
343 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
344
345 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES;
346 module_param(ql2xnvme_queues, uint, S_IRUGO);
347 MODULE_PARM_DESC(ql2xnvme_queues,
348 "Number of NVMe Queues that can be configured.\n"
349 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n"
350 "1 - Minimum number of queues supported\n"
351 "8 - Default value");
352
353 int ql2xfc2target = 1;
354 module_param(ql2xfc2target, int, 0444);
355 MODULE_PARM_DESC(qla2xfc2target,
356 "Enables FC2 Target support. "
357 "0 - FC2 Target support is disabled. "
358 "1 - FC2 Target support is enabled (default).");
359
360 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
361 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
362
363 /* TODO Convert to inlines
364 *
365 * Timer routines
366 */
367
368 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,unsigned long interval)369 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
370 {
371 timer_setup(&vha->timer, qla2x00_timer, 0);
372 vha->timer.expires = jiffies + interval * HZ;
373 add_timer(&vha->timer);
374 vha->timer_active = 1;
375 }
376
377 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)378 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
379 {
380 /* Currently used for 82XX only. */
381 if (vha->device_flags & DFLG_DEV_FAILED) {
382 ql_dbg(ql_dbg_timer, vha, 0x600d,
383 "Device in a failed state, returning.\n");
384 return;
385 }
386
387 mod_timer(&vha->timer, jiffies + interval * HZ);
388 }
389
390 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)391 qla2x00_stop_timer(scsi_qla_host_t *vha)
392 {
393 timer_delete_sync(&vha->timer);
394 vha->timer_active = 0;
395 }
396
397 static int qla2x00_do_dpc(void *data);
398
399 static void qla2x00_rst_aen(scsi_qla_host_t *);
400
401 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
402 struct req_que **, struct rsp_que **);
403 static void qla2x00_free_fw_dump(struct qla_hw_data *);
404 static void qla2x00_mem_free(struct qla_hw_data *);
405 static enum scsi_qc_status qla2xxx_mqueuecommand(struct Scsi_Host *host,
406 struct scsi_cmnd *cmd,
407 struct qla_qpair *qpair);
408
409 /* -------------------------------------------------------------------------- */
qla_init_base_qpair(struct scsi_qla_host * vha,struct req_que * req,struct rsp_que * rsp)410 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
411 struct rsp_que *rsp)
412 {
413 struct qla_hw_data *ha = vha->hw;
414
415 rsp->qpair = ha->base_qpair;
416 rsp->req = req;
417 ha->base_qpair->hw = ha;
418 ha->base_qpair->req = req;
419 ha->base_qpair->rsp = rsp;
420 ha->base_qpair->vha = vha;
421 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
422 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
423 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
424 ha->base_qpair->srb_mempool = ha->srb_mempool;
425 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
426 INIT_LIST_HEAD(&ha->base_qpair->dsd_list);
427 ha->base_qpair->enable_class_2 = ql2xenableclass2;
428 /* init qpair to this cpu. Will adjust at run time. */
429 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
430 ha->base_qpair->pdev = ha->pdev;
431
432 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
433 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
434 }
435
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)436 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
437 struct rsp_que *rsp)
438 {
439 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
440
441 ha->req_q_map = kzalloc_objs(struct req_que *, ha->max_req_queues);
442 if (!ha->req_q_map) {
443 ql_log(ql_log_fatal, vha, 0x003b,
444 "Unable to allocate memory for request queue ptrs.\n");
445 goto fail_req_map;
446 }
447
448 ha->rsp_q_map = kzalloc_objs(struct rsp_que *, ha->max_rsp_queues);
449 if (!ha->rsp_q_map) {
450 ql_log(ql_log_fatal, vha, 0x003c,
451 "Unable to allocate memory for response queue ptrs.\n");
452 goto fail_rsp_map;
453 }
454
455 ha->base_qpair = kzalloc_obj(struct qla_qpair);
456 if (ha->base_qpair == NULL) {
457 ql_log(ql_log_warn, vha, 0x00e0,
458 "Failed to allocate base queue pair memory.\n");
459 goto fail_base_qpair;
460 }
461
462 qla_init_base_qpair(vha, req, rsp);
463
464 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
465 ha->queue_pair_map = kzalloc_objs(struct qla_qpair *,
466 ha->max_qpairs);
467 if (!ha->queue_pair_map) {
468 ql_log(ql_log_fatal, vha, 0x0180,
469 "Unable to allocate memory for queue pair ptrs.\n");
470 goto fail_qpair_map;
471 }
472 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) {
473 kfree(ha->queue_pair_map);
474 ha->queue_pair_map = NULL;
475 goto fail_qpair_map;
476 }
477 }
478
479 /*
480 * Make sure we record at least the request and response queue zero in
481 * case we need to free them if part of the probe fails.
482 */
483 ha->rsp_q_map[0] = rsp;
484 ha->req_q_map[0] = req;
485 set_bit(0, ha->rsp_qid_map);
486 set_bit(0, ha->req_qid_map);
487 return 0;
488
489 fail_qpair_map:
490 kfree(ha->base_qpair);
491 ha->base_qpair = NULL;
492 fail_base_qpair:
493 kfree(ha->rsp_q_map);
494 ha->rsp_q_map = NULL;
495 fail_rsp_map:
496 kfree(ha->req_q_map);
497 ha->req_q_map = NULL;
498 fail_req_map:
499 return -ENOMEM;
500 }
501
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)502 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
503 {
504 if (IS_QLAFX00(ha)) {
505 if (req && req->ring_fx00)
506 dma_free_coherent(&ha->pdev->dev,
507 (req->length_fx00 + 1) * sizeof(request_t),
508 req->ring_fx00, req->dma_fx00);
509 } else if (req && req->ring)
510 dma_free_coherent(&ha->pdev->dev,
511 (req->length + 1) * sizeof(request_t),
512 req->ring, req->dma);
513
514 if (req)
515 kfree(req->outstanding_cmds);
516
517 kfree(req);
518 }
519
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)520 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
521 {
522 if (IS_QLAFX00(ha)) {
523 if (rsp && rsp->ring_fx00)
524 dma_free_coherent(&ha->pdev->dev,
525 (rsp->length_fx00 + 1) * sizeof(request_t),
526 rsp->ring_fx00, rsp->dma_fx00);
527 } else if (rsp && rsp->ring) {
528 dma_free_coherent(&ha->pdev->dev,
529 (rsp->length + 1) * sizeof(response_t),
530 rsp->ring, rsp->dma);
531 }
532 kfree(rsp);
533 }
534
qla2x00_free_queues(struct qla_hw_data * ha)535 static void qla2x00_free_queues(struct qla_hw_data *ha)
536 {
537 struct req_que *req;
538 struct rsp_que *rsp;
539 int cnt;
540 unsigned long flags;
541
542 if (ha->queue_pair_map) {
543 kfree(ha->queue_pair_map);
544 ha->queue_pair_map = NULL;
545 }
546 if (ha->base_qpair) {
547 kfree(ha->base_qpair);
548 ha->base_qpair = NULL;
549 }
550
551 qla_mapq_free_qp_cpu_map(ha);
552 spin_lock_irqsave(&ha->hardware_lock, flags);
553 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
554 if (!test_bit(cnt, ha->req_qid_map))
555 continue;
556
557 req = ha->req_q_map[cnt];
558 clear_bit(cnt, ha->req_qid_map);
559 ha->req_q_map[cnt] = NULL;
560
561 spin_unlock_irqrestore(&ha->hardware_lock, flags);
562 qla2x00_free_req_que(ha, req);
563 spin_lock_irqsave(&ha->hardware_lock, flags);
564 }
565 spin_unlock_irqrestore(&ha->hardware_lock, flags);
566
567 kfree(ha->req_q_map);
568 ha->req_q_map = NULL;
569
570
571 spin_lock_irqsave(&ha->hardware_lock, flags);
572 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
573 if (!test_bit(cnt, ha->rsp_qid_map))
574 continue;
575
576 rsp = ha->rsp_q_map[cnt];
577 clear_bit(cnt, ha->rsp_qid_map);
578 ha->rsp_q_map[cnt] = NULL;
579 spin_unlock_irqrestore(&ha->hardware_lock, flags);
580 qla2x00_free_rsp_que(ha, rsp);
581 spin_lock_irqsave(&ha->hardware_lock, flags);
582 }
583 spin_unlock_irqrestore(&ha->hardware_lock, flags);
584
585 kfree(ha->rsp_q_map);
586 ha->rsp_q_map = NULL;
587 }
588
589 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)590 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
591 {
592 struct qla_hw_data *ha = vha->hw;
593 static const char *const pci_bus_modes[] = {
594 "33", "66", "100", "133",
595 };
596 uint16_t pci_bus;
597
598 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
599 if (pci_bus) {
600 snprintf(str, str_len, "PCI-X (%s MHz)",
601 pci_bus_modes[pci_bus]);
602 } else {
603 pci_bus = (ha->pci_attr & BIT_8) >> 8;
604 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
605 }
606
607 return str;
608 }
609
610 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)611 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
612 {
613 static const char *const pci_bus_modes[] = {
614 "33", "66", "100", "133",
615 };
616 struct qla_hw_data *ha = vha->hw;
617 uint32_t pci_bus;
618
619 if (pci_is_pcie(ha->pdev)) {
620 uint32_t lstat, lspeed, lwidth;
621 const char *speed_str;
622
623 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
624 lspeed = FIELD_GET(PCI_EXP_LNKCAP_SLS, lstat);
625 lwidth = FIELD_GET(PCI_EXP_LNKCAP_MLW, lstat);
626
627 switch (lspeed) {
628 case 1:
629 speed_str = "2.5GT/s";
630 break;
631 case 2:
632 speed_str = "5.0GT/s";
633 break;
634 case 3:
635 speed_str = "8.0GT/s";
636 break;
637 case 4:
638 speed_str = "16.0GT/s";
639 break;
640 default:
641 speed_str = "<unknown>";
642 break;
643 }
644 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
645
646 return str;
647 }
648
649 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
650 if (pci_bus == 0 || pci_bus == 8)
651 snprintf(str, str_len, "PCI (%s MHz)",
652 pci_bus_modes[pci_bus >> 3]);
653 else
654 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
655 pci_bus & 4 ? 2 : 1,
656 pci_bus_modes[pci_bus & 3]);
657
658 return str;
659 }
660
661 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)662 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
663 {
664 char un_str[10];
665 struct qla_hw_data *ha = vha->hw;
666
667 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
668 ha->fw_minor_version, ha->fw_subminor_version);
669
670 if (ha->fw_attributes & BIT_9) {
671 strcat(str, "FLX");
672 return (str);
673 }
674
675 switch (ha->fw_attributes & 0xFF) {
676 case 0x7:
677 strcat(str, "EF");
678 break;
679 case 0x17:
680 strcat(str, "TP");
681 break;
682 case 0x37:
683 strcat(str, "IP");
684 break;
685 case 0x77:
686 strcat(str, "VI");
687 break;
688 default:
689 sprintf(un_str, "(%x)", ha->fw_attributes);
690 strcat(str, un_str);
691 break;
692 }
693 if (ha->fw_attributes & 0x100)
694 strcat(str, "X");
695
696 return (str);
697 }
698
699 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)700 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
701 {
702 struct qla_hw_data *ha = vha->hw;
703
704 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
705 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
706 return str;
707 }
708
qla2x00_sp_free_dma(srb_t * sp)709 void qla2x00_sp_free_dma(srb_t *sp)
710 {
711 struct qla_hw_data *ha = sp->vha->hw;
712 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
713
714 if (sp->flags & SRB_DMA_VALID) {
715 scsi_dma_unmap(cmd);
716 sp->flags &= ~SRB_DMA_VALID;
717 }
718
719 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
720 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
721 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
722 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
723 }
724
725 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
726 /* List assured to be having elements */
727 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
728 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
729 }
730
731 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
732 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
733
734 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
735 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
736 }
737
738 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
739 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
740
741 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
742 ctx1->fcp_cmnd_dma);
743 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
744 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
745 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
746 }
747
748 if (sp->flags & SRB_GOT_BUF)
749 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
750 }
751
qla2x00_sp_compl(srb_t * sp,int res)752 void qla2x00_sp_compl(srb_t *sp, int res)
753 {
754 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
755 struct completion *comp = sp->comp;
756
757 /* kref: INIT */
758 kref_put(&sp->cmd_kref, qla2x00_sp_release);
759 cmd->result = res;
760 sp->type = 0;
761 scsi_done(cmd);
762 if (comp)
763 complete(comp);
764 }
765
qla2xxx_qpair_sp_free_dma(srb_t * sp)766 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
767 {
768 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
769 struct qla_hw_data *ha = sp->fcport->vha->hw;
770
771 if (sp->flags & SRB_DMA_VALID) {
772 scsi_dma_unmap(cmd);
773 sp->flags &= ~SRB_DMA_VALID;
774 }
775
776 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
777 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
778 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
779 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
780 }
781
782 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
783 /* List assured to be having elements */
784 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
785 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
786 }
787
788 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
789 struct crc_context *difctx = sp->u.scmd.crc_ctx;
790 struct dsd_dma *dif_dsd, *nxt_dsd;
791
792 list_for_each_entry_safe(dif_dsd, nxt_dsd,
793 &difctx->ldif_dma_hndl_list, list) {
794 list_del(&dif_dsd->list);
795 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
796 dif_dsd->dsd_list_dma);
797 kfree(dif_dsd);
798 difctx->no_dif_bundl--;
799 }
800
801 list_for_each_entry_safe(dif_dsd, nxt_dsd,
802 &difctx->ldif_dsd_list, list) {
803 list_del(&dif_dsd->list);
804 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
805 dif_dsd->dsd_list_dma);
806 kfree(dif_dsd);
807 difctx->no_ldif_dsd--;
808 }
809
810 if (difctx->no_ldif_dsd) {
811 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
812 "%s: difctx->no_ldif_dsd=%x\n",
813 __func__, difctx->no_ldif_dsd);
814 }
815
816 if (difctx->no_dif_bundl) {
817 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
818 "%s: difctx->no_dif_bundl=%x\n",
819 __func__, difctx->no_dif_bundl);
820 }
821 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
822 }
823
824 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
825 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
826
827 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
828 ctx1->fcp_cmnd_dma);
829 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
830 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
831 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
832 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
833 }
834
835 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
836 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
837
838 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
839 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
840 }
841
842 if (sp->flags & SRB_GOT_BUF)
843 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
844 }
845
qla2xxx_qpair_sp_compl(srb_t * sp,int res)846 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
847 {
848 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
849 struct completion *comp = sp->comp;
850
851 /* ref: INIT */
852 kref_put(&sp->cmd_kref, qla2x00_sp_release);
853 cmd->result = res;
854 sp->type = 0;
855 scsi_done(cmd);
856 if (comp)
857 complete(comp);
858 }
859
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)860 static enum scsi_qc_status qla2xxx_queuecommand(struct Scsi_Host *host,
861 struct scsi_cmnd *cmd)
862 {
863 scsi_qla_host_t *vha = shost_priv(host);
864 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
865 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
866 struct qla_hw_data *ha = vha->hw;
867 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
868 srb_t *sp;
869 int rval;
870
871 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
872 WARN_ON_ONCE(!rport)) {
873 cmd->result = DID_NO_CONNECT << 16;
874 goto qc24_fail_command;
875 }
876
877 if (ha->mqenable) {
878 uint32_t tag;
879 uint16_t hwq;
880 struct qla_qpair *qpair = NULL;
881
882 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
883 hwq = blk_mq_unique_tag_to_hwq(tag);
884 qpair = ha->queue_pair_map[hwq];
885
886 if (qpair)
887 return qla2xxx_mqueuecommand(host, cmd, qpair);
888 }
889
890 if (ha->flags.eeh_busy) {
891 if (ha->flags.pci_channel_io_perm_failure) {
892 ql_dbg(ql_dbg_aer, vha, 0x9010,
893 "PCI Channel IO permanent failure, exiting "
894 "cmd=%p.\n", cmd);
895 cmd->result = DID_NO_CONNECT << 16;
896 } else {
897 ql_dbg(ql_dbg_aer, vha, 0x9011,
898 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
899 cmd->result = DID_REQUEUE << 16;
900 }
901 goto qc24_fail_command;
902 }
903
904 rval = fc_remote_port_chkready(rport);
905 if (rval) {
906 cmd->result = rval;
907 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
908 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
909 cmd, rval);
910 goto qc24_fail_command;
911 }
912
913 if (!vha->flags.difdix_supported &&
914 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
915 ql_dbg(ql_dbg_io, vha, 0x3004,
916 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
917 cmd);
918 cmd->result = DID_NO_CONNECT << 16;
919 goto qc24_fail_command;
920 }
921
922 if (!fcport || fcport->deleted) {
923 cmd->result = DID_IMM_RETRY << 16;
924 goto qc24_fail_command;
925 }
926
927 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
928 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
929 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
930 ql_dbg(ql_dbg_io, vha, 0x3005,
931 "Returning DNC, fcport_state=%d loop_state=%d.\n",
932 atomic_read(&fcport->state),
933 atomic_read(&base_vha->loop_state));
934 cmd->result = DID_NO_CONNECT << 16;
935 goto qc24_fail_command;
936 }
937 goto qc24_target_busy;
938 }
939
940 /*
941 * Return target busy if we've received a non-zero retry_delay_timer
942 * in a FCP_RSP.
943 */
944 if (fcport->retry_delay_timestamp == 0) {
945 /* retry delay not set */
946 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
947 fcport->retry_delay_timestamp = 0;
948 else
949 goto qc24_target_busy;
950
951 sp = scsi_cmd_priv(cmd);
952 /* ref: INIT */
953 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
954
955 sp->u.scmd.cmd = cmd;
956 sp->type = SRB_SCSI_CMD;
957 sp->free = qla2x00_sp_free_dma;
958 sp->done = qla2x00_sp_compl;
959
960 rval = ha->isp_ops->start_scsi(sp);
961 if (rval != QLA_SUCCESS) {
962 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
963 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
964 goto qc24_host_busy_free_sp;
965 }
966
967 return 0;
968
969 qc24_host_busy_free_sp:
970 /* ref: INIT */
971 kref_put(&sp->cmd_kref, qla2x00_sp_release);
972
973 qc24_target_busy:
974 return SCSI_MLQUEUE_TARGET_BUSY;
975
976 qc24_fail_command:
977 scsi_done(cmd);
978
979 return 0;
980 }
981
982 /* For MQ supported I/O */
983 static enum scsi_qc_status
qla2xxx_mqueuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd,struct qla_qpair * qpair)984 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
985 struct qla_qpair *qpair)
986 {
987 scsi_qla_host_t *vha = shost_priv(host);
988 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
989 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
990 struct qla_hw_data *ha = vha->hw;
991 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
992 srb_t *sp;
993 int rval;
994
995 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16);
996 if (rval) {
997 cmd->result = rval;
998 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
999 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
1000 cmd, rval);
1001 goto qc24_fail_command;
1002 }
1003
1004 if (!qpair->online) {
1005 ql_dbg(ql_dbg_io, vha, 0x3077,
1006 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
1007 cmd->result = DID_NO_CONNECT << 16;
1008 goto qc24_fail_command;
1009 }
1010
1011 if (!fcport || fcport->deleted) {
1012 cmd->result = DID_IMM_RETRY << 16;
1013 goto qc24_fail_command;
1014 }
1015
1016 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
1017 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1018 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1019 ql_dbg(ql_dbg_io, vha, 0x3077,
1020 "Returning DNC, fcport_state=%d loop_state=%d.\n",
1021 atomic_read(&fcport->state),
1022 atomic_read(&base_vha->loop_state));
1023 cmd->result = DID_NO_CONNECT << 16;
1024 goto qc24_fail_command;
1025 }
1026 goto qc24_target_busy;
1027 }
1028
1029 /*
1030 * Return target busy if we've received a non-zero retry_delay_timer
1031 * in a FCP_RSP.
1032 */
1033 if (fcport->retry_delay_timestamp == 0) {
1034 /* retry delay not set */
1035 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1036 fcport->retry_delay_timestamp = 0;
1037 else
1038 goto qc24_target_busy;
1039
1040 sp = scsi_cmd_priv(cmd);
1041 /* ref: INIT */
1042 qla2xxx_init_sp(sp, vha, qpair, fcport);
1043
1044 sp->u.scmd.cmd = cmd;
1045 sp->type = SRB_SCSI_CMD;
1046 sp->free = qla2xxx_qpair_sp_free_dma;
1047 sp->done = qla2xxx_qpair_sp_compl;
1048
1049 rval = ha->isp_ops->start_scsi_mq(sp);
1050 if (rval != QLA_SUCCESS) {
1051 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1052 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1053 goto qc24_host_busy_free_sp;
1054 }
1055
1056 return 0;
1057
1058 qc24_host_busy_free_sp:
1059 /* ref: INIT */
1060 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1061
1062 qc24_target_busy:
1063 return SCSI_MLQUEUE_TARGET_BUSY;
1064
1065 qc24_fail_command:
1066 scsi_done(cmd);
1067
1068 return 0;
1069 }
1070
1071 /*
1072 * qla2x00_wait_for_hba_online
1073 * Wait till the HBA is online after going through
1074 * <= MAX_RETRIES_OF_ISP_ABORT or
1075 * finally HBA is disabled ie marked offline
1076 *
1077 * Input:
1078 * ha - pointer to host adapter structure
1079 *
1080 * Note:
1081 * Does context switching-Release SPIN_LOCK
1082 * (if any) before calling this routine.
1083 *
1084 * Return:
1085 * Success (Adapter is online) : 0
1086 * Failed (Adapter is offline/disabled) : 1
1087 */
1088 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)1089 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1090 {
1091 int return_status;
1092 unsigned long wait_online;
1093 struct qla_hw_data *ha = vha->hw;
1094 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1095
1096 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1097 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1098 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1099 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1100 ha->dpc_active) && time_before(jiffies, wait_online)) {
1101
1102 msleep(1000);
1103 }
1104 if (base_vha->flags.online)
1105 return_status = QLA_SUCCESS;
1106 else
1107 return_status = QLA_FUNCTION_FAILED;
1108
1109 return (return_status);
1110 }
1111
test_fcport_count(scsi_qla_host_t * vha)1112 static inline int test_fcport_count(scsi_qla_host_t *vha)
1113 {
1114 struct qla_hw_data *ha = vha->hw;
1115 unsigned long flags;
1116 int res;
1117 /* Return 0 = sleep, x=wake */
1118
1119 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1120 ql_dbg(ql_dbg_init, vha, 0x00ec,
1121 "tgt %p, fcport_count=%d\n",
1122 vha, vha->fcport_count);
1123 res = (vha->fcport_count == 0);
1124 if (res) {
1125 struct fc_port *fcport;
1126
1127 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1128 if (fcport->deleted != QLA_SESS_DELETED) {
1129 /* session(s) may not be fully logged in
1130 * (ie fcport_count=0), but session
1131 * deletion thread(s) may be inflight.
1132 */
1133
1134 res = 0;
1135 break;
1136 }
1137 }
1138 }
1139 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1140
1141 return res;
1142 }
1143
1144 /*
1145 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1146 * it has dependency on UNLOADING flag to stop device discovery
1147 */
1148 void
qla2x00_wait_for_sess_deletion(scsi_qla_host_t * vha)1149 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1150 {
1151 u8 i;
1152
1153 qla2x00_mark_all_devices_lost(vha);
1154
1155 for (i = 0; i < 10; i++) {
1156 if (wait_event_timeout(vha->fcport_waitQ,
1157 test_fcport_count(vha), HZ) > 0)
1158 break;
1159 }
1160
1161 flush_workqueue(vha->hw->wq);
1162 }
1163
1164 /*
1165 * qla2x00_wait_for_hba_ready
1166 * Wait till the HBA is ready before doing driver unload
1167 *
1168 * Input:
1169 * ha - pointer to host adapter structure
1170 *
1171 * Note:
1172 * Does context switching-Release SPIN_LOCK
1173 * (if any) before calling this routine.
1174 *
1175 */
1176 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)1177 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1178 {
1179 struct qla_hw_data *ha = vha->hw;
1180 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1181
1182 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1183 ha->flags.mbox_busy) ||
1184 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1185 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags) ||
1186 (vha->scan.scan_flags & SF_SCANNING)) {
1187 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1188 break;
1189 msleep(1000);
1190 }
1191 }
1192
1193 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)1194 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1195 {
1196 int return_status;
1197 unsigned long wait_reset;
1198 struct qla_hw_data *ha = vha->hw;
1199 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1200
1201 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1202 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1203 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1204 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1205 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1206
1207 msleep(1000);
1208
1209 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1210 ha->flags.chip_reset_done)
1211 break;
1212 }
1213 if (ha->flags.chip_reset_done)
1214 return_status = QLA_SUCCESS;
1215 else
1216 return_status = QLA_FUNCTION_FAILED;
1217
1218 return return_status;
1219 }
1220
1221 /**************************************************************************
1222 * qla2xxx_eh_abort
1223 *
1224 * Description:
1225 * The abort function will abort the specified command.
1226 *
1227 * Input:
1228 * cmd = Linux SCSI command packet to be aborted.
1229 *
1230 * Returns:
1231 * Either SUCCESS or FAILED.
1232 *
1233 * Note:
1234 * Only return FAILED if command not returned by firmware.
1235 **************************************************************************/
1236 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)1237 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1238 {
1239 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1240 DECLARE_COMPLETION_ONSTACK(comp);
1241 srb_t *sp;
1242 int ret;
1243 unsigned int id;
1244 uint64_t lun;
1245 int rval;
1246 struct qla_hw_data *ha = vha->hw;
1247 uint32_t ratov_j;
1248 struct qla_qpair *qpair;
1249 unsigned long flags;
1250 int fast_fail_status = SUCCESS;
1251
1252 if (qla2x00_isp_reg_stat(ha)) {
1253 ql_log(ql_log_info, vha, 0x8042,
1254 "PCI/Register disconnect, exiting.\n");
1255 qla_pci_set_eeh_busy(vha);
1256 return FAILED;
1257 }
1258
1259 /* Save any FAST_IO_FAIL value to return later if abort succeeds */
1260 ret = fc_block_scsi_eh(cmd);
1261 if (ret != 0)
1262 fast_fail_status = ret;
1263
1264 sp = scsi_cmd_priv(cmd);
1265 qpair = sp->qpair;
1266
1267 vha->cmd_timeout_cnt++;
1268
1269 if ((sp->fcport && sp->fcport->deleted) || !qpair)
1270 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
1271
1272 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1273 sp->comp = ∁
1274 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1275
1276
1277 id = cmd->device->id;
1278 lun = cmd->device->lun;
1279
1280 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1281 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1282 vha->host_no, id, lun, sp, cmd, sp->handle);
1283
1284 /*
1285 * Abort will release the original Command/sp from FW. Let the
1286 * original command call scsi_done. In return, he will wakeup
1287 * this sleeping thread.
1288 */
1289 rval = ha->isp_ops->abort_command(sp);
1290
1291 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1292 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1293
1294 /* Wait for the command completion. */
1295 ratov_j = ha->r_a_tov / 10 * 4;
1296 ratov_j = secs_to_jiffies(ratov_j);
1297 switch (rval) {
1298 case QLA_SUCCESS:
1299 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1300 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1301 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1302 __func__, ha->r_a_tov/10);
1303 ret = FAILED;
1304 } else {
1305 ret = fast_fail_status;
1306 }
1307 break;
1308 default:
1309 ret = FAILED;
1310 break;
1311 }
1312
1313 sp->comp = NULL;
1314
1315 ql_log(ql_log_info, vha, 0x801c,
1316 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1317 vha->host_no, id, lun, ret);
1318
1319 return ret;
1320 }
1321
1322 #define ABORT_POLLING_PERIOD 1000
1323 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1324
1325 /*
1326 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1327 */
1328 static int
__qla2x00_eh_wait_for_pending_commands(struct qla_qpair * qpair,unsigned int t,uint64_t l,enum nexus_wait_type type)1329 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t,
1330 uint64_t l, enum nexus_wait_type type)
1331 {
1332 int cnt, match, status;
1333 unsigned long flags;
1334 scsi_qla_host_t *vha = qpair->vha;
1335 struct req_que *req = qpair->req;
1336 srb_t *sp;
1337 struct scsi_cmnd *cmd;
1338 unsigned long wait_iter = ABORT_WAIT_ITER;
1339 bool found;
1340 struct qla_hw_data *ha = vha->hw;
1341
1342 status = QLA_SUCCESS;
1343
1344 while (wait_iter--) {
1345 found = false;
1346
1347 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1348 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1349 sp = req->outstanding_cmds[cnt];
1350 if (!sp)
1351 continue;
1352 if (sp->type != SRB_SCSI_CMD)
1353 continue;
1354 if (vha->vp_idx != sp->vha->vp_idx)
1355 continue;
1356 match = 0;
1357 cmd = GET_CMD_SP(sp);
1358 switch (type) {
1359 case WAIT_HOST:
1360 match = 1;
1361 break;
1362 case WAIT_TARGET:
1363 if (sp->fcport)
1364 match = sp->fcport->d_id.b24 == t;
1365 else
1366 match = 0;
1367 break;
1368 case WAIT_LUN:
1369 if (sp->fcport)
1370 match = (sp->fcport->d_id.b24 == t &&
1371 cmd->device->lun == l);
1372 else
1373 match = 0;
1374 break;
1375 }
1376 if (!match)
1377 continue;
1378
1379 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1380
1381 if (unlikely(pci_channel_offline(ha->pdev)) ||
1382 ha->flags.eeh_busy) {
1383 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1384 "Return:eh_wait.\n");
1385 return status;
1386 }
1387
1388 /*
1389 * SRB_SCSI_CMD is still in the outstanding_cmds array.
1390 * it means scsi_done has not called. Wait for it to
1391 * clear from outstanding_cmds.
1392 */
1393 msleep(ABORT_POLLING_PERIOD);
1394 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1395 found = true;
1396 }
1397 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1398
1399 if (!found)
1400 break;
1401 }
1402
1403 if (wait_iter == -1)
1404 status = QLA_FUNCTION_FAILED;
1405
1406 return status;
1407 }
1408
1409 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1410 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1411 uint64_t l, enum nexus_wait_type type)
1412 {
1413 struct qla_qpair *qpair;
1414 struct qla_hw_data *ha = vha->hw;
1415 int i, status = QLA_SUCCESS;
1416
1417 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
1418 type);
1419 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
1420 qpair = ha->queue_pair_map[i];
1421 if (!qpair)
1422 continue;
1423 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l,
1424 type);
1425 }
1426 return status;
1427 }
1428
1429 static char *reset_errors[] = {
1430 "HBA not online",
1431 "HBA not ready",
1432 "Task management failed",
1433 "Waiting for command completions",
1434 };
1435
1436 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1437 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1438 {
1439 struct scsi_device *sdev = cmd->device;
1440 scsi_qla_host_t *vha = shost_priv(sdev->host);
1441 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1442 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1443 struct qla_hw_data *ha = vha->hw;
1444 int err;
1445
1446 if (qla2x00_isp_reg_stat(ha)) {
1447 ql_log(ql_log_info, vha, 0x803e,
1448 "PCI/Register disconnect, exiting.\n");
1449 qla_pci_set_eeh_busy(vha);
1450 return FAILED;
1451 }
1452
1453 if (!fcport) {
1454 return FAILED;
1455 }
1456
1457 err = fc_block_rport(rport);
1458 if (err != 0)
1459 return err;
1460
1461 if (fcport->deleted)
1462 return FAILED;
1463
1464 ql_log(ql_log_info, vha, 0x8009,
1465 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
1466 sdev->id, sdev->lun, cmd);
1467
1468 err = 0;
1469 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1470 ql_log(ql_log_warn, vha, 0x800a,
1471 "Wait for hba online failed for cmd=%p.\n", cmd);
1472 goto eh_reset_failed;
1473 }
1474 err = 2;
1475 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
1476 != QLA_SUCCESS) {
1477 ql_log(ql_log_warn, vha, 0x800c,
1478 "do_reset failed for cmd=%p.\n", cmd);
1479 goto eh_reset_failed;
1480 }
1481 err = 3;
1482 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24,
1483 cmd->device->lun,
1484 WAIT_LUN) != QLA_SUCCESS) {
1485 ql_log(ql_log_warn, vha, 0x800d,
1486 "wait for pending cmds failed for cmd=%p.\n", cmd);
1487 goto eh_reset_failed;
1488 }
1489
1490 ql_log(ql_log_info, vha, 0x800e,
1491 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n",
1492 vha->host_no, sdev->id, sdev->lun, cmd);
1493
1494 return SUCCESS;
1495
1496 eh_reset_failed:
1497 ql_log(ql_log_info, vha, 0x800f,
1498 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1499 reset_errors[err], vha->host_no, sdev->id, sdev->lun,
1500 cmd);
1501 vha->reset_cmd_err_cnt++;
1502 return FAILED;
1503 }
1504
1505 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1506 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1507 {
1508 struct scsi_device *sdev = cmd->device;
1509 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1510 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport));
1511 struct qla_hw_data *ha = vha->hw;
1512 fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
1513 int err;
1514
1515 if (qla2x00_isp_reg_stat(ha)) {
1516 ql_log(ql_log_info, vha, 0x803f,
1517 "PCI/Register disconnect, exiting.\n");
1518 qla_pci_set_eeh_busy(vha);
1519 return FAILED;
1520 }
1521
1522 if (!fcport) {
1523 return FAILED;
1524 }
1525
1526 err = fc_block_rport(rport);
1527 if (err != 0)
1528 return err;
1529
1530 if (fcport->deleted)
1531 return FAILED;
1532
1533 ql_log(ql_log_info, vha, 0x8009,
1534 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
1535 sdev->id, cmd);
1536
1537 err = 0;
1538 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1539 ql_log(ql_log_warn, vha, 0x800a,
1540 "Wait for hba online failed for cmd=%p.\n", cmd);
1541 goto eh_reset_failed;
1542 }
1543 err = 2;
1544 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
1545 ql_log(ql_log_warn, vha, 0x800c,
1546 "target_reset failed for cmd=%p.\n", cmd);
1547 goto eh_reset_failed;
1548 }
1549 err = 3;
1550 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0,
1551 WAIT_TARGET) != QLA_SUCCESS) {
1552 ql_log(ql_log_warn, vha, 0x800d,
1553 "wait for pending cmds failed for cmd=%p.\n", cmd);
1554 goto eh_reset_failed;
1555 }
1556
1557 ql_log(ql_log_info, vha, 0x800e,
1558 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n",
1559 vha->host_no, sdev->id, cmd);
1560
1561 return SUCCESS;
1562
1563 eh_reset_failed:
1564 ql_log(ql_log_info, vha, 0x800f,
1565 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1566 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1567 cmd);
1568 vha->reset_cmd_err_cnt++;
1569 return FAILED;
1570 }
1571
1572 /**************************************************************************
1573 * qla2xxx_eh_bus_reset
1574 *
1575 * Description:
1576 * The bus reset function will reset the bus and abort any executing
1577 * commands.
1578 *
1579 * Input:
1580 * cmd = Linux SCSI command packet of the command that cause the
1581 * bus reset.
1582 *
1583 * Returns:
1584 * SUCCESS/FAILURE (defined as macro in scsi.h).
1585 *
1586 **************************************************************************/
1587 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1588 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1589 {
1590 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1591 int ret = FAILED;
1592 unsigned int id;
1593 uint64_t lun;
1594 struct qla_hw_data *ha = vha->hw;
1595
1596 if (qla2x00_isp_reg_stat(ha)) {
1597 ql_log(ql_log_info, vha, 0x8040,
1598 "PCI/Register disconnect, exiting.\n");
1599 qla_pci_set_eeh_busy(vha);
1600 return FAILED;
1601 }
1602
1603 id = cmd->device->id;
1604 lun = cmd->device->lun;
1605
1606 if (qla2x00_chip_is_down(vha))
1607 return ret;
1608
1609 ql_log(ql_log_info, vha, 0x8012,
1610 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1611
1612 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1613 ql_log(ql_log_fatal, vha, 0x8013,
1614 "Wait for hba online failed board disabled.\n");
1615 goto eh_bus_reset_done;
1616 }
1617
1618 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1619 ret = SUCCESS;
1620
1621 if (ret == FAILED)
1622 goto eh_bus_reset_done;
1623
1624 /* Flush outstanding commands. */
1625 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1626 QLA_SUCCESS) {
1627 ql_log(ql_log_warn, vha, 0x8014,
1628 "Wait for pending commands failed.\n");
1629 ret = FAILED;
1630 }
1631
1632 eh_bus_reset_done:
1633 ql_log(ql_log_warn, vha, 0x802b,
1634 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1635 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1636
1637 return ret;
1638 }
1639
1640 /**************************************************************************
1641 * qla2xxx_eh_host_reset
1642 *
1643 * Description:
1644 * The reset function will reset the Adapter.
1645 *
1646 * Input:
1647 * cmd = Linux SCSI command packet of the command that cause the
1648 * adapter reset.
1649 *
1650 * Returns:
1651 * Either SUCCESS or FAILED.
1652 *
1653 * Note:
1654 **************************************************************************/
1655 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1656 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1657 {
1658 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1659 struct qla_hw_data *ha = vha->hw;
1660 int ret = FAILED;
1661 unsigned int id;
1662 uint64_t lun;
1663 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1664
1665 if (qla2x00_isp_reg_stat(ha)) {
1666 ql_log(ql_log_info, vha, 0x8041,
1667 "PCI/Register disconnect, exiting.\n");
1668 qla_pci_set_eeh_busy(vha);
1669 return SUCCESS;
1670 }
1671
1672 id = cmd->device->id;
1673 lun = cmd->device->lun;
1674
1675 ql_log(ql_log_info, vha, 0x8018,
1676 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1677
1678 /*
1679 * No point in issuing another reset if one is active. Also do not
1680 * attempt a reset if we are updating flash.
1681 */
1682 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1683 goto eh_host_reset_lock;
1684
1685 if (vha != base_vha) {
1686 if (qla2x00_vp_abort_isp(vha))
1687 goto eh_host_reset_lock;
1688 } else {
1689 if (IS_P3P_TYPE(vha->hw)) {
1690 if (!qla82xx_fcoe_ctx_reset(vha)) {
1691 /* Ctx reset success */
1692 ret = SUCCESS;
1693 goto eh_host_reset_lock;
1694 }
1695 /* fall thru if ctx reset failed */
1696 }
1697 if (ha->wq)
1698 flush_workqueue(ha->wq);
1699
1700 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1701 if (ha->isp_ops->abort_isp(base_vha)) {
1702 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1703 /* failed. schedule dpc to try */
1704 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1705
1706 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1707 ql_log(ql_log_warn, vha, 0x802a,
1708 "wait for hba online failed.\n");
1709 goto eh_host_reset_lock;
1710 }
1711 }
1712 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1713 }
1714
1715 /* Waiting for command to be returned to OS.*/
1716 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1717 QLA_SUCCESS)
1718 ret = SUCCESS;
1719
1720 eh_host_reset_lock:
1721 ql_log(ql_log_info, vha, 0x8017,
1722 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1723 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1724
1725 return ret;
1726 }
1727
1728 /*
1729 * qla2x00_loop_reset
1730 * Issue loop reset.
1731 *
1732 * Input:
1733 * ha = adapter block pointer.
1734 *
1735 * Returns:
1736 * 0 = success
1737 */
1738 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1739 qla2x00_loop_reset(scsi_qla_host_t *vha)
1740 {
1741 int ret;
1742 struct qla_hw_data *ha = vha->hw;
1743
1744 if (IS_QLAFX00(ha))
1745 return QLA_SUCCESS;
1746
1747 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1748 atomic_set(&vha->loop_state, LOOP_DOWN);
1749 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1750 qla2x00_mark_all_devices_lost(vha);
1751 ret = qla2x00_full_login_lip(vha);
1752 if (ret != QLA_SUCCESS) {
1753 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1754 "full_login_lip=%d.\n", ret);
1755 }
1756 }
1757
1758 if (ha->flags.enable_lip_reset) {
1759 ret = qla2x00_lip_reset(vha);
1760 if (ret != QLA_SUCCESS)
1761 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1762 "lip_reset failed (%d).\n", ret);
1763 }
1764
1765 /* Issue marker command only when we are going to start the I/O */
1766 vha->marker_needed = 1;
1767
1768 return QLA_SUCCESS;
1769 }
1770
1771 /*
1772 * The caller must ensure that no completion interrupts will happen
1773 * while this function is in progress.
1774 */
qla2x00_abort_srb(struct qla_qpair * qp,srb_t * sp,const int res,unsigned long * flags)1775 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1776 unsigned long *flags)
1777 __releases(qp->qp_lock_ptr)
1778 __acquires(qp->qp_lock_ptr)
1779 {
1780 DECLARE_COMPLETION_ONSTACK(comp);
1781 scsi_qla_host_t *vha = qp->vha;
1782 struct qla_hw_data *ha = vha->hw;
1783 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1784 int rval;
1785 bool ret_cmd;
1786 uint32_t ratov_j;
1787
1788 lockdep_assert_held(qp->qp_lock_ptr);
1789
1790 if (qla2x00_chip_is_down(vha)) {
1791 sp->done(sp, res);
1792 return;
1793 }
1794
1795 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1796 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1797 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1798 !qla2x00_isp_reg_stat(ha))) {
1799 if (sp->comp) {
1800 sp->done(sp, res);
1801 return;
1802 }
1803
1804 sp->comp = ∁
1805 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1806
1807 rval = ha->isp_ops->abort_command(sp);
1808 /* Wait for command completion. */
1809 ret_cmd = false;
1810 ratov_j = ha->r_a_tov / 10 * 4;
1811 ratov_j = secs_to_jiffies(ratov_j);
1812 switch (rval) {
1813 case QLA_SUCCESS:
1814 if (wait_for_completion_timeout(&comp, ratov_j)) {
1815 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1816 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1817 __func__, ha->r_a_tov/10);
1818 ret_cmd = true;
1819 }
1820 /* else FW return SP to driver */
1821 break;
1822 default:
1823 ret_cmd = true;
1824 break;
1825 }
1826
1827 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1828 switch (sp->type) {
1829 case SRB_SCSI_CMD:
1830 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd)))
1831 sp->done(sp, res);
1832 break;
1833 default:
1834 if (ret_cmd)
1835 sp->done(sp, res);
1836 break;
1837 }
1838 } else {
1839 sp->done(sp, res);
1840 }
1841 }
1842
1843 /*
1844 * The caller must ensure that no completion interrupts will happen
1845 * while this function is in progress.
1846 */
1847 static void
__qla2x00_abort_all_cmds(struct qla_qpair * qp,int res)1848 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1849 {
1850 int cnt;
1851 unsigned long flags;
1852 srb_t *sp;
1853 scsi_qla_host_t *vha = qp->vha;
1854 struct qla_hw_data *ha = vha->hw;
1855 struct req_que *req;
1856 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1857 struct qla_tgt_cmd *cmd;
1858
1859 if (!ha->req_q_map)
1860 return;
1861 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1862 req = qp->req;
1863 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1864 sp = req->outstanding_cmds[cnt];
1865 if (sp) {
1866 switch (sp->cmd_type) {
1867 case TYPE_SRB:
1868 qla2x00_abort_srb(qp, sp, res, &flags);
1869 break;
1870 case TYPE_TGT_CMD:
1871 if (!vha->hw->tgt.tgt_ops || !tgt ||
1872 qla_ini_mode_enabled(vha)) {
1873 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1874 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1875 vha->dpc_flags);
1876 continue;
1877 }
1878 cmd = (struct qla_tgt_cmd *)sp;
1879
1880 if (cmd->sg_mapped)
1881 qlt_unmap_sg(vha, cmd);
1882
1883 if (cmd->state == QLA_TGT_STATE_NEED_DATA) {
1884 cmd->aborted = 1;
1885 cmd->write_data_transferred = 0;
1886 cmd->state = QLA_TGT_STATE_DATA_IN;
1887 ha->tgt.tgt_ops->handle_data(cmd);
1888 } else {
1889 ha->tgt.tgt_ops->free_cmd(cmd);
1890 }
1891 break;
1892 case TYPE_TGT_TMCMD:
1893 /*
1894 * Currently, only ABTS response gets on the
1895 * outstanding_cmds[]
1896 */
1897 qlt_free_ul_mcmd(ha,
1898 (struct qla_tgt_mgmt_cmd *) sp);
1899 break;
1900 default:
1901 break;
1902 }
1903 req->outstanding_cmds[cnt] = NULL;
1904 }
1905 }
1906 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1907 }
1908
1909 /*
1910 * The caller must ensure that no completion interrupts will happen
1911 * while this function is in progress.
1912 */
1913 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1914 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1915 {
1916 int que;
1917 struct qla_hw_data *ha = vha->hw;
1918
1919 /* Continue only if initialization complete. */
1920 if (!ha->base_qpair)
1921 return;
1922 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1923
1924 if (!ha->queue_pair_map)
1925 return;
1926 for (que = 0; que < ha->max_qpairs; que++) {
1927 if (!ha->queue_pair_map[que])
1928 continue;
1929
1930 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1931 }
1932 }
1933
1934 static int
qla2xxx_sdev_init(struct scsi_device * sdev)1935 qla2xxx_sdev_init(struct scsi_device *sdev)
1936 {
1937 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1938
1939 if (!rport || fc_remote_port_chkready(rport))
1940 return -ENXIO;
1941
1942 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1943
1944 return 0;
1945 }
1946
1947 static int
qla2xxx_sdev_configure(struct scsi_device * sdev,struct queue_limits * lim)1948 qla2xxx_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim)
1949 {
1950 scsi_qla_host_t *vha = shost_priv(sdev->host);
1951 struct req_que *req = vha->req;
1952
1953 scsi_change_queue_depth(sdev, req->max_q_depth);
1954 return 0;
1955 }
1956
1957 static void
qla2xxx_sdev_destroy(struct scsi_device * sdev)1958 qla2xxx_sdev_destroy(struct scsi_device *sdev)
1959 {
1960 sdev->hostdata = NULL;
1961 }
1962
1963 /**
1964 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1965 * @ha: HA context
1966 *
1967 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1968 * supported addressing method.
1969 */
1970 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1971 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1972 {
1973 /* Assume a 32bit DMA mask. */
1974 ha->flags.enable_64bit_addressing = 0;
1975
1976 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1977 /* Any upper-dword bits set? */
1978 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1979 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1980 /* Ok, a 64bit DMA mask is applicable. */
1981 ha->flags.enable_64bit_addressing = 1;
1982 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1983 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1984 return;
1985 }
1986 }
1987
1988 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1989 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1990 }
1991
1992 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)1993 qla2x00_enable_intrs(struct qla_hw_data *ha)
1994 {
1995 unsigned long flags = 0;
1996 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1997
1998 spin_lock_irqsave(&ha->hardware_lock, flags);
1999 ha->interrupts_on = 1;
2000 /* enable risc and host interrupts */
2001 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
2002 rd_reg_word(®->ictrl);
2003 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2004
2005 }
2006
2007 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)2008 qla2x00_disable_intrs(struct qla_hw_data *ha)
2009 {
2010 unsigned long flags = 0;
2011 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2012
2013 spin_lock_irqsave(&ha->hardware_lock, flags);
2014 ha->interrupts_on = 0;
2015 /* disable risc and host interrupts */
2016 wrt_reg_word(®->ictrl, 0);
2017 rd_reg_word(®->ictrl);
2018 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2019 }
2020
2021 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)2022 qla24xx_enable_intrs(struct qla_hw_data *ha)
2023 {
2024 unsigned long flags = 0;
2025 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2026
2027 spin_lock_irqsave(&ha->hardware_lock, flags);
2028 ha->interrupts_on = 1;
2029 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT);
2030 rd_reg_dword(®->ictrl);
2031 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2032 }
2033
2034 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)2035 qla24xx_disable_intrs(struct qla_hw_data *ha)
2036 {
2037 unsigned long flags = 0;
2038 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2039
2040 if (IS_NOPOLLING_TYPE(ha))
2041 return;
2042 spin_lock_irqsave(&ha->hardware_lock, flags);
2043 ha->interrupts_on = 0;
2044 wrt_reg_dword(®->ictrl, 0);
2045 rd_reg_dword(®->ictrl);
2046 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2047 }
2048
2049 static int
qla2x00_iospace_config(struct qla_hw_data * ha)2050 qla2x00_iospace_config(struct qla_hw_data *ha)
2051 {
2052 resource_size_t pio;
2053 uint16_t msix;
2054
2055 if (pci_request_selected_regions(ha->pdev, ha->bars,
2056 QLA2XXX_DRIVER_NAME)) {
2057 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2058 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2059 pci_name(ha->pdev));
2060 goto iospace_error_exit;
2061 }
2062 if (!(ha->bars & 1))
2063 goto skip_pio;
2064
2065 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
2066 pio = pci_resource_start(ha->pdev, 0);
2067 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2068 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2069 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2070 "Invalid pci I/O region size (%s).\n",
2071 pci_name(ha->pdev));
2072 pio = 0;
2073 }
2074 } else {
2075 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2076 "Region #0 no a PIO resource (%s).\n",
2077 pci_name(ha->pdev));
2078 pio = 0;
2079 }
2080 ha->pio_address = pio;
2081 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2082 "PIO address=%llu.\n",
2083 (unsigned long long)ha->pio_address);
2084
2085 skip_pio:
2086 /* Use MMIO operations for all accesses. */
2087 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2088 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2089 "Region #1 not an MMIO resource (%s), aborting.\n",
2090 pci_name(ha->pdev));
2091 goto iospace_error_exit;
2092 }
2093 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2094 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2095 "Invalid PCI mem region size (%s), aborting.\n",
2096 pci_name(ha->pdev));
2097 goto iospace_error_exit;
2098 }
2099
2100 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2101 if (!ha->iobase) {
2102 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2103 "Cannot remap MMIO (%s), aborting.\n",
2104 pci_name(ha->pdev));
2105 goto iospace_error_exit;
2106 }
2107
2108 /* Determine queue resources */
2109 ha->max_req_queues = ha->max_rsp_queues = 1;
2110 ha->msix_count = QLA_BASE_VECTORS;
2111
2112 /* Check if FW supports MQ or not */
2113 if (!(ha->fw_attributes & BIT_6))
2114 goto mqiobase_exit;
2115
2116 if (!ql2xmqsupport || !ql2xnvmeenable ||
2117 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2118 goto mqiobase_exit;
2119
2120 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2121 pci_resource_len(ha->pdev, 3));
2122 if (ha->mqiobase) {
2123 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2124 "MQIO Base=%p.\n", ha->mqiobase);
2125 /* Read MSIX vector size of the board */
2126 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2127 ha->msix_count = msix + 1;
2128 /* Max queues are bounded by available msix vectors */
2129 /* MB interrupt uses 1 vector */
2130 ha->max_req_queues = ha->msix_count - 1;
2131 ha->max_rsp_queues = ha->max_req_queues;
2132 /* Queue pairs is the max value minus the base queue pair */
2133 ha->max_qpairs = ha->max_rsp_queues - 1;
2134 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2135 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2136
2137 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2138 "MSI-X vector count: %d.\n", ha->msix_count);
2139 } else
2140 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2141 "BAR 3 not enabled.\n");
2142
2143 mqiobase_exit:
2144 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2145 "MSIX Count: %d.\n", ha->msix_count);
2146 return (0);
2147
2148 iospace_error_exit:
2149 return (-ENOMEM);
2150 }
2151
2152
2153 static int
qla83xx_iospace_config(struct qla_hw_data * ha)2154 qla83xx_iospace_config(struct qla_hw_data *ha)
2155 {
2156 uint16_t msix;
2157
2158 if (pci_request_selected_regions(ha->pdev, ha->bars,
2159 QLA2XXX_DRIVER_NAME)) {
2160 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2161 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2162 pci_name(ha->pdev));
2163
2164 goto iospace_error_exit;
2165 }
2166
2167 /* Use MMIO operations for all accesses. */
2168 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2169 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2170 "Invalid pci I/O region size (%s).\n",
2171 pci_name(ha->pdev));
2172 goto iospace_error_exit;
2173 }
2174 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2175 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2176 "Invalid PCI mem region size (%s), aborting\n",
2177 pci_name(ha->pdev));
2178 goto iospace_error_exit;
2179 }
2180
2181 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2182 if (!ha->iobase) {
2183 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2184 "Cannot remap MMIO (%s), aborting.\n",
2185 pci_name(ha->pdev));
2186 goto iospace_error_exit;
2187 }
2188
2189 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2190 /* 83XX 26XX always use MQ type access for queues
2191 * - mbar 2, a.k.a region 4 */
2192 ha->max_req_queues = ha->max_rsp_queues = 1;
2193 ha->msix_count = QLA_BASE_VECTORS;
2194 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2195 pci_resource_len(ha->pdev, 4));
2196
2197 if (!ha->mqiobase) {
2198 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2199 "BAR2/region4 not enabled\n");
2200 goto mqiobase_exit;
2201 }
2202
2203 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2204 pci_resource_len(ha->pdev, 2));
2205 if (ha->msixbase) {
2206 /* Read MSIX vector size of the board */
2207 pci_read_config_word(ha->pdev,
2208 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2209 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2210 /*
2211 * By default, driver uses at least two msix vectors
2212 * (default & rspq)
2213 */
2214 if (ql2xmqsupport || ql2xnvmeenable) {
2215 /* MB interrupt uses 1 vector */
2216 ha->max_req_queues = ha->msix_count - 1;
2217
2218 /* ATIOQ needs 1 vector. That's 1 less QPair */
2219 if (QLA_TGT_MODE_ENABLED())
2220 ha->max_req_queues--;
2221
2222 ha->max_rsp_queues = ha->max_req_queues;
2223
2224 /* Queue pairs is the max value minus
2225 * the base queue pair */
2226 ha->max_qpairs = ha->max_req_queues - 1;
2227 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2228 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2229 }
2230 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2231 "MSI-X vector count: %d.\n", ha->msix_count);
2232 } else
2233 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2234 "BAR 1 not enabled.\n");
2235
2236 mqiobase_exit:
2237 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2238 "MSIX Count: %d.\n", ha->msix_count);
2239 return 0;
2240
2241 iospace_error_exit:
2242 return -ENOMEM;
2243 }
2244
2245 static struct isp_operations qla2100_isp_ops = {
2246 .pci_config = qla2100_pci_config,
2247 .reset_chip = qla2x00_reset_chip,
2248 .chip_diag = qla2x00_chip_diag,
2249 .config_rings = qla2x00_config_rings,
2250 .reset_adapter = qla2x00_reset_adapter,
2251 .nvram_config = qla2x00_nvram_config,
2252 .update_fw_options = qla2x00_update_fw_options,
2253 .load_risc = qla2x00_load_risc,
2254 .pci_info_str = qla2x00_pci_info_str,
2255 .fw_version_str = qla2x00_fw_version_str,
2256 .intr_handler = qla2100_intr_handler,
2257 .enable_intrs = qla2x00_enable_intrs,
2258 .disable_intrs = qla2x00_disable_intrs,
2259 .abort_command = qla2x00_abort_command,
2260 .target_reset = qla2x00_abort_target,
2261 .lun_reset = qla2x00_lun_reset,
2262 .fabric_login = qla2x00_login_fabric,
2263 .fabric_logout = qla2x00_fabric_logout,
2264 .calc_req_entries = qla2x00_calc_iocbs_32,
2265 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2266 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2267 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2268 .read_nvram = qla2x00_read_nvram_data,
2269 .write_nvram = qla2x00_write_nvram_data,
2270 .fw_dump = qla2100_fw_dump,
2271 .beacon_on = NULL,
2272 .beacon_off = NULL,
2273 .beacon_blink = NULL,
2274 .read_optrom = qla2x00_read_optrom_data,
2275 .write_optrom = qla2x00_write_optrom_data,
2276 .get_flash_version = qla2x00_get_flash_version,
2277 .start_scsi = qla2x00_start_scsi,
2278 .start_scsi_mq = NULL,
2279 .abort_isp = qla2x00_abort_isp,
2280 .iospace_config = qla2x00_iospace_config,
2281 .initialize_adapter = qla2x00_initialize_adapter,
2282 };
2283
2284 static struct isp_operations qla2300_isp_ops = {
2285 .pci_config = qla2300_pci_config,
2286 .reset_chip = qla2x00_reset_chip,
2287 .chip_diag = qla2x00_chip_diag,
2288 .config_rings = qla2x00_config_rings,
2289 .reset_adapter = qla2x00_reset_adapter,
2290 .nvram_config = qla2x00_nvram_config,
2291 .update_fw_options = qla2x00_update_fw_options,
2292 .load_risc = qla2x00_load_risc,
2293 .pci_info_str = qla2x00_pci_info_str,
2294 .fw_version_str = qla2x00_fw_version_str,
2295 .intr_handler = qla2300_intr_handler,
2296 .enable_intrs = qla2x00_enable_intrs,
2297 .disable_intrs = qla2x00_disable_intrs,
2298 .abort_command = qla2x00_abort_command,
2299 .target_reset = qla2x00_abort_target,
2300 .lun_reset = qla2x00_lun_reset,
2301 .fabric_login = qla2x00_login_fabric,
2302 .fabric_logout = qla2x00_fabric_logout,
2303 .calc_req_entries = qla2x00_calc_iocbs_32,
2304 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2305 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2306 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2307 .read_nvram = qla2x00_read_nvram_data,
2308 .write_nvram = qla2x00_write_nvram_data,
2309 .fw_dump = qla2300_fw_dump,
2310 .beacon_on = qla2x00_beacon_on,
2311 .beacon_off = qla2x00_beacon_off,
2312 .beacon_blink = qla2x00_beacon_blink,
2313 .read_optrom = qla2x00_read_optrom_data,
2314 .write_optrom = qla2x00_write_optrom_data,
2315 .get_flash_version = qla2x00_get_flash_version,
2316 .start_scsi = qla2x00_start_scsi,
2317 .start_scsi_mq = NULL,
2318 .abort_isp = qla2x00_abort_isp,
2319 .iospace_config = qla2x00_iospace_config,
2320 .initialize_adapter = qla2x00_initialize_adapter,
2321 };
2322
2323 static struct isp_operations qla24xx_isp_ops = {
2324 .pci_config = qla24xx_pci_config,
2325 .reset_chip = qla24xx_reset_chip,
2326 .chip_diag = qla24xx_chip_diag,
2327 .config_rings = qla24xx_config_rings,
2328 .reset_adapter = qla24xx_reset_adapter,
2329 .nvram_config = qla24xx_nvram_config,
2330 .update_fw_options = qla24xx_update_fw_options,
2331 .load_risc = qla24xx_load_risc,
2332 .pci_info_str = qla24xx_pci_info_str,
2333 .fw_version_str = qla24xx_fw_version_str,
2334 .intr_handler = qla24xx_intr_handler,
2335 .enable_intrs = qla24xx_enable_intrs,
2336 .disable_intrs = qla24xx_disable_intrs,
2337 .abort_command = qla24xx_abort_command,
2338 .target_reset = qla24xx_abort_target,
2339 .lun_reset = qla24xx_lun_reset,
2340 .fabric_login = qla24xx_login_fabric,
2341 .fabric_logout = qla24xx_fabric_logout,
2342 .calc_req_entries = NULL,
2343 .build_iocbs = NULL,
2344 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2345 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2346 .read_nvram = qla24xx_read_nvram_data,
2347 .write_nvram = qla24xx_write_nvram_data,
2348 .fw_dump = qla24xx_fw_dump,
2349 .beacon_on = qla24xx_beacon_on,
2350 .beacon_off = qla24xx_beacon_off,
2351 .beacon_blink = qla24xx_beacon_blink,
2352 .read_optrom = qla24xx_read_optrom_data,
2353 .write_optrom = qla24xx_write_optrom_data,
2354 .get_flash_version = qla24xx_get_flash_version,
2355 .start_scsi = qla24xx_start_scsi,
2356 .start_scsi_mq = NULL,
2357 .abort_isp = qla2x00_abort_isp,
2358 .iospace_config = qla2x00_iospace_config,
2359 .initialize_adapter = qla2x00_initialize_adapter,
2360 };
2361
2362 static struct isp_operations qla25xx_isp_ops = {
2363 .pci_config = qla25xx_pci_config,
2364 .reset_chip = qla24xx_reset_chip,
2365 .chip_diag = qla24xx_chip_diag,
2366 .config_rings = qla24xx_config_rings,
2367 .reset_adapter = qla24xx_reset_adapter,
2368 .nvram_config = qla24xx_nvram_config,
2369 .update_fw_options = qla24xx_update_fw_options,
2370 .load_risc = qla24xx_load_risc,
2371 .pci_info_str = qla24xx_pci_info_str,
2372 .fw_version_str = qla24xx_fw_version_str,
2373 .intr_handler = qla24xx_intr_handler,
2374 .enable_intrs = qla24xx_enable_intrs,
2375 .disable_intrs = qla24xx_disable_intrs,
2376 .abort_command = qla24xx_abort_command,
2377 .target_reset = qla24xx_abort_target,
2378 .lun_reset = qla24xx_lun_reset,
2379 .fabric_login = qla24xx_login_fabric,
2380 .fabric_logout = qla24xx_fabric_logout,
2381 .calc_req_entries = NULL,
2382 .build_iocbs = NULL,
2383 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2384 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2385 .read_nvram = qla25xx_read_nvram_data,
2386 .write_nvram = qla25xx_write_nvram_data,
2387 .fw_dump = qla25xx_fw_dump,
2388 .beacon_on = qla24xx_beacon_on,
2389 .beacon_off = qla24xx_beacon_off,
2390 .beacon_blink = qla24xx_beacon_blink,
2391 .read_optrom = qla25xx_read_optrom_data,
2392 .write_optrom = qla24xx_write_optrom_data,
2393 .get_flash_version = qla24xx_get_flash_version,
2394 .start_scsi = qla24xx_dif_start_scsi,
2395 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2396 .abort_isp = qla2x00_abort_isp,
2397 .iospace_config = qla2x00_iospace_config,
2398 .initialize_adapter = qla2x00_initialize_adapter,
2399 };
2400
2401 static struct isp_operations qla81xx_isp_ops = {
2402 .pci_config = qla25xx_pci_config,
2403 .reset_chip = qla24xx_reset_chip,
2404 .chip_diag = qla24xx_chip_diag,
2405 .config_rings = qla24xx_config_rings,
2406 .reset_adapter = qla24xx_reset_adapter,
2407 .nvram_config = qla81xx_nvram_config,
2408 .update_fw_options = qla24xx_update_fw_options,
2409 .load_risc = qla81xx_load_risc,
2410 .pci_info_str = qla24xx_pci_info_str,
2411 .fw_version_str = qla24xx_fw_version_str,
2412 .intr_handler = qla24xx_intr_handler,
2413 .enable_intrs = qla24xx_enable_intrs,
2414 .disable_intrs = qla24xx_disable_intrs,
2415 .abort_command = qla24xx_abort_command,
2416 .target_reset = qla24xx_abort_target,
2417 .lun_reset = qla24xx_lun_reset,
2418 .fabric_login = qla24xx_login_fabric,
2419 .fabric_logout = qla24xx_fabric_logout,
2420 .calc_req_entries = NULL,
2421 .build_iocbs = NULL,
2422 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2423 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2424 .read_nvram = NULL,
2425 .write_nvram = NULL,
2426 .fw_dump = qla81xx_fw_dump,
2427 .beacon_on = qla24xx_beacon_on,
2428 .beacon_off = qla24xx_beacon_off,
2429 .beacon_blink = qla83xx_beacon_blink,
2430 .read_optrom = qla25xx_read_optrom_data,
2431 .write_optrom = qla24xx_write_optrom_data,
2432 .get_flash_version = qla24xx_get_flash_version,
2433 .start_scsi = qla24xx_dif_start_scsi,
2434 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2435 .abort_isp = qla2x00_abort_isp,
2436 .iospace_config = qla2x00_iospace_config,
2437 .initialize_adapter = qla2x00_initialize_adapter,
2438 };
2439
2440 static struct isp_operations qla82xx_isp_ops = {
2441 .pci_config = qla82xx_pci_config,
2442 .reset_chip = qla82xx_reset_chip,
2443 .chip_diag = qla24xx_chip_diag,
2444 .config_rings = qla82xx_config_rings,
2445 .reset_adapter = qla24xx_reset_adapter,
2446 .nvram_config = qla81xx_nvram_config,
2447 .update_fw_options = qla24xx_update_fw_options,
2448 .load_risc = qla82xx_load_risc,
2449 .pci_info_str = qla24xx_pci_info_str,
2450 .fw_version_str = qla24xx_fw_version_str,
2451 .intr_handler = qla82xx_intr_handler,
2452 .enable_intrs = qla82xx_enable_intrs,
2453 .disable_intrs = qla82xx_disable_intrs,
2454 .abort_command = qla24xx_abort_command,
2455 .target_reset = qla24xx_abort_target,
2456 .lun_reset = qla24xx_lun_reset,
2457 .fabric_login = qla24xx_login_fabric,
2458 .fabric_logout = qla24xx_fabric_logout,
2459 .calc_req_entries = NULL,
2460 .build_iocbs = NULL,
2461 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2462 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2463 .read_nvram = qla24xx_read_nvram_data,
2464 .write_nvram = qla24xx_write_nvram_data,
2465 .fw_dump = qla82xx_fw_dump,
2466 .beacon_on = qla82xx_beacon_on,
2467 .beacon_off = qla82xx_beacon_off,
2468 .beacon_blink = NULL,
2469 .read_optrom = qla82xx_read_optrom_data,
2470 .write_optrom = qla82xx_write_optrom_data,
2471 .get_flash_version = qla82xx_get_flash_version,
2472 .start_scsi = qla82xx_start_scsi,
2473 .start_scsi_mq = NULL,
2474 .abort_isp = qla82xx_abort_isp,
2475 .iospace_config = qla82xx_iospace_config,
2476 .initialize_adapter = qla2x00_initialize_adapter,
2477 };
2478
2479 static struct isp_operations qla8044_isp_ops = {
2480 .pci_config = qla82xx_pci_config,
2481 .reset_chip = qla82xx_reset_chip,
2482 .chip_diag = qla24xx_chip_diag,
2483 .config_rings = qla82xx_config_rings,
2484 .reset_adapter = qla24xx_reset_adapter,
2485 .nvram_config = qla81xx_nvram_config,
2486 .update_fw_options = qla24xx_update_fw_options,
2487 .load_risc = qla82xx_load_risc,
2488 .pci_info_str = qla24xx_pci_info_str,
2489 .fw_version_str = qla24xx_fw_version_str,
2490 .intr_handler = qla8044_intr_handler,
2491 .enable_intrs = qla82xx_enable_intrs,
2492 .disable_intrs = qla82xx_disable_intrs,
2493 .abort_command = qla24xx_abort_command,
2494 .target_reset = qla24xx_abort_target,
2495 .lun_reset = qla24xx_lun_reset,
2496 .fabric_login = qla24xx_login_fabric,
2497 .fabric_logout = qla24xx_fabric_logout,
2498 .calc_req_entries = NULL,
2499 .build_iocbs = NULL,
2500 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2501 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2502 .read_nvram = NULL,
2503 .write_nvram = NULL,
2504 .fw_dump = qla8044_fw_dump,
2505 .beacon_on = qla82xx_beacon_on,
2506 .beacon_off = qla82xx_beacon_off,
2507 .beacon_blink = NULL,
2508 .read_optrom = qla8044_read_optrom_data,
2509 .write_optrom = qla8044_write_optrom_data,
2510 .get_flash_version = qla82xx_get_flash_version,
2511 .start_scsi = qla82xx_start_scsi,
2512 .start_scsi_mq = NULL,
2513 .abort_isp = qla8044_abort_isp,
2514 .iospace_config = qla82xx_iospace_config,
2515 .initialize_adapter = qla2x00_initialize_adapter,
2516 };
2517
2518 static struct isp_operations qla83xx_isp_ops = {
2519 .pci_config = qla25xx_pci_config,
2520 .reset_chip = qla24xx_reset_chip,
2521 .chip_diag = qla24xx_chip_diag,
2522 .config_rings = qla24xx_config_rings,
2523 .reset_adapter = qla24xx_reset_adapter,
2524 .nvram_config = qla81xx_nvram_config,
2525 .update_fw_options = qla24xx_update_fw_options,
2526 .load_risc = qla81xx_load_risc,
2527 .pci_info_str = qla24xx_pci_info_str,
2528 .fw_version_str = qla24xx_fw_version_str,
2529 .intr_handler = qla24xx_intr_handler,
2530 .enable_intrs = qla24xx_enable_intrs,
2531 .disable_intrs = qla24xx_disable_intrs,
2532 .abort_command = qla24xx_abort_command,
2533 .target_reset = qla24xx_abort_target,
2534 .lun_reset = qla24xx_lun_reset,
2535 .fabric_login = qla24xx_login_fabric,
2536 .fabric_logout = qla24xx_fabric_logout,
2537 .calc_req_entries = NULL,
2538 .build_iocbs = NULL,
2539 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2540 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2541 .read_nvram = NULL,
2542 .write_nvram = NULL,
2543 .fw_dump = qla83xx_fw_dump,
2544 .beacon_on = qla24xx_beacon_on,
2545 .beacon_off = qla24xx_beacon_off,
2546 .beacon_blink = qla83xx_beacon_blink,
2547 .read_optrom = qla25xx_read_optrom_data,
2548 .write_optrom = qla24xx_write_optrom_data,
2549 .get_flash_version = qla24xx_get_flash_version,
2550 .start_scsi = qla24xx_dif_start_scsi,
2551 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2552 .abort_isp = qla2x00_abort_isp,
2553 .iospace_config = qla83xx_iospace_config,
2554 .initialize_adapter = qla2x00_initialize_adapter,
2555 };
2556
2557 static struct isp_operations qlafx00_isp_ops = {
2558 .pci_config = qlafx00_pci_config,
2559 .reset_chip = qlafx00_soft_reset,
2560 .chip_diag = qlafx00_chip_diag,
2561 .config_rings = qlafx00_config_rings,
2562 .reset_adapter = qlafx00_soft_reset,
2563 .nvram_config = NULL,
2564 .update_fw_options = NULL,
2565 .load_risc = NULL,
2566 .pci_info_str = qlafx00_pci_info_str,
2567 .fw_version_str = qlafx00_fw_version_str,
2568 .intr_handler = qlafx00_intr_handler,
2569 .enable_intrs = qlafx00_enable_intrs,
2570 .disable_intrs = qlafx00_disable_intrs,
2571 .abort_command = qla24xx_async_abort_command,
2572 .target_reset = qlafx00_abort_target,
2573 .lun_reset = qlafx00_lun_reset,
2574 .fabric_login = NULL,
2575 .fabric_logout = NULL,
2576 .calc_req_entries = NULL,
2577 .build_iocbs = NULL,
2578 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2579 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2580 .read_nvram = qla24xx_read_nvram_data,
2581 .write_nvram = qla24xx_write_nvram_data,
2582 .fw_dump = NULL,
2583 .beacon_on = qla24xx_beacon_on,
2584 .beacon_off = qla24xx_beacon_off,
2585 .beacon_blink = NULL,
2586 .read_optrom = qla24xx_read_optrom_data,
2587 .write_optrom = qla24xx_write_optrom_data,
2588 .get_flash_version = qla24xx_get_flash_version,
2589 .start_scsi = qlafx00_start_scsi,
2590 .start_scsi_mq = NULL,
2591 .abort_isp = qlafx00_abort_isp,
2592 .iospace_config = qlafx00_iospace_config,
2593 .initialize_adapter = qlafx00_initialize_adapter,
2594 };
2595
2596 static struct isp_operations qla27xx_isp_ops = {
2597 .pci_config = qla25xx_pci_config,
2598 .reset_chip = qla24xx_reset_chip,
2599 .chip_diag = qla24xx_chip_diag,
2600 .config_rings = qla24xx_config_rings,
2601 .reset_adapter = qla24xx_reset_adapter,
2602 .nvram_config = qla81xx_nvram_config,
2603 .update_fw_options = qla24xx_update_fw_options,
2604 .load_risc = qla81xx_load_risc,
2605 .pci_info_str = qla24xx_pci_info_str,
2606 .fw_version_str = qla24xx_fw_version_str,
2607 .intr_handler = qla24xx_intr_handler,
2608 .enable_intrs = qla24xx_enable_intrs,
2609 .disable_intrs = qla24xx_disable_intrs,
2610 .abort_command = qla24xx_abort_command,
2611 .target_reset = qla24xx_abort_target,
2612 .lun_reset = qla24xx_lun_reset,
2613 .fabric_login = qla24xx_login_fabric,
2614 .fabric_logout = qla24xx_fabric_logout,
2615 .calc_req_entries = NULL,
2616 .build_iocbs = NULL,
2617 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2618 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2619 .read_nvram = NULL,
2620 .write_nvram = NULL,
2621 .fw_dump = qla27xx_fwdump,
2622 .mpi_fw_dump = qla27xx_mpi_fwdump,
2623 .beacon_on = qla24xx_beacon_on,
2624 .beacon_off = qla24xx_beacon_off,
2625 .beacon_blink = qla83xx_beacon_blink,
2626 .read_optrom = qla25xx_read_optrom_data,
2627 .write_optrom = qla24xx_write_optrom_data,
2628 .get_flash_version = qla24xx_get_flash_version,
2629 .start_scsi = qla24xx_dif_start_scsi,
2630 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2631 .abort_isp = qla2x00_abort_isp,
2632 .iospace_config = qla83xx_iospace_config,
2633 .initialize_adapter = qla2x00_initialize_adapter,
2634 };
2635
2636 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2637 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2638 {
2639 ha->device_type = DT_EXTENDED_IDS;
2640 switch (ha->pdev->device) {
2641 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2642 ha->isp_type |= DT_ISP2100;
2643 ha->device_type &= ~DT_EXTENDED_IDS;
2644 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2645 break;
2646 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2647 ha->isp_type |= DT_ISP2200;
2648 ha->device_type &= ~DT_EXTENDED_IDS;
2649 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2650 break;
2651 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2652 ha->isp_type |= DT_ISP2300;
2653 ha->device_type |= DT_ZIO_SUPPORTED;
2654 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2655 break;
2656 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2657 ha->isp_type |= DT_ISP2312;
2658 ha->device_type |= DT_ZIO_SUPPORTED;
2659 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2660 break;
2661 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2662 ha->isp_type |= DT_ISP2322;
2663 ha->device_type |= DT_ZIO_SUPPORTED;
2664 if (ha->pdev->subsystem_vendor == 0x1028 &&
2665 ha->pdev->subsystem_device == 0x0170)
2666 ha->device_type |= DT_OEM_001;
2667 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2668 break;
2669 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2670 ha->isp_type |= DT_ISP6312;
2671 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2672 break;
2673 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2674 ha->isp_type |= DT_ISP6322;
2675 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2676 break;
2677 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2678 ha->isp_type |= DT_ISP2422;
2679 ha->device_type |= DT_ZIO_SUPPORTED;
2680 ha->device_type |= DT_FWI2;
2681 ha->device_type |= DT_IIDMA;
2682 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2683 break;
2684 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2685 ha->isp_type |= DT_ISP2432;
2686 ha->device_type |= DT_ZIO_SUPPORTED;
2687 ha->device_type |= DT_FWI2;
2688 ha->device_type |= DT_IIDMA;
2689 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2690 break;
2691 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2692 ha->isp_type |= DT_ISP8432;
2693 ha->device_type |= DT_ZIO_SUPPORTED;
2694 ha->device_type |= DT_FWI2;
2695 ha->device_type |= DT_IIDMA;
2696 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2697 break;
2698 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2699 ha->isp_type |= DT_ISP5422;
2700 ha->device_type |= DT_FWI2;
2701 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2702 break;
2703 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2704 ha->isp_type |= DT_ISP5432;
2705 ha->device_type |= DT_FWI2;
2706 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2707 break;
2708 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2709 ha->isp_type |= DT_ISP2532;
2710 ha->device_type |= DT_ZIO_SUPPORTED;
2711 ha->device_type |= DT_FWI2;
2712 ha->device_type |= DT_IIDMA;
2713 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2714 break;
2715 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2716 ha->isp_type |= DT_ISP8001;
2717 ha->device_type |= DT_ZIO_SUPPORTED;
2718 ha->device_type |= DT_FWI2;
2719 ha->device_type |= DT_IIDMA;
2720 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2721 break;
2722 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2723 ha->isp_type |= DT_ISP8021;
2724 ha->device_type |= DT_ZIO_SUPPORTED;
2725 ha->device_type |= DT_FWI2;
2726 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2727 /* Initialize 82XX ISP flags */
2728 qla82xx_init_flags(ha);
2729 break;
2730 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2731 ha->isp_type |= DT_ISP8044;
2732 ha->device_type |= DT_ZIO_SUPPORTED;
2733 ha->device_type |= DT_FWI2;
2734 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2735 /* Initialize 82XX ISP flags */
2736 qla82xx_init_flags(ha);
2737 break;
2738 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2739 ha->isp_type |= DT_ISP2031;
2740 ha->device_type |= DT_ZIO_SUPPORTED;
2741 ha->device_type |= DT_FWI2;
2742 ha->device_type |= DT_IIDMA;
2743 ha->device_type |= DT_T10_PI;
2744 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2745 break;
2746 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2747 ha->isp_type |= DT_ISP8031;
2748 ha->device_type |= DT_ZIO_SUPPORTED;
2749 ha->device_type |= DT_FWI2;
2750 ha->device_type |= DT_IIDMA;
2751 ha->device_type |= DT_T10_PI;
2752 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2753 break;
2754 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2755 ha->isp_type |= DT_ISPFX00;
2756 break;
2757 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2758 ha->isp_type |= DT_ISP2071;
2759 ha->device_type |= DT_ZIO_SUPPORTED;
2760 ha->device_type |= DT_FWI2;
2761 ha->device_type |= DT_IIDMA;
2762 ha->device_type |= DT_T10_PI;
2763 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2764 break;
2765 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2766 ha->isp_type |= DT_ISP2271;
2767 ha->device_type |= DT_ZIO_SUPPORTED;
2768 ha->device_type |= DT_FWI2;
2769 ha->device_type |= DT_IIDMA;
2770 ha->device_type |= DT_T10_PI;
2771 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2772 break;
2773 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2774 ha->isp_type |= DT_ISP2261;
2775 ha->device_type |= DT_ZIO_SUPPORTED;
2776 ha->device_type |= DT_FWI2;
2777 ha->device_type |= DT_IIDMA;
2778 ha->device_type |= DT_T10_PI;
2779 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2780 break;
2781 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2782 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2783 ha->isp_type |= DT_ISP2081;
2784 ha->device_type |= DT_ZIO_SUPPORTED;
2785 ha->device_type |= DT_FWI2;
2786 ha->device_type |= DT_IIDMA;
2787 ha->device_type |= DT_T10_PI;
2788 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2789 break;
2790 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2791 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2792 ha->isp_type |= DT_ISP2281;
2793 ha->device_type |= DT_ZIO_SUPPORTED;
2794 ha->device_type |= DT_FWI2;
2795 ha->device_type |= DT_IIDMA;
2796 ha->device_type |= DT_T10_PI;
2797 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2798 break;
2799 }
2800
2801 if (IS_QLA82XX(ha))
2802 ha->port_no = ha->portnum & 1;
2803 else {
2804 /* Get adapter physical port no from interrupt pin register. */
2805 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2806 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2807 IS_QLA27XX(ha) || IS_QLA28XX(ha))
2808 ha->port_no--;
2809 else
2810 ha->port_no = !(ha->port_no & 1);
2811 }
2812
2813 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2814 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2815 ha->device_type, ha->port_no, ha->fw_srisc_address);
2816 }
2817
2818 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2819 qla2xxx_scan_start(struct Scsi_Host *shost)
2820 {
2821 scsi_qla_host_t *vha = shost_priv(shost);
2822
2823 if (vha->hw->flags.running_gold_fw)
2824 return;
2825
2826 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2827 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2828 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2829 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2830 }
2831
2832 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2833 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2834 {
2835 scsi_qla_host_t *vha = shost_priv(shost);
2836
2837 if (test_bit(UNLOADING, &vha->dpc_flags))
2838 return 1;
2839 if (!vha->host)
2840 return 1;
2841 if (time > vha->hw->loop_reset_delay * HZ)
2842 return 1;
2843
2844 return atomic_read(&vha->loop_state) == LOOP_READY;
2845 }
2846
qla_heartbeat_work_fn(struct work_struct * work)2847 static void qla_heartbeat_work_fn(struct work_struct *work)
2848 {
2849 struct qla_hw_data *ha = container_of(work,
2850 struct qla_hw_data, heartbeat_work);
2851 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2852
2853 if (!ha->flags.mbox_busy && base_vha->flags.init_done)
2854 qla_no_op_mb(base_vha);
2855 }
2856
qla2x00_iocb_work_fn(struct work_struct * work)2857 static void qla2x00_iocb_work_fn(struct work_struct *work)
2858 {
2859 struct scsi_qla_host *vha = container_of(work,
2860 struct scsi_qla_host, iocb_work);
2861 struct qla_hw_data *ha = vha->hw;
2862 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2863 int i = 2;
2864 unsigned long flags;
2865
2866 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2867 return;
2868
2869 while (!list_empty(&vha->work_list) && i > 0) {
2870 qla2x00_do_work(vha);
2871 i--;
2872 }
2873
2874 spin_lock_irqsave(&vha->work_lock, flags);
2875 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2876 spin_unlock_irqrestore(&vha->work_lock, flags);
2877 }
2878
2879 static void
qla_trace_init(void)2880 qla_trace_init(void)
2881 {
2882 qla_trc_array = trace_array_get_by_name("qla2xxx", NULL);
2883 if (!qla_trc_array) {
2884 ql_log(ql_log_fatal, NULL, 0x0001,
2885 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n");
2886 return;
2887 }
2888
2889 QLA_TRACE_ENABLE(qla_trc_array);
2890 }
2891
2892 static void
qla_trace_uninit(void)2893 qla_trace_uninit(void)
2894 {
2895 if (!qla_trc_array)
2896 return;
2897 trace_array_put(qla_trc_array);
2898 }
2899
2900 /*
2901 * PCI driver interface
2902 */
2903 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2904 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2905 {
2906 int ret = -ENODEV;
2907 struct Scsi_Host *host;
2908 scsi_qla_host_t *base_vha = NULL;
2909 struct qla_hw_data *ha;
2910 char pci_info[30];
2911 char fw_str[30], wq_name[30];
2912 struct scsi_host_template *sht;
2913 int bars, mem_only = 0;
2914 uint16_t req_length = 0, rsp_length = 0;
2915 struct req_que *req = NULL;
2916 struct rsp_que *rsp = NULL;
2917 int i;
2918
2919 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2920 sht = &qla2xxx_driver_template;
2921 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2922 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2923 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2929 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2930 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2931 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2932 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2933 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2934 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2935 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2936 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2937 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2938 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2939 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2940 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2941 mem_only = 1;
2942 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2943 "Mem only adapter.\n");
2944 }
2945 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2946 "Bars=%d.\n", bars);
2947
2948 if (mem_only) {
2949 if (pci_enable_device_mem(pdev))
2950 return ret;
2951 } else {
2952 if (pci_enable_device(pdev))
2953 return ret;
2954 }
2955
2956 if (is_kdump_kernel()) {
2957 ql2xmqsupport = 0;
2958 ql2xallocfwdump = 0;
2959 }
2960
2961 ha = kzalloc_obj(struct qla_hw_data);
2962 if (!ha) {
2963 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2964 "Unable to allocate memory for ha.\n");
2965 goto disable_device;
2966 }
2967 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2968 "Memory allocated for ha=%p.\n", ha);
2969 ha->pdev = pdev;
2970 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2971 spin_lock_init(&ha->tgt.q_full_lock);
2972 spin_lock_init(&ha->tgt.sess_lock);
2973 spin_lock_init(&ha->tgt.atio_lock);
2974
2975 spin_lock_init(&ha->sadb_lock);
2976 INIT_LIST_HEAD(&ha->sadb_tx_index_list);
2977 INIT_LIST_HEAD(&ha->sadb_rx_index_list);
2978
2979 spin_lock_init(&ha->sadb_fp_lock);
2980
2981 if (qla_edif_sadb_build_free_pool(ha)) {
2982 kfree(ha);
2983 goto disable_device;
2984 }
2985
2986 atomic_set(&ha->nvme_active_aen_cnt, 0);
2987
2988 /* Clear our data area */
2989 ha->bars = bars;
2990 ha->mem_only = mem_only;
2991 spin_lock_init(&ha->hardware_lock);
2992 spin_lock_init(&ha->vport_slock);
2993 mutex_init(&ha->selflogin_lock);
2994 mutex_init(&ha->optrom_mutex);
2995
2996 /* Set ISP-type information. */
2997 qla2x00_set_isp_flags(ha);
2998
2999 /* Set EEH reset type to fundamental if required by hba */
3000 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
3001 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3002 pdev->needs_freset = 1;
3003
3004 ha->prev_topology = 0;
3005 ha->init_cb_size = sizeof(init_cb_t);
3006 ha->link_data_rate = PORT_SPEED_UNKNOWN;
3007 ha->optrom_size = OPTROM_SIZE_2300;
3008 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
3009 atomic_set(&ha->num_pend_mbx_stage1, 0);
3010 atomic_set(&ha->num_pend_mbx_stage2, 0);
3011 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
3012 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
3013 INIT_LIST_HEAD(&ha->tmf_pending);
3014 INIT_LIST_HEAD(&ha->tmf_active);
3015
3016 /* Assign ISP specific operations. */
3017 if (IS_QLA2100(ha)) {
3018 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3019 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
3020 req_length = REQUEST_ENTRY_CNT_2100;
3021 rsp_length = RESPONSE_ENTRY_CNT_2100;
3022 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3023 ha->gid_list_info_size = 4;
3024 ha->flash_conf_off = ~0;
3025 ha->flash_data_off = ~0;
3026 ha->nvram_conf_off = ~0;
3027 ha->nvram_data_off = ~0;
3028 ha->isp_ops = &qla2100_isp_ops;
3029 } else if (IS_QLA2200(ha)) {
3030 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3031 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
3032 req_length = REQUEST_ENTRY_CNT_2200;
3033 rsp_length = RESPONSE_ENTRY_CNT_2100;
3034 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3035 ha->gid_list_info_size = 4;
3036 ha->flash_conf_off = ~0;
3037 ha->flash_data_off = ~0;
3038 ha->nvram_conf_off = ~0;
3039 ha->nvram_data_off = ~0;
3040 ha->isp_ops = &qla2100_isp_ops;
3041 } else if (IS_QLA23XX(ha)) {
3042 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3043 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3044 req_length = REQUEST_ENTRY_CNT_2200;
3045 rsp_length = RESPONSE_ENTRY_CNT_2300;
3046 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3047 ha->gid_list_info_size = 6;
3048 if (IS_QLA2322(ha) || IS_QLA6322(ha))
3049 ha->optrom_size = OPTROM_SIZE_2322;
3050 ha->flash_conf_off = ~0;
3051 ha->flash_data_off = ~0;
3052 ha->nvram_conf_off = ~0;
3053 ha->nvram_data_off = ~0;
3054 ha->isp_ops = &qla2300_isp_ops;
3055 } else if (IS_QLA24XX_TYPE(ha)) {
3056 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3057 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3058 req_length = REQUEST_ENTRY_CNT_24XX;
3059 rsp_length = RESPONSE_ENTRY_CNT_2300;
3060 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3061 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3062 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3063 ha->gid_list_info_size = 8;
3064 ha->optrom_size = OPTROM_SIZE_24XX;
3065 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
3066 ha->isp_ops = &qla24xx_isp_ops;
3067 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3068 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3069 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3070 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3071 } else if (IS_QLA25XX(ha)) {
3072 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3073 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3074 req_length = REQUEST_ENTRY_CNT_24XX;
3075 rsp_length = RESPONSE_ENTRY_CNT_2300;
3076 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3077 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3078 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3079 ha->gid_list_info_size = 8;
3080 ha->optrom_size = OPTROM_SIZE_25XX;
3081 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3082 ha->isp_ops = &qla25xx_isp_ops;
3083 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3084 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3085 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3086 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3087 } else if (IS_QLA81XX(ha)) {
3088 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3089 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3090 req_length = REQUEST_ENTRY_CNT_24XX;
3091 rsp_length = RESPONSE_ENTRY_CNT_2300;
3092 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3093 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3094 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3095 ha->gid_list_info_size = 8;
3096 ha->optrom_size = OPTROM_SIZE_81XX;
3097 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3098 ha->isp_ops = &qla81xx_isp_ops;
3099 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3100 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3101 ha->nvram_conf_off = ~0;
3102 ha->nvram_data_off = ~0;
3103 } else if (IS_QLA82XX(ha)) {
3104 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3105 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3106 req_length = REQUEST_ENTRY_CNT_82XX;
3107 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3108 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3109 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3110 ha->gid_list_info_size = 8;
3111 ha->optrom_size = OPTROM_SIZE_82XX;
3112 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3113 ha->isp_ops = &qla82xx_isp_ops;
3114 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3115 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3116 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3117 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3118 } else if (IS_QLA8044(ha)) {
3119 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3120 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3121 req_length = REQUEST_ENTRY_CNT_82XX;
3122 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3123 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3124 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3125 ha->gid_list_info_size = 8;
3126 ha->optrom_size = OPTROM_SIZE_83XX;
3127 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3128 ha->isp_ops = &qla8044_isp_ops;
3129 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3130 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3131 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3132 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3133 } else if (IS_QLA83XX(ha)) {
3134 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3135 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3136 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3137 req_length = REQUEST_ENTRY_CNT_83XX;
3138 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3139 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3140 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3141 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3142 ha->gid_list_info_size = 8;
3143 ha->optrom_size = OPTROM_SIZE_83XX;
3144 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3145 ha->isp_ops = &qla83xx_isp_ops;
3146 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3147 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3148 ha->nvram_conf_off = ~0;
3149 ha->nvram_data_off = ~0;
3150 } else if (IS_QLAFX00(ha)) {
3151 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3152 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3153 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3154 req_length = REQUEST_ENTRY_CNT_FX00;
3155 rsp_length = RESPONSE_ENTRY_CNT_FX00;
3156 ha->isp_ops = &qlafx00_isp_ops;
3157 ha->port_down_retry_count = 30; /* default value */
3158 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3159 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3160 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3161 ha->mr.fw_hbt_en = 1;
3162 ha->mr.host_info_resend = false;
3163 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3164 } else if (IS_QLA27XX(ha)) {
3165 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3166 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3167 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3168 req_length = REQUEST_ENTRY_CNT_83XX;
3169 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3170 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3171 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3172 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3173 ha->gid_list_info_size = 8;
3174 ha->optrom_size = OPTROM_SIZE_83XX;
3175 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3176 ha->isp_ops = &qla27xx_isp_ops;
3177 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3178 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3179 ha->nvram_conf_off = ~0;
3180 ha->nvram_data_off = ~0;
3181 } else if (IS_QLA28XX(ha)) {
3182 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3183 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3184 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3185 req_length = REQUEST_ENTRY_CNT_83XX;
3186 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3187 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3188 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3189 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3190 ha->gid_list_info_size = 8;
3191 ha->optrom_size = OPTROM_SIZE_28XX;
3192 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3193 ha->isp_ops = &qla27xx_isp_ops;
3194 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3195 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3196 ha->nvram_conf_off = ~0;
3197 ha->nvram_data_off = ~0;
3198 }
3199
3200 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3201 "mbx_count=%d, req_length=%d, "
3202 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3203 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3204 "max_fibre_devices=%d.\n",
3205 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3206 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3207 ha->nvram_npiv_size, ha->max_fibre_devices);
3208 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3209 "isp_ops=%p, flash_conf_off=%d, "
3210 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3211 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3212 ha->nvram_conf_off, ha->nvram_data_off);
3213
3214 /* Configure PCI I/O space */
3215 ret = ha->isp_ops->iospace_config(ha);
3216 if (ret)
3217 goto iospace_config_failed;
3218
3219 ql_log_pci(ql_log_info, pdev, 0x001d,
3220 "Found an ISP%04X irq %d iobase 0x%p.\n",
3221 pdev->device, pdev->irq, ha->iobase);
3222 mutex_init(&ha->vport_lock);
3223 mutex_init(&ha->mq_lock);
3224 init_completion(&ha->mbx_cmd_comp);
3225 complete(&ha->mbx_cmd_comp);
3226 init_completion(&ha->mbx_intr_comp);
3227 init_completion(&ha->dcbx_comp);
3228 init_completion(&ha->lb_portup_comp);
3229
3230 set_bit(0, (unsigned long *) ha->vp_idx_map);
3231
3232 qla2x00_config_dma_addressing(ha);
3233 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3234 "64 Bit addressing is %s.\n",
3235 ha->flags.enable_64bit_addressing ? "enable" :
3236 "disable");
3237 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3238 if (ret) {
3239 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3240 "Failed to allocate memory for adapter, aborting.\n");
3241
3242 goto probe_hw_failed;
3243 }
3244
3245 req->max_q_depth = MAX_Q_DEPTH;
3246 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3247 req->max_q_depth = ql2xmaxqdepth;
3248
3249
3250 base_vha = qla2x00_create_host(sht, ha);
3251 if (!base_vha) {
3252 ret = -ENOMEM;
3253 goto probe_hw_failed;
3254 }
3255
3256 pci_set_drvdata(pdev, base_vha);
3257 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3258
3259 host = base_vha->host;
3260 base_vha->req = req;
3261 if (IS_QLA2XXX_MIDTYPE(ha))
3262 base_vha->mgmt_svr_loop_id =
3263 qla2x00_reserve_mgmt_server_loop_id(base_vha);
3264 else
3265 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3266 base_vha->vp_idx;
3267
3268 /* Setup fcport template structure. */
3269 ha->mr.fcport.vha = base_vha;
3270 ha->mr.fcport.port_type = FCT_UNKNOWN;
3271 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3272 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3273 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3274 ha->mr.fcport.scan_state = 1;
3275
3276 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN |
3277 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT |
3278 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN);
3279
3280 /* Set the SG table size based on ISP type */
3281 if (!IS_FWI2_CAPABLE(ha)) {
3282 if (IS_QLA2100(ha))
3283 host->sg_tablesize = 32;
3284 } else {
3285 if (!IS_QLA82XX(ha))
3286 host->sg_tablesize = QLA_SG_ALL;
3287 }
3288 host->max_id = ha->max_fibre_devices;
3289 host->cmd_per_lun = 3;
3290 host->unique_id = host->host_no;
3291
3292 if (ql2xenabledif && ql2xenabledif != 2) {
3293 ql_log(ql_log_warn, base_vha, 0x302d,
3294 "Invalid value for ql2xenabledif, resetting it to default (2)\n");
3295 ql2xenabledif = 2;
3296 }
3297
3298 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3299 host->max_cmd_len = 32;
3300 else
3301 host->max_cmd_len = MAX_CMDSZ;
3302 host->max_channel = MAX_BUSES - 1;
3303 /* Older HBAs support only 16-bit LUNs */
3304 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3305 ql2xmaxlun > 0xffff)
3306 host->max_lun = 0xffff;
3307 else
3308 host->max_lun = ql2xmaxlun;
3309 host->transportt = qla2xxx_transport_template;
3310 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3311
3312 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3313 "max_id=%d this_id=%d "
3314 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3315 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3316 host->this_id, host->cmd_per_lun, host->unique_id,
3317 host->max_cmd_len, host->max_channel, host->max_lun,
3318 host->transportt, sht->vendor_id);
3319
3320 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
3321
3322 /* Set up the irqs */
3323 ret = qla2x00_request_irqs(ha, rsp);
3324 if (ret)
3325 goto probe_failed;
3326
3327 /* Alloc arrays of request and response ring ptrs */
3328 ret = qla2x00_alloc_queues(ha, req, rsp);
3329 if (ret) {
3330 ql_log(ql_log_fatal, base_vha, 0x003d,
3331 "Failed to allocate memory for queue pointers..."
3332 "aborting.\n");
3333 ret = -ENODEV;
3334 goto probe_failed;
3335 }
3336
3337 if (ha->mqenable) {
3338 /* number of hardware queues supported by blk/scsi-mq*/
3339 host->nr_hw_queues = ha->max_qpairs;
3340
3341 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3342 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3343 } else {
3344 if (ql2xnvmeenable) {
3345 host->nr_hw_queues = ha->max_qpairs;
3346 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3347 "FC-NVMe support is enabled, HW queues=%d\n",
3348 host->nr_hw_queues);
3349 } else {
3350 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3351 "blk/scsi-mq disabled.\n");
3352 }
3353 }
3354
3355 qlt_probe_one_stage1(base_vha, ha);
3356
3357 pci_save_state(pdev);
3358
3359 /* Assign back pointers */
3360 rsp->req = req;
3361 req->rsp = rsp;
3362
3363 if (IS_QLAFX00(ha)) {
3364 ha->rsp_q_map[0] = rsp;
3365 ha->req_q_map[0] = req;
3366 set_bit(0, ha->req_qid_map);
3367 set_bit(0, ha->rsp_qid_map);
3368 }
3369
3370 /* FWI2-capable only. */
3371 req->req_q_in = &ha->iobase->isp24.req_q_in;
3372 req->req_q_out = &ha->iobase->isp24.req_q_out;
3373 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3374 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3375 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3376 IS_QLA28XX(ha)) {
3377 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3378 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3379 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3380 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3381 }
3382
3383 if (IS_QLAFX00(ha)) {
3384 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3385 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3386 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3387 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3388 }
3389
3390 if (IS_P3P_TYPE(ha)) {
3391 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3392 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3393 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3394 }
3395
3396 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3397 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3398 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3399 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3400 "req->req_q_in=%p req->req_q_out=%p "
3401 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3402 req->req_q_in, req->req_q_out,
3403 rsp->rsp_q_in, rsp->rsp_q_out);
3404 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3405 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3406 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3407 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3408 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3409 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3410
3411 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM | WQ_PERCPU, 0);
3412 if (unlikely(!ha->wq)) {
3413 ret = -ENOMEM;
3414 goto probe_failed;
3415 }
3416
3417 if (ha->isp_ops->initialize_adapter(base_vha)) {
3418 ql_log(ql_log_fatal, base_vha, 0x00d6,
3419 "Failed to initialize adapter - Adapter flags %x.\n",
3420 base_vha->device_flags);
3421
3422 if (IS_QLA82XX(ha)) {
3423 qla82xx_idc_lock(ha);
3424 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3425 QLA8XXX_DEV_FAILED);
3426 qla82xx_idc_unlock(ha);
3427 ql_log(ql_log_fatal, base_vha, 0x00d7,
3428 "HW State: FAILED.\n");
3429 } else if (IS_QLA8044(ha)) {
3430 qla8044_idc_lock(ha);
3431 qla8044_wr_direct(base_vha,
3432 QLA8044_CRB_DEV_STATE_INDEX,
3433 QLA8XXX_DEV_FAILED);
3434 qla8044_idc_unlock(ha);
3435 ql_log(ql_log_fatal, base_vha, 0x0150,
3436 "HW State: FAILED.\n");
3437 }
3438
3439 ret = -ENODEV;
3440 goto probe_failed;
3441 }
3442
3443 if (IS_QLAFX00(ha))
3444 host->can_queue = QLAFX00_MAX_CANQUEUE;
3445 else
3446 host->can_queue = req->num_outstanding_cmds - 10;
3447
3448 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3449 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3450 host->can_queue, base_vha->req,
3451 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3452
3453 /* Check if FW supports MQ or not for ISP25xx */
3454 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
3455 ha->mqenable = 0;
3456
3457 if (ha->mqenable) {
3458 bool startit = !!(host->active_mode & MODE_INITIATOR);
3459
3460 /* Create start of day qpairs for Block MQ */
3461 for (i = 0; i < ha->max_qpairs; i++)
3462 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3463 }
3464 qla_init_iocb_limit(base_vha);
3465
3466 if (ha->flags.running_gold_fw)
3467 goto skip_dpc;
3468
3469 /*
3470 * Startup the kernel thread for this host adapter
3471 */
3472 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3473 "%s_dpc", base_vha->host_str);
3474 if (IS_ERR(ha->dpc_thread)) {
3475 ql_log(ql_log_fatal, base_vha, 0x00ed,
3476 "Failed to start DPC thread.\n");
3477 ret = PTR_ERR(ha->dpc_thread);
3478 ha->dpc_thread = NULL;
3479 goto probe_failed;
3480 }
3481 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3482 "DPC thread started successfully.\n");
3483
3484 /*
3485 * If we're not coming up in initiator mode, we might sit for
3486 * a while without waking up the dpc thread, which leads to a
3487 * stuck process warning. So just kick the dpc once here and
3488 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3489 */
3490 qla2xxx_wake_dpc(base_vha);
3491
3492 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3493
3494 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3495 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3496 ha->dpc_lp_wq =
3497 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
3498 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3499
3500 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3501 ha->dpc_hp_wq =
3502 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
3503 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3504 INIT_WORK(&ha->idc_state_handler,
3505 qla83xx_idc_state_handler_work);
3506 INIT_WORK(&ha->nic_core_unrecoverable,
3507 qla83xx_nic_core_unrecoverable_work);
3508 }
3509
3510 skip_dpc:
3511 list_add_tail(&base_vha->list, &ha->vp_list);
3512 base_vha->host->irq = ha->pdev->irq;
3513
3514 /* Initialized the timer */
3515 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3516 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3517 "Started qla2x00_timer with "
3518 "interval=%d.\n", WATCH_INTERVAL);
3519 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3520 "Detected hba at address=%p.\n",
3521 ha);
3522
3523 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3524 if (ha->fw_attributes & BIT_4) {
3525 int prot = 0, guard;
3526
3527 base_vha->flags.difdix_supported = 1;
3528 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3529 "Registering for DIF/DIX type 1 and 3 protection.\n");
3530 if (ql2xprotmask)
3531 scsi_host_set_prot(host, ql2xprotmask);
3532 else
3533 scsi_host_set_prot(host,
3534 prot | SHOST_DIF_TYPE1_PROTECTION
3535 | SHOST_DIF_TYPE2_PROTECTION
3536 | SHOST_DIF_TYPE3_PROTECTION
3537 | SHOST_DIX_TYPE1_PROTECTION
3538 | SHOST_DIX_TYPE2_PROTECTION
3539 | SHOST_DIX_TYPE3_PROTECTION);
3540
3541 guard = SHOST_DIX_GUARD_CRC;
3542
3543 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3544 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3545 guard |= SHOST_DIX_GUARD_IP;
3546
3547 if (ql2xprotguard)
3548 scsi_host_set_guard(host, ql2xprotguard);
3549 else
3550 scsi_host_set_guard(host, guard);
3551 } else
3552 base_vha->flags.difdix_supported = 0;
3553 }
3554
3555 ha->isp_ops->enable_intrs(ha);
3556
3557 if (IS_QLAFX00(ha)) {
3558 ret = qlafx00_fx_disc(base_vha,
3559 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3560 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3561 QLA_SG_ALL : 128;
3562 }
3563
3564 if (IS_T10_PI_CAPABLE(base_vha->hw))
3565 host->dma_alignment = 0x7;
3566
3567 ret = scsi_add_host(host, &pdev->dev);
3568 if (ret)
3569 goto probe_failed;
3570
3571 base_vha->flags.init_done = 1;
3572 base_vha->flags.online = 1;
3573 ha->prev_minidump_failed = 0;
3574
3575 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3576 "Init done and hba is online.\n");
3577
3578 if (qla_ini_mode_enabled(base_vha) ||
3579 qla_dual_mode_enabled(base_vha))
3580 scsi_scan_host(host);
3581 else
3582 ql_log(ql_log_info, base_vha, 0x0122,
3583 "skipping scsi_scan_host() for non-initiator port\n");
3584
3585 qla2x00_alloc_sysfs_attr(base_vha);
3586
3587 if (IS_QLAFX00(ha)) {
3588 ret = qlafx00_fx_disc(base_vha,
3589 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3590
3591 /* Register system information */
3592 ret = qlafx00_fx_disc(base_vha,
3593 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3594 }
3595
3596 qla2x00_init_host_attr(base_vha);
3597
3598 qla2x00_dfs_setup(base_vha);
3599
3600 ql_log(ql_log_info, base_vha, 0x00fb,
3601 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3602 ql_log(ql_log_info, base_vha, 0x00fc,
3603 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3604 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3605 sizeof(pci_info)),
3606 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3607 base_vha->host_no,
3608 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3609
3610 qlt_add_target(ha, base_vha);
3611
3612 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3613
3614 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3615 return -ENODEV;
3616
3617 return 0;
3618
3619 probe_failed:
3620 qla_enode_stop(base_vha);
3621 qla_edb_stop(base_vha);
3622 vfree(base_vha->scan.l);
3623 if (base_vha->gnl.l) {
3624 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3625 base_vha->gnl.l, base_vha->gnl.ldma);
3626 base_vha->gnl.l = NULL;
3627 }
3628
3629 if (base_vha->timer_active)
3630 qla2x00_stop_timer(base_vha);
3631 base_vha->flags.online = 0;
3632 if (ha->dpc_thread) {
3633 struct task_struct *t = ha->dpc_thread;
3634
3635 ha->dpc_thread = NULL;
3636 kthread_stop(t);
3637 }
3638
3639 qla2x00_free_device(base_vha);
3640 scsi_host_put(base_vha->host);
3641 /*
3642 * Need to NULL out local req/rsp after
3643 * qla2x00_free_device => qla2x00_free_queues frees
3644 * what these are pointing to. Or else we'll
3645 * fall over below in qla2x00_free_req/rsp_que.
3646 */
3647 req = NULL;
3648 rsp = NULL;
3649
3650 probe_hw_failed:
3651 qla2x00_mem_free(ha);
3652 qla2x00_free_req_que(ha, req);
3653 qla2x00_free_rsp_que(ha, rsp);
3654 qla2x00_clear_drv_active(ha);
3655
3656 iospace_config_failed:
3657 if (IS_P3P_TYPE(ha)) {
3658 if (!ha->nx_pcibase)
3659 iounmap((device_reg_t *)ha->nx_pcibase);
3660 if (!ql2xdbwr)
3661 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3662 } else {
3663 if (ha->iobase)
3664 iounmap(ha->iobase);
3665 if (ha->cregbase)
3666 iounmap(ha->cregbase);
3667 }
3668 pci_release_selected_regions(ha->pdev, ha->bars);
3669 kfree(ha);
3670
3671 disable_device:
3672 pci_disable_device(pdev);
3673 return ret;
3674 }
3675
__qla_set_remove_flag(scsi_qla_host_t * base_vha)3676 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3677 {
3678 scsi_qla_host_t *vp;
3679 unsigned long flags;
3680 struct qla_hw_data *ha;
3681
3682 if (!base_vha)
3683 return;
3684
3685 ha = base_vha->hw;
3686
3687 spin_lock_irqsave(&ha->vport_slock, flags);
3688 list_for_each_entry(vp, &ha->vp_list, list)
3689 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3690
3691 /*
3692 * Indicate device removal to prevent future board_disable
3693 * and wait until any pending board_disable has completed.
3694 */
3695 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3696 spin_unlock_irqrestore(&ha->vport_slock, flags);
3697 }
3698
3699 static void
qla2x00_shutdown(struct pci_dev * pdev)3700 qla2x00_shutdown(struct pci_dev *pdev)
3701 {
3702 scsi_qla_host_t *vha;
3703 struct qla_hw_data *ha;
3704
3705 vha = pci_get_drvdata(pdev);
3706 ha = vha->hw;
3707
3708 ql_log(ql_log_info, vha, 0xfffa,
3709 "Adapter shutdown\n");
3710
3711 /*
3712 * Prevent future board_disable and wait
3713 * until any pending board_disable has completed.
3714 */
3715 __qla_set_remove_flag(vha);
3716 cancel_work_sync(&ha->board_disable);
3717
3718 if (!atomic_read(&pdev->enable_cnt))
3719 return;
3720
3721 /* Notify ISPFX00 firmware */
3722 if (IS_QLAFX00(ha))
3723 qlafx00_driver_shutdown(vha, 20);
3724
3725 /* Turn-off FCE trace */
3726 if (ha->flags.fce_enabled) {
3727 qla2x00_disable_fce_trace(vha, NULL, NULL);
3728 ha->flags.fce_enabled = 0;
3729 }
3730
3731 /* Turn-off EFT trace */
3732 if (ha->eft)
3733 qla2x00_disable_eft_trace(vha);
3734
3735 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3736 IS_QLA28XX(ha)) {
3737 if (ha->flags.fw_started)
3738 qla2x00_abort_isp_cleanup(vha);
3739 } else {
3740 /* Stop currently executing firmware. */
3741 qla2x00_try_to_stop_firmware(vha);
3742 }
3743
3744 /* Disable timer */
3745 if (vha->timer_active)
3746 qla2x00_stop_timer(vha);
3747
3748 /* Turn adapter off line */
3749 vha->flags.online = 0;
3750
3751 /* turn-off interrupts on the card */
3752 if (ha->interrupts_on) {
3753 vha->flags.init_done = 0;
3754 ha->isp_ops->disable_intrs(ha);
3755 }
3756
3757 qla2x00_free_irqs(vha);
3758
3759 qla2x00_free_fw_dump(ha);
3760
3761 pci_disable_device(pdev);
3762 ql_log(ql_log_info, vha, 0xfffe,
3763 "Adapter shutdown successfully.\n");
3764 }
3765
3766 /* Deletes all the virtual ports for a given ha */
3767 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)3768 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3769 {
3770 scsi_qla_host_t *vha;
3771 unsigned long flags;
3772
3773 mutex_lock(&ha->vport_lock);
3774 while (ha->cur_vport_count) {
3775 spin_lock_irqsave(&ha->vport_slock, flags);
3776
3777 BUG_ON(base_vha->list.next == &ha->vp_list);
3778 /* This assumes first entry in ha->vp_list is always base vha */
3779 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3780 scsi_host_get(vha->host);
3781
3782 spin_unlock_irqrestore(&ha->vport_slock, flags);
3783 mutex_unlock(&ha->vport_lock);
3784
3785 qla_nvme_delete(vha);
3786
3787 fc_vport_terminate(vha->fc_vport);
3788 scsi_host_put(vha->host);
3789
3790 mutex_lock(&ha->vport_lock);
3791 }
3792 mutex_unlock(&ha->vport_lock);
3793 }
3794
3795 /* Stops all deferred work threads */
3796 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3797 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3798 {
3799 /* Cancel all work and destroy DPC workqueues */
3800 if (ha->dpc_lp_wq) {
3801 cancel_work_sync(&ha->idc_aen);
3802 destroy_workqueue(ha->dpc_lp_wq);
3803 ha->dpc_lp_wq = NULL;
3804 }
3805
3806 if (ha->dpc_hp_wq) {
3807 cancel_work_sync(&ha->nic_core_reset);
3808 cancel_work_sync(&ha->idc_state_handler);
3809 cancel_work_sync(&ha->nic_core_unrecoverable);
3810 destroy_workqueue(ha->dpc_hp_wq);
3811 ha->dpc_hp_wq = NULL;
3812 }
3813
3814 /* Kill the kernel thread for this host */
3815 if (ha->dpc_thread) {
3816 struct task_struct *t = ha->dpc_thread;
3817
3818 /*
3819 * qla2xxx_wake_dpc checks for ->dpc_thread
3820 * so we need to zero it out.
3821 */
3822 ha->dpc_thread = NULL;
3823 kthread_stop(t);
3824 }
3825 }
3826
3827 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3828 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3829 {
3830 if (IS_QLA82XX(ha)) {
3831
3832 iounmap((device_reg_t *)ha->nx_pcibase);
3833 if (!ql2xdbwr)
3834 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3835 } else {
3836 if (ha->iobase)
3837 iounmap(ha->iobase);
3838
3839 if (ha->cregbase)
3840 iounmap(ha->cregbase);
3841
3842 if (ha->mqiobase)
3843 iounmap(ha->mqiobase);
3844
3845 if (ha->msixbase)
3846 iounmap(ha->msixbase);
3847 }
3848 }
3849
3850 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3851 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3852 {
3853 if (IS_QLA8044(ha)) {
3854 qla8044_idc_lock(ha);
3855 qla8044_clear_drv_active(ha);
3856 qla8044_idc_unlock(ha);
3857 } else if (IS_QLA82XX(ha)) {
3858 qla82xx_idc_lock(ha);
3859 qla82xx_clear_drv_active(ha);
3860 qla82xx_idc_unlock(ha);
3861 }
3862 }
3863
3864 static void
qla2x00_remove_one(struct pci_dev * pdev)3865 qla2x00_remove_one(struct pci_dev *pdev)
3866 {
3867 scsi_qla_host_t *base_vha;
3868 struct qla_hw_data *ha;
3869
3870 base_vha = pci_get_drvdata(pdev);
3871 ha = base_vha->hw;
3872 ql_log(ql_log_info, base_vha, 0xb079,
3873 "Removing driver\n");
3874 __qla_set_remove_flag(base_vha);
3875 cancel_work_sync(&ha->board_disable);
3876
3877 /*
3878 * If the PCI device is disabled then there was a PCI-disconnect and
3879 * qla2x00_disable_board_on_pci_error has taken care of most of the
3880 * resources.
3881 */
3882 if (!atomic_read(&pdev->enable_cnt)) {
3883 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3884 base_vha->gnl.l, base_vha->gnl.ldma);
3885 base_vha->gnl.l = NULL;
3886 scsi_host_put(base_vha->host);
3887 kfree(ha);
3888 pci_set_drvdata(pdev, NULL);
3889 return;
3890 }
3891 qla2x00_wait_for_hba_ready(base_vha);
3892
3893 /*
3894 * if UNLOADING flag is already set, then continue unload,
3895 * where it was set first.
3896 */
3897 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3898 return;
3899
3900 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3901 IS_QLA28XX(ha)) {
3902 if (ha->flags.fw_started)
3903 qla2x00_abort_isp_cleanup(base_vha);
3904 } else if (!IS_QLAFX00(ha)) {
3905 if (IS_QLA8031(ha)) {
3906 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3907 "Clearing fcoe driver presence.\n");
3908 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3909 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3910 "Error while clearing DRV-Presence.\n");
3911 }
3912
3913 qla2x00_try_to_stop_firmware(base_vha);
3914 }
3915
3916 qla2x00_wait_for_sess_deletion(base_vha);
3917
3918 qla_nvme_delete(base_vha);
3919
3920 dma_free_coherent(&ha->pdev->dev,
3921 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3922
3923 base_vha->gnl.l = NULL;
3924 qla_enode_stop(base_vha);
3925 qla_edb_stop(base_vha);
3926
3927 vfree(base_vha->scan.l);
3928
3929 if (IS_QLAFX00(ha))
3930 qlafx00_driver_shutdown(base_vha, 20);
3931
3932 qla2x00_delete_all_vps(ha, base_vha);
3933
3934 qla2x00_dfs_remove(base_vha);
3935
3936 qla84xx_put_chip(base_vha);
3937
3938 /* Disable timer */
3939 if (base_vha->timer_active)
3940 qla2x00_stop_timer(base_vha);
3941
3942 base_vha->flags.online = 0;
3943
3944 /* free DMA memory */
3945 if (ha->exlogin_buf)
3946 qla2x00_free_exlogin_buffer(ha);
3947
3948 /* free DMA memory */
3949 if (ha->exchoffld_buf)
3950 qla2x00_free_exchoffld_buffer(ha);
3951
3952 qla2x00_destroy_deferred_work(ha);
3953
3954 qlt_remove_target(ha, base_vha);
3955
3956 qla2x00_free_sysfs_attr(base_vha, true);
3957
3958 fc_remove_host(base_vha->host);
3959
3960 scsi_remove_host(base_vha->host);
3961
3962 qla2x00_free_device(base_vha);
3963
3964 qla2x00_clear_drv_active(ha);
3965
3966 scsi_host_put(base_vha->host);
3967
3968 qla2x00_unmap_iobases(ha);
3969
3970 pci_release_selected_regions(ha->pdev, ha->bars);
3971 kfree(ha);
3972
3973 pci_disable_device(pdev);
3974 }
3975
3976 static inline void
qla24xx_free_purex_list(struct purex_list * list)3977 qla24xx_free_purex_list(struct purex_list *list)
3978 {
3979 struct purex_item *item, *next;
3980 ulong flags;
3981
3982 spin_lock_irqsave(&list->lock, flags);
3983 list_for_each_entry_safe(item, next, &list->head, list) {
3984 list_del(&item->list);
3985 if (item == &item->vha->default_item)
3986 continue;
3987 kfree(item);
3988 }
3989 spin_unlock_irqrestore(&list->lock, flags);
3990 }
3991
3992 static void
qla2x00_free_device(scsi_qla_host_t * vha)3993 qla2x00_free_device(scsi_qla_host_t *vha)
3994 {
3995 struct qla_hw_data *ha = vha->hw;
3996
3997 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3998
3999 /* Disable timer */
4000 if (vha->timer_active)
4001 qla2x00_stop_timer(vha);
4002
4003 qla25xx_delete_queues(vha);
4004 vha->flags.online = 0;
4005
4006 /* turn-off interrupts on the card */
4007 if (ha->interrupts_on) {
4008 vha->flags.init_done = 0;
4009 ha->isp_ops->disable_intrs(ha);
4010 }
4011
4012 qla2x00_free_fcports(vha);
4013
4014 qla2x00_free_irqs(vha);
4015
4016 /* Flush the work queue and remove it */
4017 if (ha->wq) {
4018 destroy_workqueue(ha->wq);
4019 ha->wq = NULL;
4020 }
4021
4022
4023 qla24xx_free_purex_list(&vha->purex_list);
4024
4025 qla2x00_mem_free(ha);
4026
4027 qla82xx_md_free(vha);
4028
4029 qla_edif_sadb_release_free_pool(ha);
4030 qla_edif_sadb_release(ha);
4031
4032 qla2x00_free_queues(ha);
4033 }
4034
qla2x00_free_fcports(struct scsi_qla_host * vha)4035 void qla2x00_free_fcports(struct scsi_qla_host *vha)
4036 {
4037 fc_port_t *fcport, *tfcport;
4038
4039 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
4040 qla2x00_free_fcport(fcport);
4041 }
4042
4043 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport)4044 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
4045 {
4046 int now;
4047
4048 if (!fcport->rport)
4049 return;
4050
4051 if (fcport->rport) {
4052 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
4053 "%s %8phN. rport %p roles %x\n",
4054 __func__, fcport->port_name, fcport->rport,
4055 fcport->rport->roles);
4056 fc_remote_port_delete(fcport->rport);
4057 }
4058 qlt_do_generation_tick(vha, &now);
4059 }
4060
4061 /*
4062 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
4063 *
4064 * Input: ha = adapter block pointer. fcport = port structure pointer.
4065 *
4066 * Return: None.
4067 *
4068 * Context:
4069 */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login)4070 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
4071 int do_login)
4072 {
4073 if (IS_QLAFX00(vha->hw)) {
4074 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4075 qla2x00_schedule_rport_del(vha, fcport);
4076 return;
4077 }
4078
4079 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4080 vha->vp_idx == fcport->vha->vp_idx) {
4081 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4082 qla2x00_schedule_rport_del(vha, fcport);
4083 }
4084
4085 /*
4086 * We may need to retry the login, so don't change the state of the
4087 * port but do the retries.
4088 */
4089 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
4090 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4091
4092 if (!do_login)
4093 return;
4094
4095 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4096 }
4097
4098 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha)4099 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
4100 {
4101 fc_port_t *fcport;
4102
4103 ql_dbg(ql_dbg_disc, vha, 0x20f1,
4104 "Mark all dev lost\n");
4105
4106 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4107 if (ql2xfc2target &&
4108 fcport->loop_id != FC_NO_LOOP_ID &&
4109 (fcport->flags & FCF_FCP2_DEVICE) &&
4110 fcport->port_type == FCT_TARGET &&
4111 !qla2x00_reset_active(vha)) {
4112 ql_dbg(ql_dbg_disc, vha, 0x211a,
4113 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
4114 fcport->flags, fcport->port_type,
4115 fcport->d_id.b24, fcport->port_name);
4116 continue;
4117 }
4118 fcport->scan_state = 0;
4119 qlt_schedule_sess_for_deletion(fcport);
4120 }
4121 }
4122
qla2x00_set_reserved_loop_ids(struct qla_hw_data * ha)4123 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
4124 {
4125 int i;
4126
4127 if (IS_FWI2_CAPABLE(ha))
4128 return;
4129
4130 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
4131 set_bit(i, ha->loop_id_map);
4132 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
4133 set_bit(BROADCAST, ha->loop_id_map);
4134 }
4135
4136 /*
4137 * qla2x00_mem_alloc
4138 * Allocates adapter memory.
4139 *
4140 * Returns:
4141 * 0 = success.
4142 * !0 = failure.
4143 */
4144 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)4145 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
4146 struct req_que **req, struct rsp_que **rsp)
4147 {
4148 char name[16];
4149 int rc;
4150
4151 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) {
4152 ha->vp_map = kzalloc_objs(struct qla_vp_map,
4153 MAX_MULTI_ID_FABRIC);
4154 if (!ha->vp_map)
4155 goto fail;
4156 }
4157
4158 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
4159 &ha->init_cb_dma, GFP_KERNEL);
4160 if (!ha->init_cb)
4161 goto fail_free_vp_map;
4162
4163 rc = btree_init32(&ha->host_map);
4164 if (rc)
4165 goto fail_free_init_cb;
4166
4167 if (qlt_mem_alloc(ha) < 0)
4168 goto fail_free_btree;
4169
4170 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4171 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
4172 if (!ha->gid_list)
4173 goto fail_free_tgt_mem;
4174
4175 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4176 if (!ha->srb_mempool)
4177 goto fail_free_gid_list;
4178
4179 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) {
4180 /* Allocate cache for CT6 Ctx. */
4181 if (!ctx_cachep) {
4182 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4183 sizeof(struct ct6_dsd), 0,
4184 SLAB_HWCACHE_ALIGN, NULL);
4185 if (!ctx_cachep)
4186 goto fail_free_srb_mempool;
4187 }
4188 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4189 ctx_cachep);
4190 if (!ha->ctx_mempool)
4191 goto fail_free_srb_mempool;
4192 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4193 "ctx_cachep=%p ctx_mempool=%p.\n",
4194 ctx_cachep, ha->ctx_mempool);
4195 }
4196
4197 /* Get memory for cached NVRAM */
4198 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4199 if (!ha->nvram)
4200 goto fail_free_ctx_mempool;
4201
4202 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4203 ha->pdev->device);
4204 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4205 DMA_POOL_SIZE, 8, 0);
4206 if (!ha->s_dma_pool)
4207 goto fail_free_nvram;
4208
4209 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4210 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4211 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4212
4213 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) {
4214 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4215 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4216 if (!ha->dl_dma_pool) {
4217 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4218 "Failed to allocate memory for dl_dma_pool.\n");
4219 goto fail_s_dma_pool;
4220 }
4221
4222 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4223 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4224 if (!ha->fcp_cmnd_dma_pool) {
4225 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4226 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4227 goto fail_dl_dma_pool;
4228 }
4229
4230 if (ql2xenabledif) {
4231 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4232 struct dsd_dma *dsd, *nxt;
4233 uint i;
4234 /* Creata a DMA pool of buffers for DIF bundling */
4235 ha->dif_bundl_pool = dma_pool_create(name,
4236 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4237 if (!ha->dif_bundl_pool) {
4238 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4239 "%s: failed create dif_bundl_pool\n",
4240 __func__);
4241 goto fail_dif_bundl_dma_pool;
4242 }
4243
4244 INIT_LIST_HEAD(&ha->pool.good.head);
4245 INIT_LIST_HEAD(&ha->pool.unusable.head);
4246 ha->pool.good.count = 0;
4247 ha->pool.unusable.count = 0;
4248 for (i = 0; i < 128; i++) {
4249 dsd = kzalloc_obj(*dsd, GFP_ATOMIC);
4250 if (!dsd) {
4251 ql_dbg_pci(ql_dbg_init, ha->pdev,
4252 0xe0ee, "%s: failed alloc dsd\n",
4253 __func__);
4254 return -ENOMEM;
4255 }
4256 ha->dif_bundle_kallocs++;
4257
4258 dsd->dsd_addr = dma_pool_alloc(
4259 ha->dif_bundl_pool, GFP_ATOMIC,
4260 &dsd->dsd_list_dma);
4261 if (!dsd->dsd_addr) {
4262 ql_dbg_pci(ql_dbg_init, ha->pdev,
4263 0xe0ee,
4264 "%s: failed alloc ->dsd_addr\n",
4265 __func__);
4266 kfree(dsd);
4267 ha->dif_bundle_kallocs--;
4268 continue;
4269 }
4270 ha->dif_bundle_dma_allocs++;
4271
4272 /*
4273 * if DMA buffer crosses 4G boundary,
4274 * put it on bad list
4275 */
4276 if (MSD(dsd->dsd_list_dma) ^
4277 MSD(dsd->dsd_list_dma + bufsize)) {
4278 list_add_tail(&dsd->list,
4279 &ha->pool.unusable.head);
4280 ha->pool.unusable.count++;
4281 } else {
4282 list_add_tail(&dsd->list,
4283 &ha->pool.good.head);
4284 ha->pool.good.count++;
4285 }
4286 }
4287
4288 /* return the good ones back to the pool */
4289 list_for_each_entry_safe(dsd, nxt,
4290 &ha->pool.good.head, list) {
4291 list_del(&dsd->list);
4292 dma_pool_free(ha->dif_bundl_pool,
4293 dsd->dsd_addr, dsd->dsd_list_dma);
4294 ha->dif_bundle_dma_allocs--;
4295 kfree(dsd);
4296 ha->dif_bundle_kallocs--;
4297 }
4298
4299 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4300 "%s: dif dma pool (good=%u unusable=%u)\n",
4301 __func__, ha->pool.good.count,
4302 ha->pool.unusable.count);
4303 }
4304
4305 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4306 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4307 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4308 ha->dif_bundl_pool);
4309 }
4310
4311 /* Allocate memory for SNS commands */
4312 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4313 /* Get consistent memory allocated for SNS commands */
4314 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4315 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4316 if (!ha->sns_cmd)
4317 goto fail_dma_pool;
4318 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4319 "sns_cmd: %p.\n", ha->sns_cmd);
4320 } else {
4321 /* Get consistent memory allocated for MS IOCB */
4322 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4323 &ha->ms_iocb_dma);
4324 if (!ha->ms_iocb)
4325 goto fail_dma_pool;
4326 /* Get consistent memory allocated for CT SNS commands */
4327 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4328 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4329 if (!ha->ct_sns)
4330 goto fail_free_ms_iocb;
4331 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4332 "ms_iocb=%p ct_sns=%p.\n",
4333 ha->ms_iocb, ha->ct_sns);
4334 }
4335
4336 /* Allocate memory for request ring */
4337 *req = kzalloc_obj(struct req_que);
4338 if (!*req) {
4339 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4340 "Failed to allocate memory for req.\n");
4341 goto fail_req;
4342 }
4343 (*req)->length = req_len;
4344 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4345 ((*req)->length + 1) * sizeof(request_t),
4346 &(*req)->dma, GFP_KERNEL);
4347 if (!(*req)->ring) {
4348 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4349 "Failed to allocate memory for req_ring.\n");
4350 goto fail_req_ring;
4351 }
4352 /* Allocate memory for response ring */
4353 *rsp = kzalloc_obj(struct rsp_que);
4354 if (!*rsp) {
4355 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4356 "Failed to allocate memory for rsp.\n");
4357 goto fail_rsp;
4358 }
4359 (*rsp)->hw = ha;
4360 (*rsp)->length = rsp_len;
4361 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4362 ((*rsp)->length + 1) * sizeof(response_t),
4363 &(*rsp)->dma, GFP_KERNEL);
4364 if (!(*rsp)->ring) {
4365 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4366 "Failed to allocate memory for rsp_ring.\n");
4367 goto fail_rsp_ring;
4368 }
4369 (*req)->rsp = *rsp;
4370 (*rsp)->req = *req;
4371 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4372 "req=%p req->length=%d req->ring=%p rsp=%p "
4373 "rsp->length=%d rsp->ring=%p.\n",
4374 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4375 (*rsp)->ring);
4376 /* Allocate memory for NVRAM data for vports */
4377 if (ha->nvram_npiv_size) {
4378 ha->npiv_info = kzalloc_objs(struct qla_npiv_entry,
4379 ha->nvram_npiv_size);
4380 if (!ha->npiv_info) {
4381 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4382 "Failed to allocate memory for npiv_info.\n");
4383 goto fail_npiv_info;
4384 }
4385 } else
4386 ha->npiv_info = NULL;
4387
4388 /* Get consistent memory allocated for EX-INIT-CB. */
4389 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4390 IS_QLA28XX(ha)) {
4391 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4392 &ha->ex_init_cb_dma);
4393 if (!ha->ex_init_cb)
4394 goto fail_ex_init_cb;
4395 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4396 "ex_init_cb=%p.\n", ha->ex_init_cb);
4397 }
4398
4399 /* Get consistent memory allocated for Special Features-CB. */
4400 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4401 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
4402 &ha->sf_init_cb_dma);
4403 if (!ha->sf_init_cb)
4404 goto fail_sf_init_cb;
4405 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4406 "sf_init_cb=%p.\n", ha->sf_init_cb);
4407 }
4408
4409
4410 /* Get consistent memory allocated for Async Port-Database. */
4411 if (!IS_FWI2_CAPABLE(ha)) {
4412 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4413 &ha->async_pd_dma);
4414 if (!ha->async_pd)
4415 goto fail_async_pd;
4416 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4417 "async_pd=%p.\n", ha->async_pd);
4418 }
4419
4420 INIT_LIST_HEAD(&ha->vp_list);
4421
4422 /* Allocate memory for our loop_id bitmap */
4423 ha->loop_id_map = kzalloc_objs(long, BITS_TO_LONGS(LOOPID_MAP_SIZE));
4424 if (!ha->loop_id_map)
4425 goto fail_loop_id_map;
4426 else {
4427 qla2x00_set_reserved_loop_ids(ha);
4428 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4429 "loop_id_map=%p.\n", ha->loop_id_map);
4430 }
4431
4432 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4433 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4434 if (!ha->sfp_data) {
4435 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4436 "Unable to allocate memory for SFP read-data.\n");
4437 goto fail_sfp_data;
4438 }
4439
4440 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4441 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4442 GFP_KERNEL);
4443 if (!ha->flt) {
4444 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4445 "Unable to allocate memory for FLT.\n");
4446 goto fail_flt_buffer;
4447 }
4448
4449 /* allocate the purex dma pool */
4450 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4451 ELS_MAX_PAYLOAD, 8, 0);
4452
4453 if (!ha->purex_dma_pool) {
4454 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4455 "Unable to allocate purex_dma_pool.\n");
4456 goto fail_flt;
4457 }
4458
4459 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
4460 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
4461 ha->elsrej.size,
4462 &ha->elsrej.cdma,
4463 GFP_KERNEL);
4464 if (!ha->elsrej.c) {
4465 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4466 "Alloc failed for els reject cmd.\n");
4467 goto fail_elsrej;
4468 }
4469 ha->elsrej.c->er_cmd = ELS_LS_RJT;
4470 ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
4471 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
4472
4473 ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt);
4474 ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size,
4475 &ha->lsrjt.cdma, GFP_KERNEL);
4476 if (!ha->lsrjt.c) {
4477 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4478 "Alloc failed for nvme fc reject cmd.\n");
4479 goto fail_lsrjt;
4480 }
4481
4482 return 0;
4483
4484 fail_lsrjt:
4485 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
4486 ha->elsrej.c, ha->elsrej.cdma);
4487 fail_elsrej:
4488 dma_pool_destroy(ha->purex_dma_pool);
4489 fail_flt:
4490 dma_free_coherent(&ha->pdev->dev, sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4491 ha->flt, ha->flt_dma);
4492
4493 fail_flt_buffer:
4494 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4495 ha->sfp_data, ha->sfp_data_dma);
4496 fail_sfp_data:
4497 kfree(ha->loop_id_map);
4498 fail_loop_id_map:
4499 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4500 fail_async_pd:
4501 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4502 fail_sf_init_cb:
4503 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4504 fail_ex_init_cb:
4505 kfree(ha->npiv_info);
4506 fail_npiv_info:
4507 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4508 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4509 (*rsp)->ring = NULL;
4510 (*rsp)->dma = 0;
4511 fail_rsp_ring:
4512 kfree(*rsp);
4513 *rsp = NULL;
4514 fail_rsp:
4515 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4516 sizeof(request_t), (*req)->ring, (*req)->dma);
4517 (*req)->ring = NULL;
4518 (*req)->dma = 0;
4519 fail_req_ring:
4520 kfree(*req);
4521 *req = NULL;
4522 fail_req:
4523 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4524 ha->ct_sns, ha->ct_sns_dma);
4525 ha->ct_sns = NULL;
4526 ha->ct_sns_dma = 0;
4527 fail_free_ms_iocb:
4528 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4529 ha->ms_iocb = NULL;
4530 ha->ms_iocb_dma = 0;
4531
4532 if (ha->sns_cmd)
4533 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4534 ha->sns_cmd, ha->sns_cmd_dma);
4535 fail_dma_pool:
4536 if (ql2xenabledif) {
4537 struct dsd_dma *dsd, *nxt;
4538
4539 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4540 list) {
4541 list_del(&dsd->list);
4542 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4543 dsd->dsd_list_dma);
4544 ha->dif_bundle_dma_allocs--;
4545 kfree(dsd);
4546 ha->dif_bundle_kallocs--;
4547 ha->pool.unusable.count--;
4548 }
4549 dma_pool_destroy(ha->dif_bundl_pool);
4550 ha->dif_bundl_pool = NULL;
4551 }
4552
4553 fail_dif_bundl_dma_pool:
4554 if (IS_QLA82XX(ha) || ql2xenabledif) {
4555 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4556 ha->fcp_cmnd_dma_pool = NULL;
4557 }
4558 fail_dl_dma_pool:
4559 if (IS_QLA82XX(ha) || ql2xenabledif) {
4560 dma_pool_destroy(ha->dl_dma_pool);
4561 ha->dl_dma_pool = NULL;
4562 }
4563 fail_s_dma_pool:
4564 dma_pool_destroy(ha->s_dma_pool);
4565 ha->s_dma_pool = NULL;
4566 fail_free_nvram:
4567 kfree(ha->nvram);
4568 ha->nvram = NULL;
4569 fail_free_ctx_mempool:
4570 mempool_destroy(ha->ctx_mempool);
4571 ha->ctx_mempool = NULL;
4572 fail_free_srb_mempool:
4573 mempool_destroy(ha->srb_mempool);
4574 ha->srb_mempool = NULL;
4575 fail_free_gid_list:
4576 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4577 ha->gid_list,
4578 ha->gid_list_dma);
4579 ha->gid_list = NULL;
4580 ha->gid_list_dma = 0;
4581 fail_free_tgt_mem:
4582 qlt_mem_free(ha);
4583 fail_free_btree:
4584 btree_destroy32(&ha->host_map);
4585 fail_free_init_cb:
4586 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4587 ha->init_cb_dma);
4588 ha->init_cb = NULL;
4589 ha->init_cb_dma = 0;
4590 fail_free_vp_map:
4591 kfree(ha->vp_map);
4592 ha->vp_map = NULL;
4593 fail:
4594 ql_log(ql_log_fatal, NULL, 0x0030,
4595 "Memory allocation failure.\n");
4596 return -ENOMEM;
4597 }
4598
4599 int
qla2x00_set_exlogins_buffer(scsi_qla_host_t * vha)4600 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4601 {
4602 int rval;
4603 uint16_t size, max_cnt;
4604 uint32_t temp;
4605 struct qla_hw_data *ha = vha->hw;
4606
4607 /* Return if we don't need to alloacate any extended logins */
4608 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4609 return QLA_SUCCESS;
4610
4611 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4612 return QLA_SUCCESS;
4613
4614 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4615 max_cnt = 0;
4616 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4617 if (rval != QLA_SUCCESS) {
4618 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4619 "Failed to get exlogin status.\n");
4620 return rval;
4621 }
4622
4623 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4624 temp *= size;
4625
4626 if (temp != ha->exlogin_size) {
4627 qla2x00_free_exlogin_buffer(ha);
4628 ha->exlogin_size = temp;
4629
4630 ql_log(ql_log_info, vha, 0xd024,
4631 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4632 max_cnt, size, temp);
4633
4634 ql_log(ql_log_info, vha, 0xd025,
4635 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4636
4637 /* Get consistent memory for extended logins */
4638 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4639 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4640 if (!ha->exlogin_buf) {
4641 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4642 "Failed to allocate memory for exlogin_buf_dma.\n");
4643 return -ENOMEM;
4644 }
4645 }
4646
4647 /* Now configure the dma buffer */
4648 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4649 if (rval) {
4650 ql_log(ql_log_fatal, vha, 0xd033,
4651 "Setup extended login buffer ****FAILED****.\n");
4652 qla2x00_free_exlogin_buffer(ha);
4653 }
4654
4655 return rval;
4656 }
4657
4658 /*
4659 * qla2x00_free_exlogin_buffer
4660 *
4661 * Input:
4662 * ha = adapter block pointer
4663 */
4664 void
qla2x00_free_exlogin_buffer(struct qla_hw_data * ha)4665 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4666 {
4667 if (ha->exlogin_buf) {
4668 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4669 ha->exlogin_buf, ha->exlogin_buf_dma);
4670 ha->exlogin_buf = NULL;
4671 ha->exlogin_size = 0;
4672 }
4673 }
4674
4675 static void
qla2x00_number_of_exch(scsi_qla_host_t * vha,u32 * ret_cnt,u16 max_cnt)4676 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4677 {
4678 u32 temp;
4679 struct init_cb_81xx *icb = (struct init_cb_81xx *)vha->hw->init_cb;
4680 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4681
4682 if (max_cnt > vha->hw->max_exchg)
4683 max_cnt = vha->hw->max_exchg;
4684
4685 if (qla_ini_mode_enabled(vha)) {
4686 if (vha->ql2xiniexchg > max_cnt)
4687 vha->ql2xiniexchg = max_cnt;
4688
4689 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4690 *ret_cnt = vha->ql2xiniexchg;
4691
4692 } else if (qla_tgt_mode_enabled(vha)) {
4693 if (vha->ql2xexchoffld > max_cnt) {
4694 vha->ql2xexchoffld = max_cnt;
4695 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4696 }
4697
4698 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4699 *ret_cnt = vha->ql2xexchoffld;
4700 } else if (qla_dual_mode_enabled(vha)) {
4701 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4702 if (temp > max_cnt) {
4703 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4704 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4705 temp = max_cnt;
4706 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4707 }
4708
4709 if (temp > FW_DEF_EXCHANGES_CNT)
4710 *ret_cnt = temp;
4711 }
4712 }
4713
4714 int
qla2x00_set_exchoffld_buffer(scsi_qla_host_t * vha)4715 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4716 {
4717 int rval;
4718 u16 size, max_cnt;
4719 u32 actual_cnt, totsz;
4720 struct qla_hw_data *ha = vha->hw;
4721
4722 if (!ha->flags.exchoffld_enabled)
4723 return QLA_SUCCESS;
4724
4725 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4726 return QLA_SUCCESS;
4727
4728 max_cnt = 0;
4729 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4730 if (rval != QLA_SUCCESS) {
4731 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4732 "Failed to get exlogin status.\n");
4733 return rval;
4734 }
4735
4736 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4737 ql_log(ql_log_info, vha, 0xd014,
4738 "Actual exchange offload count: %d.\n", actual_cnt);
4739
4740 totsz = actual_cnt * size;
4741
4742 if (totsz != ha->exchoffld_size) {
4743 qla2x00_free_exchoffld_buffer(ha);
4744 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4745 ha->exchoffld_size = 0;
4746 ha->flags.exchoffld_enabled = 0;
4747 return QLA_SUCCESS;
4748 }
4749
4750 ha->exchoffld_size = totsz;
4751
4752 ql_log(ql_log_info, vha, 0xd016,
4753 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4754 max_cnt, actual_cnt, size, totsz);
4755
4756 ql_log(ql_log_info, vha, 0xd017,
4757 "Exchange Buffers requested size = 0x%x\n",
4758 ha->exchoffld_size);
4759
4760 /* Get consistent memory for extended logins */
4761 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4762 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4763 if (!ha->exchoffld_buf) {
4764 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4765 "Failed to allocate memory for Exchange Offload.\n");
4766
4767 if (ha->max_exchg >
4768 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4769 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4770 } else if (ha->max_exchg >
4771 (FW_DEF_EXCHANGES_CNT + 512)) {
4772 ha->max_exchg -= 512;
4773 } else {
4774 ha->flags.exchoffld_enabled = 0;
4775 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4776 "Disabling Exchange offload due to lack of memory\n");
4777 }
4778 ha->exchoffld_size = 0;
4779
4780 return -ENOMEM;
4781 }
4782 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4783 /* pathological case */
4784 qla2x00_free_exchoffld_buffer(ha);
4785 ha->exchoffld_size = 0;
4786 ha->flags.exchoffld_enabled = 0;
4787 ql_log(ql_log_info, vha, 0xd016,
4788 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4789 ha->exchoffld_size, actual_cnt, size, totsz);
4790 return 0;
4791 }
4792
4793 /* Now configure the dma buffer */
4794 rval = qla_set_exchoffld_mem_cfg(vha);
4795 if (rval) {
4796 ql_log(ql_log_fatal, vha, 0xd02e,
4797 "Setup exchange offload buffer ****FAILED****.\n");
4798 qla2x00_free_exchoffld_buffer(ha);
4799 } else {
4800 /* re-adjust number of target exchange */
4801 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4802
4803 if (qla_ini_mode_enabled(vha))
4804 icb->exchange_count = 0;
4805 else
4806 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4807 }
4808
4809 return rval;
4810 }
4811
4812 /*
4813 * qla2x00_free_exchoffld_buffer
4814 *
4815 * Input:
4816 * ha = adapter block pointer
4817 */
4818 void
qla2x00_free_exchoffld_buffer(struct qla_hw_data * ha)4819 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4820 {
4821 if (ha->exchoffld_buf) {
4822 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4823 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4824 ha->exchoffld_buf = NULL;
4825 ha->exchoffld_size = 0;
4826 }
4827 }
4828
4829 /*
4830 * qla2x00_free_fw_dump
4831 * Frees fw dump stuff.
4832 *
4833 * Input:
4834 * ha = adapter block pointer
4835 */
4836 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)4837 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4838 {
4839 struct fwdt *fwdt = ha->fwdt;
4840 uint j;
4841
4842 if (ha->fce)
4843 dma_free_coherent(&ha->pdev->dev,
4844 FCE_SIZE, ha->fce, ha->fce_dma);
4845
4846 if (ha->eft)
4847 dma_free_coherent(&ha->pdev->dev,
4848 EFT_SIZE, ha->eft, ha->eft_dma);
4849
4850 vfree(ha->fw_dump);
4851
4852 ha->fce = NULL;
4853 ha->fce_dma = 0;
4854 ha->flags.fce_enabled = 0;
4855 ha->eft = NULL;
4856 ha->eft_dma = 0;
4857 ha->fw_dumped = false;
4858 ha->fw_dump_cap_flags = 0;
4859 ha->fw_dump_reading = 0;
4860 ha->fw_dump = NULL;
4861 ha->fw_dump_len = 0;
4862
4863 for (j = 0; j < 2; j++, fwdt++) {
4864 vfree(fwdt->template);
4865 fwdt->template = NULL;
4866 fwdt->length = 0;
4867 }
4868 }
4869
4870 /*
4871 * qla2x00_mem_free
4872 * Frees all adapter allocated memory.
4873 *
4874 * Input:
4875 * ha = adapter block pointer.
4876 */
4877 static void
qla2x00_mem_free(struct qla_hw_data * ha)4878 qla2x00_mem_free(struct qla_hw_data *ha)
4879 {
4880 qla2x00_free_fw_dump(ha);
4881
4882 if (ha->mctp_dump)
4883 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4884 ha->mctp_dump_dma);
4885 ha->mctp_dump = NULL;
4886
4887 mempool_destroy(ha->srb_mempool);
4888 ha->srb_mempool = NULL;
4889
4890 if (ha->dcbx_tlv)
4891 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4892 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4893 ha->dcbx_tlv = NULL;
4894
4895 if (ha->xgmac_data)
4896 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4897 ha->xgmac_data, ha->xgmac_data_dma);
4898 ha->xgmac_data = NULL;
4899
4900 if (ha->sns_cmd)
4901 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4902 ha->sns_cmd, ha->sns_cmd_dma);
4903 ha->sns_cmd = NULL;
4904 ha->sns_cmd_dma = 0;
4905
4906 if (ha->ct_sns)
4907 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4908 ha->ct_sns, ha->ct_sns_dma);
4909 ha->ct_sns = NULL;
4910 ha->ct_sns_dma = 0;
4911
4912 if (ha->sfp_data)
4913 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4914 ha->sfp_data_dma);
4915 ha->sfp_data = NULL;
4916
4917 if (ha->flt)
4918 dma_free_coherent(&ha->pdev->dev,
4919 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4920 ha->flt, ha->flt_dma);
4921 ha->flt = NULL;
4922 ha->flt_dma = 0;
4923
4924 if (ha->ms_iocb)
4925 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4926 ha->ms_iocb = NULL;
4927 ha->ms_iocb_dma = 0;
4928
4929 if (ha->sf_init_cb)
4930 dma_pool_free(ha->s_dma_pool,
4931 ha->sf_init_cb, ha->sf_init_cb_dma);
4932
4933 if (ha->ex_init_cb)
4934 dma_pool_free(ha->s_dma_pool,
4935 ha->ex_init_cb, ha->ex_init_cb_dma);
4936 ha->ex_init_cb = NULL;
4937 ha->ex_init_cb_dma = 0;
4938
4939 if (ha->async_pd)
4940 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4941 ha->async_pd = NULL;
4942 ha->async_pd_dma = 0;
4943
4944 dma_pool_destroy(ha->s_dma_pool);
4945 ha->s_dma_pool = NULL;
4946
4947 if (ha->gid_list)
4948 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4949 ha->gid_list, ha->gid_list_dma);
4950 ha->gid_list = NULL;
4951 ha->gid_list_dma = 0;
4952
4953 if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) {
4954 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4955
4956 /* clean up allocated prev pool */
4957 list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
4958 &ha->base_qpair->dsd_list, list) {
4959 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
4960 dsd_ptr->dsd_list_dma);
4961 list_del(&dsd_ptr->list);
4962 kfree(dsd_ptr);
4963 }
4964 }
4965
4966 dma_pool_destroy(ha->dl_dma_pool);
4967 ha->dl_dma_pool = NULL;
4968
4969 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4970 ha->fcp_cmnd_dma_pool = NULL;
4971
4972 mempool_destroy(ha->ctx_mempool);
4973 ha->ctx_mempool = NULL;
4974
4975 if (ql2xenabledif && ha->dif_bundl_pool) {
4976 struct dsd_dma *dsd, *nxt;
4977
4978 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4979 list) {
4980 list_del(&dsd->list);
4981 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4982 dsd->dsd_list_dma);
4983 ha->dif_bundle_dma_allocs--;
4984 kfree(dsd);
4985 ha->dif_bundle_kallocs--;
4986 ha->pool.unusable.count--;
4987 }
4988 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4989 list_del(&dsd->list);
4990 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4991 dsd->dsd_list_dma);
4992 ha->dif_bundle_dma_allocs--;
4993 kfree(dsd);
4994 ha->dif_bundle_kallocs--;
4995 }
4996 }
4997
4998 dma_pool_destroy(ha->dif_bundl_pool);
4999 ha->dif_bundl_pool = NULL;
5000
5001 qlt_mem_free(ha);
5002 qla_remove_hostmap(ha);
5003
5004 if (ha->init_cb)
5005 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
5006 ha->init_cb, ha->init_cb_dma);
5007
5008 dma_pool_destroy(ha->purex_dma_pool);
5009 ha->purex_dma_pool = NULL;
5010
5011 if (ha->elsrej.c) {
5012 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
5013 ha->elsrej.c, ha->elsrej.cdma);
5014 ha->elsrej.c = NULL;
5015 }
5016
5017 if (ha->lsrjt.c) {
5018 dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c,
5019 ha->lsrjt.cdma);
5020 ha->lsrjt.c = NULL;
5021 }
5022
5023 ha->init_cb = NULL;
5024 ha->init_cb_dma = 0;
5025
5026 vfree(ha->optrom_buffer);
5027 ha->optrom_buffer = NULL;
5028 kfree(ha->nvram);
5029 ha->nvram = NULL;
5030 kfree(ha->npiv_info);
5031 ha->npiv_info = NULL;
5032 kfree(ha->swl);
5033 ha->swl = NULL;
5034 kfree(ha->loop_id_map);
5035 ha->sf_init_cb = NULL;
5036 ha->sf_init_cb_dma = 0;
5037 ha->loop_id_map = NULL;
5038
5039 kfree(ha->vp_map);
5040 ha->vp_map = NULL;
5041 }
5042
qla2x00_create_host(const struct scsi_host_template * sht,struct qla_hw_data * ha)5043 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht,
5044 struct qla_hw_data *ha)
5045 {
5046 struct Scsi_Host *host;
5047 struct scsi_qla_host *vha = NULL;
5048
5049 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
5050 if (!host) {
5051 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
5052 "Failed to allocate host from the scsi layer, aborting.\n");
5053 return NULL;
5054 }
5055
5056 /* Clear our data area */
5057 vha = shost_priv(host);
5058 memset(vha, 0, sizeof(scsi_qla_host_t));
5059
5060 vha->host = host;
5061 vha->host_no = host->host_no;
5062 vha->hw = ha;
5063
5064 vha->qlini_mode = ql2x_ini_mode;
5065 vha->ql2xexchoffld = ql2xexchoffld;
5066 vha->ql2xiniexchg = ql2xiniexchg;
5067
5068 INIT_LIST_HEAD(&vha->vp_fcports);
5069 INIT_LIST_HEAD(&vha->work_list);
5070 INIT_LIST_HEAD(&vha->list);
5071 INIT_LIST_HEAD(&vha->qla_cmd_list);
5072 INIT_LIST_HEAD(&vha->logo_list);
5073 INIT_LIST_HEAD(&vha->plogi_ack_list);
5074 INIT_LIST_HEAD(&vha->qp_list);
5075 INIT_LIST_HEAD(&vha->gnl.fcports);
5076 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
5077
5078 INIT_LIST_HEAD(&vha->purex_list.head);
5079 spin_lock_init(&vha->purex_list.lock);
5080
5081 spin_lock_init(&vha->work_lock);
5082 spin_lock_init(&vha->cmd_list_lock);
5083 init_waitqueue_head(&vha->fcport_waitQ);
5084 init_waitqueue_head(&vha->vref_waitq);
5085 qla_enode_init(vha);
5086 qla_edb_init(vha);
5087
5088
5089 vha->gnl.size = sizeof(struct get_name_list_extended) *
5090 (ha->max_loop_id + 1);
5091 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
5092 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
5093 if (!vha->gnl.l) {
5094 ql_log(ql_log_fatal, vha, 0xd04a,
5095 "Alloc failed for name list.\n");
5096 scsi_host_put(vha->host);
5097 return NULL;
5098 }
5099
5100 /* todo: what about ext login? */
5101 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
5102 vha->scan.l = vmalloc(vha->scan.size);
5103 if (!vha->scan.l) {
5104 ql_log(ql_log_fatal, vha, 0xd04a,
5105 "Alloc failed for scan database.\n");
5106 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
5107 vha->gnl.l, vha->gnl.ldma);
5108 vha->gnl.l = NULL;
5109 scsi_host_put(vha->host);
5110 return NULL;
5111 }
5112 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
5113
5114 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu",
5115 QLA2XXX_DRIVER_NAME, vha->host_no);
5116 ql_dbg(ql_dbg_init, vha, 0x0041,
5117 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
5118 vha->host, vha->hw, vha,
5119 dev_name(&(ha->pdev->dev)));
5120
5121 return vha;
5122 }
5123
5124 struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)5125 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
5126 {
5127 struct qla_work_evt *e;
5128
5129 if (test_bit(UNLOADING, &vha->dpc_flags))
5130 return NULL;
5131
5132 if (qla_vha_mark_busy(vha))
5133 return NULL;
5134
5135 e = kzalloc_obj(struct qla_work_evt, GFP_ATOMIC);
5136 if (!e) {
5137 QLA_VHA_MARK_NOT_BUSY(vha);
5138 return NULL;
5139 }
5140
5141 INIT_LIST_HEAD(&e->list);
5142 e->type = type;
5143 e->flags = QLA_EVT_FLAG_FREE;
5144 return e;
5145 }
5146
5147 int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)5148 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
5149 {
5150 unsigned long flags;
5151 bool q = false;
5152
5153 spin_lock_irqsave(&vha->work_lock, flags);
5154 list_add_tail(&e->list, &vha->work_list);
5155
5156 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
5157 q = true;
5158
5159 spin_unlock_irqrestore(&vha->work_lock, flags);
5160
5161 if (q)
5162 queue_work(vha->hw->wq, &vha->iocb_work);
5163
5164 return QLA_SUCCESS;
5165 }
5166
5167 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)5168 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
5169 u32 data)
5170 {
5171 struct qla_work_evt *e;
5172
5173 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
5174 if (!e)
5175 return QLA_FUNCTION_FAILED;
5176
5177 e->u.aen.code = code;
5178 e->u.aen.data = data;
5179 return qla2x00_post_work(vha, e);
5180 }
5181
5182 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)5183 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
5184 {
5185 struct qla_work_evt *e;
5186
5187 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
5188 if (!e)
5189 return QLA_FUNCTION_FAILED;
5190
5191 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
5192 return qla2x00_post_work(vha, e);
5193 }
5194
5195 #define qla2x00_post_async_work(name, type) \
5196 int qla2x00_post_async_##name##_work( \
5197 struct scsi_qla_host *vha, \
5198 fc_port_t *fcport, uint16_t *data) \
5199 { \
5200 struct qla_work_evt *e; \
5201 \
5202 e = qla2x00_alloc_work(vha, type); \
5203 if (!e) \
5204 return QLA_FUNCTION_FAILED; \
5205 \
5206 e->u.logio.fcport = fcport; \
5207 if (data) { \
5208 e->u.logio.data[0] = data[0]; \
5209 e->u.logio.data[1] = data[1]; \
5210 } \
5211 fcport->flags |= FCF_ASYNC_ACTIVE; \
5212 return qla2x00_post_work(vha, e); \
5213 }
5214
5215 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
5216 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5217 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
5218 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
5219 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
5220
5221 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)5222 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
5223 {
5224 struct qla_work_evt *e;
5225
5226 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
5227 if (!e)
5228 return QLA_FUNCTION_FAILED;
5229
5230 e->u.uevent.code = code;
5231 return qla2x00_post_work(vha, e);
5232 }
5233
5234 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)5235 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5236 {
5237 char event_string[40];
5238 char *envp[] = { event_string, NULL };
5239
5240 switch (code) {
5241 case QLA_UEVENT_CODE_FW_DUMP:
5242 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5243 vha->host_no);
5244 break;
5245 default:
5246 /* do nothing */
5247 break;
5248 }
5249 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5250 }
5251
5252 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)5253 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5254 uint32_t *data, int cnt)
5255 {
5256 struct qla_work_evt *e;
5257
5258 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5259 if (!e)
5260 return QLA_FUNCTION_FAILED;
5261
5262 e->u.aenfx.evtcode = evtcode;
5263 e->u.aenfx.count = cnt;
5264 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5265 return qla2x00_post_work(vha, e);
5266 }
5267
qla24xx_sched_upd_fcport(fc_port_t * fcport)5268 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5269 {
5270 unsigned long flags;
5271
5272 if (IS_SW_RESV_ADDR(fcport->d_id))
5273 return;
5274
5275 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5276 if (fcport->disc_state == DSC_UPD_FCPORT) {
5277 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5278 return;
5279 }
5280 fcport->jiffies_at_registration = jiffies;
5281 fcport->sec_since_registration = 0;
5282 fcport->next_disc_state = DSC_DELETED;
5283 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5284 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5285
5286 queue_work(system_dfl_wq, &fcport->reg_work);
5287 }
5288
5289 static
qla24xx_create_new_sess(struct scsi_qla_host * vha,struct qla_work_evt * e)5290 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5291 {
5292 unsigned long flags;
5293 fc_port_t *fcport = NULL, *tfcp;
5294 struct qlt_plogi_ack_t *pla =
5295 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5296 uint8_t free_fcport = 0;
5297
5298 ql_dbg(ql_dbg_disc, vha, 0xffff,
5299 "%s %d %8phC enter\n",
5300 __func__, __LINE__, e->u.new_sess.port_name);
5301
5302 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5303 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5304 if (fcport) {
5305 fcport->d_id = e->u.new_sess.id;
5306 if (pla) {
5307 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5308 memcpy(fcport->node_name,
5309 pla->iocb.u.isp24.u.plogi.node_name,
5310 WWN_SIZE);
5311 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5312 /* we took an extra ref_count to prevent PLOGI ACK when
5313 * fcport/sess has not been created.
5314 */
5315 pla->ref_count--;
5316 }
5317 } else {
5318 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5319 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5320 if (fcport) {
5321 fcport->d_id = e->u.new_sess.id;
5322 fcport->flags |= FCF_FABRIC_DEVICE;
5323 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5324 fcport->tgt_short_link_down_cnt = 0;
5325
5326 memcpy(fcport->port_name, e->u.new_sess.port_name,
5327 WWN_SIZE);
5328
5329 fcport->fc4_type = e->u.new_sess.fc4_type;
5330 if (NVME_PRIORITY(vha->hw, fcport))
5331 fcport->do_prli_nvme = 1;
5332 else
5333 fcport->do_prli_nvme = 0;
5334
5335 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5336 fcport->dm_login_expire = jiffies +
5337 QLA_N2N_WAIT_TIME * HZ;
5338 fcport->fc4_type = FS_FC4TYPE_FCP;
5339 fcport->n2n_flag = 1;
5340 if (vha->flags.nvme_enabled)
5341 fcport->fc4_type |= FS_FC4TYPE_NVME;
5342 }
5343
5344 } else {
5345 ql_dbg(ql_dbg_disc, vha, 0xffff,
5346 "%s %8phC mem alloc fail.\n",
5347 __func__, e->u.new_sess.port_name);
5348
5349 if (pla) {
5350 list_del(&pla->list);
5351 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5352 }
5353 return;
5354 }
5355
5356 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5357 /* search again to make sure no one else got ahead */
5358 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5359 e->u.new_sess.port_name, 1);
5360 if (tfcp) {
5361 /* should rarily happen */
5362 ql_dbg(ql_dbg_disc, vha, 0xffff,
5363 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5364 __func__, tfcp->port_name, tfcp->disc_state,
5365 tfcp->fw_login_state);
5366
5367 free_fcport = 1;
5368 } else {
5369 list_add_tail(&fcport->list, &vha->vp_fcports);
5370
5371 }
5372 if (pla) {
5373 qlt_plogi_ack_link(vha, pla, fcport,
5374 QLT_PLOGI_LINK_SAME_WWN);
5375 pla->ref_count--;
5376 }
5377 }
5378 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5379
5380 if (fcport) {
5381 fcport->id_changed = 1;
5382 fcport->scan_state = QLA_FCPORT_FOUND;
5383 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5384 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5385
5386 if (pla) {
5387 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5388 u16 wd3_lo;
5389
5390 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5391 fcport->local = 0;
5392 fcport->loop_id =
5393 le16_to_cpu(
5394 pla->iocb.u.isp24.nport_handle);
5395 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5396 wd3_lo =
5397 le16_to_cpu(
5398 pla->iocb.u.isp24.u.prli.wd3_lo);
5399
5400 if (wd3_lo & BIT_7)
5401 fcport->conf_compl_supported = 1;
5402
5403 if ((wd3_lo & BIT_4) == 0)
5404 fcport->port_type = FCT_INITIATOR;
5405 else
5406 fcport->port_type = FCT_TARGET;
5407 }
5408 qlt_plogi_ack_unref(vha, pla);
5409 } else {
5410 fc_port_t *dfcp = NULL;
5411
5412 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5413 tfcp = qla2x00_find_fcport_by_nportid(vha,
5414 &e->u.new_sess.id, 1);
5415 if (tfcp && (tfcp != fcport)) {
5416 /*
5417 * We have a conflict fcport with same NportID.
5418 */
5419 ql_dbg(ql_dbg_disc, vha, 0xffff,
5420 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5421 __func__, tfcp->port_name, tfcp->disc_state,
5422 tfcp->fw_login_state);
5423
5424 switch (tfcp->disc_state) {
5425 case DSC_DELETED:
5426 break;
5427 case DSC_DELETE_PEND:
5428 fcport->login_pause = 1;
5429 tfcp->conflict = fcport;
5430 break;
5431 default:
5432 fcport->login_pause = 1;
5433 tfcp->conflict = fcport;
5434 dfcp = tfcp;
5435 break;
5436 }
5437 }
5438 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5439 if (dfcp)
5440 qlt_schedule_sess_for_deletion(tfcp);
5441
5442 if (N2N_TOPO(vha->hw)) {
5443 fcport->flags &= ~FCF_FABRIC_DEVICE;
5444 fcport->keep_nport_handle = 1;
5445 if (vha->flags.nvme_enabled) {
5446 fcport->fc4_type =
5447 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5448 fcport->n2n_flag = 1;
5449 }
5450 fcport->fw_login_state = 0;
5451
5452 schedule_delayed_work(&vha->scan.scan_work, 5);
5453 } else {
5454 qla24xx_fcport_handle_login(vha, fcport);
5455 }
5456 }
5457 }
5458
5459 if (free_fcport) {
5460 qla2x00_free_fcport(fcport);
5461 if (pla) {
5462 list_del(&pla->list);
5463 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5464 }
5465 }
5466 }
5467
qla_sp_retry(struct scsi_qla_host * vha,struct qla_work_evt * e)5468 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5469 {
5470 struct srb *sp = e->u.iosb.sp;
5471 int rval;
5472
5473 rval = qla2x00_start_sp(sp);
5474 if (rval != QLA_SUCCESS) {
5475 ql_dbg(ql_dbg_disc, vha, 0x2043,
5476 "%s: %s: Re-issue IOCB failed (%d).\n",
5477 __func__, sp->name, rval);
5478 qla24xx_sp_unmap(vha, sp);
5479 }
5480 }
5481
5482 void
qla2x00_do_work(struct scsi_qla_host * vha)5483 qla2x00_do_work(struct scsi_qla_host *vha)
5484 {
5485 struct qla_work_evt *e, *tmp;
5486 unsigned long flags;
5487 LIST_HEAD(work);
5488 int rc;
5489
5490 spin_lock_irqsave(&vha->work_lock, flags);
5491 list_splice_init(&vha->work_list, &work);
5492 spin_unlock_irqrestore(&vha->work_lock, flags);
5493
5494 list_for_each_entry_safe(e, tmp, &work, list) {
5495 rc = QLA_SUCCESS;
5496 switch (e->type) {
5497 case QLA_EVT_AEN:
5498 fc_host_post_event(vha->host, fc_get_event_number(),
5499 e->u.aen.code, e->u.aen.data);
5500 break;
5501 case QLA_EVT_IDC_ACK:
5502 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5503 break;
5504 case QLA_EVT_ASYNC_LOGIN:
5505 qla2x00_async_login(vha, e->u.logio.fcport,
5506 e->u.logio.data);
5507 break;
5508 case QLA_EVT_ASYNC_LOGOUT:
5509 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5510 break;
5511 case QLA_EVT_ASYNC_ADISC:
5512 qla2x00_async_adisc(vha, e->u.logio.fcport,
5513 e->u.logio.data);
5514 break;
5515 case QLA_EVT_UEVENT:
5516 qla2x00_uevent_emit(vha, e->u.uevent.code);
5517 break;
5518 case QLA_EVT_AENFX:
5519 qlafx00_process_aen(vha, e);
5520 break;
5521 case QLA_EVT_UNMAP:
5522 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5523 break;
5524 case QLA_EVT_RELOGIN:
5525 qla2x00_relogin(vha);
5526 break;
5527 case QLA_EVT_NEW_SESS:
5528 qla24xx_create_new_sess(vha, e);
5529 break;
5530 case QLA_EVT_GPDB:
5531 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5532 e->u.fcport.opt);
5533 break;
5534 case QLA_EVT_PRLI:
5535 qla24xx_async_prli(vha, e->u.fcport.fcport);
5536 break;
5537 case QLA_EVT_GPSC:
5538 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5539 break;
5540 case QLA_EVT_GNL:
5541 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5542 break;
5543 case QLA_EVT_NACK:
5544 qla24xx_do_nack_work(vha, e);
5545 break;
5546 case QLA_EVT_ASYNC_PRLO:
5547 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5548 break;
5549 case QLA_EVT_ASYNC_PRLO_DONE:
5550 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5551 e->u.logio.data);
5552 break;
5553 case QLA_EVT_SCAN_CMD:
5554 qla_fab_async_scan(vha, e->u.iosb.sp);
5555 break;
5556 case QLA_EVT_SCAN_FINISH:
5557 qla_fab_scan_finish(vha, e->u.iosb.sp);
5558 break;
5559 case QLA_EVT_GFPNID:
5560 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5561 break;
5562 case QLA_EVT_SP_RETRY:
5563 qla_sp_retry(vha, e);
5564 break;
5565 case QLA_EVT_IIDMA:
5566 qla_do_iidma_work(vha, e->u.fcport.fcport);
5567 break;
5568 case QLA_EVT_ELS_PLOGI:
5569 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5570 e->u.fcport.fcport);
5571 break;
5572 case QLA_EVT_SA_REPLACE:
5573 rc = qla24xx_issue_sa_replace_iocb(vha, e);
5574 break;
5575 }
5576
5577 if (rc == EAGAIN) {
5578 /* put 'work' at head of 'vha->work_list' */
5579 spin_lock_irqsave(&vha->work_lock, flags);
5580 list_splice(&work, &vha->work_list);
5581 spin_unlock_irqrestore(&vha->work_lock, flags);
5582 break;
5583 }
5584 list_del_init(&e->list);
5585 if (e->flags & QLA_EVT_FLAG_FREE)
5586 kfree(e);
5587
5588 /* For each work completed decrement vha ref count */
5589 QLA_VHA_MARK_NOT_BUSY(vha);
5590 }
5591 }
5592
qla24xx_post_relogin_work(struct scsi_qla_host * vha)5593 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5594 {
5595 struct qla_work_evt *e;
5596
5597 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5598
5599 if (!e) {
5600 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5601 return QLA_FUNCTION_FAILED;
5602 }
5603
5604 return qla2x00_post_work(vha, e);
5605 }
5606
5607 /* Relogins all the fcports of a vport
5608 * Context: dpc thread
5609 */
qla2x00_relogin(struct scsi_qla_host * vha)5610 void qla2x00_relogin(struct scsi_qla_host *vha)
5611 {
5612 fc_port_t *fcport;
5613 int status, relogin_needed = 0;
5614 struct event_arg ea;
5615
5616 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5617 /*
5618 * If the port is not ONLINE then try to login
5619 * to it if we haven't run out of retries.
5620 */
5621 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5622 fcport->login_retry) {
5623 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5624 fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
5625 fcport->disc_state == DSC_LOGIN_COMPLETE)
5626 continue;
5627
5628 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5629 fcport->disc_state == DSC_DELETE_PEND) {
5630 relogin_needed = 1;
5631 } else {
5632 if (vha->hw->current_topology != ISP_CFG_NL) {
5633 memset(&ea, 0, sizeof(ea));
5634 ea.fcport = fcport;
5635 qla24xx_handle_relogin_event(vha, &ea);
5636 } else if (vha->hw->current_topology ==
5637 ISP_CFG_NL &&
5638 IS_QLA2XXX_MIDTYPE(vha->hw)) {
5639 (void)qla24xx_fcport_handle_login(vha,
5640 fcport);
5641 } else if (vha->hw->current_topology ==
5642 ISP_CFG_NL) {
5643 fcport->login_retry--;
5644 status =
5645 qla2x00_local_device_login(vha,
5646 fcport);
5647 if (status == QLA_SUCCESS) {
5648 fcport->old_loop_id =
5649 fcport->loop_id;
5650 ql_dbg(ql_dbg_disc, vha, 0x2003,
5651 "Port login OK: logged in ID 0x%x.\n",
5652 fcport->loop_id);
5653 qla2x00_update_fcport
5654 (vha, fcport);
5655 } else if (status == 1) {
5656 set_bit(RELOGIN_NEEDED,
5657 &vha->dpc_flags);
5658 /* retry the login again */
5659 ql_dbg(ql_dbg_disc, vha, 0x2007,
5660 "Retrying %d login again loop_id 0x%x.\n",
5661 fcport->login_retry,
5662 fcport->loop_id);
5663 } else {
5664 fcport->login_retry = 0;
5665 }
5666
5667 if (fcport->login_retry == 0 &&
5668 status != QLA_SUCCESS)
5669 qla2x00_clear_loop_id(fcport);
5670 }
5671 }
5672 }
5673 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5674 break;
5675 }
5676
5677 if (relogin_needed)
5678 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5679
5680 ql_dbg(ql_dbg_disc, vha, 0x400e,
5681 "Relogin end.\n");
5682 }
5683
5684 /* Schedule work on any of the dpc-workqueues */
5685 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)5686 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5687 {
5688 struct qla_hw_data *ha = base_vha->hw;
5689
5690 switch (work_code) {
5691 case MBA_IDC_AEN: /* 0x8200 */
5692 if (ha->dpc_lp_wq)
5693 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5694 break;
5695
5696 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5697 if (!ha->flags.nic_core_reset_hdlr_active) {
5698 if (ha->dpc_hp_wq)
5699 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5700 } else
5701 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5702 "NIC Core reset is already active. Skip "
5703 "scheduling it again.\n");
5704 break;
5705 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5706 if (ha->dpc_hp_wq)
5707 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5708 break;
5709 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5710 if (ha->dpc_hp_wq)
5711 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5712 break;
5713 default:
5714 ql_log(ql_log_warn, base_vha, 0xb05f,
5715 "Unknown work-code=0x%x.\n", work_code);
5716 }
5717
5718 return;
5719 }
5720
5721 /* Work: Perform NIC Core Unrecoverable state handling */
5722 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)5723 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5724 {
5725 struct qla_hw_data *ha =
5726 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5727 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5728 uint32_t dev_state = 0;
5729
5730 qla83xx_idc_lock(base_vha, 0);
5731 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5732 qla83xx_reset_ownership(base_vha);
5733 if (ha->flags.nic_core_reset_owner) {
5734 ha->flags.nic_core_reset_owner = 0;
5735 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5736 QLA8XXX_DEV_FAILED);
5737 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5738 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5739 }
5740 qla83xx_idc_unlock(base_vha, 0);
5741 }
5742
5743 /* Work: Execute IDC state handler */
5744 void
qla83xx_idc_state_handler_work(struct work_struct * work)5745 qla83xx_idc_state_handler_work(struct work_struct *work)
5746 {
5747 struct qla_hw_data *ha =
5748 container_of(work, struct qla_hw_data, idc_state_handler);
5749 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5750 uint32_t dev_state = 0;
5751
5752 qla83xx_idc_lock(base_vha, 0);
5753 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5754 if (dev_state == QLA8XXX_DEV_FAILED ||
5755 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5756 qla83xx_idc_state_handler(base_vha);
5757 qla83xx_idc_unlock(base_vha, 0);
5758 }
5759
5760 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)5761 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5762 {
5763 int rval = QLA_SUCCESS;
5764 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5765 uint32_t heart_beat_counter1, heart_beat_counter2;
5766
5767 do {
5768 if (time_after(jiffies, heart_beat_wait)) {
5769 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5770 "Nic Core f/w is not alive.\n");
5771 rval = QLA_FUNCTION_FAILED;
5772 break;
5773 }
5774
5775 qla83xx_idc_lock(base_vha, 0);
5776 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5777 &heart_beat_counter1);
5778 qla83xx_idc_unlock(base_vha, 0);
5779 msleep(100);
5780 qla83xx_idc_lock(base_vha, 0);
5781 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5782 &heart_beat_counter2);
5783 qla83xx_idc_unlock(base_vha, 0);
5784 } while (heart_beat_counter1 == heart_beat_counter2);
5785
5786 return rval;
5787 }
5788
5789 /* Work: Perform NIC Core Reset handling */
5790 void
qla83xx_nic_core_reset_work(struct work_struct * work)5791 qla83xx_nic_core_reset_work(struct work_struct *work)
5792 {
5793 struct qla_hw_data *ha =
5794 container_of(work, struct qla_hw_data, nic_core_reset);
5795 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5796 uint32_t dev_state = 0;
5797
5798 if (IS_QLA2031(ha)) {
5799 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5800 ql_log(ql_log_warn, base_vha, 0xb081,
5801 "Failed to dump mctp\n");
5802 return;
5803 }
5804
5805 if (!ha->flags.nic_core_reset_hdlr_active) {
5806 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5807 qla83xx_idc_lock(base_vha, 0);
5808 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5809 &dev_state);
5810 qla83xx_idc_unlock(base_vha, 0);
5811 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5812 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5813 "Nic Core f/w is alive.\n");
5814 return;
5815 }
5816 }
5817
5818 ha->flags.nic_core_reset_hdlr_active = 1;
5819 if (qla83xx_nic_core_reset(base_vha)) {
5820 /* NIC Core reset failed. */
5821 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5822 "NIC Core reset failed.\n");
5823 }
5824 ha->flags.nic_core_reset_hdlr_active = 0;
5825 }
5826 }
5827
5828 /* Work: Handle 8200 IDC aens */
5829 void
qla83xx_service_idc_aen(struct work_struct * work)5830 qla83xx_service_idc_aen(struct work_struct *work)
5831 {
5832 struct qla_hw_data *ha =
5833 container_of(work, struct qla_hw_data, idc_aen);
5834 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5835 uint32_t dev_state, idc_control;
5836
5837 qla83xx_idc_lock(base_vha, 0);
5838 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5839 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5840 qla83xx_idc_unlock(base_vha, 0);
5841 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5842 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5843 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5844 "Application requested NIC Core Reset.\n");
5845 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5846 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5847 QLA_SUCCESS) {
5848 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5849 "Other protocol driver requested NIC Core Reset.\n");
5850 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5851 }
5852 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5853 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5854 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5855 }
5856 }
5857
5858 /*
5859 * Control the frequency of IDC lock retries
5860 */
5861 #define QLA83XX_WAIT_LOGIC_MS 100
5862
5863 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)5864 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5865 {
5866 int rval;
5867 uint32_t data;
5868 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5869 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5870 struct qla_hw_data *ha = base_vha->hw;
5871
5872 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5873 "Trying force recovery of the IDC lock.\n");
5874
5875 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5876 if (rval)
5877 return rval;
5878
5879 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5880 return QLA_SUCCESS;
5881 } else {
5882 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5883 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5884 data);
5885 if (rval)
5886 return rval;
5887
5888 msleep(200);
5889
5890 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5891 &data);
5892 if (rval)
5893 return rval;
5894
5895 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5896 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5897 ~(idc_lck_rcvry_stage_mask));
5898 rval = qla83xx_wr_reg(base_vha,
5899 QLA83XX_IDC_LOCK_RECOVERY, data);
5900 if (rval)
5901 return rval;
5902
5903 /* Forcefully perform IDC UnLock */
5904 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5905 &data);
5906 if (rval)
5907 return rval;
5908 /* Clear lock-id by setting 0xff */
5909 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5910 0xff);
5911 if (rval)
5912 return rval;
5913 /* Clear lock-recovery by setting 0x0 */
5914 rval = qla83xx_wr_reg(base_vha,
5915 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5916 if (rval)
5917 return rval;
5918 } else
5919 return QLA_SUCCESS;
5920 }
5921
5922 return rval;
5923 }
5924
5925 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)5926 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5927 {
5928 int rval = QLA_SUCCESS;
5929 uint32_t o_drv_lockid, n_drv_lockid;
5930 unsigned long lock_recovery_timeout;
5931
5932 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5933 retry_lockid:
5934 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5935 if (rval)
5936 goto exit;
5937
5938 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5939 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5940 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5941 return QLA_SUCCESS;
5942 else
5943 return QLA_FUNCTION_FAILED;
5944 }
5945
5946 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5947 if (rval)
5948 goto exit;
5949
5950 if (o_drv_lockid == n_drv_lockid) {
5951 msleep(QLA83XX_WAIT_LOGIC_MS);
5952 goto retry_lockid;
5953 } else
5954 return QLA_SUCCESS;
5955
5956 exit:
5957 return rval;
5958 }
5959
5960 /*
5961 * Context: task, can sleep
5962 */
5963 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)5964 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5965 {
5966 uint32_t data;
5967 uint32_t lock_owner;
5968 struct qla_hw_data *ha = base_vha->hw;
5969
5970 might_sleep();
5971
5972 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5973 retry_lock:
5974 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5975 == QLA_SUCCESS) {
5976 if (data) {
5977 /* Setting lock-id to our function-number */
5978 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5979 ha->portnum);
5980 } else {
5981 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5982 &lock_owner);
5983 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5984 "Failed to acquire IDC lock, acquired by %d, "
5985 "retrying...\n", lock_owner);
5986
5987 /* Retry/Perform IDC-Lock recovery */
5988 if (qla83xx_idc_lock_recovery(base_vha)
5989 == QLA_SUCCESS) {
5990 msleep(QLA83XX_WAIT_LOGIC_MS);
5991 goto retry_lock;
5992 } else
5993 ql_log(ql_log_warn, base_vha, 0xb075,
5994 "IDC Lock recovery FAILED.\n");
5995 }
5996
5997 }
5998
5999 return;
6000 }
6001
6002 static bool
qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host * vha,struct purex_entry_24xx * purex)6003 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
6004 struct purex_entry_24xx *purex)
6005 {
6006 char fwstr[16];
6007 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
6008 struct port_database_24xx *pdb;
6009
6010 /* Domain Controller is always logged-out. */
6011 /* if RDP request is not from Domain Controller: */
6012 if (sid != 0xfffc01)
6013 return false;
6014
6015 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
6016
6017 pdb = kzalloc_obj(*pdb);
6018 if (!pdb) {
6019 ql_dbg(ql_dbg_init, vha, 0x0181,
6020 "%s: Failed allocate pdb\n", __func__);
6021 } else if (qla24xx_get_port_database(vha,
6022 le16_to_cpu(purex->nport_handle), pdb)) {
6023 ql_dbg(ql_dbg_init, vha, 0x0181,
6024 "%s: Failed get pdb sid=%x\n", __func__, sid);
6025 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
6026 pdb->current_login_state != PDS_PRLI_COMPLETE) {
6027 ql_dbg(ql_dbg_init, vha, 0x0181,
6028 "%s: Port not logged in sid=%#x\n", __func__, sid);
6029 } else {
6030 /* RDP request is from logged in port */
6031 kfree(pdb);
6032 return false;
6033 }
6034 kfree(pdb);
6035
6036 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
6037 fwstr[strcspn(fwstr, " ")] = 0;
6038 /* if FW version allows RDP response length upto 2048 bytes: */
6039 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
6040 return false;
6041
6042 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
6043
6044 /* RDP response length is to be reduced to maximum 256 bytes */
6045 return true;
6046 }
6047
6048 /*
6049 * Function Name: qla24xx_process_purex_iocb
6050 *
6051 * Description:
6052 * Prepare a RDP response and send to Fabric switch
6053 *
6054 * PARAMETERS:
6055 * vha: SCSI qla host
6056 * purex: RDP request received by HBA
6057 */
qla24xx_process_purex_rdp(struct scsi_qla_host * vha,struct purex_item * item)6058 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
6059 struct purex_item *item)
6060 {
6061 struct qla_hw_data *ha = vha->hw;
6062 struct purex_entry_24xx *purex =
6063 (struct purex_entry_24xx *)&item->iocb;
6064 dma_addr_t rsp_els_dma;
6065 dma_addr_t rsp_payload_dma;
6066 dma_addr_t stat_dma;
6067 dma_addr_t sfp_dma;
6068 struct els_entry_24xx *rsp_els = NULL;
6069 struct rdp_rsp_payload *rsp_payload = NULL;
6070 struct link_statistics *stat = NULL;
6071 uint8_t *sfp = NULL;
6072 uint16_t sfp_flags = 0;
6073 uint rsp_payload_length = sizeof(*rsp_payload);
6074 int rval;
6075
6076 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
6077 "%s: Enter\n", __func__);
6078
6079 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
6080 "-------- ELS REQ -------\n");
6081 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
6082 purex, sizeof(*purex));
6083
6084 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
6085 rsp_payload_length =
6086 offsetof(typeof(*rsp_payload), optical_elmt_desc);
6087 ql_dbg(ql_dbg_init, vha, 0x0181,
6088 "Reducing RSP payload length to %u bytes...\n",
6089 rsp_payload_length);
6090 }
6091
6092 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6093 &rsp_els_dma, GFP_KERNEL);
6094 if (!rsp_els) {
6095 ql_log(ql_log_warn, vha, 0x0183,
6096 "Failed allocate dma buffer ELS RSP.\n");
6097 goto dealloc;
6098 }
6099
6100 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6101 &rsp_payload_dma, GFP_KERNEL);
6102 if (!rsp_payload) {
6103 ql_log(ql_log_warn, vha, 0x0184,
6104 "Failed allocate dma buffer ELS RSP payload.\n");
6105 goto dealloc;
6106 }
6107
6108 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6109 &sfp_dma, GFP_KERNEL);
6110
6111 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
6112 &stat_dma, GFP_KERNEL);
6113
6114 /* Prepare Response IOCB */
6115 rsp_els->entry_type = ELS_IOCB_TYPE;
6116 rsp_els->entry_count = 1;
6117 rsp_els->sys_define = 0;
6118 rsp_els->entry_status = 0;
6119 rsp_els->handle = 0;
6120 rsp_els->nport_handle = purex->nport_handle;
6121 rsp_els->tx_dsd_count = cpu_to_le16(1);
6122 rsp_els->vp_index = purex->vp_idx;
6123 rsp_els->sof_type = EST_SOFI3;
6124 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
6125 rsp_els->rx_dsd_count = 0;
6126 rsp_els->opcode = purex->els_frame_payload[0];
6127
6128 rsp_els->d_id[0] = purex->s_id[0];
6129 rsp_els->d_id[1] = purex->s_id[1];
6130 rsp_els->d_id[2] = purex->s_id[2];
6131
6132 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
6133 rsp_els->rx_byte_count = 0;
6134 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
6135
6136 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
6137 rsp_els->tx_len = rsp_els->tx_byte_count;
6138
6139 rsp_els->rx_address = 0;
6140 rsp_els->rx_len = 0;
6141
6142 /* Prepare Response Payload */
6143 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
6144 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6145 sizeof(rsp_payload->hdr));
6146
6147 /* Link service Request Info Descriptor */
6148 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6149 rsp_payload->ls_req_info_desc.desc_len =
6150 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6151 rsp_payload->ls_req_info_desc.req_payload_word_0 =
6152 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6153
6154 /* Link service Request Info Descriptor 2 */
6155 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6156 rsp_payload->ls_req_info_desc2.desc_len =
6157 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6158 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6159 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6160
6161
6162 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6163 rsp_payload->sfp_diag_desc.desc_len =
6164 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6165
6166 if (sfp) {
6167 /* SFP Flags */
6168 memset(sfp, 0, SFP_RTDI_LEN);
6169 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
6170 if (!rval) {
6171 /* SFP Flags bits 3-0: Port Tx Laser Type */
6172 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
6173 sfp_flags |= BIT_0; /* short wave */
6174 else if (sfp[0] & BIT_1)
6175 sfp_flags |= BIT_1; /* long wave 1310nm */
6176 else if (sfp[1] & BIT_4)
6177 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
6178 }
6179
6180 /* SFP Type */
6181 memset(sfp, 0, SFP_RTDI_LEN);
6182 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
6183 if (!rval) {
6184 sfp_flags |= BIT_4; /* optical */
6185 if (sfp[0] == 0x3)
6186 sfp_flags |= BIT_6; /* sfp+ */
6187 }
6188
6189 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6190
6191 /* SFP Diagnostics */
6192 memset(sfp, 0, SFP_RTDI_LEN);
6193 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
6194 if (!rval) {
6195 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6196 rsp_payload->sfp_diag_desc.temperature = trx[0];
6197 rsp_payload->sfp_diag_desc.vcc = trx[1];
6198 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6199 rsp_payload->sfp_diag_desc.tx_power = trx[3];
6200 rsp_payload->sfp_diag_desc.rx_power = trx[4];
6201 }
6202 }
6203
6204 /* Port Speed Descriptor */
6205 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6206 rsp_payload->port_speed_desc.desc_len =
6207 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6208 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6209 qla25xx_fdmi_port_speed_capability(ha));
6210 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6211 qla25xx_fdmi_port_speed_currently(ha));
6212
6213 /* Link Error Status Descriptor */
6214 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6215 rsp_payload->ls_err_desc.desc_len =
6216 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6217
6218 if (stat) {
6219 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
6220 if (!rval) {
6221 rsp_payload->ls_err_desc.link_fail_cnt =
6222 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
6223 rsp_payload->ls_err_desc.loss_sync_cnt =
6224 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
6225 rsp_payload->ls_err_desc.loss_sig_cnt =
6226 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6227 rsp_payload->ls_err_desc.prim_seq_err_cnt =
6228 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6229 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6230 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6231 rsp_payload->ls_err_desc.inval_crc_cnt =
6232 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6233 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6234 }
6235 }
6236
6237 /* Portname Descriptor */
6238 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6239 rsp_payload->port_name_diag_desc.desc_len =
6240 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6241 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6242 vha->node_name,
6243 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6244 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6245 vha->port_name,
6246 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6247
6248 /* F-Port Portname Descriptor */
6249 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6250 rsp_payload->port_name_direct_desc.desc_len =
6251 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6252 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6253 vha->fabric_node_name,
6254 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6255 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6256 vha->fabric_port_name,
6257 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6258
6259 /* Bufer Credit Descriptor */
6260 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6261 rsp_payload->buffer_credit_desc.desc_len =
6262 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6263 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6264 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6265 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6266
6267 if (ha->flags.plogi_template_valid) {
6268 uint32_t tmp =
6269 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6270 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6271 }
6272
6273 if (rsp_payload_length < sizeof(*rsp_payload))
6274 goto send;
6275
6276 /* Optical Element Descriptor, Temperature */
6277 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6278 rsp_payload->optical_elmt_desc[0].desc_len =
6279 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6280 /* Optical Element Descriptor, Voltage */
6281 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6282 rsp_payload->optical_elmt_desc[1].desc_len =
6283 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6284 /* Optical Element Descriptor, Tx Bias Current */
6285 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6286 rsp_payload->optical_elmt_desc[2].desc_len =
6287 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6288 /* Optical Element Descriptor, Tx Power */
6289 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6290 rsp_payload->optical_elmt_desc[3].desc_len =
6291 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6292 /* Optical Element Descriptor, Rx Power */
6293 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6294 rsp_payload->optical_elmt_desc[4].desc_len =
6295 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6296
6297 if (sfp) {
6298 memset(sfp, 0, SFP_RTDI_LEN);
6299 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6300 if (!rval) {
6301 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6302
6303 /* Optical Element Descriptor, Temperature */
6304 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6305 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6306 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6307 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6308 rsp_payload->optical_elmt_desc[0].element_flags =
6309 cpu_to_be32(1 << 28);
6310
6311 /* Optical Element Descriptor, Voltage */
6312 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6313 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6314 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6315 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6316 rsp_payload->optical_elmt_desc[1].element_flags =
6317 cpu_to_be32(2 << 28);
6318
6319 /* Optical Element Descriptor, Tx Bias Current */
6320 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6321 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6322 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6323 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6324 rsp_payload->optical_elmt_desc[2].element_flags =
6325 cpu_to_be32(3 << 28);
6326
6327 /* Optical Element Descriptor, Tx Power */
6328 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6329 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6330 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6331 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6332 rsp_payload->optical_elmt_desc[3].element_flags =
6333 cpu_to_be32(4 << 28);
6334
6335 /* Optical Element Descriptor, Rx Power */
6336 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6337 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6338 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6339 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6340 rsp_payload->optical_elmt_desc[4].element_flags =
6341 cpu_to_be32(5 << 28);
6342 }
6343
6344 memset(sfp, 0, SFP_RTDI_LEN);
6345 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6346 if (!rval) {
6347 /* Temperature high/low alarm/warning */
6348 rsp_payload->optical_elmt_desc[0].element_flags |=
6349 cpu_to_be32(
6350 (sfp[0] >> 7 & 1) << 3 |
6351 (sfp[0] >> 6 & 1) << 2 |
6352 (sfp[4] >> 7 & 1) << 1 |
6353 (sfp[4] >> 6 & 1) << 0);
6354
6355 /* Voltage high/low alarm/warning */
6356 rsp_payload->optical_elmt_desc[1].element_flags |=
6357 cpu_to_be32(
6358 (sfp[0] >> 5 & 1) << 3 |
6359 (sfp[0] >> 4 & 1) << 2 |
6360 (sfp[4] >> 5 & 1) << 1 |
6361 (sfp[4] >> 4 & 1) << 0);
6362
6363 /* Tx Bias Current high/low alarm/warning */
6364 rsp_payload->optical_elmt_desc[2].element_flags |=
6365 cpu_to_be32(
6366 (sfp[0] >> 3 & 1) << 3 |
6367 (sfp[0] >> 2 & 1) << 2 |
6368 (sfp[4] >> 3 & 1) << 1 |
6369 (sfp[4] >> 2 & 1) << 0);
6370
6371 /* Tx Power high/low alarm/warning */
6372 rsp_payload->optical_elmt_desc[3].element_flags |=
6373 cpu_to_be32(
6374 (sfp[0] >> 1 & 1) << 3 |
6375 (sfp[0] >> 0 & 1) << 2 |
6376 (sfp[4] >> 1 & 1) << 1 |
6377 (sfp[4] >> 0 & 1) << 0);
6378
6379 /* Rx Power high/low alarm/warning */
6380 rsp_payload->optical_elmt_desc[4].element_flags |=
6381 cpu_to_be32(
6382 (sfp[1] >> 7 & 1) << 3 |
6383 (sfp[1] >> 6 & 1) << 2 |
6384 (sfp[5] >> 7 & 1) << 1 |
6385 (sfp[5] >> 6 & 1) << 0);
6386 }
6387 }
6388
6389 /* Optical Product Data Descriptor */
6390 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6391 rsp_payload->optical_prod_desc.desc_len =
6392 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6393
6394 if (sfp) {
6395 memset(sfp, 0, SFP_RTDI_LEN);
6396 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6397 if (!rval) {
6398 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6399 sfp + 0,
6400 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6401 memcpy(rsp_payload->optical_prod_desc.part_number,
6402 sfp + 20,
6403 sizeof(rsp_payload->optical_prod_desc.part_number));
6404 memcpy(rsp_payload->optical_prod_desc.revision,
6405 sfp + 36,
6406 sizeof(rsp_payload->optical_prod_desc.revision));
6407 memcpy(rsp_payload->optical_prod_desc.serial_number,
6408 sfp + 48,
6409 sizeof(rsp_payload->optical_prod_desc.serial_number));
6410 }
6411
6412 memset(sfp, 0, SFP_RTDI_LEN);
6413 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6414 if (!rval) {
6415 memcpy(rsp_payload->optical_prod_desc.date,
6416 sfp + 0,
6417 sizeof(rsp_payload->optical_prod_desc.date));
6418 }
6419 }
6420
6421 send:
6422 ql_dbg(ql_dbg_init, vha, 0x0183,
6423 "Sending ELS Response to RDP Request...\n");
6424 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6425 "-------- ELS RSP -------\n");
6426 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6427 rsp_els, sizeof(*rsp_els));
6428 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6429 "-------- ELS RSP PAYLOAD -------\n");
6430 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6431 rsp_payload, rsp_payload_length);
6432
6433 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6434
6435 if (rval) {
6436 ql_log(ql_log_warn, vha, 0x0188,
6437 "%s: iocb failed to execute -> %x\n", __func__, rval);
6438 } else if (rsp_els->comp_status) {
6439 ql_log(ql_log_warn, vha, 0x0189,
6440 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6441 __func__, rsp_els->comp_status,
6442 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6443 } else {
6444 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6445 }
6446
6447 dealloc:
6448 if (stat)
6449 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6450 stat, stat_dma);
6451 if (sfp)
6452 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6453 sfp, sfp_dma);
6454 if (rsp_payload)
6455 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6456 rsp_payload, rsp_payload_dma);
6457 if (rsp_els)
6458 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6459 rsp_els, rsp_els_dma);
6460 }
6461
6462 void
qla24xx_free_purex_item(struct purex_item * item)6463 qla24xx_free_purex_item(struct purex_item *item)
6464 {
6465 if (item == &item->vha->default_item)
6466 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6467 else
6468 kfree(item);
6469 }
6470
qla24xx_process_purex_list(struct purex_list * list)6471 void qla24xx_process_purex_list(struct purex_list *list)
6472 {
6473 struct list_head head = LIST_HEAD_INIT(head);
6474 struct purex_item *item, *next;
6475 ulong flags;
6476
6477 spin_lock_irqsave(&list->lock, flags);
6478 list_splice_init(&list->head, &head);
6479 spin_unlock_irqrestore(&list->lock, flags);
6480
6481 list_for_each_entry_safe(item, next, &head, list) {
6482 list_del(&item->list);
6483 item->process_item(item->vha, item);
6484 qla24xx_free_purex_item(item);
6485 }
6486 }
6487
6488 /*
6489 * Context: task, can sleep
6490 */
6491 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)6492 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6493 {
6494 #if 0
6495 uint16_t options = (requester_id << 15) | BIT_7;
6496 #endif
6497 uint16_t retry;
6498 uint32_t data;
6499 struct qla_hw_data *ha = base_vha->hw;
6500
6501 might_sleep();
6502
6503 /* IDC-unlock implementation using driver-unlock/lock-id
6504 * remote registers
6505 */
6506 retry = 0;
6507 retry_unlock:
6508 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6509 == QLA_SUCCESS) {
6510 if (data == ha->portnum) {
6511 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6512 /* Clearing lock-id by setting 0xff */
6513 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6514 } else if (retry < 10) {
6515 /* SV: XXX: IDC unlock retrying needed here? */
6516
6517 /* Retry for IDC-unlock */
6518 msleep(QLA83XX_WAIT_LOGIC_MS);
6519 retry++;
6520 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6521 "Failed to release IDC lock, retrying=%d\n", retry);
6522 goto retry_unlock;
6523 }
6524 } else if (retry < 10) {
6525 /* Retry for IDC-unlock */
6526 msleep(QLA83XX_WAIT_LOGIC_MS);
6527 retry++;
6528 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6529 "Failed to read drv-lockid, retrying=%d\n", retry);
6530 goto retry_unlock;
6531 }
6532
6533 return;
6534
6535 #if 0
6536 /* XXX: IDC-unlock implementation using access-control mbx */
6537 retry = 0;
6538 retry_unlock2:
6539 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6540 if (retry < 10) {
6541 /* Retry for IDC-unlock */
6542 msleep(QLA83XX_WAIT_LOGIC_MS);
6543 retry++;
6544 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6545 "Failed to release IDC lock, retrying=%d\n", retry);
6546 goto retry_unlock2;
6547 }
6548 }
6549
6550 return;
6551 #endif
6552 }
6553
6554 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)6555 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6556 {
6557 int rval = QLA_SUCCESS;
6558 struct qla_hw_data *ha = vha->hw;
6559 uint32_t drv_presence;
6560
6561 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6562 if (rval == QLA_SUCCESS) {
6563 drv_presence |= (1 << ha->portnum);
6564 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6565 drv_presence);
6566 }
6567
6568 return rval;
6569 }
6570
6571 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)6572 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6573 {
6574 int rval = QLA_SUCCESS;
6575
6576 qla83xx_idc_lock(vha, 0);
6577 rval = __qla83xx_set_drv_presence(vha);
6578 qla83xx_idc_unlock(vha, 0);
6579
6580 return rval;
6581 }
6582
6583 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6584 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6585 {
6586 int rval = QLA_SUCCESS;
6587 struct qla_hw_data *ha = vha->hw;
6588 uint32_t drv_presence;
6589
6590 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6591 if (rval == QLA_SUCCESS) {
6592 drv_presence &= ~(1 << ha->portnum);
6593 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6594 drv_presence);
6595 }
6596
6597 return rval;
6598 }
6599
6600 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6601 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6602 {
6603 int rval = QLA_SUCCESS;
6604
6605 qla83xx_idc_lock(vha, 0);
6606 rval = __qla83xx_clear_drv_presence(vha);
6607 qla83xx_idc_unlock(vha, 0);
6608
6609 return rval;
6610 }
6611
6612 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)6613 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6614 {
6615 struct qla_hw_data *ha = vha->hw;
6616 uint32_t drv_ack, drv_presence;
6617 unsigned long ack_timeout;
6618
6619 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6620 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6621 while (1) {
6622 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6623 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6624 if ((drv_ack & drv_presence) == drv_presence)
6625 break;
6626
6627 if (time_after_eq(jiffies, ack_timeout)) {
6628 ql_log(ql_log_warn, vha, 0xb067,
6629 "RESET ACK TIMEOUT! drv_presence=0x%x "
6630 "drv_ack=0x%x\n", drv_presence, drv_ack);
6631 /*
6632 * The function(s) which did not ack in time are forced
6633 * to withdraw any further participation in the IDC
6634 * reset.
6635 */
6636 if (drv_ack != drv_presence)
6637 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6638 drv_ack);
6639 break;
6640 }
6641
6642 qla83xx_idc_unlock(vha, 0);
6643 msleep(1000);
6644 qla83xx_idc_lock(vha, 0);
6645 }
6646
6647 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6648 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6649 }
6650
6651 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)6652 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6653 {
6654 int rval = QLA_SUCCESS;
6655 uint32_t idc_control;
6656
6657 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6658 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6659
6660 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6661 __qla83xx_get_idc_control(vha, &idc_control);
6662 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6663 __qla83xx_set_idc_control(vha, 0);
6664
6665 qla83xx_idc_unlock(vha, 0);
6666 rval = qla83xx_restart_nic_firmware(vha);
6667 qla83xx_idc_lock(vha, 0);
6668
6669 if (rval != QLA_SUCCESS) {
6670 ql_log(ql_log_fatal, vha, 0xb06a,
6671 "Failed to restart NIC f/w.\n");
6672 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6673 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6674 } else {
6675 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6676 "Success in restarting nic f/w.\n");
6677 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6678 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6679 }
6680
6681 return rval;
6682 }
6683
6684 /* Assumes idc_lock always held on entry */
6685 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)6686 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6687 {
6688 struct qla_hw_data *ha = base_vha->hw;
6689 int rval = QLA_SUCCESS;
6690 unsigned long dev_init_timeout;
6691 uint32_t dev_state;
6692
6693 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6694 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6695
6696 while (1) {
6697
6698 if (time_after_eq(jiffies, dev_init_timeout)) {
6699 ql_log(ql_log_warn, base_vha, 0xb06e,
6700 "Initialization TIMEOUT!\n");
6701 /* Init timeout. Disable further NIC Core
6702 * communication.
6703 */
6704 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6705 QLA8XXX_DEV_FAILED);
6706 ql_log(ql_log_info, base_vha, 0xb06f,
6707 "HW State: FAILED.\n");
6708 }
6709
6710 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6711 switch (dev_state) {
6712 case QLA8XXX_DEV_READY:
6713 if (ha->flags.nic_core_reset_owner)
6714 qla83xx_idc_audit(base_vha,
6715 IDC_AUDIT_COMPLETION);
6716 ha->flags.nic_core_reset_owner = 0;
6717 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6718 "Reset_owner reset by 0x%x.\n",
6719 ha->portnum);
6720 goto exit;
6721 case QLA8XXX_DEV_COLD:
6722 if (ha->flags.nic_core_reset_owner)
6723 rval = qla83xx_device_bootstrap(base_vha);
6724 else {
6725 /* Wait for AEN to change device-state */
6726 qla83xx_idc_unlock(base_vha, 0);
6727 msleep(1000);
6728 qla83xx_idc_lock(base_vha, 0);
6729 }
6730 break;
6731 case QLA8XXX_DEV_INITIALIZING:
6732 /* Wait for AEN to change device-state */
6733 qla83xx_idc_unlock(base_vha, 0);
6734 msleep(1000);
6735 qla83xx_idc_lock(base_vha, 0);
6736 break;
6737 case QLA8XXX_DEV_NEED_RESET:
6738 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6739 qla83xx_need_reset_handler(base_vha);
6740 else {
6741 /* Wait for AEN to change device-state */
6742 qla83xx_idc_unlock(base_vha, 0);
6743 msleep(1000);
6744 qla83xx_idc_lock(base_vha, 0);
6745 }
6746 /* reset timeout value after need reset handler */
6747 dev_init_timeout = jiffies +
6748 (ha->fcoe_dev_init_timeout * HZ);
6749 break;
6750 case QLA8XXX_DEV_NEED_QUIESCENT:
6751 /* XXX: DEBUG for now */
6752 qla83xx_idc_unlock(base_vha, 0);
6753 msleep(1000);
6754 qla83xx_idc_lock(base_vha, 0);
6755 break;
6756 case QLA8XXX_DEV_QUIESCENT:
6757 /* XXX: DEBUG for now */
6758 if (ha->flags.quiesce_owner)
6759 goto exit;
6760
6761 qla83xx_idc_unlock(base_vha, 0);
6762 msleep(1000);
6763 qla83xx_idc_lock(base_vha, 0);
6764 dev_init_timeout = jiffies +
6765 (ha->fcoe_dev_init_timeout * HZ);
6766 break;
6767 case QLA8XXX_DEV_FAILED:
6768 if (ha->flags.nic_core_reset_owner)
6769 qla83xx_idc_audit(base_vha,
6770 IDC_AUDIT_COMPLETION);
6771 ha->flags.nic_core_reset_owner = 0;
6772 __qla83xx_clear_drv_presence(base_vha);
6773 qla83xx_idc_unlock(base_vha, 0);
6774 qla8xxx_dev_failed_handler(base_vha);
6775 rval = QLA_FUNCTION_FAILED;
6776 qla83xx_idc_lock(base_vha, 0);
6777 goto exit;
6778 case QLA8XXX_BAD_VALUE:
6779 qla83xx_idc_unlock(base_vha, 0);
6780 msleep(1000);
6781 qla83xx_idc_lock(base_vha, 0);
6782 break;
6783 default:
6784 ql_log(ql_log_warn, base_vha, 0xb071,
6785 "Unknown Device State: %x.\n", dev_state);
6786 qla83xx_idc_unlock(base_vha, 0);
6787 qla8xxx_dev_failed_handler(base_vha);
6788 rval = QLA_FUNCTION_FAILED;
6789 qla83xx_idc_lock(base_vha, 0);
6790 goto exit;
6791 }
6792 }
6793
6794 exit:
6795 return rval;
6796 }
6797
6798 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)6799 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6800 {
6801 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6802 board_disable);
6803 struct pci_dev *pdev = ha->pdev;
6804 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6805
6806 ql_log(ql_log_warn, base_vha, 0x015b,
6807 "Disabling adapter.\n");
6808
6809 if (!atomic_read(&pdev->enable_cnt)) {
6810 ql_log(ql_log_info, base_vha, 0xfffc,
6811 "PCI device disabled, no action req for PCI error=%lx\n",
6812 base_vha->pci_flags);
6813 return;
6814 }
6815
6816 /*
6817 * if UNLOADING flag is already set, then continue unload,
6818 * where it was set first.
6819 */
6820 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6821 return;
6822
6823 qla2x00_wait_for_sess_deletion(base_vha);
6824
6825 qla2x00_delete_all_vps(ha, base_vha);
6826
6827 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6828
6829 qla2x00_dfs_remove(base_vha);
6830
6831 qla84xx_put_chip(base_vha);
6832
6833 if (base_vha->timer_active)
6834 qla2x00_stop_timer(base_vha);
6835
6836 base_vha->flags.online = 0;
6837
6838 qla2x00_destroy_deferred_work(ha);
6839
6840 /*
6841 * Do not try to stop beacon blink as it will issue a mailbox
6842 * command.
6843 */
6844 qla2x00_free_sysfs_attr(base_vha, false);
6845
6846 fc_remove_host(base_vha->host);
6847
6848 scsi_remove_host(base_vha->host);
6849
6850 base_vha->flags.init_done = 0;
6851 qla25xx_delete_queues(base_vha);
6852 qla2x00_free_fcports(base_vha);
6853 qla2x00_free_irqs(base_vha);
6854 qla2x00_mem_free(ha);
6855 qla82xx_md_free(base_vha);
6856 qla2x00_free_queues(ha);
6857
6858 qla2x00_unmap_iobases(ha);
6859
6860 pci_release_selected_regions(ha->pdev, ha->bars);
6861 pci_disable_device(pdev);
6862
6863 /*
6864 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6865 */
6866 }
6867
6868 /**************************************************************************
6869 * qla2x00_do_dpc
6870 * This kernel thread is a task that is schedule by the interrupt handler
6871 * to perform the background processing for interrupts.
6872 *
6873 * Notes:
6874 * This task always run in the context of a kernel thread. It
6875 * is kick-off by the driver's detect code and starts up
6876 * up one per adapter. It immediately goes to sleep and waits for
6877 * some fibre event. When either the interrupt handler or
6878 * the timer routine detects a event it will one of the task
6879 * bits then wake us up.
6880 **************************************************************************/
6881 static int
qla2x00_do_dpc(void * data)6882 qla2x00_do_dpc(void *data)
6883 {
6884 scsi_qla_host_t *base_vha;
6885 struct qla_hw_data *ha;
6886 uint32_t online;
6887 struct qla_qpair *qpair;
6888
6889 ha = (struct qla_hw_data *)data;
6890 base_vha = pci_get_drvdata(ha->pdev);
6891
6892 set_user_nice(current, MIN_NICE);
6893
6894 set_current_state(TASK_INTERRUPTIBLE);
6895 while (1) {
6896 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6897 "DPC handler sleeping.\n");
6898
6899 schedule();
6900
6901 if (kthread_should_stop())
6902 break;
6903
6904 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
6905 qla_pci_set_eeh_busy(base_vha);
6906
6907 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6908 goto end_loop;
6909
6910 if (ha->flags.eeh_busy) {
6911 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6912 "eeh_busy=%d.\n", ha->flags.eeh_busy);
6913 goto end_loop;
6914 }
6915
6916 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6917 /* don't do any work. Wait to be terminated by kthread_stop */
6918 goto end_loop;
6919
6920 ha->dpc_active = 1;
6921
6922 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6923 "DPC handler waking up, dpc_flags=0x%lx.\n",
6924 base_vha->dpc_flags);
6925
6926 if (IS_P3P_TYPE(ha)) {
6927 if (IS_QLA8044(ha)) {
6928 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6929 &base_vha->dpc_flags)) {
6930 qla8044_idc_lock(ha);
6931 qla8044_wr_direct(base_vha,
6932 QLA8044_CRB_DEV_STATE_INDEX,
6933 QLA8XXX_DEV_FAILED);
6934 qla8044_idc_unlock(ha);
6935 ql_log(ql_log_info, base_vha, 0x4004,
6936 "HW State: FAILED.\n");
6937 qla8044_device_state_handler(base_vha);
6938 continue;
6939 }
6940
6941 } else {
6942 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6943 &base_vha->dpc_flags)) {
6944 qla82xx_idc_lock(ha);
6945 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6946 QLA8XXX_DEV_FAILED);
6947 qla82xx_idc_unlock(ha);
6948 ql_log(ql_log_info, base_vha, 0x0151,
6949 "HW State: FAILED.\n");
6950 qla82xx_device_state_handler(base_vha);
6951 continue;
6952 }
6953 }
6954
6955 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6956 &base_vha->dpc_flags)) {
6957
6958 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6959 "FCoE context reset scheduled.\n");
6960 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6961 &base_vha->dpc_flags))) {
6962 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6963 /* FCoE-ctx reset failed.
6964 * Escalate to chip-reset
6965 */
6966 set_bit(ISP_ABORT_NEEDED,
6967 &base_vha->dpc_flags);
6968 }
6969 clear_bit(ABORT_ISP_ACTIVE,
6970 &base_vha->dpc_flags);
6971 }
6972
6973 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6974 "FCoE context reset end.\n");
6975 }
6976 } else if (IS_QLAFX00(ha)) {
6977 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6978 &base_vha->dpc_flags)) {
6979 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6980 "Firmware Reset Recovery\n");
6981 if (qlafx00_reset_initialize(base_vha)) {
6982 /* Failed. Abort isp later. */
6983 if (!test_bit(UNLOADING,
6984 &base_vha->dpc_flags)) {
6985 set_bit(ISP_UNRECOVERABLE,
6986 &base_vha->dpc_flags);
6987 ql_dbg(ql_dbg_dpc, base_vha,
6988 0x4021,
6989 "Reset Recovery Failed\n");
6990 }
6991 }
6992 }
6993
6994 if (test_and_clear_bit(FX00_TARGET_SCAN,
6995 &base_vha->dpc_flags)) {
6996 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6997 "ISPFx00 Target Scan scheduled\n");
6998 if (qlafx00_rescan_isp(base_vha)) {
6999 if (!test_bit(UNLOADING,
7000 &base_vha->dpc_flags))
7001 set_bit(ISP_UNRECOVERABLE,
7002 &base_vha->dpc_flags);
7003 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
7004 "ISPFx00 Target Scan Failed\n");
7005 }
7006 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
7007 "ISPFx00 Target Scan End\n");
7008 }
7009 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
7010 &base_vha->dpc_flags)) {
7011 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
7012 "ISPFx00 Host Info resend scheduled\n");
7013 qlafx00_fx_disc(base_vha,
7014 &base_vha->hw->mr.fcport,
7015 FXDISC_REG_HOST_INFO);
7016 }
7017 }
7018
7019 if (test_and_clear_bit(DETECT_SFP_CHANGE,
7020 &base_vha->dpc_flags)) {
7021 /* Semantic:
7022 * - NO-OP -- await next ISP-ABORT. Preferred method
7023 * to minimize disruptions that will occur
7024 * when a forced chip-reset occurs.
7025 * - Force -- ISP-ABORT scheduled.
7026 */
7027 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
7028 }
7029
7030 if (test_and_clear_bit
7031 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
7032 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
7033 bool do_reset = true;
7034
7035 switch (base_vha->qlini_mode) {
7036 case QLA2XXX_INI_MODE_ENABLED:
7037 break;
7038 case QLA2XXX_INI_MODE_DISABLED:
7039 if (!qla_tgt_mode_enabled(base_vha) &&
7040 !ha->flags.fw_started)
7041 do_reset = false;
7042 break;
7043 case QLA2XXX_INI_MODE_DUAL:
7044 if (!qla_dual_mode_enabled(base_vha) &&
7045 !ha->flags.fw_started)
7046 do_reset = false;
7047 break;
7048 default:
7049 break;
7050 }
7051
7052 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
7053 &base_vha->dpc_flags))) {
7054 base_vha->flags.online = 1;
7055 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
7056 "ISP abort scheduled.\n");
7057 if (ha->isp_ops->abort_isp(base_vha)) {
7058 /* failed. retry later */
7059 set_bit(ISP_ABORT_NEEDED,
7060 &base_vha->dpc_flags);
7061 }
7062 clear_bit(ABORT_ISP_ACTIVE,
7063 &base_vha->dpc_flags);
7064 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
7065 "ISP abort end.\n");
7066 }
7067 }
7068
7069 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
7070 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
7071 qla24xx_process_purex_list
7072 (&base_vha->purex_list);
7073 clear_bit(PROCESS_PUREX_IOCB,
7074 &base_vha->dpc_flags);
7075 }
7076 }
7077
7078 if (IS_QLAFX00(ha))
7079 goto loop_resync_check;
7080
7081 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7082 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
7083 "Quiescence mode scheduled.\n");
7084 if (IS_P3P_TYPE(ha)) {
7085 if (IS_QLA82XX(ha))
7086 qla82xx_device_state_handler(base_vha);
7087 if (IS_QLA8044(ha))
7088 qla8044_device_state_handler(base_vha);
7089 clear_bit(ISP_QUIESCE_NEEDED,
7090 &base_vha->dpc_flags);
7091 if (!ha->flags.quiesce_owner) {
7092 qla2x00_perform_loop_resync(base_vha);
7093 if (IS_QLA82XX(ha)) {
7094 qla82xx_idc_lock(ha);
7095 qla82xx_clear_qsnt_ready(
7096 base_vha);
7097 qla82xx_idc_unlock(ha);
7098 } else if (IS_QLA8044(ha)) {
7099 qla8044_idc_lock(ha);
7100 qla8044_clear_qsnt_ready(
7101 base_vha);
7102 qla8044_idc_unlock(ha);
7103 }
7104 }
7105 } else {
7106 clear_bit(ISP_QUIESCE_NEEDED,
7107 &base_vha->dpc_flags);
7108 qla2x00_quiesce_io(base_vha);
7109 }
7110 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
7111 "Quiescence mode end.\n");
7112 }
7113
7114 if (test_and_clear_bit(RESET_MARKER_NEEDED,
7115 &base_vha->dpc_flags) &&
7116 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
7117
7118 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
7119 "Reset marker scheduled.\n");
7120 qla2x00_rst_aen(base_vha);
7121 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7122 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
7123 "Reset marker end.\n");
7124 }
7125
7126 /* Retry each device up to login retry count */
7127 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
7128 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
7129 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
7130
7131 if (!base_vha->relogin_jif ||
7132 time_after_eq(jiffies, base_vha->relogin_jif)) {
7133 base_vha->relogin_jif = jiffies + HZ;
7134 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
7135
7136 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
7137 "Relogin scheduled.\n");
7138 qla24xx_post_relogin_work(base_vha);
7139 }
7140 }
7141 loop_resync_check:
7142 if (!qla2x00_reset_active(base_vha) &&
7143 test_and_clear_bit(LOOP_RESYNC_NEEDED,
7144 &base_vha->dpc_flags)) {
7145 /*
7146 * Allow abort_isp to complete before moving on to scanning.
7147 */
7148 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
7149 "Loop resync scheduled.\n");
7150
7151 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
7152 &base_vha->dpc_flags))) {
7153
7154 qla2x00_loop_resync(base_vha);
7155
7156 clear_bit(LOOP_RESYNC_ACTIVE,
7157 &base_vha->dpc_flags);
7158 }
7159
7160 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
7161 "Loop resync end.\n");
7162 }
7163
7164 if (IS_QLAFX00(ha))
7165 goto intr_on_check;
7166
7167 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7168 atomic_read(&base_vha->loop_state) == LOOP_READY) {
7169 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7170 qla2xxx_flash_npiv_conf(base_vha);
7171 }
7172
7173 intr_on_check:
7174 if (!ha->interrupts_on)
7175 ha->isp_ops->enable_intrs(ha);
7176
7177 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
7178 &base_vha->dpc_flags)) {
7179 if (ha->beacon_blink_led == 1)
7180 ha->isp_ops->beacon_blink(base_vha);
7181 }
7182
7183 /* qpair online check */
7184 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
7185 &base_vha->dpc_flags)) {
7186 if (ha->flags.eeh_busy ||
7187 ha->flags.pci_channel_io_perm_failure)
7188 online = 0;
7189 else
7190 online = 1;
7191
7192 mutex_lock(&ha->mq_lock);
7193 list_for_each_entry(qpair, &base_vha->qp_list,
7194 qp_list_elem)
7195 qpair->online = online;
7196 mutex_unlock(&ha->mq_lock);
7197 }
7198
7199 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
7200 &base_vha->dpc_flags)) {
7201 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;
7202
7203 if (threshold > ha->orig_fw_xcb_count)
7204 threshold = ha->orig_fw_xcb_count;
7205
7206 ql_log(ql_log_info, base_vha, 0xffffff,
7207 "SET ZIO Activity exchange threshold to %d.\n",
7208 threshold);
7209 if (qla27xx_set_zio_threshold(base_vha, threshold)) {
7210 ql_log(ql_log_info, base_vha, 0xffffff,
7211 "Unable to SET ZIO Activity exchange threshold to %d.\n",
7212 threshold);
7213 }
7214 }
7215
7216 if (!IS_QLAFX00(ha))
7217 qla2x00_do_dpc_all_vps(base_vha);
7218
7219 if (test_and_clear_bit(N2N_LINK_RESET,
7220 &base_vha->dpc_flags)) {
7221 qla2x00_lip_reset(base_vha);
7222 }
7223
7224 ha->dpc_active = 0;
7225 end_loop:
7226 set_current_state(TASK_INTERRUPTIBLE);
7227 } /* End of while(1) */
7228 __set_current_state(TASK_RUNNING);
7229
7230 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7231 "DPC handler exiting.\n");
7232
7233 /*
7234 * Make sure that nobody tries to wake us up again.
7235 */
7236 ha->dpc_active = 0;
7237
7238 return 0;
7239 }
7240
7241 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)7242 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7243 {
7244 struct qla_hw_data *ha = vha->hw;
7245 struct task_struct *t = ha->dpc_thread;
7246
7247 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7248 wake_up_process(t);
7249 }
7250 EXPORT_SYMBOL(qla2xxx_wake_dpc);
7251
7252 /*
7253 * qla2x00_rst_aen
7254 * Processes asynchronous reset.
7255 *
7256 * Input:
7257 * ha = adapter block pointer.
7258 */
7259 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)7260 qla2x00_rst_aen(scsi_qla_host_t *vha)
7261 {
7262 if (vha->flags.online && !vha->flags.reset_active &&
7263 !atomic_read(&vha->loop_down_timer) &&
7264 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7265 do {
7266 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7267
7268 /*
7269 * Issue marker command only when we are going to start
7270 * the I/O.
7271 */
7272 vha->marker_needed = 1;
7273 } while (!atomic_read(&vha->loop_down_timer) &&
7274 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7275 }
7276 }
7277
qla_do_heartbeat(struct scsi_qla_host * vha)7278 static bool qla_do_heartbeat(struct scsi_qla_host *vha)
7279 {
7280 struct qla_hw_data *ha = vha->hw;
7281 u32 cmpl_cnt;
7282 u16 i;
7283 bool do_heartbeat = false;
7284
7285 /*
7286 * Allow do_heartbeat only if we don’t have any active interrupts,
7287 * but there are still IOs outstanding with firmware.
7288 */
7289 cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
7290 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
7291 cmpl_cnt != ha->base_qpair->cmd_cnt) {
7292 do_heartbeat = true;
7293 goto skip;
7294 }
7295 ha->base_qpair->prev_completion_cnt = cmpl_cnt;
7296
7297 for (i = 0; i < ha->max_qpairs; i++) {
7298 if (ha->queue_pair_map[i]) {
7299 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
7300 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
7301 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
7302 do_heartbeat = true;
7303 break;
7304 }
7305 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
7306 }
7307 }
7308
7309 skip:
7310 return do_heartbeat;
7311 }
7312
qla_heart_beat(struct scsi_qla_host * vha,u16 dpc_started)7313 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started)
7314 {
7315 struct qla_hw_data *ha = vha->hw;
7316
7317 if (vha->vp_idx)
7318 return;
7319
7320 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
7321 return;
7322
7323 /*
7324 * dpc thread cannot run if heartbeat is running at the same time.
7325 * We also do not want to starve heartbeat task. Therefore, do
7326 * heartbeat task at least once every 5 seconds.
7327 */
7328 if (dpc_started &&
7329 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
7330 return;
7331
7332 if (qla_do_heartbeat(vha)) {
7333 ha->last_heartbeat_run_jiffies = jiffies;
7334 queue_work(ha->wq, &ha->heartbeat_work);
7335 }
7336 }
7337
qla_wind_down_chip(scsi_qla_host_t * vha)7338 static void qla_wind_down_chip(scsi_qla_host_t *vha)
7339 {
7340 struct qla_hw_data *ha = vha->hw;
7341
7342 if (!ha->flags.eeh_busy)
7343 return;
7344 if (ha->pci_error_state)
7345 /* system is trying to recover */
7346 return;
7347
7348 /*
7349 * Current system is not handling PCIE error. At this point, this is
7350 * best effort to wind down the adapter.
7351 */
7352 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
7353 !ha->flags.eeh_flush) {
7354 ql_log(ql_log_info, vha, 0x9009,
7355 "PCI Error detected, attempting to reset hardware.\n");
7356
7357 ha->isp_ops->reset_chip(vha);
7358 ha->isp_ops->disable_intrs(ha);
7359
7360 ha->flags.eeh_flush = EEH_FLUSH_RDY;
7361 ha->eeh_jif = jiffies;
7362
7363 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
7364 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) {
7365 pci_clear_master(ha->pdev);
7366
7367 /* flush all command */
7368 qla2x00_abort_isp_cleanup(vha);
7369 ha->flags.eeh_flush = EEH_FLUSH_DONE;
7370
7371 ql_log(ql_log_info, vha, 0x900a,
7372 "PCI Error handling complete, all IOs aborted.\n");
7373 }
7374 }
7375
7376 /**************************************************************************
7377 * qla2x00_timer
7378 *
7379 * Description:
7380 * One second timer
7381 *
7382 * Context: Interrupt
7383 ***************************************************************************/
7384 void
qla2x00_timer(struct timer_list * t)7385 qla2x00_timer(struct timer_list *t)
7386 {
7387 scsi_qla_host_t *vha = timer_container_of(vha, t, timer);
7388 unsigned long cpu_flags = 0;
7389 int start_dpc = 0;
7390 int index;
7391 srb_t *sp;
7392 uint16_t w;
7393 struct qla_hw_data *ha = vha->hw;
7394 struct req_que *req;
7395 unsigned long flags;
7396 fc_port_t *fcport = NULL;
7397
7398 if (ha->flags.eeh_busy) {
7399 qla_wind_down_chip(vha);
7400
7401 ql_dbg(ql_dbg_timer, vha, 0x6000,
7402 "EEH = %d, restarting timer.\n",
7403 ha->flags.eeh_busy);
7404 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7405 return;
7406 }
7407
7408 /*
7409 * Hardware read to raise pending EEH errors during mailbox waits. If
7410 * the read returns -1 then disable the board.
7411 */
7412 if (!pci_channel_offline(ha->pdev)) {
7413 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7414 qla2x00_check_reg16_for_disconnect(vha, w);
7415 }
7416
7417 /* Make sure qla82xx_watchdog is run only for physical port */
7418 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7419 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7420 start_dpc++;
7421 if (IS_QLA82XX(ha))
7422 qla82xx_watchdog(vha);
7423 else if (IS_QLA8044(ha))
7424 qla8044_watchdog(vha);
7425 }
7426
7427 if (!vha->vp_idx && IS_QLAFX00(ha))
7428 qlafx00_timer_routine(vha);
7429
7430 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7431 vha->link_down_time++;
7432
7433 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7434 list_for_each_entry(fcport, &vha->vp_fcports, list) {
7435 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7436 fcport->tgt_link_down_time++;
7437 }
7438 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
7439
7440 /* Loop down handler. */
7441 if (atomic_read(&vha->loop_down_timer) > 0 &&
7442 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7443 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7444 && vha->flags.online) {
7445
7446 if (atomic_read(&vha->loop_down_timer) ==
7447 vha->loop_down_abort_time) {
7448
7449 ql_log(ql_log_info, vha, 0x6008,
7450 "Loop down - aborting the queues before time expires.\n");
7451
7452 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7453 atomic_set(&vha->loop_state, LOOP_DEAD);
7454
7455 /*
7456 * Schedule an ISP abort to return any FCP2-device
7457 * commands.
7458 */
7459 /* NPIV - scan physical port only */
7460 if (!vha->vp_idx) {
7461 spin_lock_irqsave(&ha->hardware_lock,
7462 cpu_flags);
7463 req = ha->req_q_map[0];
7464 for (index = 1;
7465 index < req->num_outstanding_cmds;
7466 index++) {
7467 fc_port_t *sfcp;
7468
7469 sp = req->outstanding_cmds[index];
7470 if (!sp)
7471 continue;
7472 if (sp->cmd_type != TYPE_SRB)
7473 continue;
7474 if (sp->type != SRB_SCSI_CMD)
7475 continue;
7476 sfcp = sp->fcport;
7477 if (!(sfcp->flags & FCF_FCP2_DEVICE))
7478 continue;
7479
7480 if (IS_QLA82XX(ha))
7481 set_bit(FCOE_CTX_RESET_NEEDED,
7482 &vha->dpc_flags);
7483 else
7484 set_bit(ISP_ABORT_NEEDED,
7485 &vha->dpc_flags);
7486 break;
7487 }
7488 spin_unlock_irqrestore(&ha->hardware_lock,
7489 cpu_flags);
7490 }
7491 start_dpc++;
7492 }
7493
7494 /* if the loop has been down for 4 minutes, reinit adapter */
7495 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7496 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) {
7497 ql_log(ql_log_warn, vha, 0x6009,
7498 "Loop down - aborting ISP.\n");
7499
7500 if (IS_QLA82XX(ha))
7501 set_bit(FCOE_CTX_RESET_NEEDED,
7502 &vha->dpc_flags);
7503 else
7504 set_bit(ISP_ABORT_NEEDED,
7505 &vha->dpc_flags);
7506 }
7507 }
7508 ql_dbg(ql_dbg_timer, vha, 0x600a,
7509 "Loop down - seconds remaining %d.\n",
7510 atomic_read(&vha->loop_down_timer));
7511 }
7512 /* Check if beacon LED needs to be blinked for physical host only */
7513 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7514 /* There is no beacon_blink function for ISP82xx */
7515 if (!IS_P3P_TYPE(ha)) {
7516 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7517 start_dpc++;
7518 }
7519 }
7520
7521 /* check if edif running */
7522 if (vha->hw->flags.edif_enabled)
7523 qla_edif_timer(vha);
7524
7525 /* Process any deferred work. */
7526 if (!list_empty(&vha->work_list)) {
7527 unsigned long flags;
7528 bool q = false;
7529
7530 spin_lock_irqsave(&vha->work_lock, flags);
7531 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7532 q = true;
7533 spin_unlock_irqrestore(&vha->work_lock, flags);
7534 if (q)
7535 queue_work(vha->hw->wq, &vha->iocb_work);
7536 }
7537
7538 /*
7539 * FC-NVME
7540 * see if the active AEN count has changed from what was last reported.
7541 */
7542 index = atomic_read(&ha->nvme_active_aen_cnt);
7543 if (!vha->vp_idx &&
7544 (index != ha->nvme_last_rptd_aen) &&
7545 ha->zio_mode == QLA_ZIO_MODE_6 &&
7546 !ha->flags.host_shutting_down) {
7547 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7548 ql_log(ql_log_info, vha, 0x3002,
7549 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7550 ha->nvme_last_rptd_aen);
7551 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7552 start_dpc++;
7553 }
7554
7555 if (!vha->vp_idx &&
7556 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7557 IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7558 ql_log(ql_log_info, vha, 0x3002,
7559 "Sched: Set ZIO exchange threshold to %d.\n",
7560 ha->last_zio_threshold);
7561 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7562 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7563 start_dpc++;
7564 }
7565 qla_adjust_buf(vha);
7566
7567 /* borrowing w to signify dpc will run */
7568 w = 0;
7569 /* Schedule the DPC routine if needed */
7570 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7571 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7572 start_dpc ||
7573 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7574 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7575 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7576 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7577 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7578 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7579 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7580 ql_dbg(ql_dbg_timer, vha, 0x600b,
7581 "isp_abort_needed=%d loop_resync_needed=%d "
7582 "start_dpc=%d reset_marker_needed=%d",
7583 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7584 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7585 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7586 ql_dbg(ql_dbg_timer, vha, 0x600c,
7587 "beacon_blink_needed=%d isp_unrecoverable=%d "
7588 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7589 "relogin_needed=%d, Process_purex_iocb=%d.\n",
7590 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7591 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7592 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7593 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7594 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7595 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7596 qla2xxx_wake_dpc(vha);
7597 w = 1;
7598 }
7599
7600 qla_heart_beat(vha, w);
7601
7602 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7603 }
7604
7605 /* Firmware interface routines. */
7606
7607 #define FW_ISP21XX 0
7608 #define FW_ISP22XX 1
7609 #define FW_ISP2300 2
7610 #define FW_ISP2322 3
7611 #define FW_ISP24XX 4
7612 #define FW_ISP25XX 5
7613 #define FW_ISP81XX 6
7614 #define FW_ISP82XX 7
7615 #define FW_ISP2031 8
7616 #define FW_ISP8031 9
7617 #define FW_ISP27XX 10
7618 #define FW_ISP28XX 11
7619
7620 #define FW_FILE_ISP21XX "ql2100_fw.bin"
7621 #define FW_FILE_ISP22XX "ql2200_fw.bin"
7622 #define FW_FILE_ISP2300 "ql2300_fw.bin"
7623 #define FW_FILE_ISP2322 "ql2322_fw.bin"
7624 #define FW_FILE_ISP24XX "ql2400_fw.bin"
7625 #define FW_FILE_ISP25XX "ql2500_fw.bin"
7626 #define FW_FILE_ISP81XX "ql8100_fw.bin"
7627 #define FW_FILE_ISP82XX "ql8200_fw.bin"
7628 #define FW_FILE_ISP2031 "ql2600_fw.bin"
7629 #define FW_FILE_ISP8031 "ql8300_fw.bin"
7630 #define FW_FILE_ISP27XX "ql2700_fw.bin"
7631 #define FW_FILE_ISP28XX "ql2800_fw.bin"
7632
7633
7634 static DEFINE_MUTEX(qla_fw_lock);
7635
7636 static struct fw_blob qla_fw_blobs[] = {
7637 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7638 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7639 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7640 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7641 { .name = FW_FILE_ISP24XX, },
7642 { .name = FW_FILE_ISP25XX, },
7643 { .name = FW_FILE_ISP81XX, },
7644 { .name = FW_FILE_ISP82XX, },
7645 { .name = FW_FILE_ISP2031, },
7646 { .name = FW_FILE_ISP8031, },
7647 { .name = FW_FILE_ISP27XX, },
7648 { .name = FW_FILE_ISP28XX, },
7649 { .name = NULL, },
7650 };
7651
7652 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)7653 qla2x00_request_firmware(scsi_qla_host_t *vha)
7654 {
7655 struct qla_hw_data *ha = vha->hw;
7656 struct fw_blob *blob;
7657
7658 if (IS_QLA2100(ha)) {
7659 blob = &qla_fw_blobs[FW_ISP21XX];
7660 } else if (IS_QLA2200(ha)) {
7661 blob = &qla_fw_blobs[FW_ISP22XX];
7662 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7663 blob = &qla_fw_blobs[FW_ISP2300];
7664 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7665 blob = &qla_fw_blobs[FW_ISP2322];
7666 } else if (IS_QLA24XX_TYPE(ha)) {
7667 blob = &qla_fw_blobs[FW_ISP24XX];
7668 } else if (IS_QLA25XX(ha)) {
7669 blob = &qla_fw_blobs[FW_ISP25XX];
7670 } else if (IS_QLA81XX(ha)) {
7671 blob = &qla_fw_blobs[FW_ISP81XX];
7672 } else if (IS_QLA82XX(ha)) {
7673 blob = &qla_fw_blobs[FW_ISP82XX];
7674 } else if (IS_QLA2031(ha)) {
7675 blob = &qla_fw_blobs[FW_ISP2031];
7676 } else if (IS_QLA8031(ha)) {
7677 blob = &qla_fw_blobs[FW_ISP8031];
7678 } else if (IS_QLA27XX(ha)) {
7679 blob = &qla_fw_blobs[FW_ISP27XX];
7680 } else if (IS_QLA28XX(ha)) {
7681 blob = &qla_fw_blobs[FW_ISP28XX];
7682 } else {
7683 return NULL;
7684 }
7685
7686 if (!blob->name)
7687 return NULL;
7688
7689 mutex_lock(&qla_fw_lock);
7690 if (blob->fw)
7691 goto out;
7692
7693 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7694 ql_log(ql_log_warn, vha, 0x0063,
7695 "Failed to load firmware image (%s).\n", blob->name);
7696 blob->fw = NULL;
7697 blob = NULL;
7698 }
7699
7700 out:
7701 mutex_unlock(&qla_fw_lock);
7702 return blob;
7703 }
7704
7705 static void
qla2x00_release_firmware(void)7706 qla2x00_release_firmware(void)
7707 {
7708 struct fw_blob *blob;
7709
7710 mutex_lock(&qla_fw_lock);
7711 for (blob = qla_fw_blobs; blob->name; blob++)
7712 release_firmware(blob->fw);
7713 mutex_unlock(&qla_fw_lock);
7714 }
7715
qla_pci_error_cleanup(scsi_qla_host_t * vha)7716 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7717 {
7718 struct qla_hw_data *ha = vha->hw;
7719 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7720 struct qla_qpair *qpair = NULL;
7721 struct scsi_qla_host *vp, *tvp;
7722 fc_port_t *fcport;
7723 int i;
7724 unsigned long flags;
7725
7726 ql_dbg(ql_dbg_aer, vha, 0x9000,
7727 "%s\n", __func__);
7728 ha->chip_reset++;
7729
7730 ha->base_qpair->chip_reset = ha->chip_reset;
7731 for (i = 0; i < ha->max_qpairs; i++) {
7732 if (ha->queue_pair_map[i])
7733 ha->queue_pair_map[i]->chip_reset =
7734 ha->base_qpair->chip_reset;
7735 }
7736
7737 /*
7738 * purge mailbox might take a while. Slot Reset/chip reset
7739 * will take care of the purge
7740 */
7741
7742 mutex_lock(&ha->mq_lock);
7743 ha->base_qpair->online = 0;
7744 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7745 qpair->online = 0;
7746 wmb();
7747 mutex_unlock(&ha->mq_lock);
7748
7749 qla2x00_mark_all_devices_lost(vha);
7750
7751 spin_lock_irqsave(&ha->vport_slock, flags);
7752 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7753 atomic_inc(&vp->vref_count);
7754 spin_unlock_irqrestore(&ha->vport_slock, flags);
7755 qla2x00_mark_all_devices_lost(vp);
7756 spin_lock_irqsave(&ha->vport_slock, flags);
7757 atomic_dec(&vp->vref_count);
7758 }
7759 spin_unlock_irqrestore(&ha->vport_slock, flags);
7760
7761 /* Clear all async request states across all VPs. */
7762 list_for_each_entry(fcport, &vha->vp_fcports, list)
7763 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7764
7765 spin_lock_irqsave(&ha->vport_slock, flags);
7766 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7767 atomic_inc(&vp->vref_count);
7768 spin_unlock_irqrestore(&ha->vport_slock, flags);
7769 list_for_each_entry(fcport, &vp->vp_fcports, list)
7770 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7771 spin_lock_irqsave(&ha->vport_slock, flags);
7772 atomic_dec(&vp->vref_count);
7773 }
7774 spin_unlock_irqrestore(&ha->vport_slock, flags);
7775 }
7776
7777
7778 /**
7779 * qla2xxx_set_affinity_nobalance
7780 * @pdev: pci_dev struct for a qla2xxx device
7781 * @flag: bool
7782 * true: enable "IRQ_NO_BALANCING" bit for msix interrupt
7783 * false: disable "IRQ_NO_BALANCING" bit for msix interrupt
7784 * Description: This function will be called to disable/enable
7785 * "IRQ_NO_BALANCING" to avoid irqbalance daemon
7786 * kicking in during adapter reset.
7787 **/
7788
qla2xxx_set_affinity_nobalance(struct pci_dev * pdev,bool flag)7789 static void qla2xxx_set_affinity_nobalance(struct pci_dev *pdev, bool flag)
7790 {
7791 int irq, i;
7792
7793 for (i = 0; i < QLA_BASE_VECTORS; i++) {
7794 irq = pci_irq_vector(pdev, i);
7795
7796 if (flag)
7797 irq_set_status_flags(irq, IRQ_NO_BALANCING);
7798 else
7799 irq_clear_status_flags(irq, IRQ_NO_BALANCING);
7800 }
7801 }
7802
7803 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7804 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7805 {
7806 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7807 struct qla_hw_data *ha = vha->hw;
7808 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET;
7809
7810 ql_log(ql_log_warn, vha, 0x9000,
7811 "PCI error detected, state %x.\n", state);
7812 ha->pci_error_state = QLA_PCI_ERR_DETECTED;
7813
7814 if (!atomic_read(&pdev->enable_cnt)) {
7815 ql_log(ql_log_info, vha, 0xffff,
7816 "PCI device is disabled,state %x\n", state);
7817 ret = PCI_ERS_RESULT_NEED_RESET;
7818 goto out;
7819 }
7820
7821 qla2xxx_set_affinity_nobalance(pdev, false);
7822
7823 switch (state) {
7824 case pci_channel_io_normal:
7825 qla_pci_set_eeh_busy(vha);
7826 if (ql2xmqsupport || ql2xnvmeenable) {
7827 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7828 qla2xxx_wake_dpc(vha);
7829 }
7830 ret = PCI_ERS_RESULT_CAN_RECOVER;
7831 break;
7832 case pci_channel_io_frozen:
7833 qla_pci_set_eeh_busy(vha);
7834 ret = PCI_ERS_RESULT_NEED_RESET;
7835 break;
7836 case pci_channel_io_perm_failure:
7837 ha->flags.pci_channel_io_perm_failure = 1;
7838 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7839 if (ql2xmqsupport || ql2xnvmeenable) {
7840 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7841 qla2xxx_wake_dpc(vha);
7842 }
7843 ret = PCI_ERS_RESULT_DISCONNECT;
7844 }
7845 out:
7846 ql_dbg(ql_dbg_aer, vha, 0x600d,
7847 "PCI error detected returning [%x].\n", ret);
7848 return ret;
7849 }
7850
7851 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)7852 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7853 {
7854 int risc_paused = 0;
7855 uint32_t stat;
7856 unsigned long flags;
7857 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7858 struct qla_hw_data *ha = base_vha->hw;
7859 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7860 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7861
7862 ql_log(ql_log_warn, base_vha, 0x9000,
7863 "mmio enabled\n");
7864
7865 ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
7866
7867 if (IS_QLA82XX(ha))
7868 return PCI_ERS_RESULT_RECOVERED;
7869
7870 if (qla2x00_isp_reg_stat(ha)) {
7871 ql_log(ql_log_info, base_vha, 0x803f,
7872 "During mmio enabled, PCI/Register disconnect still detected.\n");
7873 goto out;
7874 }
7875
7876 spin_lock_irqsave(&ha->hardware_lock, flags);
7877 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7878 stat = rd_reg_word(®->hccr);
7879 if (stat & HCCR_RISC_PAUSE)
7880 risc_paused = 1;
7881 } else if (IS_QLA23XX(ha)) {
7882 stat = rd_reg_dword(®->u.isp2300.host_status);
7883 if (stat & HSR_RISC_PAUSED)
7884 risc_paused = 1;
7885 } else if (IS_FWI2_CAPABLE(ha)) {
7886 stat = rd_reg_dword(®24->host_status);
7887 if (stat & HSRX_RISC_PAUSED)
7888 risc_paused = 1;
7889 }
7890 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7891
7892 if (risc_paused) {
7893 ql_log(ql_log_info, base_vha, 0x9003,
7894 "RISC paused -- mmio_enabled, Dumping firmware.\n");
7895 qla2xxx_dump_fw(base_vha);
7896 }
7897 out:
7898 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */
7899 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7900 "mmio enabled returning.\n");
7901 return PCI_ERS_RESULT_NEED_RESET;
7902 }
7903
7904 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)7905 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7906 {
7907 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7908 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7909 struct qla_hw_data *ha = base_vha->hw;
7910 int rc;
7911 struct qla_qpair *qpair = NULL;
7912
7913 ql_log(ql_log_warn, base_vha, 0x9004,
7914 "Slot Reset.\n");
7915
7916 ha->pci_error_state = QLA_PCI_SLOT_RESET;
7917
7918 pci_restore_state(pdev);
7919
7920 if (ha->mem_only)
7921 rc = pci_enable_device_mem(pdev);
7922 else
7923 rc = pci_enable_device(pdev);
7924
7925 if (rc) {
7926 ql_log(ql_log_warn, base_vha, 0x9005,
7927 "Can't re-enable PCI device after reset.\n");
7928 goto exit_slot_reset;
7929 }
7930
7931
7932 if (ha->isp_ops->pci_config(base_vha))
7933 goto exit_slot_reset;
7934
7935 mutex_lock(&ha->mq_lock);
7936 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7937 qpair->online = 1;
7938 mutex_unlock(&ha->mq_lock);
7939
7940 ha->flags.eeh_busy = 0;
7941 base_vha->flags.online = 1;
7942 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7943 ha->isp_ops->abort_isp(base_vha);
7944 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7945
7946 if (qla2x00_isp_reg_stat(ha)) {
7947 ha->flags.eeh_busy = 1;
7948 qla_pci_error_cleanup(base_vha);
7949 ql_log(ql_log_warn, base_vha, 0x9005,
7950 "Device unable to recover from PCI error.\n");
7951 } else {
7952 ret = PCI_ERS_RESULT_RECOVERED;
7953 }
7954
7955 exit_slot_reset:
7956 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7957 "Slot Reset returning %x.\n", ret);
7958
7959 qla2xxx_set_affinity_nobalance(pdev, true);
7960
7961 return ret;
7962 }
7963
7964 static void
qla2xxx_pci_resume(struct pci_dev * pdev)7965 qla2xxx_pci_resume(struct pci_dev *pdev)
7966 {
7967 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7968 struct qla_hw_data *ha = base_vha->hw;
7969 int ret;
7970
7971 ql_log(ql_log_warn, base_vha, 0x900f,
7972 "Pci Resume.\n");
7973
7974
7975 ret = qla2x00_wait_for_hba_online(base_vha);
7976 if (ret != QLA_SUCCESS) {
7977 ql_log(ql_log_fatal, base_vha, 0x9002,
7978 "The device failed to resume I/O from slot/link_reset.\n");
7979 }
7980 ha->pci_error_state = QLA_PCI_RESUME;
7981 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7982 "Pci Resume returning.\n");
7983 }
7984
qla_pci_set_eeh_busy(struct scsi_qla_host * vha)7985 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha)
7986 {
7987 struct qla_hw_data *ha = vha->hw;
7988 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7989 bool do_cleanup = false;
7990 unsigned long flags;
7991
7992 if (ha->flags.eeh_busy)
7993 return;
7994
7995 spin_lock_irqsave(&base_vha->work_lock, flags);
7996 if (!ha->flags.eeh_busy) {
7997 ha->eeh_jif = jiffies;
7998 ha->flags.eeh_flush = 0;
7999
8000 ha->flags.eeh_busy = 1;
8001 do_cleanup = true;
8002 }
8003 spin_unlock_irqrestore(&base_vha->work_lock, flags);
8004
8005 if (do_cleanup)
8006 qla_pci_error_cleanup(base_vha);
8007 }
8008
8009 /*
8010 * this routine will schedule a task to pause IO from interrupt context
8011 * if caller sees a PCIE error event (register read = 0xf's)
8012 */
qla_schedule_eeh_work(struct scsi_qla_host * vha)8013 void qla_schedule_eeh_work(struct scsi_qla_host *vha)
8014 {
8015 struct qla_hw_data *ha = vha->hw;
8016 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
8017
8018 if (ha->flags.eeh_busy)
8019 return;
8020
8021 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
8022 qla2xxx_wake_dpc(base_vha);
8023 }
8024
8025 static void
qla_pci_reset_prepare(struct pci_dev * pdev)8026 qla_pci_reset_prepare(struct pci_dev *pdev)
8027 {
8028 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8029 struct qla_hw_data *ha = base_vha->hw;
8030 struct qla_qpair *qpair;
8031
8032 ql_log(ql_log_warn, base_vha, 0xffff,
8033 "%s.\n", __func__);
8034
8035 /*
8036 * PCI FLR/function reset is about to reset the
8037 * slot. Stop the chip to stop all DMA access.
8038 * It is assumed that pci_reset_done will be called
8039 * after FLR to resume Chip operation.
8040 */
8041 ha->flags.eeh_busy = 1;
8042 mutex_lock(&ha->mq_lock);
8043 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8044 qpair->online = 0;
8045 mutex_unlock(&ha->mq_lock);
8046
8047 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8048 qla2x00_abort_isp_cleanup(base_vha);
8049 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
8050 }
8051
8052 static void
qla_pci_reset_done(struct pci_dev * pdev)8053 qla_pci_reset_done(struct pci_dev *pdev)
8054 {
8055 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8056 struct qla_hw_data *ha = base_vha->hw;
8057 struct qla_qpair *qpair;
8058
8059 ql_log(ql_log_warn, base_vha, 0xffff,
8060 "%s.\n", __func__);
8061
8062 /*
8063 * FLR just completed by PCI layer. Resume adapter
8064 */
8065 ha->flags.eeh_busy = 0;
8066 mutex_lock(&ha->mq_lock);
8067 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8068 qpair->online = 1;
8069 mutex_unlock(&ha->mq_lock);
8070
8071 base_vha->flags.online = 1;
8072 ha->isp_ops->abort_isp(base_vha);
8073 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8074 }
8075
qla2xxx_map_queues(struct Scsi_Host * shost)8076 static void qla2xxx_map_queues(struct Scsi_Host *shost)
8077 {
8078 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
8079 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
8080
8081 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
8082 blk_mq_map_queues(qmap);
8083 else
8084 blk_mq_map_hw_queues(qmap, &vha->hw->pdev->dev,
8085 vha->irq_offset);
8086 }
8087
8088 struct scsi_host_template qla2xxx_driver_template = {
8089 .module = THIS_MODULE,
8090 .name = QLA2XXX_DRIVER_NAME,
8091 .queuecommand = qla2xxx_queuecommand,
8092
8093 .eh_timed_out = fc_eh_timed_out,
8094 .eh_abort_handler = qla2xxx_eh_abort,
8095 .eh_should_retry_cmd = fc_eh_should_retry_cmd,
8096 .eh_device_reset_handler = qla2xxx_eh_device_reset,
8097 .eh_target_reset_handler = qla2xxx_eh_target_reset,
8098 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
8099 .eh_host_reset_handler = qla2xxx_eh_host_reset,
8100
8101 .sdev_configure = qla2xxx_sdev_configure,
8102
8103 .sdev_init = qla2xxx_sdev_init,
8104 .sdev_destroy = qla2xxx_sdev_destroy,
8105 .scan_finished = qla2xxx_scan_finished,
8106 .scan_start = qla2xxx_scan_start,
8107 .change_queue_depth = scsi_change_queue_depth,
8108 .map_queues = qla2xxx_map_queues,
8109 .this_id = -1,
8110 .cmd_per_lun = 3,
8111 .sg_tablesize = SG_ALL,
8112
8113 .max_sectors = 0xFFFF,
8114 .shost_groups = qla2x00_host_groups,
8115
8116 .supported_mode = MODE_INITIATOR,
8117 .track_queue_depth = 1,
8118 .cmd_size = sizeof(srb_t),
8119 };
8120
8121 static const struct pci_error_handlers qla2xxx_err_handler = {
8122 .error_detected = qla2xxx_pci_error_detected,
8123 .mmio_enabled = qla2xxx_pci_mmio_enabled,
8124 .slot_reset = qla2xxx_pci_slot_reset,
8125 .resume = qla2xxx_pci_resume,
8126 .reset_prepare = qla_pci_reset_prepare,
8127 .reset_done = qla_pci_reset_done,
8128 };
8129
8130 static const struct pci_device_id qla2xxx_pci_tbl[] = {
8131 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
8132 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
8133 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
8134 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
8135 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
8136 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
8137 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
8138 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
8139 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
8140 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
8141 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
8142 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
8143 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
8144 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
8145 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
8146 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
8147 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8148 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
8149 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
8150 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
8151 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
8152 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
8153 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
8154 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
8155 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
8156 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
8157 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
8158 { 0 },
8159 };
8160 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
8161
8162 static struct pci_driver qla2xxx_pci_driver = {
8163 .name = QLA2XXX_DRIVER_NAME,
8164 .id_table = qla2xxx_pci_tbl,
8165 .probe = qla2x00_probe_one,
8166 .remove = qla2x00_remove_one,
8167 .shutdown = qla2x00_shutdown,
8168 .err_handler = &qla2xxx_err_handler,
8169 };
8170
8171 static const struct file_operations apidev_fops = {
8172 .owner = THIS_MODULE,
8173 .llseek = noop_llseek,
8174 };
8175
8176 /**
8177 * qla2x00_module_init - Module initialization.
8178 **/
8179 static int __init
qla2x00_module_init(void)8180 qla2x00_module_init(void)
8181 {
8182 int ret = 0;
8183
8184 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
8185 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
8186 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
8187 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
8188 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8189 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
8190 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
8191 BUILD_BUG_ON(sizeof(request_t) != 64);
8192 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
8193 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
8194 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
8195 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8196 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
8197 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
8198 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
8199 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
8200 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
8201 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
8202 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
8203 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
8204 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604);
8205 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
8206 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
8207 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
8208 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
8209 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
8210 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8211 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
8212 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
8213 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
8214 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
8215 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
8216 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
8217 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
8218 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
8219 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
8220 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
8221 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
8222 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
8223 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
8224 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
8225 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
8226 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
8227 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
8228 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
8229 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
8230 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
8231 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
8232 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
8233 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
8234 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
8235 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
8236 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
8237 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
8238 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
8239 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
8240 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
8241 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
8242 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
8243 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
8244 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
8245 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
8246 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
8247 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
8248 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
8249 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
8250 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
8251 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
8252 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
8253 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
8254 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
8255 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
8256 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8257 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
8258 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
8259 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
8260 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
8261 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
8262 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
8263 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
8264 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
8265 BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
8266 BUILD_BUG_ON(sizeof(sw_info_t) != 32);
8267 BUILD_BUG_ON(sizeof(target_id_t) != 2);
8268
8269 qla_trace_init();
8270
8271 /* Allocate cache for SRBs. */
8272 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
8273 SLAB_HWCACHE_ALIGN, NULL);
8274 if (srb_cachep == NULL) {
8275 ql_log(ql_log_fatal, NULL, 0x0001,
8276 "Unable to allocate SRB cache...Failing load!.\n");
8277 return -ENOMEM;
8278 }
8279
8280 /* Initialize target kmem_cache and mem_pools */
8281 ret = qlt_init();
8282 if (ret < 0) {
8283 goto destroy_cache;
8284 } else if (ret > 0) {
8285 /*
8286 * If initiator mode is explictly disabled by qlt_init(),
8287 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
8288 * performing scsi_scan_target() during LOOP UP event.
8289 */
8290 qla2xxx_transport_functions.disable_target_scan = 1;
8291 qla2xxx_transport_vport_functions.disable_target_scan = 1;
8292 }
8293
8294 /* Derive version string. */
8295 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
8296 if (ql2xextended_error_logging)
8297 strcat(qla2x00_version_str, "-debug");
8298 if (ql2xextended_error_logging == 1)
8299 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
8300
8301 qla2xxx_transport_template =
8302 fc_attach_transport(&qla2xxx_transport_functions);
8303 if (!qla2xxx_transport_template) {
8304 ql_log(ql_log_fatal, NULL, 0x0002,
8305 "fc_attach_transport failed...Failing load!.\n");
8306 ret = -ENODEV;
8307 goto qlt_exit;
8308 }
8309
8310 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
8311 if (apidev_major < 0) {
8312 ql_log(ql_log_fatal, NULL, 0x0003,
8313 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
8314 }
8315
8316 qla2xxx_transport_vport_template =
8317 fc_attach_transport(&qla2xxx_transport_vport_functions);
8318 if (!qla2xxx_transport_vport_template) {
8319 ql_log(ql_log_fatal, NULL, 0x0004,
8320 "fc_attach_transport vport failed...Failing load!.\n");
8321 ret = -ENODEV;
8322 goto unreg_chrdev;
8323 }
8324 ql_log(ql_log_info, NULL, 0x0005,
8325 "QLogic Fibre Channel HBA Driver: %s.\n",
8326 qla2x00_version_str);
8327 ret = pci_register_driver(&qla2xxx_pci_driver);
8328 if (ret) {
8329 ql_log(ql_log_fatal, NULL, 0x0006,
8330 "pci_register_driver failed...ret=%d Failing load!.\n",
8331 ret);
8332 goto release_vport_transport;
8333 }
8334 return ret;
8335
8336 release_vport_transport:
8337 fc_release_transport(qla2xxx_transport_vport_template);
8338
8339 unreg_chrdev:
8340 if (apidev_major >= 0)
8341 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8342 fc_release_transport(qla2xxx_transport_template);
8343
8344 qlt_exit:
8345 qlt_exit();
8346
8347 destroy_cache:
8348 kmem_cache_destroy(srb_cachep);
8349
8350 qla_trace_uninit();
8351 return ret;
8352 }
8353
8354 /**
8355 * qla2x00_module_exit - Module cleanup.
8356 **/
8357 static void __exit
qla2x00_module_exit(void)8358 qla2x00_module_exit(void)
8359 {
8360 pci_unregister_driver(&qla2xxx_pci_driver);
8361 qla2x00_release_firmware();
8362 kmem_cache_destroy(ctx_cachep);
8363 fc_release_transport(qla2xxx_transport_vport_template);
8364 if (apidev_major >= 0)
8365 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8366 fc_release_transport(qla2xxx_transport_template);
8367 qlt_exit();
8368 kmem_cache_destroy(srb_cachep);
8369 qla_trace_uninit();
8370 }
8371
8372 module_init(qla2x00_module_init);
8373 module_exit(qla2x00_module_exit);
8374
8375 MODULE_AUTHOR("QLogic Corporation");
8376 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
8377 MODULE_LICENSE("GPL");
8378 MODULE_FIRMWARE(FW_FILE_ISP21XX);
8379 MODULE_FIRMWARE(FW_FILE_ISP22XX);
8380 MODULE_FIRMWARE(FW_FILE_ISP2300);
8381 MODULE_FIRMWARE(FW_FILE_ISP2322);
8382 MODULE_FIRMWARE(FW_FILE_ISP24XX);
8383 MODULE_FIRMWARE(FW_FILE_ISP25XX);
8384