1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4 #include <linux/module.h>
5 #include <linux/slab.h>
6 #include <linux/platform_device.h>
7 #include <linux/device.h>
8 #include <linux/delay.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/kernel.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/component.h>
13 #include <sound/tlv.h>
14 #include <linux/of.h>
15 #include <sound/jack.h>
16 #include <sound/pcm.h>
17 #include <sound/pcm_params.h>
18 #include <linux/regmap.h>
19 #include <sound/soc.h>
20 #include <sound/soc-dapm.h>
21 #include <linux/mux/consumer.h>
22 #include <linux/regulator/consumer.h>
23
24 #include "wcd-clsh-v2.h"
25 #include "wcd-mbhc-v2.h"
26 #include "wcd938x.h"
27
28 #define WCD938X_MAX_MICBIAS (4)
29 #define WCD938X_MAX_SUPPLY (4)
30 #define WCD938X_MBHC_MAX_BUTTONS (8)
31 #define TX_ADC_MAX (4)
32
33 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
34 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
35 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
36 /* Fractional Rates */
37 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
38 SNDRV_PCM_RATE_176400)
39 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
40 SNDRV_PCM_FMTBIT_S24_LE)
41 #define SWR_CLK_RATE_0P6MHZ (600000)
42 #define SWR_CLK_RATE_1P2MHZ (1200000)
43 #define SWR_CLK_RATE_2P4MHZ (2400000)
44 #define SWR_CLK_RATE_4P8MHZ (4800000)
45 #define SWR_CLK_RATE_9P6MHZ (9600000)
46 #define SWR_CLK_RATE_11P2896MHZ (1128960)
47
48 #define EAR_RX_PATH_AUX (1)
49
50 #define ADC_MODE_VAL_HIFI 0x01
51 #define ADC_MODE_VAL_LO_HIF 0x02
52 #define ADC_MODE_VAL_NORMAL 0x03
53 #define ADC_MODE_VAL_LP 0x05
54 #define ADC_MODE_VAL_ULP1 0x09
55 #define ADC_MODE_VAL_ULP2 0x0B
56
57 /* Z value defined in milliohm */
58 #define WCD938X_ZDET_VAL_32 (32000)
59 #define WCD938X_ZDET_VAL_400 (400000)
60 #define WCD938X_ZDET_VAL_1200 (1200000)
61 #define WCD938X_ZDET_VAL_100K (100000000)
62 /* Z floating defined in ohms */
63 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
64 #define WCD938X_ZDET_NUM_MEASUREMENTS (900)
65 #define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14)
66 #define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF)
67 /* Z value compared in milliOhm */
68 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
69 #define WCD938X_MBHC_ZDET_CONST (86 * 16384)
70 #define WCD_MBHC_HS_V_MAX 1600
71
72 #define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
73 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, snd_soc_get_volsw, \
74 wcd938x_ear_pa_put_gain, tlv_array)
75
76 enum {
77 WCD9380 = 0,
78 WCD9385 = 5,
79 };
80
81 enum {
82 /* INTR_CTRL_INT_MASK_0 */
83 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
84 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET,
85 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
86 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
87 WCD938X_IRQ_MBHC_SW_DET,
88 WCD938X_IRQ_HPHR_OCP_INT,
89 WCD938X_IRQ_HPHR_CNP_INT,
90 WCD938X_IRQ_HPHL_OCP_INT,
91
92 /* INTR_CTRL_INT_MASK_1 */
93 WCD938X_IRQ_HPHL_CNP_INT,
94 WCD938X_IRQ_EAR_CNP_INT,
95 WCD938X_IRQ_EAR_SCD_INT,
96 WCD938X_IRQ_AUX_CNP_INT,
97 WCD938X_IRQ_AUX_SCD_INT,
98 WCD938X_IRQ_HPHL_PDM_WD_INT,
99 WCD938X_IRQ_HPHR_PDM_WD_INT,
100 WCD938X_IRQ_AUX_PDM_WD_INT,
101
102 /* INTR_CTRL_INT_MASK_2 */
103 WCD938X_IRQ_LDORT_SCD_INT,
104 WCD938X_IRQ_MBHC_MOISTURE_INT,
105 WCD938X_IRQ_HPHL_SURGE_DET_INT,
106 WCD938X_IRQ_HPHR_SURGE_DET_INT,
107 WCD938X_NUM_IRQS,
108 };
109
110 enum {
111 WCD_ADC1 = 0,
112 WCD_ADC2,
113 WCD_ADC3,
114 WCD_ADC4,
115 ALLOW_BUCK_DISABLE,
116 HPH_COMP_DELAY,
117 HPH_PA_DELAY,
118 AMIC2_BCS_ENABLE,
119 WCD_SUPPLIES_LPM_MODE,
120 };
121
122 enum {
123 ADC_MODE_INVALID = 0,
124 ADC_MODE_HIFI,
125 ADC_MODE_LO_HIF,
126 ADC_MODE_NORMAL,
127 ADC_MODE_LP,
128 ADC_MODE_ULP1,
129 ADC_MODE_ULP2,
130 };
131
132 enum {
133 AIF1_PB = 0,
134 AIF1_CAP,
135 NUM_CODEC_DAIS,
136 };
137
138 static u8 tx_mode_bit[] = {
139 [ADC_MODE_INVALID] = 0x00,
140 [ADC_MODE_HIFI] = 0x01,
141 [ADC_MODE_LO_HIF] = 0x02,
142 [ADC_MODE_NORMAL] = 0x04,
143 [ADC_MODE_LP] = 0x08,
144 [ADC_MODE_ULP1] = 0x10,
145 [ADC_MODE_ULP2] = 0x20,
146 };
147
148 struct wcd938x_priv {
149 struct sdw_slave *tx_sdw_dev;
150 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
151 struct device *txdev;
152 struct device *rxdev;
153 struct device_node *rxnode, *txnode;
154 struct regmap *regmap;
155 struct mutex micb_lock;
156 /* mbhc module */
157 struct wcd_mbhc *wcd_mbhc;
158 struct wcd_mbhc_config mbhc_cfg;
159 struct wcd_mbhc_intr intr_ids;
160 struct wcd_clsh_ctrl *clsh_info;
161 struct irq_domain *virq;
162 struct regmap_irq_chip *wcd_regmap_irq_chip;
163 struct regmap_irq_chip_data *irq_chip;
164 struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY];
165 struct snd_soc_jack *jack;
166 unsigned long status_mask;
167 s32 micb_ref[WCD938X_MAX_MICBIAS];
168 s32 pullup_ref[WCD938X_MAX_MICBIAS];
169 u32 hph_mode;
170 u32 tx_mode[TX_ADC_MAX];
171 int flyback_cur_det_disable;
172 int ear_rx_path;
173 int variant;
174 struct gpio_desc *reset_gpio;
175 struct gpio_desc *us_euro_gpio;
176 struct mux_control *us_euro_mux;
177 unsigned int mux_state;
178 u32 micb1_mv;
179 u32 micb2_mv;
180 u32 micb3_mv;
181 u32 micb4_mv;
182 int hphr_pdm_wd_int;
183 int hphl_pdm_wd_int;
184 int aux_pdm_wd_int;
185 bool comp1_enable;
186 bool comp2_enable;
187 bool ldoh;
188 bool mux_setup_done;
189 };
190
191 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
192 static const DECLARE_TLV_DB_SCALE(line_gain, -3000, 150, 0);
193 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
194
195 struct wcd938x_mbhc_zdet_param {
196 u16 ldo_ctl;
197 u16 noff;
198 u16 nshift;
199 u16 btn5;
200 u16 btn6;
201 u16 btn7;
202 };
203
204 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
205 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80),
206 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40),
207 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20),
208 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
209 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08),
210 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
211 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04),
212 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10),
213 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08),
214 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01),
215 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06),
216 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80),
217 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
218 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03),
219 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03),
220 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08),
221 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
222 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20),
223 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80),
224 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40),
225 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10),
226 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07),
227 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70),
228 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF),
229 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0),
230 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF),
231 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40),
232 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80),
233 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0),
234 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
235 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02),
236 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01),
237 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70),
238 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20),
239 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40),
240 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10),
241 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01),
242 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01),
243 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80),
244 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20),
245 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08),
246 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40),
247 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80),
248 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF),
249 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F),
250 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10),
251 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04),
252 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02),
253 };
254
255 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
256 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
257 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
258 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
259 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
260 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
261 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
262 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
263 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
264 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
265 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
266 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
267 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
268 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
269 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
270 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
271 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
272 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
273 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
274 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
275 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
276 };
277
278 static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
279 .name = "wcd938x",
280 .irqs = wcd938x_irqs,
281 .num_irqs = ARRAY_SIZE(wcd938x_irqs),
282 .num_regs = 3,
283 .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
284 .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
285 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
286 .use_ack = 1,
287 .runtime_pm = true,
288 .irq_drv_data = NULL,
289 };
290
wcd938x_get_clk_rate(int mode)291 static int wcd938x_get_clk_rate(int mode)
292 {
293 int rate;
294
295 switch (mode) {
296 case ADC_MODE_ULP2:
297 rate = SWR_CLK_RATE_0P6MHZ;
298 break;
299 case ADC_MODE_ULP1:
300 rate = SWR_CLK_RATE_1P2MHZ;
301 break;
302 case ADC_MODE_LP:
303 rate = SWR_CLK_RATE_4P8MHZ;
304 break;
305 case ADC_MODE_NORMAL:
306 case ADC_MODE_LO_HIF:
307 case ADC_MODE_HIFI:
308 case ADC_MODE_INVALID:
309 default:
310 rate = SWR_CLK_RATE_9P6MHZ;
311 break;
312 }
313
314 return rate;
315 }
316
wcd938x_set_swr_clk_rate(struct snd_soc_component * component,int rate,int bank)317 static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)
318 {
319 u8 mask = (bank ? 0xF0 : 0x0F);
320 u8 val = 0;
321
322 switch (rate) {
323 case SWR_CLK_RATE_0P6MHZ:
324 val = (bank ? 0x60 : 0x06);
325 break;
326 case SWR_CLK_RATE_1P2MHZ:
327 val = (bank ? 0x50 : 0x05);
328 break;
329 case SWR_CLK_RATE_2P4MHZ:
330 val = (bank ? 0x30 : 0x03);
331 break;
332 case SWR_CLK_RATE_4P8MHZ:
333 val = (bank ? 0x10 : 0x01);
334 break;
335 case SWR_CLK_RATE_9P6MHZ:
336 default:
337 val = 0x00;
338 break;
339 }
340 snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE,
341 mask, val);
342
343 return 0;
344 }
345
wcd938x_io_init(struct wcd938x_priv * wcd938x)346 static int wcd938x_io_init(struct wcd938x_priv *wcd938x)
347 {
348 struct regmap *rm = wcd938x->regmap;
349
350 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
351 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80);
352 /* 1 msec delay as per HW requirement */
353 usleep_range(1000, 1010);
354 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40);
355 /* 1 msec delay as per HW requirement */
356 usleep_range(1000, 1010);
357 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00);
358 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ,
359 0xF0, 0x80);
360 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80);
361 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40);
362 /* 10 msec delay as per HW requirement */
363 usleep_range(10000, 10010);
364
365 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00);
366 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
367 0xF0, 0x00);
368 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
369 0x1F, 0x15);
370 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
371 0x1F, 0x15);
372 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL,
373 0xC0, 0x80);
374 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL,
375 0x02, 0x02);
376
377 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
378 0xFF, 0x14);
379 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
380 0x1F, 0x08);
381
382 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
383 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
384 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
385 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
386 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
387
388 /* Set Noise Filter Resistor value */
389 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
390 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
391 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
392 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
393
394 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
395 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
396
397 return 0;
398
399 }
400
wcd938x_sdw_connect_port(const struct wcd938x_sdw_ch_info * ch_info,struct sdw_port_config * port_config,u8 enable)401 static int wcd938x_sdw_connect_port(const struct wcd938x_sdw_ch_info *ch_info,
402 struct sdw_port_config *port_config,
403 u8 enable)
404 {
405 u8 ch_mask, port_num;
406
407 port_num = ch_info->port_num;
408 ch_mask = ch_info->ch_mask;
409
410 port_config->num = port_num;
411
412 if (enable)
413 port_config->ch_mask |= ch_mask;
414 else
415 port_config->ch_mask &= ~ch_mask;
416
417 return 0;
418 }
419
wcd938x_connect_port(struct wcd938x_sdw_priv * wcd,u8 port_num,u8 ch_id,u8 enable)420 static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable)
421 {
422 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id],
423 &wcd->port_config[port_num - 1],
424 enable);
425 }
426
wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)427 static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
428 struct snd_kcontrol *kcontrol,
429 int event)
430 {
431 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
432
433 switch (event) {
434 case SND_SOC_DAPM_PRE_PMU:
435 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
436 WCD938X_ANA_RX_CLK_EN_MASK, 1);
437 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
438 WCD938X_RX_BIAS_EN_MASK, 1);
439 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL,
440 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
441 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL,
442 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
443 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL,
444 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
445 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
446 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1);
447 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA,
448 WCD938X_AUXPA_CLK_EN_MASK, 1);
449 break;
450 case SND_SOC_DAPM_POST_PMD:
451 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
452 WCD938X_VNEG_EN_MASK, 0);
453 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
454 WCD938X_VPOS_EN_MASK, 0);
455 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
456 WCD938X_RX_BIAS_EN_MASK, 0);
457 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
458 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0);
459 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
460 WCD938X_ANA_RX_CLK_EN_MASK, 0);
461 break;
462 }
463 return 0;
464 }
465
wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)466 static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
467 struct snd_kcontrol *kcontrol,
468 int event)
469 {
470 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
471 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
472
473 switch (event) {
474 case SND_SOC_DAPM_PRE_PMU:
475 snd_soc_component_write_field(component,
476 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
477 WCD938X_RXD0_CLK_EN_MASK, 0x01);
478 snd_soc_component_write_field(component,
479 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
480 WCD938X_HPHL_RX_EN_MASK, 1);
481 snd_soc_component_write_field(component,
482 WCD938X_HPH_RDAC_CLK_CTL1,
483 WCD938X_CHOP_CLK_EN_MASK, 0);
484 break;
485 case SND_SOC_DAPM_POST_PMU:
486 snd_soc_component_write_field(component,
487 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,
488 WCD938X_HPH_RES_DIV_MASK, 0x02);
489 if (wcd938x->comp1_enable) {
490 snd_soc_component_write_field(component,
491 WCD938X_DIGITAL_CDC_COMP_CTL_0,
492 WCD938X_HPHL_COMP_EN_MASK, 1);
493 /* 5msec compander delay as per HW requirement */
494 if (!wcd938x->comp2_enable || (snd_soc_component_read(component,
495 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
496 usleep_range(5000, 5010);
497 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
498 WCD938X_AUTOCHOP_TIMER_EN, 0);
499 } else {
500 snd_soc_component_write_field(component,
501 WCD938X_DIGITAL_CDC_COMP_CTL_0,
502 WCD938X_HPHL_COMP_EN_MASK, 0);
503 snd_soc_component_write_field(component,
504 WCD938X_HPH_L_EN,
505 WCD938X_GAIN_SRC_SEL_MASK,
506 WCD938X_GAIN_SRC_SEL_REGISTER);
507
508 }
509 break;
510 case SND_SOC_DAPM_POST_PMD:
511 snd_soc_component_write_field(component,
512 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
513 WCD938X_HPH_RES_DIV_MASK, 0x1);
514 break;
515 }
516
517 return 0;
518 }
519
wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)520 static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
521 struct snd_kcontrol *kcontrol,
522 int event)
523 {
524 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
525 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
526
527 switch (event) {
528 case SND_SOC_DAPM_PRE_PMU:
529 snd_soc_component_write_field(component,
530 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
531 WCD938X_RXD1_CLK_EN_MASK, 1);
532 snd_soc_component_write_field(component,
533 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
534 WCD938X_HPHR_RX_EN_MASK, 1);
535 snd_soc_component_write_field(component,
536 WCD938X_HPH_RDAC_CLK_CTL1,
537 WCD938X_CHOP_CLK_EN_MASK, 0);
538 break;
539 case SND_SOC_DAPM_POST_PMU:
540 snd_soc_component_write_field(component,
541 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
542 WCD938X_HPH_RES_DIV_MASK, 0x02);
543 if (wcd938x->comp2_enable) {
544 snd_soc_component_write_field(component,
545 WCD938X_DIGITAL_CDC_COMP_CTL_0,
546 WCD938X_HPHR_COMP_EN_MASK, 1);
547 /* 5msec compander delay as per HW requirement */
548 if (!wcd938x->comp1_enable ||
549 (snd_soc_component_read(component,
550 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
551 usleep_range(5000, 5010);
552 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
553 WCD938X_AUTOCHOP_TIMER_EN, 0);
554 } else {
555 snd_soc_component_write_field(component,
556 WCD938X_DIGITAL_CDC_COMP_CTL_0,
557 WCD938X_HPHR_COMP_EN_MASK, 0);
558 snd_soc_component_write_field(component,
559 WCD938X_HPH_R_EN,
560 WCD938X_GAIN_SRC_SEL_MASK,
561 WCD938X_GAIN_SRC_SEL_REGISTER);
562 }
563 break;
564 case SND_SOC_DAPM_POST_PMD:
565 snd_soc_component_write_field(component,
566 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
567 WCD938X_HPH_RES_DIV_MASK, 0x01);
568 break;
569 }
570
571 return 0;
572 }
573
wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)574 static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
575 struct snd_kcontrol *kcontrol,
576 int event)
577 {
578 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
579 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
580
581 switch (event) {
582 case SND_SOC_DAPM_PRE_PMU:
583 wcd938x->ear_rx_path =
584 snd_soc_component_read(
585 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
586 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
587 snd_soc_component_write_field(component,
588 WCD938X_EAR_EAR_DAC_CON,
589 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0);
590 snd_soc_component_write_field(component,
591 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
592 WCD938X_AUX_EN_MASK, 1);
593 snd_soc_component_write_field(component,
594 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
595 WCD938X_RXD2_CLK_EN_MASK, 1);
596 snd_soc_component_write_field(component,
597 WCD938X_ANA_EAR_COMPANDER_CTL,
598 WCD938X_GAIN_OVRD_REG_MASK, 1);
599 } else {
600 snd_soc_component_write_field(component,
601 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
602 WCD938X_HPHL_RX_EN_MASK, 1);
603 snd_soc_component_write_field(component,
604 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
605 WCD938X_RXD0_CLK_EN_MASK, 1);
606 if (wcd938x->comp1_enable)
607 snd_soc_component_write_field(component,
608 WCD938X_DIGITAL_CDC_COMP_CTL_0,
609 WCD938X_HPHL_COMP_EN_MASK, 1);
610 }
611 /* 5 msec delay as per HW requirement */
612 usleep_range(5000, 5010);
613 if (wcd938x->flyback_cur_det_disable == 0)
614 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
615 WCD938X_EN_CUR_DET_MASK, 0);
616 wcd938x->flyback_cur_det_disable++;
617 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
618 WCD_CLSH_EVENT_PRE_DAC,
619 WCD_CLSH_STATE_EAR,
620 wcd938x->hph_mode);
621 break;
622 case SND_SOC_DAPM_POST_PMD:
623 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
624 snd_soc_component_write_field(component,
625 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
626 WCD938X_AUX_EN_MASK, 0);
627 snd_soc_component_write_field(component,
628 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
629 WCD938X_RXD2_CLK_EN_MASK, 0);
630 } else {
631 snd_soc_component_write_field(component,
632 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
633 WCD938X_HPHL_RX_EN_MASK, 0);
634 snd_soc_component_write_field(component,
635 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
636 WCD938X_RXD0_CLK_EN_MASK, 0);
637 if (wcd938x->comp1_enable)
638 snd_soc_component_write_field(component,
639 WCD938X_DIGITAL_CDC_COMP_CTL_0,
640 WCD938X_HPHL_COMP_EN_MASK, 0);
641 }
642 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
643 WCD938X_GAIN_OVRD_REG_MASK, 0);
644 snd_soc_component_write_field(component,
645 WCD938X_EAR_EAR_DAC_CON,
646 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1);
647 break;
648 }
649 return 0;
650
651 }
652
wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)653 static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
654 struct snd_kcontrol *kcontrol,
655 int event)
656 {
657 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
658 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
659
660 switch (event) {
661 case SND_SOC_DAPM_PRE_PMU:
662 snd_soc_component_write_field(component,
663 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
664 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1);
665 snd_soc_component_write_field(component,
666 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
667 WCD938X_RXD2_CLK_EN_MASK, 1);
668 snd_soc_component_write_field(component,
669 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
670 WCD938X_AUX_EN_MASK, 1);
671 if (wcd938x->flyback_cur_det_disable == 0)
672 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
673 WCD938X_EN_CUR_DET_MASK, 0);
674 wcd938x->flyback_cur_det_disable++;
675 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
676 WCD_CLSH_EVENT_PRE_DAC,
677 WCD_CLSH_STATE_AUX,
678 wcd938x->hph_mode);
679 break;
680 case SND_SOC_DAPM_POST_PMD:
681 snd_soc_component_write_field(component,
682 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
683 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0);
684 break;
685 }
686 return 0;
687
688 }
689
wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)690 static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
691 struct snd_kcontrol *kcontrol, int event)
692 {
693 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
694 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
695 int hph_mode = wcd938x->hph_mode;
696
697 switch (event) {
698 case SND_SOC_DAPM_PRE_PMU:
699 if (wcd938x->ldoh)
700 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
701 WCD938X_LDOH_EN_MASK, 1);
702 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
703 WCD_CLSH_STATE_HPHR, hph_mode);
704 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
705
706 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
707 hph_mode == CLS_H_ULP) {
708 snd_soc_component_write_field(component,
709 WCD938X_HPH_REFBUFF_LP_CTL,
710 WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
711 }
712 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
713 WCD938X_HPHR_REF_EN_MASK, 1);
714 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
715 /* 100 usec delay as per HW requirement */
716 usleep_range(100, 110);
717 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
718 snd_soc_component_write_field(component,
719 WCD938X_DIGITAL_PDM_WD_CTL1,
720 WCD938X_PDM_WD_EN_MASK, 0x3);
721 break;
722 case SND_SOC_DAPM_POST_PMU:
723 /*
724 * 7ms sleep is required if compander is enabled as per
725 * HW requirement. If compander is disabled, then
726 * 20ms delay is required.
727 */
728 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
729 if (!wcd938x->comp2_enable)
730 usleep_range(20000, 20100);
731 else
732 usleep_range(7000, 7100);
733
734 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
735 hph_mode == CLS_H_ULP)
736 snd_soc_component_write_field(component,
737 WCD938X_HPH_REFBUFF_LP_CTL,
738 WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
739 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
740 }
741 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
742 WCD938X_AUTOCHOP_TIMER_EN, 1);
743 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
744 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
745 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
746 WCD938X_REGULATOR_MODE_MASK,
747 WCD938X_REGULATOR_MODE_CLASS_AB);
748 enable_irq(wcd938x->hphr_pdm_wd_int);
749 break;
750 case SND_SOC_DAPM_PRE_PMD:
751 disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
752 /*
753 * 7ms sleep is required if compander is enabled as per
754 * HW requirement. If compander is disabled, then
755 * 20ms delay is required.
756 */
757 if (!wcd938x->comp2_enable)
758 usleep_range(20000, 20100);
759 else
760 usleep_range(7000, 7100);
761 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
762 WCD938X_HPHR_EN_MASK, 0);
763 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
764 WCD_EVENT_PRE_HPHR_PA_OFF);
765 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
766 break;
767 case SND_SOC_DAPM_POST_PMD:
768 /*
769 * 7ms sleep is required if compander is enabled as per
770 * HW requirement. If compander is disabled, then
771 * 20ms delay is required.
772 */
773 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
774 if (!wcd938x->comp2_enable)
775 usleep_range(20000, 20100);
776 else
777 usleep_range(7000, 7100);
778 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
779 }
780 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
781 WCD_EVENT_POST_HPHR_PA_OFF);
782 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
783 WCD938X_HPHR_REF_EN_MASK, 0);
784 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1,
785 WCD938X_PDM_WD_EN_MASK, 0);
786 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
787 WCD_CLSH_STATE_HPHR, hph_mode);
788 if (wcd938x->ldoh)
789 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
790 WCD938X_LDOH_EN_MASK, 0);
791 break;
792 }
793
794 return 0;
795 }
796
wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)797 static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
798 struct snd_kcontrol *kcontrol, int event)
799 {
800 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
801 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
802 int hph_mode = wcd938x->hph_mode;
803
804 switch (event) {
805 case SND_SOC_DAPM_PRE_PMU:
806 if (wcd938x->ldoh)
807 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
808 WCD938X_LDOH_EN_MASK, 1);
809 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
810 WCD_CLSH_STATE_HPHL, hph_mode);
811 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
812 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
813 hph_mode == CLS_H_ULP) {
814 snd_soc_component_write_field(component,
815 WCD938X_HPH_REFBUFF_LP_CTL,
816 WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
817 }
818 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
819 WCD938X_HPHL_REF_EN_MASK, 1);
820 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
821 /* 100 usec delay as per HW requirement */
822 usleep_range(100, 110);
823 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
824 snd_soc_component_write_field(component,
825 WCD938X_DIGITAL_PDM_WD_CTL0,
826 WCD938X_PDM_WD_EN_MASK, 0x3);
827 break;
828 case SND_SOC_DAPM_POST_PMU:
829 /*
830 * 7ms sleep is required if compander is enabled as per
831 * HW requirement. If compander is disabled, then
832 * 20ms delay is required.
833 */
834 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
835 if (!wcd938x->comp1_enable)
836 usleep_range(20000, 20100);
837 else
838 usleep_range(7000, 7100);
839 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
840 hph_mode == CLS_H_ULP)
841 snd_soc_component_write_field(component,
842 WCD938X_HPH_REFBUFF_LP_CTL,
843 WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
844 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
845 }
846
847 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
848 WCD938X_AUTOCHOP_TIMER_EN, 1);
849 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
850 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
851 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
852 WCD938X_REGULATOR_MODE_MASK,
853 WCD938X_REGULATOR_MODE_CLASS_AB);
854 enable_irq(wcd938x->hphl_pdm_wd_int);
855 break;
856 case SND_SOC_DAPM_PRE_PMD:
857 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
858 /*
859 * 7ms sleep is required if compander is enabled as per
860 * HW requirement. If compander is disabled, then
861 * 20ms delay is required.
862 */
863 if (!wcd938x->comp1_enable)
864 usleep_range(20000, 20100);
865 else
866 usleep_range(7000, 7100);
867 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
868 WCD938X_HPHL_EN_MASK, 0);
869 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
870 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
871 break;
872 case SND_SOC_DAPM_POST_PMD:
873 /*
874 * 7ms sleep is required if compander is enabled as per
875 * HW requirement. If compander is disabled, then
876 * 20ms delay is required.
877 */
878 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
879 if (!wcd938x->comp1_enable)
880 usleep_range(21000, 21100);
881 else
882 usleep_range(7000, 7100);
883 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
884 }
885 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
886 WCD_EVENT_POST_HPHL_PA_OFF);
887 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
888 WCD938X_HPHL_REF_EN_MASK, 0);
889 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
890 WCD938X_PDM_WD_EN_MASK, 0);
891 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
892 WCD_CLSH_STATE_HPHL, hph_mode);
893 if (wcd938x->ldoh)
894 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
895 WCD938X_LDOH_EN_MASK, 0);
896 break;
897 }
898
899 return 0;
900 }
901
wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)902 static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
903 struct snd_kcontrol *kcontrol, int event)
904 {
905 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
906 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
907 int hph_mode = wcd938x->hph_mode;
908
909 switch (event) {
910 case SND_SOC_DAPM_PRE_PMU:
911 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
912 WCD938X_AUX_PDM_WD_EN_MASK, 1);
913 break;
914 case SND_SOC_DAPM_POST_PMU:
915 /* 1 msec delay as per HW requirement */
916 usleep_range(1000, 1010);
917 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
918 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
919 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
920 WCD938X_REGULATOR_MODE_MASK,
921 WCD938X_REGULATOR_MODE_CLASS_AB);
922 enable_irq(wcd938x->aux_pdm_wd_int);
923 break;
924 case SND_SOC_DAPM_PRE_PMD:
925 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
926 break;
927 case SND_SOC_DAPM_POST_PMD:
928 /* 1 msec delay as per HW requirement */
929 usleep_range(1000, 1010);
930 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
931 WCD938X_AUX_PDM_WD_EN_MASK, 0);
932 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
933 WCD_CLSH_EVENT_POST_PA,
934 WCD_CLSH_STATE_AUX,
935 hph_mode);
936
937 wcd938x->flyback_cur_det_disable--;
938 if (wcd938x->flyback_cur_det_disable == 0)
939 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
940 WCD938X_EN_CUR_DET_MASK, 1);
941 break;
942 }
943 return 0;
944 }
945
wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)946 static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
947 struct snd_kcontrol *kcontrol, int event)
948 {
949 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
950 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
951 int hph_mode = wcd938x->hph_mode;
952
953 switch (event) {
954 case SND_SOC_DAPM_PRE_PMU:
955 /*
956 * Enable watchdog interrupt for HPHL or AUX
957 * depending on mux value
958 */
959 wcd938x->ear_rx_path = snd_soc_component_read(component,
960 WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
961 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
962 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
963 WCD938X_AUX_PDM_WD_EN_MASK, 1);
964 else
965 snd_soc_component_write_field(component,
966 WCD938X_DIGITAL_PDM_WD_CTL0,
967 WCD938X_PDM_WD_EN_MASK, 0x3);
968 if (!wcd938x->comp1_enable)
969 snd_soc_component_write_field(component,
970 WCD938X_ANA_EAR_COMPANDER_CTL,
971 WCD938X_GAIN_OVRD_REG_MASK, 1);
972
973 break;
974 case SND_SOC_DAPM_POST_PMU:
975 /* 6 msec delay as per HW requirement */
976 usleep_range(6000, 6010);
977 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
978 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
979 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
980 WCD938X_REGULATOR_MODE_MASK,
981 WCD938X_REGULATOR_MODE_CLASS_AB);
982 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
983 enable_irq(wcd938x->aux_pdm_wd_int);
984 else
985 enable_irq(wcd938x->hphl_pdm_wd_int);
986 break;
987 case SND_SOC_DAPM_PRE_PMD:
988 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
989 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
990 else
991 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
992 break;
993 case SND_SOC_DAPM_POST_PMD:
994 if (!wcd938x->comp1_enable)
995 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
996 WCD938X_GAIN_OVRD_REG_MASK, 0);
997 /* 7 msec delay as per HW requirement */
998 usleep_range(7000, 7010);
999 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1000 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1001 WCD938X_AUX_PDM_WD_EN_MASK, 0);
1002 else
1003 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
1004 WCD938X_PDM_WD_EN_MASK, 0);
1005
1006 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1007 WCD_CLSH_STATE_EAR, hph_mode);
1008
1009 wcd938x->flyback_cur_det_disable--;
1010 if (wcd938x->flyback_cur_det_disable == 0)
1011 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1012 WCD938X_EN_CUR_DET_MASK, 1);
1013 break;
1014 }
1015
1016 return 0;
1017 }
1018
wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1019 static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
1020 struct snd_kcontrol *kcontrol,
1021 int event)
1022 {
1023 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1024 u16 dmic_clk_reg, dmic_clk_en_reg;
1025 u8 dmic_sel_mask, dmic_clk_mask;
1026
1027 switch (w->shift) {
1028 case 0:
1029 case 1:
1030 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
1031 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
1032 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK;
1033 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK;
1034 break;
1035 case 2:
1036 case 3:
1037 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
1038 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
1039 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK;
1040 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK;
1041 break;
1042 case 4:
1043 case 5:
1044 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
1045 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
1046 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK;
1047 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK;
1048 break;
1049 case 6:
1050 case 7:
1051 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
1052 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
1053 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK;
1054 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK;
1055 break;
1056 default:
1057 dev_err(component->dev, "%s: Invalid DMIC Selection\n",
1058 __func__);
1059 return -EINVAL;
1060 }
1061
1062 switch (event) {
1063 case SND_SOC_DAPM_PRE_PMU:
1064 snd_soc_component_write_field(component,
1065 WCD938X_DIGITAL_CDC_AMIC_CTL,
1066 dmic_sel_mask,
1067 WCD938X_AMIC1_IN_SEL_DMIC);
1068 /* 250us sleep as per HW requirement */
1069 usleep_range(250, 260);
1070 /* Setting DMIC clock rate to 2.4MHz */
1071 snd_soc_component_write_field(component, dmic_clk_reg,
1072 dmic_clk_mask,
1073 WCD938X_DMIC4_RATE_2P4MHZ);
1074 snd_soc_component_write_field(component, dmic_clk_en_reg,
1075 WCD938X_DMIC_CLK_EN_MASK, 1);
1076 /* enable clock scaling */
1077 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
1078 WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3);
1079 break;
1080 case SND_SOC_DAPM_POST_PMD:
1081 snd_soc_component_write_field(component,
1082 WCD938X_DIGITAL_CDC_AMIC_CTL,
1083 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC);
1084 snd_soc_component_write_field(component, dmic_clk_en_reg,
1085 WCD938X_DMIC_CLK_EN_MASK, 0);
1086 break;
1087 }
1088 return 0;
1089 }
1090
wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1091 static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
1092 struct snd_kcontrol *kcontrol, int event)
1093 {
1094 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1095 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1096 int bank;
1097 int rate;
1098
1099 bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1;
1100 bank = bank ? 0 : 1;
1101
1102 switch (event) {
1103 case SND_SOC_DAPM_PRE_PMU:
1104 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
1105 int i = 0, mode = 0;
1106
1107 if (test_bit(WCD_ADC1, &wcd938x->status_mask))
1108 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
1109 if (test_bit(WCD_ADC2, &wcd938x->status_mask))
1110 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
1111 if (test_bit(WCD_ADC3, &wcd938x->status_mask))
1112 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
1113 if (test_bit(WCD_ADC4, &wcd938x->status_mask))
1114 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
1115
1116 if (mode != 0) {
1117 for (i = 0; i < ADC_MODE_ULP2; i++) {
1118 if (mode & (1 << i)) {
1119 i++;
1120 break;
1121 }
1122 }
1123 }
1124 rate = wcd938x_get_clk_rate(i);
1125 wcd938x_set_swr_clk_rate(component, rate, bank);
1126 /* Copy clk settings to active bank */
1127 wcd938x_set_swr_clk_rate(component, rate, !bank);
1128 }
1129 break;
1130 case SND_SOC_DAPM_POST_PMD:
1131 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
1132 rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
1133 wcd938x_set_swr_clk_rate(component, rate, !bank);
1134 wcd938x_set_swr_clk_rate(component, rate, bank);
1135 }
1136 break;
1137 }
1138
1139 return 0;
1140 }
1141
wcd938x_get_adc_mode(int val)1142 static int wcd938x_get_adc_mode(int val)
1143 {
1144 int ret = 0;
1145
1146 switch (val) {
1147 case ADC_MODE_INVALID:
1148 ret = ADC_MODE_VAL_NORMAL;
1149 break;
1150 case ADC_MODE_HIFI:
1151 ret = ADC_MODE_VAL_HIFI;
1152 break;
1153 case ADC_MODE_LO_HIF:
1154 ret = ADC_MODE_VAL_LO_HIF;
1155 break;
1156 case ADC_MODE_NORMAL:
1157 ret = ADC_MODE_VAL_NORMAL;
1158 break;
1159 case ADC_MODE_LP:
1160 ret = ADC_MODE_VAL_LP;
1161 break;
1162 case ADC_MODE_ULP1:
1163 ret = ADC_MODE_VAL_ULP1;
1164 break;
1165 case ADC_MODE_ULP2:
1166 ret = ADC_MODE_VAL_ULP2;
1167 break;
1168 default:
1169 ret = -EINVAL;
1170 break;
1171 }
1172 return ret;
1173 }
1174
wcd938x_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1175 static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
1176 struct snd_kcontrol *kcontrol, int event)
1177 {
1178 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1179 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1180
1181 switch (event) {
1182 case SND_SOC_DAPM_PRE_PMU:
1183 snd_soc_component_write_field(component,
1184 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1185 WCD938X_ANA_TX_CLK_EN_MASK, 1);
1186 snd_soc_component_write_field(component,
1187 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1188 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
1189 set_bit(w->shift, &wcd938x->status_mask);
1190 break;
1191 case SND_SOC_DAPM_POST_PMD:
1192 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1193 WCD938X_ANA_TX_CLK_EN_MASK, 0);
1194 clear_bit(w->shift, &wcd938x->status_mask);
1195 break;
1196 }
1197
1198 return 0;
1199 }
1200
wcd938x_tx_channel_config(struct snd_soc_component * component,int channel,int mode)1201 static void wcd938x_tx_channel_config(struct snd_soc_component *component,
1202 int channel, int mode)
1203 {
1204 int reg, mask;
1205
1206 switch (channel) {
1207 case 0:
1208 reg = WCD938X_ANA_TX_CH2;
1209 mask = WCD938X_HPF1_INIT_MASK;
1210 break;
1211 case 1:
1212 reg = WCD938X_ANA_TX_CH2;
1213 mask = WCD938X_HPF2_INIT_MASK;
1214 break;
1215 case 2:
1216 reg = WCD938X_ANA_TX_CH4;
1217 mask = WCD938X_HPF3_INIT_MASK;
1218 break;
1219 case 3:
1220 reg = WCD938X_ANA_TX_CH4;
1221 mask = WCD938X_HPF4_INIT_MASK;
1222 break;
1223 default:
1224 return;
1225 }
1226
1227 snd_soc_component_write_field(component, reg, mask, mode);
1228 }
1229
wcd938x_adc_enable_req(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1230 static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w,
1231 struct snd_kcontrol *kcontrol, int event)
1232 {
1233 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1234 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1235 int mode;
1236
1237 switch (event) {
1238 case SND_SOC_DAPM_PRE_PMU:
1239 snd_soc_component_write_field(component,
1240 WCD938X_DIGITAL_CDC_REQ_CTL,
1241 WCD938X_FS_RATE_4P8_MASK, 1);
1242 snd_soc_component_write_field(component,
1243 WCD938X_DIGITAL_CDC_REQ_CTL,
1244 WCD938X_NO_NOTCH_MASK, 0);
1245 wcd938x_tx_channel_config(component, w->shift, 1);
1246 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
1247 if (mode < 0) {
1248 dev_info(component->dev, "Invalid ADC mode\n");
1249 return -EINVAL;
1250 }
1251 switch (w->shift) {
1252 case 0:
1253 snd_soc_component_write_field(component,
1254 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1255 WCD938X_TXD0_MODE_MASK, mode);
1256 snd_soc_component_write_field(component,
1257 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1258 WCD938X_TXD0_CLK_EN_MASK, 1);
1259 break;
1260 case 1:
1261 snd_soc_component_write_field(component,
1262 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1263 WCD938X_TXD1_MODE_MASK, mode);
1264 snd_soc_component_write_field(component,
1265 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1266 WCD938X_TXD1_CLK_EN_MASK, 1);
1267 break;
1268 case 2:
1269 snd_soc_component_write_field(component,
1270 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1271 WCD938X_TXD2_MODE_MASK, mode);
1272 snd_soc_component_write_field(component,
1273 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1274 WCD938X_TXD2_CLK_EN_MASK, 1);
1275 break;
1276 case 3:
1277 snd_soc_component_write_field(component,
1278 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1279 WCD938X_TXD3_MODE_MASK, mode);
1280 snd_soc_component_write_field(component,
1281 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1282 WCD938X_TXD3_CLK_EN_MASK, 1);
1283 break;
1284 default:
1285 break;
1286 }
1287
1288 wcd938x_tx_channel_config(component, w->shift, 0);
1289 break;
1290 case SND_SOC_DAPM_POST_PMD:
1291 switch (w->shift) {
1292 case 0:
1293 snd_soc_component_write_field(component,
1294 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1295 WCD938X_TXD0_MODE_MASK, 0);
1296 snd_soc_component_write_field(component,
1297 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1298 WCD938X_TXD0_CLK_EN_MASK, 0);
1299 break;
1300 case 1:
1301 snd_soc_component_write_field(component,
1302 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1303 WCD938X_TXD1_MODE_MASK, 0);
1304 snd_soc_component_write_field(component,
1305 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1306 WCD938X_TXD1_CLK_EN_MASK, 0);
1307 break;
1308 case 2:
1309 snd_soc_component_write_field(component,
1310 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1311 WCD938X_TXD2_MODE_MASK, 0);
1312 snd_soc_component_write_field(component,
1313 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1314 WCD938X_TXD2_CLK_EN_MASK, 0);
1315 break;
1316 case 3:
1317 snd_soc_component_write_field(component,
1318 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1319 WCD938X_TXD3_MODE_MASK, 0);
1320 snd_soc_component_write_field(component,
1321 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1322 WCD938X_TXD3_CLK_EN_MASK, 0);
1323 break;
1324 default:
1325 break;
1326 }
1327 snd_soc_component_write_field(component,
1328 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1329 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0);
1330 break;
1331 }
1332
1333 return 0;
1334 }
1335
wcd938x_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)1336 static int wcd938x_micbias_control(struct snd_soc_component *component,
1337 int micb_num, int req, bool is_dapm)
1338 {
1339 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1340 int micb_index = micb_num - 1;
1341 u16 micb_reg;
1342
1343 switch (micb_num) {
1344 case MIC_BIAS_1:
1345 micb_reg = WCD938X_ANA_MICB1;
1346 break;
1347 case MIC_BIAS_2:
1348 micb_reg = WCD938X_ANA_MICB2;
1349 break;
1350 case MIC_BIAS_3:
1351 micb_reg = WCD938X_ANA_MICB3;
1352 break;
1353 case MIC_BIAS_4:
1354 micb_reg = WCD938X_ANA_MICB4;
1355 break;
1356 default:
1357 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
1358 __func__, micb_num);
1359 return -EINVAL;
1360 }
1361
1362 switch (req) {
1363 case MICB_PULLUP_ENABLE:
1364 wcd938x->pullup_ref[micb_index]++;
1365 if ((wcd938x->pullup_ref[micb_index] == 1) &&
1366 (wcd938x->micb_ref[micb_index] == 0))
1367 snd_soc_component_write_field(component, micb_reg,
1368 WCD938X_MICB_EN_MASK,
1369 WCD938X_MICB_PULL_UP);
1370 break;
1371 case MICB_PULLUP_DISABLE:
1372 if (wcd938x->pullup_ref[micb_index] > 0)
1373 wcd938x->pullup_ref[micb_index]--;
1374
1375 if ((wcd938x->pullup_ref[micb_index] == 0) &&
1376 (wcd938x->micb_ref[micb_index] == 0))
1377 snd_soc_component_write_field(component, micb_reg,
1378 WCD938X_MICB_EN_MASK, 0);
1379 break;
1380 case MICB_ENABLE:
1381 wcd938x->micb_ref[micb_index]++;
1382 if (wcd938x->micb_ref[micb_index] == 1) {
1383 snd_soc_component_write_field(component,
1384 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1385 WCD938X_TX_CLK_EN_MASK, 0xF);
1386 snd_soc_component_write_field(component,
1387 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1388 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
1389 snd_soc_component_write_field(component,
1390 WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL,
1391 WCD938X_TX_SC_CLK_EN_MASK, 1);
1392
1393 snd_soc_component_write_field(component, micb_reg,
1394 WCD938X_MICB_EN_MASK,
1395 WCD938X_MICB_ENABLE);
1396 if (micb_num == MIC_BIAS_2)
1397 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1398 WCD_EVENT_POST_MICBIAS_2_ON);
1399 }
1400 if (micb_num == MIC_BIAS_2 && is_dapm)
1401 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1402 WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
1403
1404
1405 break;
1406 case MICB_DISABLE:
1407 if (wcd938x->micb_ref[micb_index] > 0)
1408 wcd938x->micb_ref[micb_index]--;
1409
1410 if ((wcd938x->micb_ref[micb_index] == 0) &&
1411 (wcd938x->pullup_ref[micb_index] > 0))
1412 snd_soc_component_write_field(component, micb_reg,
1413 WCD938X_MICB_EN_MASK,
1414 WCD938X_MICB_PULL_UP);
1415 else if ((wcd938x->micb_ref[micb_index] == 0) &&
1416 (wcd938x->pullup_ref[micb_index] == 0)) {
1417 if (micb_num == MIC_BIAS_2)
1418 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1419 WCD_EVENT_PRE_MICBIAS_2_OFF);
1420
1421 snd_soc_component_write_field(component, micb_reg,
1422 WCD938X_MICB_EN_MASK, 0);
1423 if (micb_num == MIC_BIAS_2)
1424 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1425 WCD_EVENT_POST_MICBIAS_2_OFF);
1426 }
1427 if (is_dapm && micb_num == MIC_BIAS_2)
1428 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1429 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
1430 break;
1431 }
1432
1433 return 0;
1434 }
1435
wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1436 static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
1437 struct snd_kcontrol *kcontrol,
1438 int event)
1439 {
1440 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1441 int micb_num = w->shift;
1442
1443 switch (event) {
1444 case SND_SOC_DAPM_PRE_PMU:
1445 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true);
1446 break;
1447 case SND_SOC_DAPM_POST_PMU:
1448 /* 1 msec delay as per HW requirement */
1449 usleep_range(1000, 1100);
1450 break;
1451 case SND_SOC_DAPM_POST_PMD:
1452 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true);
1453 break;
1454 }
1455
1456 return 0;
1457 }
1458
wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1459 static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
1460 struct snd_kcontrol *kcontrol,
1461 int event)
1462 {
1463 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1464 int micb_num = w->shift;
1465
1466 switch (event) {
1467 case SND_SOC_DAPM_PRE_PMU:
1468 wcd938x_micbias_control(component, micb_num,
1469 MICB_PULLUP_ENABLE, true);
1470 break;
1471 case SND_SOC_DAPM_POST_PMU:
1472 /* 1 msec delay as per HW requirement */
1473 usleep_range(1000, 1100);
1474 break;
1475 case SND_SOC_DAPM_POST_PMD:
1476 wcd938x_micbias_control(component, micb_num,
1477 MICB_PULLUP_DISABLE, true);
1478 break;
1479 }
1480
1481 return 0;
1482 }
1483
wcd938x_tx_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1484 static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
1485 struct snd_ctl_elem_value *ucontrol)
1486 {
1487 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1488 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1489 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1490 int path = e->shift_l;
1491
1492 ucontrol->value.enumerated.item[0] = wcd938x->tx_mode[path];
1493
1494 return 0;
1495 }
1496
wcd938x_tx_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1497 static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
1498 struct snd_ctl_elem_value *ucontrol)
1499 {
1500 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1501 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1502 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1503 int path = e->shift_l;
1504
1505 if (wcd938x->tx_mode[path] == ucontrol->value.enumerated.item[0])
1506 return 0;
1507
1508 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0];
1509
1510 return 1;
1511 }
1512
wcd938x_rx_hph_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1513 static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
1514 struct snd_ctl_elem_value *ucontrol)
1515 {
1516 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1517 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1518
1519 ucontrol->value.enumerated.item[0] = wcd938x->hph_mode;
1520
1521 return 0;
1522 }
1523
wcd938x_rx_hph_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1524 static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
1525 struct snd_ctl_elem_value *ucontrol)
1526 {
1527 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1528 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1529
1530 if (wcd938x->hph_mode == ucontrol->value.enumerated.item[0])
1531 return 0;
1532
1533 wcd938x->hph_mode = ucontrol->value.enumerated.item[0];
1534
1535 return 1;
1536 }
1537
wcd938x_ear_pa_put_gain(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1538 static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
1539 struct snd_ctl_elem_value *ucontrol)
1540 {
1541 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1542 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1543
1544 if (wcd938x->comp1_enable) {
1545 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
1546 return -EINVAL;
1547 }
1548
1549 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
1550 WCD938X_EAR_GAIN_MASK,
1551 ucontrol->value.integer.value[0]);
1552
1553 return 1;
1554 }
1555
wcd938x_get_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1556 static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
1557 struct snd_ctl_elem_value *ucontrol)
1558 {
1559
1560 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1561 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1562 struct soc_mixer_control *mc;
1563 bool hphr;
1564
1565 mc = (struct soc_mixer_control *)(kcontrol->private_value);
1566 hphr = mc->shift;
1567
1568 if (hphr)
1569 ucontrol->value.integer.value[0] = wcd938x->comp2_enable;
1570 else
1571 ucontrol->value.integer.value[0] = wcd938x->comp1_enable;
1572
1573 return 0;
1574 }
1575
wcd938x_set_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1576 static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
1577 struct snd_ctl_elem_value *ucontrol)
1578 {
1579 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1580 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1581 struct wcd938x_sdw_priv *wcd;
1582 int value = ucontrol->value.integer.value[0];
1583 int portidx;
1584 struct soc_mixer_control *mc;
1585 bool hphr;
1586
1587 mc = (struct soc_mixer_control *)(kcontrol->private_value);
1588 hphr = mc->shift;
1589
1590 wcd = wcd938x->sdw_priv[AIF1_PB];
1591
1592 if (hphr)
1593 wcd938x->comp2_enable = value;
1594 else
1595 wcd938x->comp1_enable = value;
1596
1597 portidx = wcd->ch_info[mc->reg].port_num;
1598
1599 if (value)
1600 wcd938x_connect_port(wcd, portidx, mc->reg, true);
1601 else
1602 wcd938x_connect_port(wcd, portidx, mc->reg, false);
1603
1604 return 1;
1605 }
1606
wcd938x_ldoh_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1607 static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
1608 struct snd_ctl_elem_value *ucontrol)
1609 {
1610 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1611 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1612
1613 ucontrol->value.integer.value[0] = wcd938x->ldoh;
1614
1615 return 0;
1616 }
1617
wcd938x_ldoh_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1618 static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
1619 struct snd_ctl_elem_value *ucontrol)
1620 {
1621 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1622 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1623
1624 if (wcd938x->ldoh == ucontrol->value.integer.value[0])
1625 return 0;
1626
1627 wcd938x->ldoh = ucontrol->value.integer.value[0];
1628
1629 return 1;
1630 }
1631
1632 static const char * const tx_mode_mux_text_wcd9380[] = {
1633 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
1634 };
1635
1636 static const char * const tx_mode_mux_text[] = {
1637 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
1638 "ADC_ULP1", "ADC_ULP2",
1639 };
1640
1641 static const char * const rx_hph_mode_mux_text_wcd9380[] = {
1642 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
1643 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
1644 "CLS_AB_LOHIFI",
1645 };
1646
1647 static const char * const rx_hph_mode_mux_text[] = {
1648 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
1649 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
1650 };
1651
1652 static const char * const adc2_mux_text[] = {
1653 "INP2", "INP3"
1654 };
1655
1656 static const char * const adc3_mux_text[] = {
1657 "INP4", "INP6"
1658 };
1659
1660 static const char * const adc4_mux_text[] = {
1661 "INP5", "INP7"
1662 };
1663
1664 static const char * const rdac3_mux_text[] = {
1665 "RX1", "RX3"
1666 };
1667
1668 static const char * const hdr12_mux_text[] = {
1669 "NO_HDR12", "HDR12"
1670 };
1671
1672 static const char * const hdr34_mux_text[] = {
1673 "NO_HDR34", "HDR34"
1674 };
1675
1676 static const struct soc_enum tx0_mode_enum_wcd9380 =
1677 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
1678 tx_mode_mux_text_wcd9380);
1679
1680 static const struct soc_enum tx1_mode_enum_wcd9380 =
1681 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
1682 tx_mode_mux_text_wcd9380);
1683
1684 static const struct soc_enum tx2_mode_enum_wcd9380 =
1685 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
1686 tx_mode_mux_text_wcd9380);
1687
1688 static const struct soc_enum tx3_mode_enum_wcd9380 =
1689 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
1690 tx_mode_mux_text_wcd9380);
1691
1692 static const struct soc_enum tx0_mode_enum_wcd9385 =
1693 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
1694 tx_mode_mux_text);
1695
1696 static const struct soc_enum tx1_mode_enum_wcd9385 =
1697 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
1698 tx_mode_mux_text);
1699
1700 static const struct soc_enum tx2_mode_enum_wcd9385 =
1701 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
1702 tx_mode_mux_text);
1703
1704 static const struct soc_enum tx3_mode_enum_wcd9385 =
1705 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
1706 tx_mode_mux_text);
1707
1708 static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
1709 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
1710 rx_hph_mode_mux_text_wcd9380);
1711
1712 static const struct soc_enum rx_hph_mode_mux_enum =
1713 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
1714 rx_hph_mode_mux_text);
1715
1716 static const struct soc_enum adc2_enum =
1717 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
1718 ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
1719
1720 static const struct soc_enum adc3_enum =
1721 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
1722 ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
1723
1724 static const struct soc_enum adc4_enum =
1725 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
1726 ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
1727
1728 static const struct soc_enum hdr12_enum =
1729 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
1730 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
1731
1732 static const struct soc_enum hdr34_enum =
1733 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
1734 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
1735
1736 static const struct soc_enum rdac3_enum =
1737 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
1738 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
1739
1740 static const struct snd_kcontrol_new adc1_switch[] = {
1741 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1742 };
1743
1744 static const struct snd_kcontrol_new adc2_switch[] = {
1745 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1746 };
1747
1748 static const struct snd_kcontrol_new adc3_switch[] = {
1749 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1750 };
1751
1752 static const struct snd_kcontrol_new adc4_switch[] = {
1753 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1754 };
1755
1756 static const struct snd_kcontrol_new dmic1_switch[] = {
1757 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1758 };
1759
1760 static const struct snd_kcontrol_new dmic2_switch[] = {
1761 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1762 };
1763
1764 static const struct snd_kcontrol_new dmic3_switch[] = {
1765 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1766 };
1767
1768 static const struct snd_kcontrol_new dmic4_switch[] = {
1769 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1770 };
1771
1772 static const struct snd_kcontrol_new dmic5_switch[] = {
1773 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1774 };
1775
1776 static const struct snd_kcontrol_new dmic6_switch[] = {
1777 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1778 };
1779
1780 static const struct snd_kcontrol_new dmic7_switch[] = {
1781 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1782 };
1783
1784 static const struct snd_kcontrol_new dmic8_switch[] = {
1785 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1786 };
1787
1788 static const struct snd_kcontrol_new ear_rdac_switch[] = {
1789 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1790 };
1791
1792 static const struct snd_kcontrol_new aux_rdac_switch[] = {
1793 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1794 };
1795
1796 static const struct snd_kcontrol_new hphl_rdac_switch[] = {
1797 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1798 };
1799
1800 static const struct snd_kcontrol_new hphr_rdac_switch[] = {
1801 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1802 };
1803
1804 static const struct snd_kcontrol_new tx_adc2_mux =
1805 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
1806
1807 static const struct snd_kcontrol_new tx_adc3_mux =
1808 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
1809
1810 static const struct snd_kcontrol_new tx_adc4_mux =
1811 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
1812
1813 static const struct snd_kcontrol_new tx_hdr12_mux =
1814 SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
1815
1816 static const struct snd_kcontrol_new tx_hdr34_mux =
1817 SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
1818
1819 static const struct snd_kcontrol_new rx_rdac3_mux =
1820 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
1821
1822 static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
1823 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
1824 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
1825 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380,
1826 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
1827 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380,
1828 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
1829 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380,
1830 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
1831 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380,
1832 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
1833 };
1834
1835 static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
1836 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
1837 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
1838 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385,
1839 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
1840 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385,
1841 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
1842 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385,
1843 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
1844 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385,
1845 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
1846 };
1847
wcd938x_get_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1848 static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol,
1849 struct snd_ctl_elem_value *ucontrol)
1850 {
1851 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1852 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
1853 struct wcd938x_sdw_priv *wcd;
1854 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1855 int dai_id = mixer->shift;
1856 int portidx, ch_idx = mixer->reg;
1857
1858
1859 wcd = wcd938x->sdw_priv[dai_id];
1860 portidx = wcd->ch_info[ch_idx].port_num;
1861
1862 ucontrol->value.integer.value[0] = wcd->port_enable[portidx];
1863
1864 return 0;
1865 }
1866
wcd938x_set_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1867 static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol,
1868 struct snd_ctl_elem_value *ucontrol)
1869 {
1870 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1871 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
1872 struct wcd938x_sdw_priv *wcd;
1873 struct soc_mixer_control *mixer =
1874 (struct soc_mixer_control *)kcontrol->private_value;
1875 int ch_idx = mixer->reg;
1876 int portidx;
1877 int dai_id = mixer->shift;
1878 bool enable;
1879
1880 wcd = wcd938x->sdw_priv[dai_id];
1881
1882 portidx = wcd->ch_info[ch_idx].port_num;
1883 if (ucontrol->value.integer.value[0])
1884 enable = true;
1885 else
1886 enable = false;
1887
1888 wcd->port_enable[portidx] = enable;
1889
1890 wcd938x_connect_port(wcd, portidx, ch_idx, enable);
1891
1892 return 1;
1893
1894 }
1895
1896 /* MBHC related */
wcd938x_mbhc_clk_setup(struct snd_soc_component * component,bool enable)1897 static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component,
1898 bool enable)
1899 {
1900 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1,
1901 WCD938X_MBHC_CTL_RCO_EN_MASK, enable);
1902 }
1903
wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component * component,bool enable)1904 static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
1905 bool enable)
1906 {
1907 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT,
1908 WCD938X_ANA_MBHC_BIAS_EN, enable);
1909 }
1910
wcd938x_mbhc_program_btn_thr(struct snd_soc_component * component,int * btn_low,int * btn_high,int num_btn,bool is_micbias)1911 static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component,
1912 int *btn_low, int *btn_high,
1913 int num_btn, bool is_micbias)
1914 {
1915 int i, vth;
1916
1917 if (num_btn > WCD_MBHC_DEF_BUTTONS) {
1918 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
1919 __func__, num_btn);
1920 return;
1921 }
1922
1923 for (i = 0; i < num_btn; i++) {
1924 vth = ((btn_high[i] * 2) / 25) & 0x3F;
1925 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i,
1926 WCD938X_MBHC_BTN_VTH_MASK, vth);
1927 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
1928 __func__, i, btn_high[i], vth);
1929 }
1930 }
1931
wcd938x_mbhc_micb_en_status(struct snd_soc_component * component,int micb_num)1932 static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
1933 {
1934 u8 val;
1935
1936 if (micb_num == MIC_BIAS_2) {
1937 val = snd_soc_component_read_field(component,
1938 WCD938X_ANA_MICB2,
1939 WCD938X_MICB_EN_MASK);
1940 if (val == WCD938X_MICB_ENABLE)
1941 return true;
1942 }
1943 return false;
1944 }
1945
wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component * component,int pull_up_cur)1946 static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
1947 int pull_up_cur)
1948 {
1949 /* Default pull up current to 2uA */
1950 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA)
1951 pull_up_cur = HS_PULLUP_I_2P0_UA;
1952
1953 snd_soc_component_write_field(component,
1954 WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT,
1955 WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur);
1956 }
1957
wcd938x_mbhc_request_micbias(struct snd_soc_component * component,int micb_num,int req)1958 static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component,
1959 int micb_num, int req)
1960 {
1961 return wcd938x_micbias_control(component, micb_num, req, false);
1962 }
1963
wcd938x_mbhc_micb_ramp_control(struct snd_soc_component * component,bool enable)1964 static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component,
1965 bool enable)
1966 {
1967 if (enable) {
1968 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
1969 WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C);
1970 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
1971 WCD938X_RAMP_EN_MASK, 1);
1972 } else {
1973 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
1974 WCD938X_RAMP_EN_MASK, 0);
1975 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
1976 WCD938X_RAMP_SHIFT_CTRL_MASK, 0);
1977 }
1978 }
1979
wcd938x_get_micb_vout_ctl_val(u32 micb_mv)1980 static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
1981 {
1982 /* min micbias voltage is 1V and maximum is 2.85V */
1983 if (micb_mv < 1000 || micb_mv > 2850)
1984 return -EINVAL;
1985
1986 return (micb_mv - 1000) / 50;
1987 }
1988
wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component * component,int req_volt,int micb_num)1989 static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
1990 int req_volt, int micb_num)
1991 {
1992 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1993 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
1994
1995 switch (micb_num) {
1996 case MIC_BIAS_1:
1997 micb_reg = WCD938X_ANA_MICB1;
1998 break;
1999 case MIC_BIAS_2:
2000 micb_reg = WCD938X_ANA_MICB2;
2001 break;
2002 case MIC_BIAS_3:
2003 micb_reg = WCD938X_ANA_MICB3;
2004 break;
2005 case MIC_BIAS_4:
2006 micb_reg = WCD938X_ANA_MICB4;
2007 break;
2008 default:
2009 return -EINVAL;
2010 }
2011 mutex_lock(&wcd938x->micb_lock);
2012 /*
2013 * If requested micbias voltage is same as current micbias
2014 * voltage, then just return. Otherwise, adjust voltage as
2015 * per requested value. If micbias is already enabled, then
2016 * to avoid slow micbias ramp-up or down enable pull-up
2017 * momentarily, change the micbias value and then re-enable
2018 * micbias.
2019 */
2020 micb_en = snd_soc_component_read_field(component, micb_reg,
2021 WCD938X_MICB_EN_MASK);
2022 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
2023 WCD938X_MICB_VOUT_MASK);
2024
2025 req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
2026 if (req_vout_ctl < 0) {
2027 ret = -EINVAL;
2028 goto exit;
2029 }
2030
2031 if (cur_vout_ctl == req_vout_ctl) {
2032 ret = 0;
2033 goto exit;
2034 }
2035
2036 if (micb_en == WCD938X_MICB_ENABLE)
2037 snd_soc_component_write_field(component, micb_reg,
2038 WCD938X_MICB_EN_MASK,
2039 WCD938X_MICB_PULL_UP);
2040
2041 snd_soc_component_write_field(component, micb_reg,
2042 WCD938X_MICB_VOUT_MASK,
2043 req_vout_ctl);
2044
2045 if (micb_en == WCD938X_MICB_ENABLE) {
2046 snd_soc_component_write_field(component, micb_reg,
2047 WCD938X_MICB_EN_MASK,
2048 WCD938X_MICB_ENABLE);
2049 /*
2050 * Add 2ms delay as per HW requirement after enabling
2051 * micbias
2052 */
2053 usleep_range(2000, 2100);
2054 }
2055 exit:
2056 mutex_unlock(&wcd938x->micb_lock);
2057 return ret;
2058 }
2059
wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component * component,int micb_num,bool req_en)2060 static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
2061 int micb_num, bool req_en)
2062 {
2063 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2064 int micb_mv;
2065
2066 if (micb_num != MIC_BIAS_2)
2067 return -EINVAL;
2068 /*
2069 * If device tree micbias level is already above the minimum
2070 * voltage needed to detect threshold microphone, then do
2071 * not change the micbias, just return.
2072 */
2073 if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
2074 return 0;
2075
2076 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv;
2077
2078 return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
2079 }
2080
wcd938x_mbhc_get_result_params(struct snd_soc_component * component,s16 * d1_a,u16 noff,int32_t * zdet)2081 static void wcd938x_mbhc_get_result_params(struct snd_soc_component *component,
2082 s16 *d1_a, u16 noff,
2083 int32_t *zdet)
2084 {
2085 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2086 int i;
2087 int val, val1;
2088 s16 c1;
2089 s32 x1, d1;
2090 int32_t denom;
2091 static const int minCode_param[] = {
2092 3277, 1639, 820, 410, 205, 103, 52, 26
2093 };
2094
2095 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20);
2096 for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) {
2097 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val);
2098 if (val & 0x80)
2099 break;
2100 }
2101 val = val << 0x8;
2102 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1);
2103 val |= val1;
2104 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00);
2105 x1 = WCD938X_MBHC_GET_X1(val);
2106 c1 = WCD938X_MBHC_GET_C1(val);
2107 /* If ramp is not complete, give additional 5ms */
2108 if ((c1 < 2) && x1)
2109 usleep_range(5000, 5050);
2110
2111 if (!c1 || !x1) {
2112 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n",
2113 c1, x1);
2114 goto ramp_down;
2115 }
2116 d1 = d1_a[c1];
2117 denom = (x1 * d1) - (1 << (14 - noff));
2118 if (denom > 0)
2119 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom;
2120 else if (x1 < minCode_param[noff])
2121 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE;
2122
2123 dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n",
2124 __func__, d1, c1, x1, *zdet);
2125 ramp_down:
2126 i = 0;
2127 while (x1) {
2128 regmap_read(wcd938x->regmap,
2129 WCD938X_ANA_MBHC_RESULT_1, &val);
2130 regmap_read(wcd938x->regmap,
2131 WCD938X_ANA_MBHC_RESULT_2, &val1);
2132 val = val << 0x08;
2133 val |= val1;
2134 x1 = WCD938X_MBHC_GET_X1(val);
2135 i++;
2136 if (i == WCD938X_ZDET_NUM_MEASUREMENTS)
2137 break;
2138 }
2139 }
2140
wcd938x_mbhc_zdet_ramp(struct snd_soc_component * component,struct wcd938x_mbhc_zdet_param * zdet_param,int32_t * zl,int32_t * zr,s16 * d1_a)2141 static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component,
2142 struct wcd938x_mbhc_zdet_param *zdet_param,
2143 int32_t *zl, int32_t *zr, s16 *d1_a)
2144 {
2145 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2146 int32_t zdet = 0;
2147
2148 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
2149 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
2150 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5,
2151 WCD938X_VTH_MASK, zdet_param->btn5);
2152 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6,
2153 WCD938X_VTH_MASK, zdet_param->btn6);
2154 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7,
2155 WCD938X_VTH_MASK, zdet_param->btn7);
2156 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
2157 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
2158 snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL,
2159 0x0F, zdet_param->nshift);
2160
2161 if (!zl)
2162 goto z_right;
2163 /* Start impedance measurement for HPH_L */
2164 regmap_update_bits(wcd938x->regmap,
2165 WCD938X_ANA_MBHC_ZDET, 0x80, 0x80);
2166 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n",
2167 __func__, zdet_param->noff);
2168 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet);
2169 regmap_update_bits(wcd938x->regmap,
2170 WCD938X_ANA_MBHC_ZDET, 0x80, 0x00);
2171
2172 *zl = zdet;
2173
2174 z_right:
2175 if (!zr)
2176 return;
2177 /* Start impedance measurement for HPH_R */
2178 regmap_update_bits(wcd938x->regmap,
2179 WCD938X_ANA_MBHC_ZDET, 0x40, 0x40);
2180 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n",
2181 __func__, zdet_param->noff);
2182 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet);
2183 regmap_update_bits(wcd938x->regmap,
2184 WCD938X_ANA_MBHC_ZDET, 0x40, 0x00);
2185
2186 *zr = zdet;
2187 }
2188
wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component * component,int32_t * z_val,int flag_l_r)2189 static void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
2190 int32_t *z_val, int flag_l_r)
2191 {
2192 s16 q1;
2193 int q1_cal;
2194
2195 if (*z_val < (WCD938X_ZDET_VAL_400/1000))
2196 q1 = snd_soc_component_read(component,
2197 WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r));
2198 else
2199 q1 = snd_soc_component_read(component,
2200 WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r));
2201 if (q1 & 0x80)
2202 q1_cal = (10000 - ((q1 & 0x7F) * 25));
2203 else
2204 q1_cal = (10000 + (q1 * 25));
2205 if (q1_cal > 0)
2206 *z_val = ((*z_val) * 10000) / q1_cal;
2207 }
2208
wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component * component,uint32_t * zl,uint32_t * zr)2209 static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
2210 uint32_t *zl, uint32_t *zr)
2211 {
2212 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2213 s16 reg0, reg1, reg2, reg3, reg4;
2214 int32_t z1L, z1R, z1Ls;
2215 int zMono, z_diff1, z_diff2;
2216 bool is_fsm_disable = false;
2217 struct wcd938x_mbhc_zdet_param zdet_param[] = {
2218 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
2219 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
2220 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
2221 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
2222 };
2223 struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL;
2224 s16 d1_a[][4] = {
2225 {0, 30, 90, 30},
2226 {0, 30, 30, 5},
2227 {0, 30, 30, 5},
2228 {0, 30, 30, 5},
2229 };
2230 s16 *d1 = NULL;
2231
2232 reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5);
2233 reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6);
2234 reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7);
2235 reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK);
2236 reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL);
2237
2238 if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) {
2239 is_fsm_disable = true;
2240 regmap_update_bits(wcd938x->regmap,
2241 WCD938X_ANA_MBHC_ELECT, 0x80, 0x00);
2242 }
2243
2244 /* For NO-jack, disable L_DET_EN before Z-det measurements */
2245 if (wcd938x->mbhc_cfg.hphl_swh)
2246 regmap_update_bits(wcd938x->regmap,
2247 WCD938X_ANA_MBHC_MECH, 0x80, 0x00);
2248
2249 /* Turn off 100k pull down on HPHL */
2250 regmap_update_bits(wcd938x->regmap,
2251 WCD938X_ANA_MBHC_MECH, 0x01, 0x00);
2252
2253 /* Disable surge protection before impedance detection.
2254 * This is done to give correct value for high impedance.
2255 */
2256 regmap_update_bits(wcd938x->regmap,
2257 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00);
2258 /* 1ms delay needed after disable surge protection */
2259 usleep_range(1000, 1010);
2260
2261 /* First get impedance on Left */
2262 d1 = d1_a[1];
2263 zdet_param_ptr = &zdet_param[1];
2264 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2265
2266 if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
2267 goto left_ch_impedance;
2268
2269 /* Second ramp for left ch */
2270 if (z1L < WCD938X_ZDET_VAL_32) {
2271 zdet_param_ptr = &zdet_param[0];
2272 d1 = d1_a[0];
2273 } else if ((z1L > WCD938X_ZDET_VAL_400) &&
2274 (z1L <= WCD938X_ZDET_VAL_1200)) {
2275 zdet_param_ptr = &zdet_param[2];
2276 d1 = d1_a[2];
2277 } else if (z1L > WCD938X_ZDET_VAL_1200) {
2278 zdet_param_ptr = &zdet_param[3];
2279 d1 = d1_a[3];
2280 }
2281 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2282
2283 left_ch_impedance:
2284 if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
2285 (z1L > WCD938X_ZDET_VAL_100K)) {
2286 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE;
2287 zdet_param_ptr = &zdet_param[1];
2288 d1 = d1_a[1];
2289 } else {
2290 *zl = z1L/1000;
2291 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0);
2292 }
2293 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2294 __func__, *zl);
2295
2296 /* Start of right impedance ramp and calculation */
2297 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2298 if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
2299 if (((z1R > WCD938X_ZDET_VAL_1200) &&
2300 (zdet_param_ptr->noff == 0x6)) ||
2301 ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE))
2302 goto right_ch_impedance;
2303 /* Second ramp for right ch */
2304 if (z1R < WCD938X_ZDET_VAL_32) {
2305 zdet_param_ptr = &zdet_param[0];
2306 d1 = d1_a[0];
2307 } else if ((z1R > WCD938X_ZDET_VAL_400) &&
2308 (z1R <= WCD938X_ZDET_VAL_1200)) {
2309 zdet_param_ptr = &zdet_param[2];
2310 d1 = d1_a[2];
2311 } else if (z1R > WCD938X_ZDET_VAL_1200) {
2312 zdet_param_ptr = &zdet_param[3];
2313 d1 = d1_a[3];
2314 }
2315 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2316 }
2317 right_ch_impedance:
2318 if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
2319 (z1R > WCD938X_ZDET_VAL_100K)) {
2320 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE;
2321 } else {
2322 *zr = z1R/1000;
2323 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1);
2324 }
2325 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2326 __func__, *zr);
2327
2328 /* Mono/stereo detection */
2329 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) &&
2330 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) {
2331 dev_dbg(component->dev,
2332 "%s: plug type is invalid or extension cable\n",
2333 __func__);
2334 goto zdet_complete;
2335 }
2336 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
2337 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
2338 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
2339 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
2340 dev_dbg(component->dev,
2341 "%s: Mono plug type with one ch floating or shorted to GND\n",
2342 __func__);
2343 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
2344 goto zdet_complete;
2345 }
2346 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
2347 WCD938X_HPHPA_GND_OVR_MASK, 1);
2348 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
2349 WCD938X_HPHPA_GND_R_MASK, 1);
2350 if (*zl < (WCD938X_ZDET_VAL_32/1000))
2351 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
2352 else
2353 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
2354 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
2355 WCD938X_HPHPA_GND_R_MASK, 0);
2356 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
2357 WCD938X_HPHPA_GND_OVR_MASK, 0);
2358 z1Ls /= 1000;
2359 wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
2360 /* Parallel of left Z and 9 ohm pull down resistor */
2361 zMono = ((*zl) * 9) / ((*zl) + 9);
2362 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
2363 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
2364 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
2365 dev_dbg(component->dev, "%s: stereo plug type detected\n",
2366 __func__);
2367 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
2368 } else {
2369 dev_dbg(component->dev, "%s: MONO plug type detected\n",
2370 __func__);
2371 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
2372 }
2373
2374 /* Enable surge protection again after impedance detection */
2375 regmap_update_bits(wcd938x->regmap,
2376 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
2377 zdet_complete:
2378 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0);
2379 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1);
2380 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2);
2381 /* Turn on 100k pull down on HPHL */
2382 regmap_update_bits(wcd938x->regmap,
2383 WCD938X_ANA_MBHC_MECH, 0x01, 0x01);
2384
2385 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2386 if (wcd938x->mbhc_cfg.hphl_swh)
2387 regmap_update_bits(wcd938x->regmap,
2388 WCD938X_ANA_MBHC_MECH, 0x80, 0x80);
2389
2390 snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4);
2391 snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3);
2392 if (is_fsm_disable)
2393 regmap_update_bits(wcd938x->regmap,
2394 WCD938X_ANA_MBHC_ELECT, 0x80, 0x80);
2395 }
2396
wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component * component,bool enable)2397 static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
2398 bool enable)
2399 {
2400 if (enable) {
2401 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
2402 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1);
2403 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
2404 WCD938X_MBHC_GND_DET_EN_MASK, 1);
2405 } else {
2406 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
2407 WCD938X_MBHC_GND_DET_EN_MASK, 0);
2408 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
2409 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0);
2410 }
2411 }
2412
wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component * component,bool enable)2413 static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
2414 bool enable)
2415 {
2416 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
2417 WCD938X_HPHPA_GND_R_MASK, enable);
2418 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
2419 WCD938X_HPHPA_GND_L_MASK, enable);
2420 }
2421
wcd938x_mbhc_moisture_config(struct snd_soc_component * component)2422 static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component)
2423 {
2424 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2425
2426 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
2427 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
2428 WCD938X_M_RTH_CTL_MASK, R_OFF);
2429 return;
2430 }
2431
2432 /* Do not enable moisture detection if jack type is NC */
2433 if (!wcd938x->mbhc_cfg.hphl_swh) {
2434 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
2435 __func__);
2436 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
2437 WCD938X_M_RTH_CTL_MASK, R_OFF);
2438 return;
2439 }
2440
2441 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
2442 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
2443 }
2444
wcd938x_mbhc_moisture_detect_en(struct snd_soc_component * component,bool enable)2445 static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
2446 {
2447 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2448
2449 if (enable)
2450 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
2451 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
2452 else
2453 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
2454 WCD938X_M_RTH_CTL_MASK, R_OFF);
2455 }
2456
wcd938x_mbhc_get_moisture_status(struct snd_soc_component * component)2457 static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component)
2458 {
2459 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2460 bool ret = false;
2461
2462 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
2463 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
2464 WCD938X_M_RTH_CTL_MASK, R_OFF);
2465 goto done;
2466 }
2467
2468 /* Do not enable moisture detection if jack type is NC */
2469 if (!wcd938x->mbhc_cfg.hphl_swh) {
2470 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
2471 __func__);
2472 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
2473 WCD938X_M_RTH_CTL_MASK, R_OFF);
2474 goto done;
2475 }
2476
2477 /*
2478 * If moisture_en is already enabled, then skip to plug type
2479 * detection.
2480 */
2481 if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK))
2482 goto done;
2483
2484 wcd938x_mbhc_moisture_detect_en(component, true);
2485 /* Read moisture comparator status */
2486 ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS)
2487 & 0x20) ? 0 : 1);
2488
2489 done:
2490 return ret;
2491
2492 }
2493
wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component * component,bool enable)2494 static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
2495 bool enable)
2496 {
2497 snd_soc_component_write_field(component,
2498 WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
2499 WCD938X_MOISTURE_EN_POLLING_MASK, enable);
2500 }
2501
2502 static const struct wcd_mbhc_cb mbhc_cb = {
2503 .clk_setup = wcd938x_mbhc_clk_setup,
2504 .mbhc_bias = wcd938x_mbhc_mbhc_bias_control,
2505 .set_btn_thr = wcd938x_mbhc_program_btn_thr,
2506 .micbias_enable_status = wcd938x_mbhc_micb_en_status,
2507 .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control,
2508 .mbhc_micbias_control = wcd938x_mbhc_request_micbias,
2509 .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control,
2510 .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic,
2511 .compute_impedance = wcd938x_wcd_mbhc_calc_impedance,
2512 .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl,
2513 .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl,
2514 .mbhc_moisture_config = wcd938x_mbhc_moisture_config,
2515 .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status,
2516 .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl,
2517 .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en,
2518 };
2519
wcd938x_get_hph_type(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2520 static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol,
2521 struct snd_ctl_elem_value *ucontrol)
2522 {
2523 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2524 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2525
2526 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc);
2527
2528 return 0;
2529 }
2530
wcd938x_hph_impedance_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2531 static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol,
2532 struct snd_ctl_elem_value *ucontrol)
2533 {
2534 uint32_t zl, zr;
2535 bool hphr;
2536 struct soc_mixer_control *mc;
2537 struct snd_soc_component *component =
2538 snd_soc_kcontrol_component(kcontrol);
2539 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2540
2541 mc = (struct soc_mixer_control *)(kcontrol->private_value);
2542 hphr = mc->shift;
2543 wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr);
2544 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
2545 ucontrol->value.integer.value[0] = hphr ? zr : zl;
2546
2547 return 0;
2548 }
2549
2550 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
2551 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
2552 wcd938x_get_hph_type, NULL),
2553 };
2554
2555 static const struct snd_kcontrol_new impedance_detect_controls[] = {
2556 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
2557 wcd938x_hph_impedance_get, NULL),
2558 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
2559 wcd938x_hph_impedance_get, NULL),
2560 };
2561
wcd938x_mbhc_init(struct snd_soc_component * component)2562 static int wcd938x_mbhc_init(struct snd_soc_component *component)
2563 {
2564 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2565 struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids;
2566
2567 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip,
2568 WCD938X_IRQ_MBHC_SW_DET);
2569 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip,
2570 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET);
2571 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip,
2572 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET);
2573 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip,
2574 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
2575 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip,
2576 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET);
2577 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
2578 WCD938X_IRQ_HPHL_OCP_INT);
2579 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
2580 WCD938X_IRQ_HPHR_OCP_INT);
2581
2582 wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
2583 if (IS_ERR(wcd938x->wcd_mbhc))
2584 return PTR_ERR(wcd938x->wcd_mbhc);
2585
2586 snd_soc_add_component_controls(component, impedance_detect_controls,
2587 ARRAY_SIZE(impedance_detect_controls));
2588 snd_soc_add_component_controls(component, hph_type_detect_controls,
2589 ARRAY_SIZE(hph_type_detect_controls));
2590
2591 return 0;
2592 }
2593
wcd938x_mbhc_deinit(struct snd_soc_component * component)2594 static void wcd938x_mbhc_deinit(struct snd_soc_component *component)
2595 {
2596 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2597
2598 wcd_mbhc_deinit(wcd938x->wcd_mbhc);
2599 }
2600
2601 /* END MBHC */
2602
2603 static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
2604 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0,
2605 wcd938x_get_compander, wcd938x_set_compander),
2606 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0,
2607 wcd938x_get_compander, wcd938x_set_compander),
2608 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0,
2609 wcd938x_get_swr_port, wcd938x_set_swr_port),
2610 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0,
2611 wcd938x_get_swr_port, wcd938x_set_swr_port),
2612 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0,
2613 wcd938x_get_swr_port, wcd938x_set_swr_port),
2614 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0,
2615 wcd938x_get_swr_port, wcd938x_set_swr_port),
2616 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0,
2617 wcd938x_get_swr_port, wcd938x_set_swr_port),
2618 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0,
2619 wcd938x_get_swr_port, wcd938x_set_swr_port),
2620 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 1, line_gain),
2621 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 1, line_gain),
2622 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL,
2623 2, 0x10, 0, ear_pa_gain),
2624 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0,
2625 wcd938x_get_swr_port, wcd938x_set_swr_port),
2626 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0,
2627 wcd938x_get_swr_port, wcd938x_set_swr_port),
2628 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0,
2629 wcd938x_get_swr_port, wcd938x_set_swr_port),
2630 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0,
2631 wcd938x_get_swr_port, wcd938x_set_swr_port),
2632 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0,
2633 wcd938x_get_swr_port, wcd938x_set_swr_port),
2634 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0,
2635 wcd938x_get_swr_port, wcd938x_set_swr_port),
2636 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0,
2637 wcd938x_get_swr_port, wcd938x_set_swr_port),
2638 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0,
2639 wcd938x_get_swr_port, wcd938x_set_swr_port),
2640 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0,
2641 wcd938x_get_swr_port, wcd938x_set_swr_port),
2642 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0,
2643 wcd938x_get_swr_port, wcd938x_set_swr_port),
2644 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0,
2645 wcd938x_get_swr_port, wcd938x_set_swr_port),
2646 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0,
2647 wcd938x_get_swr_port, wcd938x_set_swr_port),
2648 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0,
2649 wcd938x_get_swr_port, wcd938x_set_swr_port),
2650 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
2651 wcd938x_ldoh_get, wcd938x_ldoh_put),
2652
2653 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain),
2654 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain),
2655 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain),
2656 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain),
2657 };
2658
2659 static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
2660
2661 /*input widgets*/
2662 SND_SOC_DAPM_INPUT("AMIC1"),
2663 SND_SOC_DAPM_INPUT("AMIC2"),
2664 SND_SOC_DAPM_INPUT("AMIC3"),
2665 SND_SOC_DAPM_INPUT("AMIC4"),
2666 SND_SOC_DAPM_INPUT("AMIC5"),
2667 SND_SOC_DAPM_INPUT("AMIC6"),
2668 SND_SOC_DAPM_INPUT("AMIC7"),
2669 SND_SOC_DAPM_MIC("Analog Mic1", NULL),
2670 SND_SOC_DAPM_MIC("Analog Mic2", NULL),
2671 SND_SOC_DAPM_MIC("Analog Mic3", NULL),
2672 SND_SOC_DAPM_MIC("Analog Mic4", NULL),
2673 SND_SOC_DAPM_MIC("Analog Mic5", NULL),
2674
2675 /*tx widgets*/
2676 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
2677 wcd938x_codec_enable_adc,
2678 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2679 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
2680 wcd938x_codec_enable_adc,
2681 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2682 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
2683 wcd938x_codec_enable_adc,
2684 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2685 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
2686 wcd938x_codec_enable_adc,
2687 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2688 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
2689 wcd938x_codec_enable_dmic,
2690 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2691 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
2692 wcd938x_codec_enable_dmic,
2693 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2694 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
2695 wcd938x_codec_enable_dmic,
2696 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2697 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
2698 wcd938x_codec_enable_dmic,
2699 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2700 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
2701 wcd938x_codec_enable_dmic,
2702 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2703 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
2704 wcd938x_codec_enable_dmic,
2705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2706 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
2707 wcd938x_codec_enable_dmic,
2708 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2709 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
2710 wcd938x_codec_enable_dmic,
2711 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2712
2713 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
2714 NULL, 0, wcd938x_adc_enable_req,
2715 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2716 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
2717 NULL, 0, wcd938x_adc_enable_req,
2718 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2719 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
2720 NULL, 0, wcd938x_adc_enable_req,
2721 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2722 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0,
2723 wcd938x_adc_enable_req,
2724 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2725
2726 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
2727 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux),
2728 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux),
2729 SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux),
2730 SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux),
2731
2732 /*tx mixers*/
2733 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch,
2734 ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl,
2735 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2736 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch,
2737 ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl,
2738 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2739 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
2740 ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
2741 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2742 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
2743 ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
2744 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2745 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch,
2746 ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl,
2747 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2748 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch,
2749 ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl,
2750 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2751 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch,
2752 ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl,
2753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2754 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch,
2755 ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl,
2756 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2757 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch,
2758 ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl,
2759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2760 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch,
2761 ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl,
2762 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2763 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch,
2764 ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl,
2765 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2766 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch,
2767 ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl,
2768 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2769 /* micbias widgets*/
2770 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2771 wcd938x_codec_enable_micbias,
2772 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2773 SND_SOC_DAPM_POST_PMD),
2774 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2775 wcd938x_codec_enable_micbias,
2776 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2777 SND_SOC_DAPM_POST_PMD),
2778 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2779 wcd938x_codec_enable_micbias,
2780 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2781 SND_SOC_DAPM_POST_PMD),
2782 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
2783 wcd938x_codec_enable_micbias,
2784 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2785 SND_SOC_DAPM_POST_PMD),
2786
2787 /* micbias pull up widgets*/
2788 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2789 wcd938x_codec_enable_micbias_pullup,
2790 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2791 SND_SOC_DAPM_POST_PMD),
2792 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2793 wcd938x_codec_enable_micbias_pullup,
2794 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2795 SND_SOC_DAPM_POST_PMD),
2796 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2797 wcd938x_codec_enable_micbias_pullup,
2798 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2799 SND_SOC_DAPM_POST_PMD),
2800 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
2801 wcd938x_codec_enable_micbias_pullup,
2802 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2803 SND_SOC_DAPM_POST_PMD),
2804
2805 /*output widgets tx*/
2806 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
2807 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
2808 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
2809 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
2810 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
2811 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
2812 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
2813 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
2814 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
2815 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
2816 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
2817 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
2818
2819 SND_SOC_DAPM_INPUT("IN1_HPHL"),
2820 SND_SOC_DAPM_INPUT("IN2_HPHR"),
2821 SND_SOC_DAPM_INPUT("IN3_AUX"),
2822
2823 /*rx widgets*/
2824 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
2825 wcd938x_codec_enable_ear_pa,
2826 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2827 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2828 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
2829 wcd938x_codec_enable_aux_pa,
2830 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2831 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2832 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
2833 wcd938x_codec_enable_hphl_pa,
2834 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2835 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2836 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
2837 wcd938x_codec_enable_hphr_pa,
2838 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2839 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2840
2841 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
2842 wcd938x_codec_hphl_dac_event,
2843 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2844 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2845 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
2846 wcd938x_codec_hphr_dac_event,
2847 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2848 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2849 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
2850 wcd938x_codec_ear_dac_event,
2851 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2852 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2853 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
2854 wcd938x_codec_aux_dac_event,
2855 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2856 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2857
2858 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
2859
2860 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
2861 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
2862 wcd938x_codec_enable_rxclk,
2863 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2864 SND_SOC_DAPM_POST_PMD),
2865
2866 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
2867
2868 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2869 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2870 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2871
2872 /* rx mixer widgets*/
2873 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
2874 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
2875 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
2876 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
2877 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
2878 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
2879 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
2880 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
2881
2882 /*output widgets rx*/
2883 SND_SOC_DAPM_OUTPUT("EAR"),
2884 SND_SOC_DAPM_OUTPUT("AUX"),
2885 SND_SOC_DAPM_OUTPUT("HPHL"),
2886 SND_SOC_DAPM_OUTPUT("HPHR"),
2887
2888 };
2889
2890 static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
2891 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
2892 {"ADC1_MIXER", "Switch", "ADC1 REQ"},
2893 {"ADC1 REQ", NULL, "ADC1"},
2894 {"ADC1", NULL, "AMIC1"},
2895
2896 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
2897 {"ADC2_MIXER", "Switch", "ADC2 REQ"},
2898 {"ADC2 REQ", NULL, "ADC2"},
2899 {"ADC2", NULL, "HDR12 MUX"},
2900 {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
2901 {"HDR12 MUX", "HDR12", "AMIC1"},
2902 {"ADC2 MUX", "INP3", "AMIC3"},
2903 {"ADC2 MUX", "INP2", "AMIC2"},
2904
2905 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
2906 {"ADC3_MIXER", "Switch", "ADC3 REQ"},
2907 {"ADC3 REQ", NULL, "ADC3"},
2908 {"ADC3", NULL, "HDR34 MUX"},
2909 {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
2910 {"HDR34 MUX", "HDR34", "AMIC5"},
2911 {"ADC3 MUX", "INP4", "AMIC4"},
2912 {"ADC3 MUX", "INP6", "AMIC6"},
2913
2914 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
2915 {"ADC4_MIXER", "Switch", "ADC4 REQ"},
2916 {"ADC4 REQ", NULL, "ADC4"},
2917 {"ADC4", NULL, "ADC4 MUX"},
2918 {"ADC4 MUX", "INP5", "AMIC5"},
2919 {"ADC4 MUX", "INP7", "AMIC7"},
2920
2921 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
2922 {"DMIC1_MIXER", "Switch", "DMIC1"},
2923
2924 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
2925 {"DMIC2_MIXER", "Switch", "DMIC2"},
2926
2927 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
2928 {"DMIC3_MIXER", "Switch", "DMIC3"},
2929
2930 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
2931 {"DMIC4_MIXER", "Switch", "DMIC4"},
2932
2933 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
2934 {"DMIC5_MIXER", "Switch", "DMIC5"},
2935
2936 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
2937 {"DMIC6_MIXER", "Switch", "DMIC6"},
2938
2939 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
2940 {"DMIC7_MIXER", "Switch", "DMIC7"},
2941
2942 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
2943 {"DMIC8_MIXER", "Switch", "DMIC8"},
2944
2945 {"IN1_HPHL", NULL, "VDD_BUCK"},
2946 {"IN1_HPHL", NULL, "CLS_H_PORT"},
2947
2948 {"RX1", NULL, "IN1_HPHL"},
2949 {"RX1", NULL, "RXCLK"},
2950 {"RDAC1", NULL, "RX1"},
2951 {"HPHL_RDAC", "Switch", "RDAC1"},
2952 {"HPHL PGA", NULL, "HPHL_RDAC"},
2953 {"HPHL", NULL, "HPHL PGA"},
2954
2955 {"IN2_HPHR", NULL, "VDD_BUCK"},
2956 {"IN2_HPHR", NULL, "CLS_H_PORT"},
2957 {"RX2", NULL, "IN2_HPHR"},
2958 {"RDAC2", NULL, "RX2"},
2959 {"RX2", NULL, "RXCLK"},
2960 {"HPHR_RDAC", "Switch", "RDAC2"},
2961 {"HPHR PGA", NULL, "HPHR_RDAC"},
2962 {"HPHR", NULL, "HPHR PGA"},
2963
2964 {"IN3_AUX", NULL, "VDD_BUCK"},
2965 {"IN3_AUX", NULL, "CLS_H_PORT"},
2966 {"RX3", NULL, "IN3_AUX"},
2967 {"RDAC4", NULL, "RX3"},
2968 {"RX3", NULL, "RXCLK"},
2969 {"AUX_RDAC", "Switch", "RDAC4"},
2970 {"AUX PGA", NULL, "AUX_RDAC"},
2971 {"AUX", NULL, "AUX PGA"},
2972
2973 {"RDAC3_MUX", "RX3", "RX3"},
2974 {"RDAC3_MUX", "RX1", "RX1"},
2975 {"RDAC3", NULL, "RDAC3_MUX"},
2976 {"EAR_RDAC", "Switch", "RDAC3"},
2977 {"EAR PGA", NULL, "EAR_RDAC"},
2978 {"EAR", NULL, "EAR PGA"},
2979 };
2980
wcd938x_set_micbias_data(struct wcd938x_priv * wcd938x)2981 static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x)
2982 {
2983 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2984
2985 /* set micbias voltage */
2986 vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv);
2987 vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv);
2988 vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv);
2989 vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv);
2990 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
2991 return -EINVAL;
2992
2993 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1,
2994 WCD938X_MICB_VOUT_MASK, vout_ctl_1);
2995 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2,
2996 WCD938X_MICB_VOUT_MASK, vout_ctl_2);
2997 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3,
2998 WCD938X_MICB_VOUT_MASK, vout_ctl_3);
2999 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4,
3000 WCD938X_MICB_VOUT_MASK, vout_ctl_4);
3001
3002 return 0;
3003 }
3004
wcd938x_wd_handle_irq(int irq,void * data)3005 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
3006 {
3007 return IRQ_HANDLED;
3008 }
3009
3010 static const struct irq_chip wcd_irq_chip = {
3011 .name = "WCD938x",
3012 };
3013
wcd_irq_chip_map(struct irq_domain * irqd,unsigned int virq,irq_hw_number_t hw)3014 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
3015 irq_hw_number_t hw)
3016 {
3017 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
3018 irq_set_nested_thread(virq, 1);
3019 irq_set_noprobe(virq);
3020
3021 return 0;
3022 }
3023
3024 static const struct irq_domain_ops wcd_domain_ops = {
3025 .map = wcd_irq_chip_map,
3026 };
3027
wcd938x_irq_init(struct wcd938x_priv * wcd,struct device * dev)3028 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev)
3029 {
3030
3031 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL);
3032 if (!(wcd->virq)) {
3033 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
3034 return -EINVAL;
3035 }
3036
3037 return devm_regmap_add_irq_chip(dev, wcd->regmap,
3038 irq_create_mapping(wcd->virq, 0),
3039 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip,
3040 &wcd->irq_chip);
3041 }
3042
wcd938x_soc_codec_probe(struct snd_soc_component * component)3043 static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
3044 {
3045 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3046 struct sdw_slave *tx_sdw_dev = wcd938x->tx_sdw_dev;
3047 struct device *dev = component->dev;
3048 unsigned long time_left;
3049 int ret, i;
3050
3051 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete,
3052 msecs_to_jiffies(2000));
3053 if (!time_left) {
3054 dev_err(dev, "soundwire device init timeout\n");
3055 return -ETIMEDOUT;
3056 }
3057
3058 snd_soc_component_init_regmap(component, wcd938x->regmap);
3059
3060 ret = pm_runtime_resume_and_get(dev);
3061 if (ret < 0)
3062 return ret;
3063
3064 wcd938x->variant = snd_soc_component_read_field(component,
3065 WCD938X_DIGITAL_EFUSE_REG_0,
3066 WCD938X_ID_MASK);
3067
3068 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X);
3069 if (IS_ERR(wcd938x->clsh_info)) {
3070 pm_runtime_put(dev);
3071 return PTR_ERR(wcd938x->clsh_info);
3072 }
3073
3074 wcd938x_io_init(wcd938x);
3075 /* Set all interrupts as edge triggered */
3076 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) {
3077 regmap_write(wcd938x->regmap,
3078 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
3079 }
3080
3081 pm_runtime_put(dev);
3082
3083 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
3084 WCD938X_IRQ_HPHR_PDM_WD_INT);
3085 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
3086 WCD938X_IRQ_HPHL_PDM_WD_INT);
3087 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
3088 WCD938X_IRQ_AUX_PDM_WD_INT);
3089
3090 /* Request for watchdog interrupt */
3091 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
3092 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3093 "HPHR PDM WD INT", wcd938x);
3094 if (ret) {
3095 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
3096 goto err_free_clsh_ctrl;
3097 }
3098
3099 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
3100 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3101 "HPHL PDM WD INT", wcd938x);
3102 if (ret) {
3103 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
3104 goto err_free_hphr_pdm_wd_int;
3105 }
3106
3107 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
3108 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3109 "AUX PDM WD INT", wcd938x);
3110 if (ret) {
3111 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
3112 goto err_free_hphl_pdm_wd_int;
3113 }
3114
3115 /* Disable watchdog interrupt for HPH and AUX */
3116 disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
3117 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
3118 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
3119
3120 switch (wcd938x->variant) {
3121 case WCD9380:
3122 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
3123 ARRAY_SIZE(wcd9380_snd_controls));
3124 if (ret < 0) {
3125 dev_err(component->dev,
3126 "%s: Failed to add snd ctrls for variant: %d\n",
3127 __func__, wcd938x->variant);
3128 goto err_free_aux_pdm_wd_int;
3129 }
3130 break;
3131 case WCD9385:
3132 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
3133 ARRAY_SIZE(wcd9385_snd_controls));
3134 if (ret < 0) {
3135 dev_err(component->dev,
3136 "%s: Failed to add snd ctrls for variant: %d\n",
3137 __func__, wcd938x->variant);
3138 goto err_free_aux_pdm_wd_int;
3139 }
3140 break;
3141 default:
3142 break;
3143 }
3144
3145 ret = wcd938x_mbhc_init(component);
3146 if (ret) {
3147 dev_err(component->dev, "mbhc initialization failed\n");
3148 goto err_free_aux_pdm_wd_int;
3149 }
3150
3151 return 0;
3152
3153 err_free_aux_pdm_wd_int:
3154 free_irq(wcd938x->aux_pdm_wd_int, wcd938x);
3155 err_free_hphl_pdm_wd_int:
3156 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x);
3157 err_free_hphr_pdm_wd_int:
3158 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x);
3159 err_free_clsh_ctrl:
3160 wcd_clsh_ctrl_free(wcd938x->clsh_info);
3161
3162 return ret;
3163 }
3164
wcd938x_soc_codec_remove(struct snd_soc_component * component)3165 static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
3166 {
3167 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3168
3169 wcd938x_mbhc_deinit(component);
3170
3171 free_irq(wcd938x->aux_pdm_wd_int, wcd938x);
3172 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x);
3173 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x);
3174
3175 wcd_clsh_ctrl_free(wcd938x->clsh_info);
3176 }
3177
wcd938x_codec_set_jack(struct snd_soc_component * comp,struct snd_soc_jack * jack,void * data)3178 static int wcd938x_codec_set_jack(struct snd_soc_component *comp,
3179 struct snd_soc_jack *jack, void *data)
3180 {
3181 struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev);
3182
3183 if (jack)
3184 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
3185 else
3186 wcd_mbhc_stop(wcd->wcd_mbhc);
3187
3188 return 0;
3189 }
3190
3191 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = {
3192 .name = "wcd938x_codec",
3193 .probe = wcd938x_soc_codec_probe,
3194 .remove = wcd938x_soc_codec_remove,
3195 .controls = wcd938x_snd_controls,
3196 .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
3197 .dapm_widgets = wcd938x_dapm_widgets,
3198 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
3199 .dapm_routes = wcd938x_audio_map,
3200 .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
3201 .set_jack = wcd938x_codec_set_jack,
3202 .endianness = 1,
3203 };
3204
wcd938x_dt_parse_micbias_info(struct device * dev,struct wcd938x_priv * wcd)3205 static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd)
3206 {
3207 struct device_node *np = dev->of_node;
3208 u32 prop_val = 0;
3209 int rc = 0;
3210
3211 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val);
3212 if (!rc)
3213 wcd->micb1_mv = prop_val/1000;
3214 else
3215 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
3216
3217 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val);
3218 if (!rc)
3219 wcd->micb2_mv = prop_val/1000;
3220 else
3221 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
3222
3223 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
3224 if (!rc)
3225 wcd->micb3_mv = prop_val/1000;
3226 else
3227 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
3228
3229 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val);
3230 if (!rc)
3231 wcd->micb4_mv = prop_val/1000;
3232 else
3233 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
3234 }
3235
wcd938x_swap_gnd_mic(struct snd_soc_component * component)3236 static bool wcd938x_swap_gnd_mic(struct snd_soc_component *component)
3237 {
3238 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3239 struct device *dev = component->dev;
3240 int ret;
3241
3242 if (wcd938x->us_euro_mux) {
3243 if (wcd938x->mux_setup_done)
3244 mux_control_deselect(wcd938x->us_euro_mux);
3245
3246 ret = mux_control_try_select(wcd938x->us_euro_mux, !wcd938x->mux_state);
3247 if (ret) {
3248 dev_err(dev, "Error (%d) Unable to select us/euro mux state\n", ret);
3249 wcd938x->mux_setup_done = false;
3250 return false;
3251 }
3252 wcd938x->mux_setup_done = true;
3253 } else {
3254 gpiod_set_value(wcd938x->us_euro_gpio, !wcd938x->mux_state);
3255 }
3256
3257 wcd938x->mux_state = !wcd938x->mux_state;
3258
3259 return true;
3260 }
3261
3262
wcd938x_populate_dt_data(struct wcd938x_priv * wcd938x,struct device * dev)3263 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev)
3264 {
3265 struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg;
3266 int ret;
3267
3268 wcd938x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
3269 if (IS_ERR(wcd938x->reset_gpio))
3270 return dev_err_probe(dev, PTR_ERR(wcd938x->reset_gpio),
3271 "Failed to get reset gpio\n");
3272
3273 if (of_property_present(dev->of_node, "mux-controls")) {
3274 wcd938x->us_euro_mux = devm_mux_control_get(dev, NULL);
3275 if (IS_ERR(wcd938x->us_euro_mux)) {
3276 ret = PTR_ERR(wcd938x->us_euro_mux);
3277 return dev_err_probe(dev, ret, "failed to get mux control\n");
3278 }
3279
3280 ret = mux_control_try_select(wcd938x->us_euro_mux, wcd938x->mux_state);
3281 if (ret) {
3282 dev_err(dev, "Error (%d) Unable to select us/euro mux state\n", ret);
3283 return ret;
3284 }
3285 wcd938x->mux_setup_done = true;
3286 } else {
3287 wcd938x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW);
3288 if (IS_ERR(wcd938x->us_euro_gpio))
3289 return dev_err_probe(dev, PTR_ERR(wcd938x->us_euro_gpio),
3290 "us-euro swap Control GPIO not found\n");
3291 }
3292
3293 cfg->swap_gnd_mic = wcd938x_swap_gnd_mic;
3294
3295 wcd938x->supplies[0].supply = "vdd-rxtx";
3296 wcd938x->supplies[1].supply = "vdd-io";
3297 wcd938x->supplies[2].supply = "vdd-buck";
3298 wcd938x->supplies[3].supply = "vdd-mic-bias";
3299
3300 ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies);
3301 if (ret)
3302 return dev_err_probe(dev, ret, "Failed to get supplies\n");
3303
3304 ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies);
3305 if (ret) {
3306 regulator_bulk_free(WCD938X_MAX_SUPPLY, wcd938x->supplies);
3307 return dev_err_probe(dev, ret, "Failed to enable supplies\n");
3308 }
3309
3310 wcd938x_dt_parse_micbias_info(dev, wcd938x);
3311
3312 cfg->mbhc_micbias = MIC_BIAS_2;
3313 cfg->anc_micbias = MIC_BIAS_2;
3314 cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
3315 cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS;
3316 cfg->micb_mv = wcd938x->micb2_mv;
3317 cfg->linein_th = 5000;
3318 cfg->hs_thr = 1700;
3319 cfg->hph_thr = 50;
3320
3321 wcd_dt_parse_mbhc_data(dev, cfg);
3322
3323 return 0;
3324 }
3325
wcd938x_reset(struct wcd938x_priv * wcd938x)3326 static int wcd938x_reset(struct wcd938x_priv *wcd938x)
3327 {
3328 gpiod_set_value(wcd938x->reset_gpio, 1);
3329 /* 20us sleep required after pulling the reset gpio to LOW */
3330 usleep_range(20, 30);
3331 gpiod_set_value(wcd938x->reset_gpio, 0);
3332 /* 20us sleep required after pulling the reset gpio to HIGH */
3333 usleep_range(20, 30);
3334
3335 return 0;
3336 }
3337
wcd938x_codec_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)3338 static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream,
3339 struct snd_pcm_hw_params *params,
3340 struct snd_soc_dai *dai)
3341 {
3342 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
3343 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
3344
3345 return wcd938x_sdw_hw_params(wcd, substream, params, dai);
3346 }
3347
wcd938x_codec_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)3348 static int wcd938x_codec_free(struct snd_pcm_substream *substream,
3349 struct snd_soc_dai *dai)
3350 {
3351 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
3352 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
3353
3354 return wcd938x_sdw_free(wcd, substream, dai);
3355 }
3356
wcd938x_codec_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)3357 static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai,
3358 void *stream, int direction)
3359 {
3360 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
3361 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
3362
3363 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction);
3364
3365 }
3366
3367 static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = {
3368 .hw_params = wcd938x_codec_hw_params,
3369 .hw_free = wcd938x_codec_free,
3370 .set_stream = wcd938x_codec_set_sdw_stream,
3371 };
3372
3373 static struct snd_soc_dai_driver wcd938x_dais[] = {
3374 [AIF1_PB] = {
3375 .name = "wcd938x-sdw-rx",
3376 .playback = {
3377 .stream_name = "WCD AIF1 Playback",
3378 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK,
3379 .formats = WCD938X_FORMATS_S16_S24_LE,
3380 .rate_max = 192000,
3381 .rate_min = 8000,
3382 .channels_min = 1,
3383 .channels_max = 2,
3384 },
3385 .ops = &wcd938x_sdw_dai_ops,
3386 },
3387 [AIF1_CAP] = {
3388 .name = "wcd938x-sdw-tx",
3389 .capture = {
3390 .stream_name = "WCD AIF1 Capture",
3391 .rates = WCD938X_RATES_MASK,
3392 .formats = SNDRV_PCM_FMTBIT_S16_LE,
3393 .rate_min = 8000,
3394 .rate_max = 192000,
3395 .channels_min = 1,
3396 .channels_max = 4,
3397 },
3398 .ops = &wcd938x_sdw_dai_ops,
3399 },
3400 };
3401
wcd938x_bind(struct device * dev)3402 static int wcd938x_bind(struct device *dev)
3403 {
3404 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
3405 int ret;
3406
3407 ret = component_bind_all(dev, wcd938x);
3408 if (ret) {
3409 dev_err(dev, "%s: Slave bind failed, ret = %d\n",
3410 __func__, ret);
3411 return ret;
3412 }
3413
3414 wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode);
3415 if (!wcd938x->rxdev) {
3416 dev_err(dev, "could not find slave with matching of node\n");
3417 ret = -EINVAL;
3418 goto err_unbind;
3419 }
3420 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev);
3421 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x;
3422
3423 wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode);
3424 if (!wcd938x->txdev) {
3425 dev_err(dev, "could not find txslave with matching of node\n");
3426 ret = -EINVAL;
3427 goto err_put_rxdev;
3428 }
3429 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev);
3430 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x;
3431 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev);
3432
3433 /* As TX is main CSR reg interface, which should not be suspended first.
3434 * expicilty add the dependency link */
3435 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS |
3436 DL_FLAG_PM_RUNTIME)) {
3437 dev_err(dev, "could not devlink tx and rx\n");
3438 ret = -EINVAL;
3439 goto err_put_txdev;
3440 }
3441
3442 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS |
3443 DL_FLAG_PM_RUNTIME)) {
3444 dev_err(dev, "could not devlink wcd and tx\n");
3445 ret = -EINVAL;
3446 goto err_remove_rxtx_link;
3447 }
3448
3449 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS |
3450 DL_FLAG_PM_RUNTIME)) {
3451 dev_err(dev, "could not devlink wcd and rx\n");
3452 ret = -EINVAL;
3453 goto err_remove_tx_link;
3454 }
3455
3456 wcd938x->regmap = dev_get_regmap(&wcd938x->tx_sdw_dev->dev, NULL);
3457 if (!wcd938x->regmap) {
3458 dev_err(dev, "could not get TX device regmap\n");
3459 ret = -EINVAL;
3460 goto err_remove_rx_link;
3461 }
3462
3463 ret = wcd938x_irq_init(wcd938x, dev);
3464 if (ret) {
3465 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret);
3466 goto err_remove_rx_link;
3467 }
3468
3469 wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq;
3470 wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq;
3471
3472 ret = wcd938x_set_micbias_data(wcd938x);
3473 if (ret < 0) {
3474 dev_err(dev, "%s: bad micbias pdata\n", __func__);
3475 goto err_remove_rx_link;
3476 }
3477
3478 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
3479 wcd938x_dais, ARRAY_SIZE(wcd938x_dais));
3480 if (ret) {
3481 dev_err(dev, "%s: Codec registration failed\n",
3482 __func__);
3483 goto err_remove_rx_link;
3484 }
3485
3486 return 0;
3487
3488 err_remove_rx_link:
3489 device_link_remove(dev, wcd938x->rxdev);
3490 err_remove_tx_link:
3491 device_link_remove(dev, wcd938x->txdev);
3492 err_remove_rxtx_link:
3493 device_link_remove(wcd938x->rxdev, wcd938x->txdev);
3494 err_put_txdev:
3495 put_device(wcd938x->txdev);
3496 err_put_rxdev:
3497 put_device(wcd938x->rxdev);
3498 err_unbind:
3499 component_unbind_all(dev, wcd938x);
3500
3501 return ret;
3502 }
3503
wcd938x_unbind(struct device * dev)3504 static void wcd938x_unbind(struct device *dev)
3505 {
3506 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
3507
3508 snd_soc_unregister_component(dev);
3509 device_link_remove(dev, wcd938x->txdev);
3510 device_link_remove(dev, wcd938x->rxdev);
3511 device_link_remove(wcd938x->rxdev, wcd938x->txdev);
3512 put_device(wcd938x->txdev);
3513 put_device(wcd938x->rxdev);
3514 component_unbind_all(dev, wcd938x);
3515 }
3516
3517 static const struct component_master_ops wcd938x_comp_ops = {
3518 .bind = wcd938x_bind,
3519 .unbind = wcd938x_unbind,
3520 };
3521
wcd938x_add_slave_components(struct wcd938x_priv * wcd938x,struct device * dev,struct component_match ** matchptr)3522 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x,
3523 struct device *dev,
3524 struct component_match **matchptr)
3525 {
3526 struct device_node *np;
3527
3528 np = dev->of_node;
3529
3530 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
3531 if (!wcd938x->rxnode) {
3532 dev_err(dev, "%s: Rx-device node not defined\n", __func__);
3533 return -ENODEV;
3534 }
3535
3536 of_node_get(wcd938x->rxnode);
3537 component_match_add_release(dev, matchptr, component_release_of,
3538 component_compare_of, wcd938x->rxnode);
3539
3540 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
3541 if (!wcd938x->txnode) {
3542 dev_err(dev, "%s: Tx-device node not defined\n", __func__);
3543 return -ENODEV;
3544 }
3545 of_node_get(wcd938x->txnode);
3546 component_match_add_release(dev, matchptr, component_release_of,
3547 component_compare_of, wcd938x->txnode);
3548 return 0;
3549 }
3550
wcd938x_probe(struct platform_device * pdev)3551 static int wcd938x_probe(struct platform_device *pdev)
3552 {
3553 struct component_match *match = NULL;
3554 struct wcd938x_priv *wcd938x = NULL;
3555 struct device *dev = &pdev->dev;
3556 int ret;
3557
3558 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
3559 GFP_KERNEL);
3560 if (!wcd938x)
3561 return -ENOMEM;
3562
3563 dev_set_drvdata(dev, wcd938x);
3564 mutex_init(&wcd938x->micb_lock);
3565
3566 ret = wcd938x_populate_dt_data(wcd938x, dev);
3567 if (ret)
3568 return ret;
3569
3570 ret = wcd938x_add_slave_components(wcd938x, dev, &match);
3571 if (ret)
3572 goto err_disable_regulators;
3573
3574 wcd938x_reset(wcd938x);
3575
3576 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match);
3577 if (ret)
3578 goto err_disable_regulators;
3579
3580 pm_runtime_set_autosuspend_delay(dev, 1000);
3581 pm_runtime_use_autosuspend(dev);
3582 pm_runtime_mark_last_busy(dev);
3583 pm_runtime_set_active(dev);
3584 pm_runtime_enable(dev);
3585 pm_runtime_idle(dev);
3586
3587 return 0;
3588
3589 err_disable_regulators:
3590 regulator_bulk_disable(WCD938X_MAX_SUPPLY, wcd938x->supplies);
3591 regulator_bulk_free(WCD938X_MAX_SUPPLY, wcd938x->supplies);
3592
3593 return ret;
3594 }
3595
wcd938x_remove(struct platform_device * pdev)3596 static void wcd938x_remove(struct platform_device *pdev)
3597 {
3598 struct device *dev = &pdev->dev;
3599 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
3600
3601 component_master_del(dev, &wcd938x_comp_ops);
3602
3603 pm_runtime_disable(dev);
3604 pm_runtime_set_suspended(dev);
3605 pm_runtime_dont_use_autosuspend(dev);
3606
3607 if (wcd938x->us_euro_mux && wcd938x->mux_setup_done)
3608 mux_control_deselect(wcd938x->us_euro_mux);
3609
3610 regulator_bulk_disable(WCD938X_MAX_SUPPLY, wcd938x->supplies);
3611 regulator_bulk_free(WCD938X_MAX_SUPPLY, wcd938x->supplies);
3612 }
3613
3614 #if defined(CONFIG_OF)
3615 static const struct of_device_id wcd938x_dt_match[] = {
3616 { .compatible = "qcom,wcd9380-codec" },
3617 { .compatible = "qcom,wcd9385-codec" },
3618 {}
3619 };
3620 MODULE_DEVICE_TABLE(of, wcd938x_dt_match);
3621 #endif
3622
3623 static struct platform_driver wcd938x_codec_driver = {
3624 .probe = wcd938x_probe,
3625 .remove = wcd938x_remove,
3626 .driver = {
3627 .name = "wcd938x_codec",
3628 .of_match_table = of_match_ptr(wcd938x_dt_match),
3629 .suppress_bind_attrs = true,
3630 },
3631 };
3632
3633 module_platform_driver(wcd938x_codec_driver);
3634 MODULE_DESCRIPTION("WCD938X Codec driver");
3635 MODULE_LICENSE("GPL");
3636