1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/N1 ADC driver
4 *
5 * Copyright (C) 2025 Schneider-Electric
6 *
7 * Author: Herve Codina <herve.codina@bootlin.com>
8 *
9 * The RZ/N1 ADC controller can handle channels from its internal ADC1 and/or
10 * ADC2 cores. The driver use ADC1 and/or ADC2 cores depending on the presence
11 * of the related power supplies (AVDD and VREF) description in the device-tree.
12 */
13
14 #include <linux/array_size.h>
15 #include <linux/bitfield.h>
16 #include <linux/bits.h>
17 #include <linux/cleanup.h>
18 #include <linux/clk.h>
19 #include <linux/dev_printk.h>
20 #include <linux/err.h>
21 #include <linux/iio/iio.h>
22 #include <linux/io.h>
23 #include <linux/iopoll.h>
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/types.h>
30
31 #define RZN1_ADC_CONTROL_REG 0x02c
32 #define RZN1_ADC_CONTROL_ADC_BUSY BIT(6)
33
34 #define RZN1_ADC_FORCE_REG 0x030
35 #define RZN1_ADC_SET_FORCE_REG 0x034
36 #define RZN1_ADC_CLEAR_FORCE_REG 0x038
37 #define RZN1_ADC_FORCE_VC(_n) BIT(_n)
38
39 #define RZN1_ADC_CONFIG_REG 0x040
40 #define RZN1_ADC_CONFIG_ADC_POWER_DOWN BIT(3)
41
42 #define RZN1_ADC_VC_REG(_n) (0x0c0 + 4 * (_n))
43 #define RZN1_ADC_VC_ADC2_ENABLE BIT(16)
44 #define RZN1_ADC_VC_ADC1_ENABLE BIT(15)
45 #define RZN1_ADC_VC_ADC2_CHANNEL_SEL_MASK GENMASK(5, 3)
46 #define RZN1_ADC_VC_ADC1_CHANNEL_SEL_MASK GENMASK(2, 0)
47
48 #define RZN1_ADC_ADC1_DATA_REG(_n) (0x100 + 4 * (_n))
49 #define RZN1_ADC_ADC2_DATA_REG(_n) (0x140 + 4 * (_n))
50 #define RZN1_ADC_ADCX_DATA_DATA_MASK GENMASK(11, 0)
51
52 #define RZN1_ADC_NO_CHANNEL -1
53
54 #define RZN1_ADC_CHANNEL_SHARED_SCALE(_ch, _ds_name) { \
55 .type = IIO_VOLTAGE, \
56 .indexed = 1, \
57 .channel = (_ch), \
58 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
59 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
60 .datasheet_name = (_ds_name), \
61 }
62
63 #define RZN1_ADC_CHANNEL_SEPARATED_SCALE(_ch, _ds_name) { \
64 .type = IIO_VOLTAGE, \
65 .indexed = 1, \
66 .channel = (_ch), \
67 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
68 BIT(IIO_CHAN_INFO_SCALE), \
69 .datasheet_name = (_ds_name), \
70 }
71
72 /*
73 * 8 ADC1_IN signals existed numbered 0..4, 6..8
74 * ADCx_IN5 doesn't exist in RZ/N1 datasheet
75 */
76 static struct iio_chan_spec rzn1_adc1_channels[] = {
77 RZN1_ADC_CHANNEL_SHARED_SCALE(0, "ADC1_IN0"),
78 RZN1_ADC_CHANNEL_SHARED_SCALE(1, "ADC1_IN1"),
79 RZN1_ADC_CHANNEL_SHARED_SCALE(2, "ADC1_IN2"),
80 RZN1_ADC_CHANNEL_SHARED_SCALE(3, "ADC1_IN3"),
81 RZN1_ADC_CHANNEL_SHARED_SCALE(4, "ADC1_IN4"),
82 RZN1_ADC_CHANNEL_SHARED_SCALE(5, "ADC1_IN6"),
83 RZN1_ADC_CHANNEL_SHARED_SCALE(6, "ADC1_IN7"),
84 RZN1_ADC_CHANNEL_SHARED_SCALE(7, "ADC1_IN8"),
85 };
86
87 static struct iio_chan_spec rzn1_adc2_channels[] = {
88 RZN1_ADC_CHANNEL_SHARED_SCALE(8, "ADC2_IN0"),
89 RZN1_ADC_CHANNEL_SHARED_SCALE(9, "ADC2_IN1"),
90 RZN1_ADC_CHANNEL_SHARED_SCALE(10, "ADC2_IN2"),
91 RZN1_ADC_CHANNEL_SHARED_SCALE(11, "ADC2_IN3"),
92 RZN1_ADC_CHANNEL_SHARED_SCALE(12, "ADC2_IN4"),
93 RZN1_ADC_CHANNEL_SHARED_SCALE(13, "ADC2_IN6"),
94 RZN1_ADC_CHANNEL_SHARED_SCALE(14, "ADC2_IN7"),
95 RZN1_ADC_CHANNEL_SHARED_SCALE(15, "ADC2_IN8"),
96 };
97
98 /*
99 * If both ADCs core are used, scale cannot be common. Indeed, scale is
100 * based on Vref connected on each ADC core.
101 */
102 static struct iio_chan_spec rzn1_adc1_adc2_channels[] = {
103 RZN1_ADC_CHANNEL_SEPARATED_SCALE(0, "ADC1_IN0"),
104 RZN1_ADC_CHANNEL_SEPARATED_SCALE(1, "ADC1_IN1"),
105 RZN1_ADC_CHANNEL_SEPARATED_SCALE(2, "ADC1_IN2"),
106 RZN1_ADC_CHANNEL_SEPARATED_SCALE(3, "ADC1_IN3"),
107 RZN1_ADC_CHANNEL_SEPARATED_SCALE(4, "ADC1_IN4"),
108 RZN1_ADC_CHANNEL_SEPARATED_SCALE(5, "ADC1_IN6"),
109 RZN1_ADC_CHANNEL_SEPARATED_SCALE(6, "ADC1_IN7"),
110 RZN1_ADC_CHANNEL_SEPARATED_SCALE(7, "ADC1_IN8"),
111 RZN1_ADC_CHANNEL_SEPARATED_SCALE(8, "ADC2_IN0"),
112 RZN1_ADC_CHANNEL_SEPARATED_SCALE(9, "ADC2_IN1"),
113 RZN1_ADC_CHANNEL_SEPARATED_SCALE(10, "ADC2_IN2"),
114 RZN1_ADC_CHANNEL_SEPARATED_SCALE(11, "ADC2_IN3"),
115 RZN1_ADC_CHANNEL_SEPARATED_SCALE(12, "ADC2_IN4"),
116 RZN1_ADC_CHANNEL_SEPARATED_SCALE(13, "ADC2_IN6"),
117 RZN1_ADC_CHANNEL_SEPARATED_SCALE(14, "ADC2_IN7"),
118 RZN1_ADC_CHANNEL_SEPARATED_SCALE(15, "ADC2_IN8"),
119 };
120
121 struct rzn1_adc {
122 struct device *dev;
123 void __iomem *regs;
124 struct mutex lock; /* ADC lock */
125 int adc1_vref_mV; /* ADC1 Vref in mV. Negative if ADC1 is not used */
126 int adc2_vref_mV; /* ADC2 Vref in mV. Negative if ADC2 is not used */
127 };
128
rzn1_adc_power(struct rzn1_adc * rzn1_adc,bool power)129 static int rzn1_adc_power(struct rzn1_adc *rzn1_adc, bool power)
130 {
131 u32 v;
132
133 writel(power ? 0 : RZN1_ADC_CONFIG_ADC_POWER_DOWN,
134 rzn1_adc->regs + RZN1_ADC_CONFIG_REG);
135
136 /* Wait for the ADC_BUSY to clear */
137 return readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_CONTROL_REG,
138 v, !(v & RZN1_ADC_CONTROL_ADC_BUSY),
139 0, 500);
140 }
141
rzn1_adc_vc_setup_conversion(struct rzn1_adc * rzn1_adc,u32 ch,int adc1_ch,int adc2_ch)142 static void rzn1_adc_vc_setup_conversion(struct rzn1_adc *rzn1_adc, u32 ch,
143 int adc1_ch, int adc2_ch)
144 {
145 u32 vc = 0;
146
147 if (adc1_ch != RZN1_ADC_NO_CHANNEL)
148 vc |= RZN1_ADC_VC_ADC1_ENABLE |
149 FIELD_PREP(RZN1_ADC_VC_ADC1_CHANNEL_SEL_MASK, adc1_ch);
150
151 if (adc2_ch != RZN1_ADC_NO_CHANNEL)
152 vc |= RZN1_ADC_VC_ADC2_ENABLE |
153 FIELD_PREP(RZN1_ADC_VC_ADC2_CHANNEL_SEL_MASK, adc2_ch);
154
155 writel(vc, rzn1_adc->regs + RZN1_ADC_VC_REG(ch));
156 }
157
rzn1_adc_vc_start_conversion(struct rzn1_adc * rzn1_adc,u32 ch)158 static int rzn1_adc_vc_start_conversion(struct rzn1_adc *rzn1_adc, u32 ch)
159 {
160 u32 val;
161
162 val = readl(rzn1_adc->regs + RZN1_ADC_FORCE_REG);
163 if (val & RZN1_ADC_FORCE_VC(ch))
164 return -EBUSY;
165
166 writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_SET_FORCE_REG);
167
168 return 0;
169 }
170
rzn1_adc_vc_stop_conversion(struct rzn1_adc * rzn1_adc,u32 ch)171 static void rzn1_adc_vc_stop_conversion(struct rzn1_adc *rzn1_adc, u32 ch)
172 {
173 writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_CLEAR_FORCE_REG);
174 }
175
rzn1_adc_vc_wait_conversion(struct rzn1_adc * rzn1_adc,u32 ch,u32 * adc1_data,u32 * adc2_data)176 static int rzn1_adc_vc_wait_conversion(struct rzn1_adc *rzn1_adc, u32 ch,
177 u32 *adc1_data, u32 *adc2_data)
178 {
179 u32 data_reg;
180 int ret;
181 u32 v;
182
183 /*
184 * When a VC is selected, it needs 20 ADC clocks to perform the
185 * conversion.
186 *
187 * The worst case is when the 16 VCs need to perform a conversion and
188 * our VC is the lowest in term of priority.
189 *
190 * In that case, the conversion is performed in 16 * 20 ADC clocks.
191 *
192 * The ADC clock can be set from 4MHz to 20MHz. This leads to a worst
193 * case of 16 * 20 * 1/4Mhz = 80us.
194 *
195 * Round it up to 100us.
196 */
197
198 /* Wait for the ADC_FORCE_VC(n) to clear */
199 ret = readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_FORCE_REG,
200 v, !(v & RZN1_ADC_FORCE_VC(ch)),
201 0, 100);
202 if (ret)
203 return ret;
204
205 if (adc1_data) {
206 data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC1_DATA_REG(ch));
207 *adc1_data = FIELD_GET(RZN1_ADC_ADCX_DATA_DATA_MASK, data_reg);
208 }
209
210 if (adc2_data) {
211 data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC2_DATA_REG(ch));
212 *adc2_data = FIELD_GET(RZN1_ADC_ADCX_DATA_DATA_MASK, data_reg);
213 }
214
215 return 0;
216 }
217
rzn1_adc_read_raw_ch(struct rzn1_adc * rzn1_adc,unsigned int chan,int * val)218 static int rzn1_adc_read_raw_ch(struct rzn1_adc *rzn1_adc, unsigned int chan, int *val)
219 {
220 u32 *adc1_data, *adc2_data;
221 int adc1_ch, adc2_ch;
222 u32 adc_data;
223 int ret;
224
225 /*
226 * IIO chan are decoupled from chans used in rzn1_adc_vc_*() functions.
227 * The RZ/N1 ADC VC controller can handle on a single VC chan one
228 * channel from the ADC1 core and one channel from the ADC2 core.
229 *
230 * Even if IIO chans are mapped 1:1 to ADC core chans and so uses only
231 * a chan from ADC1 or a chan from ADC2, future improvements can define
232 * an IIO chan that uses one chan from ADC1 and one chan from ADC2.
233 */
234
235 if (chan < 8) {
236 /* chan 0..7 used to get ADC1 ch 0..7 */
237 adc1_ch = chan;
238 adc1_data = &adc_data;
239 adc2_ch = RZN1_ADC_NO_CHANNEL;
240 adc2_data = NULL;
241 } else if (chan < 16) {
242 /* chan 8..15 used to get ADC2 ch 0..7 */
243 adc1_ch = RZN1_ADC_NO_CHANNEL;
244 adc1_data = NULL;
245 adc2_ch = chan - 8;
246 adc2_data = &adc_data;
247 } else {
248 return -EINVAL;
249 }
250
251 ACQUIRE(pm_runtime_active_auto_try_enabled, pm)(rzn1_adc->dev);
252 ret = ACQUIRE_ERR(pm_runtime_active_auto_try_enabled, &pm);
253 if (ret < 0)
254 return ret;
255
256 scoped_guard(mutex, &rzn1_adc->lock) {
257 rzn1_adc_vc_setup_conversion(rzn1_adc, chan, adc1_ch, adc2_ch);
258
259 ret = rzn1_adc_vc_start_conversion(rzn1_adc, chan);
260 if (ret)
261 return ret;
262
263 ret = rzn1_adc_vc_wait_conversion(rzn1_adc, chan, adc1_data, adc2_data);
264 if (ret) {
265 rzn1_adc_vc_stop_conversion(rzn1_adc, chan);
266 return ret;
267 }
268 }
269
270 *val = adc_data;
271 ret = IIO_VAL_INT;
272
273 return 0;
274 }
275
rzn1_adc_get_vref_mV(struct rzn1_adc * rzn1_adc,unsigned int chan)276 static int rzn1_adc_get_vref_mV(struct rzn1_adc *rzn1_adc, unsigned int chan)
277 {
278 /* chan 0..7 use ADC1 ch 0..7. Vref related to ADC1 core */
279 if (chan < 8)
280 return rzn1_adc->adc1_vref_mV;
281
282 /* chan 8..15 use ADC2 ch 0..7. Vref related to ADC2 core */
283 if (chan < 16)
284 return rzn1_adc->adc2_vref_mV;
285
286 return -EINVAL;
287 }
288
rzn1_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)289 static int rzn1_adc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
290 int *val, int *val2, long mask)
291 {
292 struct rzn1_adc *rzn1_adc = iio_priv(indio_dev);
293 int ret;
294
295 switch (mask) {
296 case IIO_CHAN_INFO_RAW:
297 ret = rzn1_adc_read_raw_ch(rzn1_adc, chan->channel, val);
298 if (ret)
299 return ret;
300 return IIO_VAL_INT;
301
302 case IIO_CHAN_INFO_SCALE:
303 ret = rzn1_adc_get_vref_mV(rzn1_adc, chan->channel);
304 if (ret < 0)
305 return ret;
306 *val = ret;
307 *val2 = 12;
308 return IIO_VAL_FRACTIONAL_LOG2;
309
310 default:
311 return -EINVAL;
312 }
313 }
314
315 static const struct iio_info rzn1_adc_info = {
316 .read_raw = &rzn1_adc_read_raw,
317 };
318
rzn1_adc_set_iio_dev_channels(struct rzn1_adc * rzn1_adc,struct iio_dev * indio_dev)319 static int rzn1_adc_set_iio_dev_channels(struct rzn1_adc *rzn1_adc,
320 struct iio_dev *indio_dev)
321 {
322 /*
323 * When an ADC core is not used, its related vref_mV is set to a
324 * negative error code. Use the correct IIO channels table based on
325 * those vref_mV values.
326 */
327 if (rzn1_adc->adc1_vref_mV >= 0) {
328 if (rzn1_adc->adc2_vref_mV >= 0) {
329 indio_dev->channels = rzn1_adc1_adc2_channels;
330 indio_dev->num_channels = ARRAY_SIZE(rzn1_adc1_adc2_channels);
331 } else {
332 indio_dev->channels = rzn1_adc1_channels;
333 indio_dev->num_channels = ARRAY_SIZE(rzn1_adc1_channels);
334 }
335 return 0;
336 }
337
338 if (rzn1_adc->adc2_vref_mV >= 0) {
339 indio_dev->channels = rzn1_adc2_channels;
340 indio_dev->num_channels = ARRAY_SIZE(rzn1_adc2_channels);
341 return 0;
342 }
343
344 return dev_err_probe(rzn1_adc->dev, -ENODEV,
345 "Failed to set IIO channels, no ADC core used\n");
346 }
347
rzn1_adc_core_get_regulators(struct rzn1_adc * rzn1_adc,int * adc_vref_mV,const char * avdd_name,const char * vref_name)348 static int rzn1_adc_core_get_regulators(struct rzn1_adc *rzn1_adc,
349 int *adc_vref_mV,
350 const char *avdd_name, const char *vref_name)
351 {
352 struct device *dev = rzn1_adc->dev;
353 int ret;
354
355 /*
356 * For a given ADC core (ADC1 or ADC2), both regulators (AVDD and VREF)
357 * must be available in order to have the ADC core used.
358 *
359 * We use the regulators presence to check the usage of the related
360 * ADC core. If both regulators are available, the ADC core is used.
361 * Otherwise, the ADC core is not used.
362 *
363 * The adc_vref_mV value is set to a negative error code (-ENODEV) when
364 * the ADC core is not used. Otherwise it is set to the VRef mV value.
365 */
366
367 *adc_vref_mV = -ENODEV;
368
369 ret = devm_regulator_get_enable_optional(dev, avdd_name);
370 if (ret == -ENODEV)
371 return 0;
372 if (ret < 0)
373 return dev_err_probe(dev, ret, "Failed to get '%s' regulator\n",
374 avdd_name);
375
376 ret = devm_regulator_get_enable_read_voltage(dev, vref_name);
377 if (ret == -ENODEV)
378 return 0;
379 if (ret < 0)
380 return dev_err_probe(dev, ret, "Failed to get '%s' regulator\n",
381 vref_name);
382
383 /*
384 * Both regulators are available.
385 * Set adc_vref_mV to the Vref value in mV. This, as the value set is
386 * positive, also signals that the ADC is used.
387 */
388 *adc_vref_mV = ret / 1000;
389
390 return 0;
391 }
392
rzn1_adc_probe(struct platform_device * pdev)393 static int rzn1_adc_probe(struct platform_device *pdev)
394 {
395 struct device *dev = &pdev->dev;
396 struct iio_dev *indio_dev;
397 struct rzn1_adc *rzn1_adc;
398 struct clk *clk;
399 int ret;
400
401 indio_dev = devm_iio_device_alloc(dev, sizeof(*rzn1_adc));
402 if (!indio_dev)
403 return -ENOMEM;
404
405 rzn1_adc = iio_priv(indio_dev);
406 rzn1_adc->dev = dev;
407
408 ret = devm_mutex_init(dev, &rzn1_adc->lock);
409 if (ret)
410 return ret;
411
412 rzn1_adc->regs = devm_platform_ioremap_resource(pdev, 0);
413 if (IS_ERR(rzn1_adc->regs))
414 return PTR_ERR(rzn1_adc->regs);
415
416 clk = devm_clk_get_enabled(dev, "pclk");
417 if (IS_ERR(clk))
418 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get pclk\n");
419
420 clk = devm_clk_get_enabled(dev, "adc");
421 if (IS_ERR(clk))
422 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get adc clk\n");
423
424 ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc1_vref_mV,
425 "adc1-avdd", "adc1-vref");
426 if (ret)
427 return ret;
428
429 ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc2_vref_mV,
430 "adc2-avdd", "adc2-vref");
431 if (ret)
432 return ret;
433
434 platform_set_drvdata(pdev, rzn1_adc);
435
436 indio_dev->name = "rzn1-adc";
437 indio_dev->info = &rzn1_adc_info;
438 indio_dev->modes = INDIO_DIRECT_MODE;
439 ret = rzn1_adc_set_iio_dev_channels(rzn1_adc, indio_dev);
440 if (ret)
441 return ret;
442
443 pm_runtime_set_autosuspend_delay(dev, 500);
444 pm_runtime_use_autosuspend(dev);
445 ret = devm_pm_runtime_enable(dev);
446 if (ret)
447 return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
448
449 return devm_iio_device_register(dev, indio_dev);
450 }
451
rzn1_adc_pm_runtime_suspend(struct device * dev)452 static int rzn1_adc_pm_runtime_suspend(struct device *dev)
453 {
454 struct rzn1_adc *rzn1_adc = dev_get_drvdata(dev);
455
456 return rzn1_adc_power(rzn1_adc, false);
457 }
458
rzn1_adc_pm_runtime_resume(struct device * dev)459 static int rzn1_adc_pm_runtime_resume(struct device *dev)
460 {
461 struct rzn1_adc *rzn1_adc = dev_get_drvdata(dev);
462
463 return rzn1_adc_power(rzn1_adc, true);
464 }
465
466 static DEFINE_RUNTIME_DEV_PM_OPS(rzn1_adc_pm_ops,
467 rzn1_adc_pm_runtime_suspend,
468 rzn1_adc_pm_runtime_resume,
469 NULL);
470
471 static const struct of_device_id rzn1_adc_of_match[] = {
472 { .compatible = "renesas,rzn1-adc" },
473 { }
474 };
475 MODULE_DEVICE_TABLE(of, rzn1_adc_of_match);
476
477 static struct platform_driver rzn1_adc_driver = {
478 .probe = rzn1_adc_probe,
479 .driver = {
480 .name = "rzn1-adc",
481 .of_match_table = rzn1_adc_of_match,
482 .pm = pm_ptr(&rzn1_adc_pm_ops),
483 },
484 };
485 module_platform_driver(rzn1_adc_driver);
486
487 MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
488 MODULE_DESCRIPTION("Renesas RZ/N1 ADC Driver");
489 MODULE_LICENSE("GPL");
490