1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <drm/drm_drv.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_vpe.h"
29 #include "amdgpu_smu.h"
30 #include "soc15_common.h"
31 #include "vpe_v6_1.h"
32
33 #define AMDGPU_CSA_VPE_SIZE 64
34 /* VPE CSA resides in the 4th page of CSA */
35 #define AMDGPU_CSA_VPE_OFFSET (4096 * 3)
36
37 /* 1 second timeout */
38 #define VPE_IDLE_TIMEOUT msecs_to_jiffies(1000)
39
40 #define VPE_MAX_DPM_LEVEL 4
41 #define FIXED1_8_BITS_PER_FRACTIONAL_PART 8
42 #define GET_PRATIO_INTEGER_PART(x) ((x) >> FIXED1_8_BITS_PER_FRACTIONAL_PART)
43
44 static void vpe_set_ring_funcs(struct amdgpu_device *adev);
45
div16_u16_rem(uint16_t dividend,uint16_t divisor,uint16_t * remainder)46 static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder)
47 {
48 *remainder = dividend % divisor;
49 return dividend / divisor;
50 }
51
complete_integer_division_u16(uint16_t dividend,uint16_t divisor,uint16_t * remainder)52 static inline uint16_t complete_integer_division_u16(
53 uint16_t dividend,
54 uint16_t divisor,
55 uint16_t *remainder)
56 {
57 return div16_u16_rem(dividend, divisor, (uint16_t *)remainder);
58 }
59
vpe_u1_8_from_fraction(uint16_t numerator,uint16_t denominator)60 static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator)
61 {
62 u16 arg1_value = numerator;
63 u16 arg2_value = denominator;
64
65 uint16_t remainder;
66
67 /* determine integer part */
68 uint16_t res_value = complete_integer_division_u16(
69 arg1_value, arg2_value, &remainder);
70
71 if (res_value > 127 /* CHAR_MAX */)
72 return 0;
73
74 /* determine fractional part */
75 {
76 unsigned int i = FIXED1_8_BITS_PER_FRACTIONAL_PART;
77
78 do {
79 remainder <<= 1;
80
81 res_value <<= 1;
82
83 if (remainder >= arg2_value) {
84 res_value |= 1;
85 remainder -= arg2_value;
86 }
87 } while (--i != 0);
88 }
89
90 /* round up LSB */
91 {
92 uint16_t summand = (remainder << 1) >= arg2_value;
93
94 if ((res_value + summand) > 32767 /* SHRT_MAX */)
95 return 0;
96
97 res_value += summand;
98 }
99
100 return res_value;
101 }
102
vpe_internal_get_pratio(uint16_t from_frequency,uint16_t to_frequency)103 static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency)
104 {
105 uint16_t pratio = vpe_u1_8_from_fraction(from_frequency, to_frequency);
106
107 if (GET_PRATIO_INTEGER_PART(pratio) > 1)
108 pratio = 0;
109
110 return pratio;
111 }
112
113 /*
114 * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest),
115 * VPE FW will dynamically decide which level should be used according to current loading.
116 *
117 * Get VPE and SOC clocks from PM, and select the appropriate four clock values,
118 * calculate the ratios of adjusting from one clock to another.
119 * The VPE FW can then request the appropriate frequency from the PMFW.
120 */
amdgpu_vpe_configure_dpm(struct amdgpu_vpe * vpe)121 int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)
122 {
123 struct amdgpu_device *adev = vpe->ring.adev;
124 uint32_t dpm_ctl;
125
126 if (adev->pm.dpm_enabled) {
127 struct dpm_clocks clock_table = { 0 };
128 struct dpm_clock *VPEClks;
129 struct dpm_clock *SOCClks;
130 uint32_t idx;
131 uint32_t vpeclk_enalbled_num = 0;
132 uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0;
133 uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0;
134
135 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));
136 dpm_ctl |= 1; /* DPM enablement */
137 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
138
139 /* Get VPECLK and SOCCLK */
140 if (amdgpu_dpm_get_dpm_clock_table(adev, &clock_table)) {
141 dev_dbg(adev->dev, "%s: get clock failed!\n", __func__);
142 goto disable_dpm;
143 }
144
145 SOCClks = clock_table.SocClocks;
146 VPEClks = clock_table.VPEClocks;
147
148 /* Comfirm enabled vpe clk num
149 * Enabled VPE clocks are ordered from low to high in VPEClks
150 * The highest valid clock index+1 is the number of VPEClks
151 */
152 for (idx = PP_SMU_NUM_VPECLK_DPM_LEVELS; idx && !vpeclk_enalbled_num; idx--)
153 if (VPEClks[idx-1].Freq)
154 vpeclk_enalbled_num = idx;
155
156 /* vpe dpm only cares 4 levels. */
157 for (idx = 0; idx < VPE_MAX_DPM_LEVEL; idx++) {
158 uint32_t soc_dpm_level;
159 uint32_t min_freq;
160
161 if (idx == 0)
162 soc_dpm_level = 0;
163 else
164 soc_dpm_level = (idx * 2) + 1;
165
166 /* clamp the max level */
167 if (soc_dpm_level > vpeclk_enalbled_num - 1)
168 soc_dpm_level = vpeclk_enalbled_num - 1;
169
170 min_freq = (SOCClks[soc_dpm_level].Freq < VPEClks[soc_dpm_level].Freq) ?
171 SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq;
172
173 switch (idx) {
174 case 0:
175 pratio_vmin_freq = min_freq;
176 break;
177 case 1:
178 pratio_vmid_freq = min_freq;
179 break;
180 case 2:
181 pratio_vnorm_freq = min_freq;
182 break;
183 case 3:
184 pratio_vmax_freq = min_freq;
185 break;
186 default:
187 break;
188 }
189 }
190
191 if (pratio_vmin_freq && pratio_vmid_freq && pratio_vnorm_freq && pratio_vmax_freq) {
192 uint32_t pratio_ctl;
193
194 pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq);
195 pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq);
196 pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq);
197
198 pratio_ctl = pratio_vmax_vnorm | (pratio_vnorm_vmid << 9) | (pratio_vmid_vmin << 18);
199 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */
200 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */
201 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */
202 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */
203 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */
204 dev_dbg(adev->dev, "%s: configure vpe dpm pratio done!\n", __func__);
205 } else {
206 dev_dbg(adev->dev, "%s: invalid pratio parameters!\n", __func__);
207 goto disable_dpm;
208 }
209 }
210 return 0;
211
212 disable_dpm:
213 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));
214 dpm_ctl &= 0xfffffffe; /* Disable DPM */
215 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
216 dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__);
217 return -EINVAL;
218 }
219
amdgpu_vpe_psp_update_sram(struct amdgpu_device * adev)220 int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev)
221 {
222 struct amdgpu_firmware_info ucode = {
223 .ucode_id = AMDGPU_UCODE_ID_VPE,
224 .mc_addr = adev->vpe.cmdbuf_gpu_addr,
225 .ucode_size = 8,
226 };
227
228 return psp_execute_ip_fw_load(&adev->psp, &ucode);
229 }
230
amdgpu_vpe_init_microcode(struct amdgpu_vpe * vpe)231 int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe)
232 {
233 struct amdgpu_device *adev = vpe->ring.adev;
234 const struct vpe_firmware_header_v1_0 *vpe_hdr;
235 char fw_prefix[32];
236 int ret;
237
238 amdgpu_ucode_ip_version_decode(adev, VPE_HWIP, fw_prefix, sizeof(fw_prefix));
239 ret = amdgpu_ucode_request(adev, &adev->vpe.fw, AMDGPU_UCODE_REQUIRED,
240 "amdgpu/%s.bin", fw_prefix);
241 if (ret)
242 goto out;
243
244 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;
245 adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version);
246 adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version);
247
248 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
249 struct amdgpu_firmware_info *info;
250
251 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTX];
252 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTX;
253 info->fw = adev->vpe.fw;
254 adev->firmware.fw_size +=
255 ALIGN(le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes), PAGE_SIZE);
256
257 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTL];
258 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTL;
259 info->fw = adev->vpe.fw;
260 adev->firmware.fw_size +=
261 ALIGN(le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes), PAGE_SIZE);
262 }
263
264 return 0;
265 out:
266 dev_err(adev->dev, "fail to initialize vpe microcode\n");
267 release_firmware(adev->vpe.fw);
268 adev->vpe.fw = NULL;
269 return ret;
270 }
271
amdgpu_vpe_ring_init(struct amdgpu_vpe * vpe)272 int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe)
273 {
274 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);
275 struct amdgpu_ring *ring = &vpe->ring;
276 int ret;
277
278 ring->ring_obj = NULL;
279 ring->use_doorbell = true;
280 ring->vm_hub = AMDGPU_MMHUB0(0);
281 ring->doorbell_index = (adev->doorbell_index.vpe_ring << 1);
282 snprintf(ring->name, 4, "vpe");
283
284 ret = amdgpu_ring_init(adev, ring, 1024, &vpe->trap_irq, 0,
285 AMDGPU_RING_PRIO_DEFAULT, NULL);
286 if (ret)
287 return ret;
288
289 return 0;
290 }
291
amdgpu_vpe_ring_fini(struct amdgpu_vpe * vpe)292 int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe)
293 {
294 amdgpu_ring_fini(&vpe->ring);
295
296 return 0;
297 }
298
vpe_early_init(struct amdgpu_ip_block * ip_block)299 static int vpe_early_init(struct amdgpu_ip_block *ip_block)
300 {
301 struct amdgpu_device *adev = ip_block->adev;
302 struct amdgpu_vpe *vpe = &adev->vpe;
303
304 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
305 case IP_VERSION(6, 1, 0):
306 case IP_VERSION(6, 1, 3):
307 vpe_v6_1_set_funcs(vpe);
308 break;
309 case IP_VERSION(6, 1, 1):
310 vpe_v6_1_set_funcs(vpe);
311 vpe->collaborate_mode = true;
312 break;
313 default:
314 return -EINVAL;
315 }
316
317 vpe_set_ring_funcs(adev);
318 vpe_set_regs(vpe);
319
320 dev_info(adev->dev, "VPE: collaborate mode %s", vpe->collaborate_mode ? "true" : "false");
321
322 return 0;
323 }
324
vpe_need_dpm0_at_power_down(struct amdgpu_device * adev)325 static bool vpe_need_dpm0_at_power_down(struct amdgpu_device *adev)
326 {
327 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
328 case IP_VERSION(6, 1, 1):
329 return adev->pm.fw_version < 0x0a640500;
330 default:
331 return false;
332 }
333 }
334
vpe_get_dpm_level(struct amdgpu_device * adev)335 static int vpe_get_dpm_level(struct amdgpu_device *adev)
336 {
337 struct amdgpu_vpe *vpe = &adev->vpe;
338
339 if (!adev->pm.dpm_enabled)
340 return 0;
341
342 return RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_lv));
343 }
344
vpe_idle_work_handler(struct work_struct * work)345 static void vpe_idle_work_handler(struct work_struct *work)
346 {
347 struct amdgpu_device *adev =
348 container_of(work, struct amdgpu_device, vpe.idle_work.work);
349 unsigned int fences = 0;
350
351 fences += amdgpu_fence_count_emitted(&adev->vpe.ring);
352 if (fences)
353 goto reschedule;
354
355 if (vpe_need_dpm0_at_power_down(adev) && vpe_get_dpm_level(adev) != 0)
356 goto reschedule;
357
358 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);
359 return;
360
361 reschedule:
362 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);
363 }
364
vpe_common_init(struct amdgpu_vpe * vpe)365 static int vpe_common_init(struct amdgpu_vpe *vpe)
366 {
367 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);
368 int r;
369
370 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
371 AMDGPU_GEM_DOMAIN_GTT,
372 &adev->vpe.cmdbuf_obj,
373 &adev->vpe.cmdbuf_gpu_addr,
374 (void **)&adev->vpe.cmdbuf_cpu_addr);
375 if (r) {
376 dev_err(adev->dev, "VPE: failed to allocate cmdbuf bo %d\n", r);
377 return r;
378 }
379
380 vpe->context_started = false;
381 INIT_DELAYED_WORK(&adev->vpe.idle_work, vpe_idle_work_handler);
382
383 return 0;
384 }
385
vpe_sw_init(struct amdgpu_ip_block * ip_block)386 static int vpe_sw_init(struct amdgpu_ip_block *ip_block)
387 {
388 struct amdgpu_device *adev = ip_block->adev;
389 struct amdgpu_vpe *vpe = &adev->vpe;
390 int ret;
391
392 ret = vpe_common_init(vpe);
393 if (ret)
394 goto out;
395
396 ret = vpe_irq_init(vpe);
397 if (ret)
398 goto out;
399
400 ret = vpe_ring_init(vpe);
401 if (ret)
402 goto out;
403
404 ret = vpe_init_microcode(vpe);
405 if (ret)
406 goto out;
407
408 adev->vpe.supported_reset =
409 amdgpu_get_soft_full_reset_mask(&adev->vpe.ring);
410 if (!amdgpu_sriov_vf(adev))
411 adev->vpe.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
412 ret = amdgpu_vpe_sysfs_reset_mask_init(adev);
413 if (ret)
414 goto out;
415 out:
416 return ret;
417 }
418
vpe_sw_fini(struct amdgpu_ip_block * ip_block)419 static int vpe_sw_fini(struct amdgpu_ip_block *ip_block)
420 {
421 struct amdgpu_device *adev = ip_block->adev;
422 struct amdgpu_vpe *vpe = &adev->vpe;
423
424 release_firmware(vpe->fw);
425 vpe->fw = NULL;
426
427 amdgpu_vpe_sysfs_reset_mask_fini(adev);
428 vpe_ring_fini(vpe);
429
430 amdgpu_bo_free_kernel(&adev->vpe.cmdbuf_obj,
431 &adev->vpe.cmdbuf_gpu_addr,
432 (void **)&adev->vpe.cmdbuf_cpu_addr);
433
434 return 0;
435 }
436
vpe_hw_init(struct amdgpu_ip_block * ip_block)437 static int vpe_hw_init(struct amdgpu_ip_block *ip_block)
438 {
439 struct amdgpu_device *adev = ip_block->adev;
440 struct amdgpu_vpe *vpe = &adev->vpe;
441 int ret;
442
443 /* Power on VPE */
444 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,
445 AMD_PG_STATE_UNGATE);
446 if (ret)
447 return ret;
448
449 ret = vpe_load_microcode(vpe);
450 if (ret)
451 return ret;
452
453 ret = vpe_ring_start(vpe);
454 if (ret)
455 return ret;
456
457 return 0;
458 }
459
vpe_hw_fini(struct amdgpu_ip_block * ip_block)460 static int vpe_hw_fini(struct amdgpu_ip_block *ip_block)
461 {
462 struct amdgpu_device *adev = ip_block->adev;
463 struct amdgpu_vpe *vpe = &adev->vpe;
464
465 cancel_delayed_work_sync(&adev->vpe.idle_work);
466
467 vpe_ring_stop(vpe);
468
469 /* Power off VPE */
470 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);
471
472 return 0;
473 }
474
vpe_suspend(struct amdgpu_ip_block * ip_block)475 static int vpe_suspend(struct amdgpu_ip_block *ip_block)
476 {
477 return vpe_hw_fini(ip_block);
478 }
479
vpe_resume(struct amdgpu_ip_block * ip_block)480 static int vpe_resume(struct amdgpu_ip_block *ip_block)
481 {
482 return vpe_hw_init(ip_block);
483 }
484
vpe_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)485 static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
486 {
487 int i;
488
489 for (i = 0; i < count; i++)
490 if (i == 0)
491 amdgpu_ring_write(ring, ring->funcs->nop |
492 VPE_CMD_NOP_HEADER_COUNT(count - 1));
493 else
494 amdgpu_ring_write(ring, ring->funcs->nop);
495 }
496
vpe_get_csa_mc_addr(struct amdgpu_ring * ring,uint32_t vmid)497 static uint64_t vpe_get_csa_mc_addr(struct amdgpu_ring *ring, uint32_t vmid)
498 {
499 struct amdgpu_device *adev = ring->adev;
500 uint32_t index = 0;
501 uint64_t csa_mc_addr;
502
503 if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev->gfx.mcbp)
504 return 0;
505
506 csa_mc_addr = amdgpu_csa_vaddr(adev) + AMDGPU_CSA_VPE_OFFSET +
507 index * AMDGPU_CSA_VPE_SIZE;
508
509 return csa_mc_addr;
510 }
511
vpe_ring_emit_pred_exec(struct amdgpu_ring * ring,uint32_t device_select,uint32_t exec_count)512 static void vpe_ring_emit_pred_exec(struct amdgpu_ring *ring,
513 uint32_t device_select,
514 uint32_t exec_count)
515 {
516 if (!ring->adev->vpe.collaborate_mode)
517 return;
518
519 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) |
520 (device_select << 16));
521 amdgpu_ring_write(ring, exec_count & 0x1fff);
522 }
523
vpe_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)524 static void vpe_ring_emit_ib(struct amdgpu_ring *ring,
525 struct amdgpu_job *job,
526 struct amdgpu_ib *ib,
527 uint32_t flags)
528 {
529 uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
530 uint64_t csa_mc_addr = vpe_get_csa_mc_addr(ring, vmid);
531
532 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) |
533 VPE_CMD_INDIRECT_HEADER_VMID(vmid & 0xf));
534
535 /* base must be 32 byte aligned */
536 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0);
537 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
538 amdgpu_ring_write(ring, ib->length_dw);
539 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
540 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
541 }
542
vpe_ring_emit_fence(struct amdgpu_ring * ring,uint64_t addr,uint64_t seq,unsigned int flags)543 static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr,
544 uint64_t seq, unsigned int flags)
545 {
546 int i = 0;
547
548 do {
549 /* write the fence */
550 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0));
551 /* zero in first two bits */
552 WARN_ON_ONCE(addr & 0x3);
553 amdgpu_ring_write(ring, lower_32_bits(addr));
554 amdgpu_ring_write(ring, upper_32_bits(addr));
555 amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq));
556 addr += 4;
557 } while ((flags & AMDGPU_FENCE_FLAG_64BIT) && (i++ < 1));
558
559 if (flags & AMDGPU_FENCE_FLAG_INT) {
560 /* generate an interrupt */
561 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_TRAP, 0));
562 amdgpu_ring_write(ring, 0);
563 }
564
565 /* WA: Force sync after TRAP to avoid VPE1 fail to power off */
566 if (ring->adev->vpe.collaborate_mode) {
567 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COLLAB_SYNC, 0));
568 amdgpu_ring_write(ring, 0xabcd);
569 }
570 }
571
vpe_ring_emit_pipeline_sync(struct amdgpu_ring * ring)572 static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
573 {
574 uint32_t seq = ring->fence_drv.sync_seq;
575 uint64_t addr = ring->fence_drv.gpu_addr;
576
577 vpe_ring_emit_pred_exec(ring, 0, 6);
578
579 /* wait for idle */
580 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM,
581 VPE_POLL_REGMEM_SUBOP_REGMEM) |
582 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
583 VPE_CMD_POLL_REGMEM_HEADER_MEM(1));
584 amdgpu_ring_write(ring, addr & 0xfffffffc);
585 amdgpu_ring_write(ring, upper_32_bits(addr));
586 amdgpu_ring_write(ring, seq); /* reference */
587 amdgpu_ring_write(ring, 0xffffffff); /* mask */
588 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
589 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(4));
590 }
591
vpe_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)592 static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
593 {
594 vpe_ring_emit_pred_exec(ring, 0, 3);
595
596 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_REG_WRITE, 0));
597 amdgpu_ring_write(ring, reg << 2);
598 amdgpu_ring_write(ring, val);
599 }
600
vpe_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)601 static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
602 uint32_t val, uint32_t mask)
603 {
604 vpe_ring_emit_pred_exec(ring, 0, 6);
605
606 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM,
607 VPE_POLL_REGMEM_SUBOP_REGMEM) |
608 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
609 VPE_CMD_POLL_REGMEM_HEADER_MEM(0));
610 amdgpu_ring_write(ring, reg << 2);
611 amdgpu_ring_write(ring, 0);
612 amdgpu_ring_write(ring, val); /* reference */
613 amdgpu_ring_write(ring, mask); /* mask */
614 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
615 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(10));
616 }
617
vpe_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)618 static void vpe_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid,
619 uint64_t pd_addr)
620 {
621 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
622 }
623
vpe_ring_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)624 static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring,
625 uint64_t addr)
626 {
627 unsigned int ret;
628
629 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COND_EXE, 0));
630 amdgpu_ring_write(ring, lower_32_bits(addr));
631 amdgpu_ring_write(ring, upper_32_bits(addr));
632 amdgpu_ring_write(ring, 1);
633 ret = ring->wptr & ring->buf_mask;
634 amdgpu_ring_write(ring, 0);
635
636 return ret;
637 }
638
vpe_ring_preempt_ib(struct amdgpu_ring * ring)639 static int vpe_ring_preempt_ib(struct amdgpu_ring *ring)
640 {
641 struct amdgpu_device *adev = ring->adev;
642 struct amdgpu_vpe *vpe = &adev->vpe;
643 uint32_t preempt_reg = vpe->regs.queue0_preempt;
644 int i, r = 0;
645
646 /* assert preemption condition */
647 amdgpu_ring_set_preempt_cond_exec(ring, false);
648
649 /* emit the trailing fence */
650 ring->trail_seq += 1;
651 amdgpu_ring_alloc(ring, 10);
652 vpe_ring_emit_fence(ring, ring->trail_fence_gpu_addr, ring->trail_seq, 0);
653 amdgpu_ring_commit(ring);
654
655 /* assert IB preemption */
656 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1);
657
658 /* poll the trailing fence */
659 for (i = 0; i < adev->usec_timeout; i++) {
660 if (ring->trail_seq ==
661 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
662 break;
663 udelay(1);
664 }
665
666 if (i >= adev->usec_timeout) {
667 r = -EINVAL;
668 dev_err(adev->dev, "ring %d failed to be preempted\n", ring->idx);
669 }
670
671 /* deassert IB preemption */
672 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0);
673
674 /* deassert the preemption condition */
675 amdgpu_ring_set_preempt_cond_exec(ring, true);
676
677 return r;
678 }
679
vpe_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)680 static int vpe_set_clockgating_state(struct amdgpu_ip_block *ip_block,
681 enum amd_clockgating_state state)
682 {
683 return 0;
684 }
685
vpe_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)686 static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block,
687 enum amd_powergating_state state)
688 {
689 struct amdgpu_device *adev = ip_block->adev;
690 struct amdgpu_vpe *vpe = &adev->vpe;
691
692 if (!adev->pm.dpm_enabled)
693 dev_err(adev->dev, "Without PM, cannot support powergating\n");
694
695 dev_dbg(adev->dev, "%s: %s!\n", __func__, (state == AMD_PG_STATE_GATE) ? "GATE":"UNGATE");
696
697 if (state == AMD_PG_STATE_GATE) {
698 amdgpu_dpm_enable_vpe(adev, false);
699 vpe->context_started = false;
700 } else {
701 amdgpu_dpm_enable_vpe(adev, true);
702 }
703
704 return 0;
705 }
706
vpe_ring_get_rptr(struct amdgpu_ring * ring)707 static uint64_t vpe_ring_get_rptr(struct amdgpu_ring *ring)
708 {
709 struct amdgpu_device *adev = ring->adev;
710 struct amdgpu_vpe *vpe = &adev->vpe;
711 uint64_t rptr;
712
713 if (ring->use_doorbell) {
714 rptr = atomic64_read((atomic64_t *)ring->rptr_cpu_addr);
715 dev_dbg(adev->dev, "rptr/doorbell before shift == 0x%016llx\n", rptr);
716 } else {
717 rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi));
718 rptr = rptr << 32;
719 rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo));
720 dev_dbg(adev->dev, "rptr before shift [%i] == 0x%016llx\n", ring->me, rptr);
721 }
722
723 return (rptr >> 2);
724 }
725
vpe_ring_get_wptr(struct amdgpu_ring * ring)726 static uint64_t vpe_ring_get_wptr(struct amdgpu_ring *ring)
727 {
728 struct amdgpu_device *adev = ring->adev;
729 struct amdgpu_vpe *vpe = &adev->vpe;
730 uint64_t wptr;
731
732 if (ring->use_doorbell) {
733 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
734 dev_dbg(adev->dev, "wptr/doorbell before shift == 0x%016llx\n", wptr);
735 } else {
736 wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi));
737 wptr = wptr << 32;
738 wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo));
739 dev_dbg(adev->dev, "wptr before shift [%i] == 0x%016llx\n", ring->me, wptr);
740 }
741
742 return (wptr >> 2);
743 }
744
vpe_ring_set_wptr(struct amdgpu_ring * ring)745 static void vpe_ring_set_wptr(struct amdgpu_ring *ring)
746 {
747 struct amdgpu_device *adev = ring->adev;
748 struct amdgpu_vpe *vpe = &adev->vpe;
749
750 if (ring->use_doorbell) {
751 dev_dbg(adev->dev, "Using doorbell, \
752 wptr_offs == 0x%08x, \
753 lower_32_bits(ring->wptr) << 2 == 0x%08x, \
754 upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
755 ring->wptr_offs,
756 lower_32_bits(ring->wptr << 2),
757 upper_32_bits(ring->wptr << 2));
758 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr << 2);
759 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
760 if (vpe->collaborate_mode)
761 WDOORBELL64(ring->doorbell_index + 4, ring->wptr << 2);
762 } else {
763 int i;
764
765 for (i = 0; i < vpe->num_instances; i++) {
766 dev_dbg(adev->dev, "Not using doorbell, \
767 regVPEC_QUEUE0_RB_WPTR == 0x%08x, \
768 regVPEC_QUEUE0_RB_WPTR_HI == 0x%08x\n",
769 lower_32_bits(ring->wptr << 2),
770 upper_32_bits(ring->wptr << 2));
771 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_lo),
772 lower_32_bits(ring->wptr << 2));
773 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_hi),
774 upper_32_bits(ring->wptr << 2));
775 }
776 }
777 }
778
vpe_ring_test_ring(struct amdgpu_ring * ring)779 static int vpe_ring_test_ring(struct amdgpu_ring *ring)
780 {
781 struct amdgpu_device *adev = ring->adev;
782 const uint32_t test_pattern = 0xdeadbeef;
783 uint32_t index, i;
784 uint64_t wb_addr;
785 int ret;
786
787 ret = amdgpu_device_wb_get(adev, &index);
788 if (ret) {
789 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret);
790 return ret;
791 }
792
793 adev->wb.wb[index] = 0;
794 wb_addr = adev->wb.gpu_addr + (index * 4);
795
796 ret = amdgpu_ring_alloc(ring, 4);
797 if (ret) {
798 dev_err(adev->dev, "dma failed to lock ring %d (%d).\n", ring->idx, ret);
799 goto out;
800 }
801
802 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0));
803 amdgpu_ring_write(ring, lower_32_bits(wb_addr));
804 amdgpu_ring_write(ring, upper_32_bits(wb_addr));
805 amdgpu_ring_write(ring, test_pattern);
806 amdgpu_ring_commit(ring);
807
808 for (i = 0; i < adev->usec_timeout; i++) {
809 if (le32_to_cpu(adev->wb.wb[index]) == test_pattern)
810 goto out;
811 udelay(1);
812 }
813
814 ret = -ETIMEDOUT;
815 out:
816 amdgpu_device_wb_free(adev, index);
817
818 return ret;
819 }
820
vpe_ring_test_ib(struct amdgpu_ring * ring,long timeout)821 static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout)
822 {
823 struct amdgpu_device *adev = ring->adev;
824 const uint32_t test_pattern = 0xdeadbeef;
825 struct amdgpu_ib ib = {};
826 struct dma_fence *f = NULL;
827 uint32_t index;
828 uint64_t wb_addr;
829 int ret;
830
831 ret = amdgpu_device_wb_get(adev, &index);
832 if (ret) {
833 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret);
834 return ret;
835 }
836
837 adev->wb.wb[index] = 0;
838 wb_addr = adev->wb.gpu_addr + (index * 4);
839
840 ret = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
841 if (ret)
842 goto err0;
843
844 ib.ptr[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0);
845 ib.ptr[1] = lower_32_bits(wb_addr);
846 ib.ptr[2] = upper_32_bits(wb_addr);
847 ib.ptr[3] = test_pattern;
848 ib.ptr[4] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
849 ib.ptr[5] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
850 ib.ptr[6] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
851 ib.ptr[7] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
852 ib.length_dw = 8;
853
854 ret = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
855 if (ret)
856 goto err1;
857
858 ret = dma_fence_wait_timeout(f, false, timeout);
859 if (ret <= 0) {
860 ret = ret ? : -ETIMEDOUT;
861 goto err1;
862 }
863
864 ret = (le32_to_cpu(adev->wb.wb[index]) == test_pattern) ? 0 : -EINVAL;
865
866 err1:
867 amdgpu_ib_free(&ib, NULL);
868 dma_fence_put(f);
869 err0:
870 amdgpu_device_wb_free(adev, index);
871
872 return ret;
873 }
874
vpe_ring_begin_use(struct amdgpu_ring * ring)875 static void vpe_ring_begin_use(struct amdgpu_ring *ring)
876 {
877 struct amdgpu_device *adev = ring->adev;
878 struct amdgpu_vpe *vpe = &adev->vpe;
879
880 cancel_delayed_work_sync(&adev->vpe.idle_work);
881
882 /* Power on VPE and notify VPE of new context */
883 if (!vpe->context_started) {
884 uint32_t context_notify;
885
886 /* Power on VPE */
887 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE);
888
889 /* Indicates that a job from a new context has been submitted. */
890 context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator));
891 if ((context_notify & 0x1) == 0)
892 context_notify |= 0x1;
893 else
894 context_notify &= ~(0x1);
895 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify);
896 vpe->context_started = true;
897 }
898 }
899
vpe_ring_end_use(struct amdgpu_ring * ring)900 static void vpe_ring_end_use(struct amdgpu_ring *ring)
901 {
902 struct amdgpu_device *adev = ring->adev;
903
904 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);
905 }
906
vpe_ring_reset(struct amdgpu_ring * ring,unsigned int vmid,struct amdgpu_fence * timedout_fence)907 static int vpe_ring_reset(struct amdgpu_ring *ring,
908 unsigned int vmid,
909 struct amdgpu_fence *timedout_fence)
910 {
911 struct amdgpu_device *adev = ring->adev;
912 int r;
913
914 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
915
916 r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,
917 AMD_PG_STATE_GATE);
918 if (r)
919 return r;
920 r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,
921 AMD_PG_STATE_UNGATE);
922 if (r)
923 return r;
924
925 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
926 }
927
amdgpu_get_vpe_reset_mask(struct device * dev,struct device_attribute * attr,char * buf)928 static ssize_t amdgpu_get_vpe_reset_mask(struct device *dev,
929 struct device_attribute *attr,
930 char *buf)
931 {
932 struct drm_device *ddev = dev_get_drvdata(dev);
933 struct amdgpu_device *adev = drm_to_adev(ddev);
934
935 if (!adev)
936 return -ENODEV;
937
938 return amdgpu_show_reset_mask(buf, adev->vpe.supported_reset);
939 }
940
941 static DEVICE_ATTR(vpe_reset_mask, 0444,
942 amdgpu_get_vpe_reset_mask, NULL);
943
amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device * adev)944 int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev)
945 {
946 int r = 0;
947
948 if (adev->vpe.num_instances) {
949 r = device_create_file(adev->dev, &dev_attr_vpe_reset_mask);
950 if (r)
951 return r;
952 }
953
954 return r;
955 }
956
amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device * adev)957 void amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device *adev)
958 {
959 if (adev->dev->kobj.sd) {
960 if (adev->vpe.num_instances)
961 device_remove_file(adev->dev, &dev_attr_vpe_reset_mask);
962 }
963 }
964
965 static const struct amdgpu_ring_funcs vpe_ring_funcs = {
966 .type = AMDGPU_RING_TYPE_VPE,
967 .align_mask = 0xf,
968 .nop = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0),
969 .support_64bit_ptrs = true,
970 .get_rptr = vpe_ring_get_rptr,
971 .get_wptr = vpe_ring_get_wptr,
972 .set_wptr = vpe_ring_set_wptr,
973 .emit_frame_size =
974 5 + /* vpe_ring_init_cond_exec */
975 6 + /* vpe_ring_emit_pipeline_sync */
976 12 + 12 + 12 + /* vpe_ring_emit_fence */
977 /* vpe_ring_emit_vm_flush */
978 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
979 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6,
980 .emit_ib_size = 7 + 6,
981 .emit_ib = vpe_ring_emit_ib,
982 .emit_pipeline_sync = vpe_ring_emit_pipeline_sync,
983 .emit_fence = vpe_ring_emit_fence,
984 .emit_vm_flush = vpe_ring_emit_vm_flush,
985 .emit_wreg = vpe_ring_emit_wreg,
986 .emit_reg_wait = vpe_ring_emit_reg_wait,
987 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
988 .insert_nop = vpe_ring_insert_nop,
989 .pad_ib = amdgpu_ring_generic_pad_ib,
990 .test_ring = vpe_ring_test_ring,
991 .test_ib = vpe_ring_test_ib,
992 .init_cond_exec = vpe_ring_init_cond_exec,
993 .preempt_ib = vpe_ring_preempt_ib,
994 .begin_use = vpe_ring_begin_use,
995 .end_use = vpe_ring_end_use,
996 .reset = vpe_ring_reset,
997 };
998
vpe_set_ring_funcs(struct amdgpu_device * adev)999 static void vpe_set_ring_funcs(struct amdgpu_device *adev)
1000 {
1001 adev->vpe.ring.funcs = &vpe_ring_funcs;
1002 }
1003
1004 const struct amd_ip_funcs vpe_ip_funcs = {
1005 .name = "vpe_v6_1",
1006 .early_init = vpe_early_init,
1007 .sw_init = vpe_sw_init,
1008 .sw_fini = vpe_sw_fini,
1009 .hw_init = vpe_hw_init,
1010 .hw_fini = vpe_hw_fini,
1011 .suspend = vpe_suspend,
1012 .resume = vpe_resume,
1013 .set_clockgating_state = vpe_set_clockgating_state,
1014 .set_powergating_state = vpe_set_powergating_state,
1015 };
1016
1017 const struct amdgpu_ip_block_version vpe_v6_1_ip_block = {
1018 .type = AMD_IP_BLOCK_TYPE_VPE,
1019 .major = 6,
1020 .minor = 1,
1021 .rev = 0,
1022 .funcs = &vpe_ip_funcs,
1023 };
1024