xref: /linux/drivers/pci/controller/vmd.c (revision 41cd3fd152634250fdd09a52a35352b3f323800d)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Volume Management Device driver
4  * Copyright (c) 2015, Intel Corporation.
5  */
6 
7 #include <linux/device.h>
8 #include <linux/interrupt.h>
9 #include <linux/irq.h>
10 #include <linux/irqchip/irq-msi-lib.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/msi.h>
14 #include <linux/pci.h>
15 #include <linux/pci-acpi.h>
16 #include <linux/pci-ecam.h>
17 #include <linux/srcu.h>
18 #include <linux/rculist.h>
19 #include <linux/rcupdate.h>
20 
21 #include <xen/xen.h>
22 
23 #include <asm/irqdomain.h>
24 
25 #define VMD_CFGBAR	0
26 #define VMD_MEMBAR1	2
27 #define VMD_MEMBAR2	4
28 
29 #define PCI_REG_VMCAP		0x40
30 #define BUS_RESTRICT_CAP(vmcap)	(vmcap & 0x1)
31 #define PCI_REG_VMCONFIG	0x44
32 #define BUS_RESTRICT_CFG(vmcfg)	((vmcfg >> 8) & 0x3)
33 #define VMCONFIG_MSI_REMAP	0x2
34 #define PCI_REG_VMLOCK		0x70
35 #define MB2_SHADOW_EN(vmlock)	(vmlock & 0x2)
36 
37 #define MB2_SHADOW_OFFSET	0x2000
38 #define MB2_SHADOW_SIZE		16
39 
40 enum vmd_features {
41 	/*
42 	 * Device may contain registers which hint the physical location of the
43 	 * membars, in order to allow proper address translation during
44 	 * resource assignment to enable guest virtualization
45 	 */
46 	VMD_FEAT_HAS_MEMBAR_SHADOW		= (1 << 0),
47 
48 	/*
49 	 * Device may provide root port configuration information which limits
50 	 * bus numbering
51 	 */
52 	VMD_FEAT_HAS_BUS_RESTRICTIONS		= (1 << 1),
53 
54 	/*
55 	 * Device contains physical location shadow registers in
56 	 * vendor-specific capability space
57 	 */
58 	VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP	= (1 << 2),
59 
60 	/*
61 	 * Device may use MSI-X vector 0 for software triggering and will not
62 	 * be used for MSI remapping
63 	 */
64 	VMD_FEAT_OFFSET_FIRST_VECTOR		= (1 << 3),
65 
66 	/*
67 	 * Device can bypass remapping MSI-X transactions into its MSI-X table,
68 	 * avoiding the requirement of a VMD MSI domain for child device
69 	 * interrupt handling.
70 	 */
71 	VMD_FEAT_CAN_BYPASS_MSI_REMAP		= (1 << 4),
72 
73 	/*
74 	 * Enable ASPM on the PCIE root ports and set the default LTR of the
75 	 * storage devices on platforms where these values are not configured by
76 	 * BIOS. This is needed for laptops, which require these settings for
77 	 * proper power management of the SoC.
78 	 */
79 	VMD_FEAT_BIOS_PM_QUIRK		= (1 << 5),
80 };
81 
82 #define VMD_BIOS_PM_QUIRK_LTR	0x1003	/* 3145728 ns */
83 
84 #define VMD_FEATS_CLIENT	(VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |	\
85 				 VMD_FEAT_HAS_BUS_RESTRICTIONS |	\
86 				 VMD_FEAT_OFFSET_FIRST_VECTOR |		\
87 				 VMD_FEAT_BIOS_PM_QUIRK)
88 
89 static DEFINE_IDA(vmd_instance_ida);
90 
91 /*
92  * Lock for manipulating VMD IRQ lists.
93  */
94 static DEFINE_RAW_SPINLOCK(list_lock);
95 
96 /**
97  * struct vmd_irq - private data to map driver IRQ to the VMD shared vector
98  * @node:	list item for parent traversal.
99  * @irq:	back pointer to parent.
100  * @enabled:	true if driver enabled IRQ
101  * @virq:	the virtual IRQ value provided to the requesting driver.
102  *
103  * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to
104  * a VMD IRQ using this structure.
105  */
106 struct vmd_irq {
107 	struct list_head	node;
108 	struct vmd_irq_list	*irq;
109 	bool			enabled;
110 	unsigned int		virq;
111 };
112 
113 /**
114  * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector
115  * @irq_list:	the list of irq's the VMD one demuxes to.
116  * @srcu:	SRCU struct for local synchronization.
117  * @count:	number of child IRQs assigned to this vector; used to track
118  *		sharing.
119  * @virq:	The underlying VMD Linux interrupt number
120  */
121 struct vmd_irq_list {
122 	struct list_head	irq_list;
123 	struct srcu_struct	srcu;
124 	unsigned int		count;
125 	unsigned int		virq;
126 };
127 
128 struct vmd_dev {
129 	struct pci_dev		*dev;
130 
131 	raw_spinlock_t		cfg_lock;
132 	void __iomem		*cfgbar;
133 
134 	int msix_count;
135 	struct vmd_irq_list	*irqs;
136 
137 	struct pci_sysdata	sysdata;
138 	struct resource		resources[3];
139 	struct irq_domain	*irq_domain;
140 	struct pci_bus		*bus;
141 	u8			busn_start;
142 	u8			first_vec;
143 	char			*name;
144 	int			instance;
145 };
146 
vmd_from_bus(struct pci_bus * bus)147 static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus)
148 {
149 	return container_of(bus->sysdata, struct vmd_dev, sysdata);
150 }
151 
index_from_irqs(struct vmd_dev * vmd,struct vmd_irq_list * irqs)152 static inline unsigned int index_from_irqs(struct vmd_dev *vmd,
153 					   struct vmd_irq_list *irqs)
154 {
155 	return irqs - vmd->irqs;
156 }
157 
158 /*
159  * Drivers managing a device in a VMD domain allocate their own IRQs as before,
160  * but the MSI entry for the hardware it's driving will be programmed with a
161  * destination ID for the VMD MSI-X table.  The VMD muxes interrupts in its
162  * domain into one of its own, and the VMD driver de-muxes these for the
163  * handlers sharing that VMD IRQ.  The vmd irq_domain provides the operations
164  * and irq_chip to set this up.
165  */
vmd_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)166 static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
167 {
168 	struct vmd_irq *vmdirq = data->chip_data;
169 	struct vmd_irq_list *irq = vmdirq->irq;
170 	struct vmd_dev *vmd = irq_data_get_irq_handler_data(data);
171 
172 	memset(msg, 0, sizeof(*msg));
173 	msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
174 	msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
175 	msg->arch_addr_lo.destid_0_7 = index_from_irqs(vmd, irq);
176 }
177 
vmd_irq_enable(struct irq_data * data)178 static void vmd_irq_enable(struct irq_data *data)
179 {
180 	struct vmd_irq *vmdirq = data->chip_data;
181 
182 	scoped_guard(raw_spinlock_irqsave, &list_lock) {
183 		WARN_ON(vmdirq->enabled);
184 		list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list);
185 		vmdirq->enabled = true;
186 	}
187 }
188 
vmd_pci_msi_enable(struct irq_data * data)189 static void vmd_pci_msi_enable(struct irq_data *data)
190 {
191 	vmd_irq_enable(data->parent_data);
192 	data->chip->irq_unmask(data);
193 }
194 
vmd_irq_disable(struct irq_data * data)195 static void vmd_irq_disable(struct irq_data *data)
196 {
197 	struct vmd_irq *vmdirq = data->chip_data;
198 
199 	scoped_guard(raw_spinlock_irqsave, &list_lock) {
200 		if (vmdirq->enabled) {
201 			list_del_rcu(&vmdirq->node);
202 			vmdirq->enabled = false;
203 		}
204 	}
205 }
206 
vmd_pci_msi_disable(struct irq_data * data)207 static void vmd_pci_msi_disable(struct irq_data *data)
208 {
209 	data->chip->irq_mask(data);
210 	vmd_irq_disable(data->parent_data);
211 }
212 
213 static struct irq_chip vmd_msi_controller = {
214 	.name			= "VMD-MSI",
215 	.irq_compose_msi_msg	= vmd_compose_msi_msg,
216 };
217 
218 /*
219  * XXX: We can be even smarter selecting the best IRQ once we solve the
220  * affinity problem.
221  */
vmd_next_irq(struct vmd_dev * vmd,struct msi_desc * desc)222 static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc)
223 {
224 	int i, best;
225 
226 	if (vmd->msix_count == 1 + vmd->first_vec)
227 		return &vmd->irqs[vmd->first_vec];
228 
229 	/*
230 	 * White list for fast-interrupt handlers. All others will share the
231 	 * "slow" interrupt vector.
232 	 */
233 	switch (msi_desc_to_pci_dev(desc)->class) {
234 	case PCI_CLASS_STORAGE_EXPRESS:
235 		break;
236 	default:
237 		return &vmd->irqs[vmd->first_vec];
238 	}
239 
240 	scoped_guard(raw_spinlock_irq, &list_lock) {
241 		best = vmd->first_vec + 1;
242 		for (i = best; i < vmd->msix_count; i++)
243 			if (vmd->irqs[i].count < vmd->irqs[best].count)
244 				best = i;
245 		vmd->irqs[best].count++;
246 	}
247 
248 	return &vmd->irqs[best];
249 }
250 
251 static void vmd_msi_free(struct irq_domain *domain, unsigned int virq,
252 			 unsigned int nr_irqs);
253 
vmd_msi_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)254 static int vmd_msi_alloc(struct irq_domain *domain, unsigned int virq,
255 			 unsigned int nr_irqs, void *arg)
256 {
257 	struct msi_desc *desc = ((msi_alloc_info_t *)arg)->desc;
258 	struct vmd_dev *vmd = domain->host_data;
259 	struct vmd_irq *vmdirq;
260 
261 	for (int i = 0; i < nr_irqs; ++i) {
262 		vmdirq = kzalloc(sizeof(*vmdirq), GFP_KERNEL);
263 		if (!vmdirq) {
264 			vmd_msi_free(domain, virq, i);
265 			return -ENOMEM;
266 		}
267 
268 		INIT_LIST_HEAD(&vmdirq->node);
269 		vmdirq->irq = vmd_next_irq(vmd, desc);
270 		vmdirq->virq = virq + i;
271 
272 		irq_domain_set_info(domain, virq + i, vmdirq->irq->virq,
273 				    &vmd_msi_controller, vmdirq,
274 				    handle_untracked_irq, vmd, NULL);
275 	}
276 
277 	return 0;
278 }
279 
vmd_msi_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)280 static void vmd_msi_free(struct irq_domain *domain, unsigned int virq,
281 			 unsigned int nr_irqs)
282 {
283 	struct irq_data *irq_data;
284 	struct vmd_irq *vmdirq;
285 
286 	for (int i = 0; i < nr_irqs; ++i) {
287 		irq_data = irq_domain_get_irq_data(domain, virq + i);
288 		vmdirq = irq_data->chip_data;
289 
290 		synchronize_srcu(&vmdirq->irq->srcu);
291 
292 		/* XXX: Potential optimization to rebalance */
293 		scoped_guard(raw_spinlock_irq, &list_lock)
294 			vmdirq->irq->count--;
295 
296 		kfree(vmdirq);
297 	}
298 }
299 
300 static const struct irq_domain_ops vmd_msi_domain_ops = {
301 	.alloc		= vmd_msi_alloc,
302 	.free		= vmd_msi_free,
303 };
304 
vmd_init_dev_msi_info(struct device * dev,struct irq_domain * domain,struct irq_domain * real_parent,struct msi_domain_info * info)305 static bool vmd_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
306 				  struct irq_domain *real_parent,
307 				  struct msi_domain_info *info)
308 {
309 	if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info))
310 		return false;
311 
312 	info->chip->irq_enable		= vmd_pci_msi_enable;
313 	info->chip->irq_disable		= vmd_pci_msi_disable;
314 	return true;
315 }
316 
317 #define VMD_MSI_FLAGS_SUPPORTED	(MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX)
318 #define VMD_MSI_FLAGS_REQUIRED	(MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_NO_AFFINITY)
319 
320 static const struct msi_parent_ops vmd_msi_parent_ops = {
321 	.supported_flags	= VMD_MSI_FLAGS_SUPPORTED,
322 	.required_flags		= VMD_MSI_FLAGS_REQUIRED,
323 	.bus_select_token	= DOMAIN_BUS_VMD_MSI,
324 	.bus_select_mask	= MATCH_PCI_MSI,
325 	.prefix			= "VMD-",
326 	.init_dev_msi_info	= vmd_init_dev_msi_info,
327 };
328 
vmd_create_irq_domain(struct vmd_dev * vmd)329 static int vmd_create_irq_domain(struct vmd_dev *vmd)
330 {
331 	struct irq_domain_info info = {
332 		.size		= vmd->msix_count,
333 		.ops		= &vmd_msi_domain_ops,
334 		.host_data	= vmd,
335 	};
336 
337 	info.fwnode = irq_domain_alloc_named_id_fwnode("VMD-MSI",
338 						       vmd->sysdata.domain);
339 	if (!info.fwnode)
340 		return -ENODEV;
341 
342 	vmd->irq_domain = msi_create_parent_irq_domain(&info,
343 						       &vmd_msi_parent_ops);
344 	if (!vmd->irq_domain) {
345 		irq_domain_free_fwnode(info.fwnode);
346 		return -ENODEV;
347 	}
348 
349 	return 0;
350 }
351 
vmd_set_msi_remapping(struct vmd_dev * vmd,bool enable)352 static void vmd_set_msi_remapping(struct vmd_dev *vmd, bool enable)
353 {
354 	u16 reg;
355 
356 	pci_read_config_word(vmd->dev, PCI_REG_VMCONFIG, &reg);
357 	reg = enable ? (reg & ~VMCONFIG_MSI_REMAP) :
358 		       (reg | VMCONFIG_MSI_REMAP);
359 	pci_write_config_word(vmd->dev, PCI_REG_VMCONFIG, reg);
360 }
361 
vmd_remove_irq_domain(struct vmd_dev * vmd)362 static void vmd_remove_irq_domain(struct vmd_dev *vmd)
363 {
364 	/*
365 	 * Some production BIOS won't enable remapping between soft reboots.
366 	 * Ensure remapping is restored before unloading the driver.
367 	 */
368 	if (!vmd->msix_count)
369 		vmd_set_msi_remapping(vmd, true);
370 
371 	if (vmd->irq_domain) {
372 		struct fwnode_handle *fn = vmd->irq_domain->fwnode;
373 
374 		irq_domain_remove(vmd->irq_domain);
375 		irq_domain_free_fwnode(fn);
376 	}
377 }
378 
vmd_cfg_addr(struct vmd_dev * vmd,struct pci_bus * bus,unsigned int devfn,int reg,int len)379 static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus,
380 				  unsigned int devfn, int reg, int len)
381 {
382 	unsigned int busnr_ecam = bus->number - vmd->busn_start;
383 	u32 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg);
384 
385 	if (offset + len >= resource_size(&vmd->dev->resource[VMD_CFGBAR]))
386 		return NULL;
387 
388 	return vmd->cfgbar + offset;
389 }
390 
391 /*
392  * CPU may deadlock if config space is not serialized on some versions of this
393  * hardware, so all config space access is done under a spinlock.
394  */
vmd_pci_read(struct pci_bus * bus,unsigned int devfn,int reg,int len,u32 * value)395 static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg,
396 			int len, u32 *value)
397 {
398 	struct vmd_dev *vmd = vmd_from_bus(bus);
399 	void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
400 
401 	if (!addr)
402 		return -EFAULT;
403 
404 	guard(raw_spinlock_irqsave)(&vmd->cfg_lock);
405 	switch (len) {
406 	case 1:
407 		*value = readb(addr);
408 		return 0;
409 	case 2:
410 		*value = readw(addr);
411 		return 0;
412 	case 4:
413 		*value = readl(addr);
414 		return 0;
415 	default:
416 		return -EINVAL;
417 	}
418 }
419 
420 /*
421  * VMD h/w converts non-posted config writes to posted memory writes. The
422  * read-back in this function forces the completion so it returns only after
423  * the config space was written, as expected.
424  */
vmd_pci_write(struct pci_bus * bus,unsigned int devfn,int reg,int len,u32 value)425 static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg,
426 			 int len, u32 value)
427 {
428 	struct vmd_dev *vmd = vmd_from_bus(bus);
429 	void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
430 
431 	if (!addr)
432 		return -EFAULT;
433 
434 	guard(raw_spinlock_irqsave)(&vmd->cfg_lock);
435 	switch (len) {
436 	case 1:
437 		writeb(value, addr);
438 		readb(addr);
439 		return 0;
440 	case 2:
441 		writew(value, addr);
442 		readw(addr);
443 		return 0;
444 	case 4:
445 		writel(value, addr);
446 		readl(addr);
447 		return 0;
448 	default:
449 		return -EINVAL;
450 	}
451 }
452 
453 static struct pci_ops vmd_ops = {
454 	.read		= vmd_pci_read,
455 	.write		= vmd_pci_write,
456 };
457 
458 #ifdef CONFIG_ACPI
vmd_acpi_find_companion(struct pci_dev * pci_dev)459 static struct acpi_device *vmd_acpi_find_companion(struct pci_dev *pci_dev)
460 {
461 	struct pci_host_bridge *bridge;
462 	u32 busnr, addr;
463 
464 	if (pci_dev->bus->ops != &vmd_ops)
465 		return NULL;
466 
467 	bridge = pci_find_host_bridge(pci_dev->bus);
468 	busnr = pci_dev->bus->number - bridge->bus->number;
469 	/*
470 	 * The address computation below is only applicable to relative bus
471 	 * numbers below 32.
472 	 */
473 	if (busnr > 31)
474 		return NULL;
475 
476 	addr = (busnr << 24) | ((u32)pci_dev->devfn << 16) | 0x8000FFFFU;
477 
478 	dev_dbg(&pci_dev->dev, "Looking for ACPI companion (address 0x%x)\n",
479 		addr);
480 
481 	return acpi_find_child_device(ACPI_COMPANION(bridge->dev.parent), addr,
482 				      false);
483 }
484 
485 static bool hook_installed;
486 
vmd_acpi_begin(void)487 static void vmd_acpi_begin(void)
488 {
489 	if (pci_acpi_set_companion_lookup_hook(vmd_acpi_find_companion))
490 		return;
491 
492 	hook_installed = true;
493 }
494 
vmd_acpi_end(void)495 static void vmd_acpi_end(void)
496 {
497 	if (!hook_installed)
498 		return;
499 
500 	pci_acpi_clear_companion_lookup_hook();
501 	hook_installed = false;
502 }
503 #else
vmd_acpi_begin(void)504 static inline void vmd_acpi_begin(void) { }
vmd_acpi_end(void)505 static inline void vmd_acpi_end(void) { }
506 #endif /* CONFIG_ACPI */
507 
vmd_domain_reset(struct vmd_dev * vmd)508 static void vmd_domain_reset(struct vmd_dev *vmd)
509 {
510 	u16 bus, max_buses = resource_size(&vmd->resources[0]);
511 	u8 dev, functions, fn, hdr_type;
512 	char __iomem *base;
513 
514 	for (bus = 0; bus < max_buses; bus++) {
515 		for (dev = 0; dev < 32; dev++) {
516 			base = vmd->cfgbar + PCIE_ECAM_OFFSET(bus,
517 						PCI_DEVFN(dev, 0), 0);
518 
519 			hdr_type = readb(base + PCI_HEADER_TYPE);
520 
521 			functions = (hdr_type & PCI_HEADER_TYPE_MFD) ? 8 : 1;
522 			for (fn = 0; fn < functions; fn++) {
523 				base = vmd->cfgbar + PCIE_ECAM_OFFSET(bus,
524 						PCI_DEVFN(dev, fn), 0);
525 
526 				hdr_type = readb(base + PCI_HEADER_TYPE) &
527 						PCI_HEADER_TYPE_MASK;
528 
529 				if (hdr_type != PCI_HEADER_TYPE_BRIDGE ||
530 				    (readw(base + PCI_CLASS_DEVICE) !=
531 				     PCI_CLASS_BRIDGE_PCI))
532 					continue;
533 
534 				/*
535 				 * Temporarily disable the I/O range before updating
536 				 * PCI_IO_BASE.
537 				 */
538 				writel(0x0000ffff, base + PCI_IO_BASE_UPPER16);
539 				/* Update lower 16 bits of I/O base/limit */
540 				writew(0x00f0, base + PCI_IO_BASE);
541 				/* Update upper 16 bits of I/O base/limit */
542 				writel(0, base + PCI_IO_BASE_UPPER16);
543 
544 				/* MMIO Base/Limit */
545 				writel(0x0000fff0, base + PCI_MEMORY_BASE);
546 
547 				/* Prefetchable MMIO Base/Limit */
548 				writel(0, base + PCI_PREF_LIMIT_UPPER32);
549 				writel(0x0000fff0, base + PCI_PREF_MEMORY_BASE);
550 				writel(0xffffffff, base + PCI_PREF_BASE_UPPER32);
551 			}
552 		}
553 	}
554 }
555 
vmd_attach_resources(struct vmd_dev * vmd)556 static void vmd_attach_resources(struct vmd_dev *vmd)
557 {
558 	vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1];
559 	vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2];
560 }
561 
vmd_detach_resources(struct vmd_dev * vmd)562 static void vmd_detach_resources(struct vmd_dev *vmd)
563 {
564 	vmd->dev->resource[VMD_MEMBAR1].child = NULL;
565 	vmd->dev->resource[VMD_MEMBAR2].child = NULL;
566 }
567 
568 /*
569  * VMD domains start at 0x10000 to not clash with ACPI _SEG domains.
570  * Per ACPI r6.0, sec 6.5.6,  _SEG returns an integer, of which the lower
571  * 16 bits are the PCI Segment Group (domain) number.  Other bits are
572  * currently reserved.
573  */
vmd_find_free_domain(void)574 static int vmd_find_free_domain(void)
575 {
576 	int domain = 0xffff;
577 	struct pci_bus *bus = NULL;
578 
579 	while ((bus = pci_find_next_bus(bus)) != NULL)
580 		domain = max_t(int, domain, pci_domain_nr(bus));
581 	return domain + 1;
582 }
583 
vmd_get_phys_offsets(struct vmd_dev * vmd,bool native_hint,resource_size_t * offset1,resource_size_t * offset2)584 static int vmd_get_phys_offsets(struct vmd_dev *vmd, bool native_hint,
585 				resource_size_t *offset1,
586 				resource_size_t *offset2)
587 {
588 	struct pci_dev *dev = vmd->dev;
589 	u64 phys1, phys2;
590 
591 	if (native_hint) {
592 		u32 vmlock;
593 		int ret;
594 
595 		ret = pci_read_config_dword(dev, PCI_REG_VMLOCK, &vmlock);
596 		if (ret || PCI_POSSIBLE_ERROR(vmlock))
597 			return -ENODEV;
598 
599 		if (MB2_SHADOW_EN(vmlock)) {
600 			void __iomem *membar2;
601 
602 			membar2 = pci_iomap(dev, VMD_MEMBAR2, 0);
603 			if (!membar2)
604 				return -ENOMEM;
605 			phys1 = readq(membar2 + MB2_SHADOW_OFFSET);
606 			phys2 = readq(membar2 + MB2_SHADOW_OFFSET + 8);
607 			pci_iounmap(dev, membar2);
608 		} else
609 			return 0;
610 	} else {
611 		/* Hypervisor-Emulated Vendor-Specific Capability */
612 		int pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
613 		u32 reg, regu;
614 
615 		pci_read_config_dword(dev, pos + 4, &reg);
616 
617 		/* "SHDW" */
618 		if (pos && reg == 0x53484457) {
619 			pci_read_config_dword(dev, pos + 8, &reg);
620 			pci_read_config_dword(dev, pos + 12, &regu);
621 			phys1 = (u64) regu << 32 | reg;
622 
623 			pci_read_config_dword(dev, pos + 16, &reg);
624 			pci_read_config_dword(dev, pos + 20, &regu);
625 			phys2 = (u64) regu << 32 | reg;
626 		} else
627 			return 0;
628 	}
629 
630 	*offset1 = dev->resource[VMD_MEMBAR1].start -
631 			(phys1 & PCI_BASE_ADDRESS_MEM_MASK);
632 	*offset2 = dev->resource[VMD_MEMBAR2].start -
633 			(phys2 & PCI_BASE_ADDRESS_MEM_MASK);
634 
635 	return 0;
636 }
637 
vmd_get_bus_number_start(struct vmd_dev * vmd)638 static int vmd_get_bus_number_start(struct vmd_dev *vmd)
639 {
640 	struct pci_dev *dev = vmd->dev;
641 	u16 reg;
642 
643 	pci_read_config_word(dev, PCI_REG_VMCAP, &reg);
644 	if (BUS_RESTRICT_CAP(reg)) {
645 		pci_read_config_word(dev, PCI_REG_VMCONFIG, &reg);
646 
647 		switch (BUS_RESTRICT_CFG(reg)) {
648 		case 0:
649 			vmd->busn_start = 0;
650 			break;
651 		case 1:
652 			vmd->busn_start = 128;
653 			break;
654 		case 2:
655 			vmd->busn_start = 224;
656 			break;
657 		default:
658 			pci_err(dev, "Unknown Bus Offset Setting (%d)\n",
659 				BUS_RESTRICT_CFG(reg));
660 			return -ENODEV;
661 		}
662 	}
663 
664 	return 0;
665 }
666 
vmd_irq(int irq,void * data)667 static irqreturn_t vmd_irq(int irq, void *data)
668 {
669 	struct vmd_irq_list *irqs = data;
670 	struct vmd_irq *vmdirq;
671 	int idx;
672 
673 	idx = srcu_read_lock(&irqs->srcu);
674 	list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node)
675 		generic_handle_irq(vmdirq->virq);
676 	srcu_read_unlock(&irqs->srcu, idx);
677 
678 	return IRQ_HANDLED;
679 }
680 
vmd_alloc_irqs(struct vmd_dev * vmd)681 static int vmd_alloc_irqs(struct vmd_dev *vmd)
682 {
683 	struct pci_dev *dev = vmd->dev;
684 	int i, err;
685 
686 	vmd->msix_count = pci_msix_vec_count(dev);
687 	if (vmd->msix_count < 0)
688 		return -ENODEV;
689 
690 	vmd->msix_count = pci_alloc_irq_vectors(dev, vmd->first_vec + 1,
691 						vmd->msix_count, PCI_IRQ_MSIX);
692 	if (vmd->msix_count < 0)
693 		return vmd->msix_count;
694 
695 	vmd->irqs = devm_kcalloc(&dev->dev, vmd->msix_count, sizeof(*vmd->irqs),
696 				 GFP_KERNEL);
697 	if (!vmd->irqs)
698 		return -ENOMEM;
699 
700 	for (i = 0; i < vmd->msix_count; i++) {
701 		err = init_srcu_struct(&vmd->irqs[i].srcu);
702 		if (err)
703 			return err;
704 
705 		INIT_LIST_HEAD(&vmd->irqs[i].irq_list);
706 		vmd->irqs[i].virq = pci_irq_vector(dev, i);
707 		err = devm_request_irq(&dev->dev, vmd->irqs[i].virq,
708 				       vmd_irq, IRQF_NO_THREAD,
709 				       vmd->name, &vmd->irqs[i]);
710 		if (err)
711 			return err;
712 	}
713 
714 	return 0;
715 }
716 
717 /*
718  * Since VMD is an aperture to regular PCIe root ports, only allow it to
719  * control features that the OS is allowed to control on the physical PCI bus.
720  */
vmd_copy_host_bridge_flags(struct pci_host_bridge * root_bridge,struct pci_host_bridge * vmd_bridge)721 static void vmd_copy_host_bridge_flags(struct pci_host_bridge *root_bridge,
722 				       struct pci_host_bridge *vmd_bridge)
723 {
724 	vmd_bridge->native_pcie_hotplug = root_bridge->native_pcie_hotplug;
725 	vmd_bridge->native_shpc_hotplug = root_bridge->native_shpc_hotplug;
726 	vmd_bridge->native_aer = root_bridge->native_aer;
727 	vmd_bridge->native_pme = root_bridge->native_pme;
728 	vmd_bridge->native_ltr = root_bridge->native_ltr;
729 	vmd_bridge->native_dpc = root_bridge->native_dpc;
730 }
731 
732 /*
733  * Enable ASPM and LTR settings on devices that aren't configured by BIOS.
734  */
vmd_pm_enable_quirk(struct pci_dev * pdev,void * userdata)735 static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata)
736 {
737 	unsigned long features = *(unsigned long *)userdata;
738 	u16 ltr = VMD_BIOS_PM_QUIRK_LTR;
739 	u32 ltr_reg;
740 	int pos;
741 
742 	if (!(features & VMD_FEAT_BIOS_PM_QUIRK))
743 		return 0;
744 
745 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR);
746 	if (!pos)
747 		goto out_state_change;
748 
749 	/*
750 	 * Skip if the max snoop LTR is non-zero, indicating BIOS has set it
751 	 * so the LTR quirk is not needed.
752 	 */
753 	pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, &ltr_reg);
754 	if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK)))
755 		goto out_state_change;
756 
757 	/*
758 	 * Set the default values to the maximum required by the platform to
759 	 * allow the deepest power management savings. Write as a DWORD where
760 	 * the lower word is the max snoop latency and the upper word is the
761 	 * max non-snoop latency.
762 	 */
763 	ltr_reg = (ltr << 16) | ltr;
764 	pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg);
765 	pci_info(pdev, "VMD: Default LTR value set by driver\n");
766 
767 out_state_change:
768 	/*
769 	 * Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
770 	 * PCIe r6.0, sec 5.5.4.
771 	 */
772 	pci_set_power_state_locked(pdev, PCI_D0);
773 	pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL);
774 	return 0;
775 }
776 
vmd_enable_domain(struct vmd_dev * vmd,unsigned long features)777 static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
778 {
779 	struct pci_sysdata *sd = &vmd->sysdata;
780 	struct resource *res;
781 	u32 upper_bits;
782 	unsigned long flags;
783 	LIST_HEAD(resources);
784 	resource_size_t offset[2] = {0};
785 	resource_size_t membar2_offset = 0x2000;
786 	struct pci_bus *child;
787 	struct pci_dev *dev;
788 	int ret;
789 
790 	/*
791 	 * Shadow registers may exist in certain VMD device ids which allow
792 	 * guests to correctly assign host physical addresses to the root ports
793 	 * and child devices. These registers will either return the host value
794 	 * or 0, depending on an enable bit in the VMD device.
795 	 */
796 	if (features & VMD_FEAT_HAS_MEMBAR_SHADOW) {
797 		membar2_offset = MB2_SHADOW_OFFSET + MB2_SHADOW_SIZE;
798 		ret = vmd_get_phys_offsets(vmd, true, &offset[0], &offset[1]);
799 		if (ret)
800 			return ret;
801 	} else if (features & VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP) {
802 		ret = vmd_get_phys_offsets(vmd, false, &offset[0], &offset[1]);
803 		if (ret)
804 			return ret;
805 	}
806 
807 	/*
808 	 * Certain VMD devices may have a root port configuration option which
809 	 * limits the bus range to between 0-127, 128-255, or 224-255
810 	 */
811 	if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) {
812 		ret = vmd_get_bus_number_start(vmd);
813 		if (ret)
814 			return ret;
815 	}
816 
817 	res = &vmd->dev->resource[VMD_CFGBAR];
818 	vmd->resources[0] = (struct resource) {
819 		.name  = "VMD CFGBAR",
820 		.start = vmd->busn_start,
821 		.end   = vmd->busn_start + (resource_size(res) >> 20) - 1,
822 		.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED,
823 	};
824 
825 	/*
826 	 * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can
827 	 * put 32-bit resources in the window.
828 	 *
829 	 * There's no hardware reason why a 64-bit window *couldn't*
830 	 * contain a 32-bit resource, but pbus_size_mem() computes the
831 	 * bridge window size assuming a 64-bit window will contain no
832 	 * 32-bit resources.  __pci_assign_resource() enforces that
833 	 * artificial restriction to make sure everything will fit.
834 	 *
835 	 * The only way we could use a 64-bit non-prefetchable MEMBAR is
836 	 * if its address is <4GB so that we can convert it to a 32-bit
837 	 * resource.  To be visible to the host OS, all VMD endpoints must
838 	 * be initially configured by platform BIOS, which includes setting
839 	 * up these resources.  We can assume the device is configured
840 	 * according to the platform needs.
841 	 */
842 	res = &vmd->dev->resource[VMD_MEMBAR1];
843 	upper_bits = upper_32_bits(res->end);
844 	flags = res->flags & ~IORESOURCE_SIZEALIGN;
845 	if (!upper_bits)
846 		flags &= ~IORESOURCE_MEM_64;
847 	vmd->resources[1] = (struct resource) {
848 		.name  = "VMD MEMBAR1",
849 		.start = res->start,
850 		.end   = res->end,
851 		.flags = flags,
852 		.parent = res,
853 	};
854 
855 	res = &vmd->dev->resource[VMD_MEMBAR2];
856 	upper_bits = upper_32_bits(res->end);
857 	flags = res->flags & ~IORESOURCE_SIZEALIGN;
858 	if (!upper_bits)
859 		flags &= ~IORESOURCE_MEM_64;
860 	vmd->resources[2] = (struct resource) {
861 		.name  = "VMD MEMBAR2",
862 		.start = res->start + membar2_offset,
863 		.end   = res->end,
864 		.flags = flags,
865 		.parent = res,
866 	};
867 
868 	sd->vmd_dev = vmd->dev;
869 	sd->domain = vmd_find_free_domain();
870 	if (sd->domain < 0)
871 		return sd->domain;
872 
873 	sd->node = pcibus_to_node(vmd->dev->bus);
874 
875 	/*
876 	 * Currently MSI remapping must be enabled in guest passthrough mode
877 	 * due to some missing interrupt remapping plumbing. This is probably
878 	 * acceptable because the guest is usually CPU-limited and MSI
879 	 * remapping doesn't become a performance bottleneck.
880 	 */
881 	if (!(features & VMD_FEAT_CAN_BYPASS_MSI_REMAP) ||
882 	    offset[0] || offset[1]) {
883 		ret = vmd_alloc_irqs(vmd);
884 		if (ret)
885 			return ret;
886 
887 		vmd_set_msi_remapping(vmd, true);
888 
889 		ret = vmd_create_irq_domain(vmd);
890 		if (ret)
891 			return ret;
892 	} else {
893 		vmd_set_msi_remapping(vmd, false);
894 	}
895 
896 	pci_add_resource(&resources, &vmd->resources[0]);
897 	pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]);
898 	pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]);
899 
900 	vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start,
901 				       &vmd_ops, sd, &resources);
902 	if (!vmd->bus) {
903 		pci_free_resource_list(&resources);
904 		vmd_remove_irq_domain(vmd);
905 		return -ENODEV;
906 	}
907 
908 	vmd_copy_host_bridge_flags(pci_find_host_bridge(vmd->dev->bus),
909 				   to_pci_host_bridge(vmd->bus->bridge));
910 
911 	vmd_attach_resources(vmd);
912 	if (vmd->irq_domain)
913 		dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain);
914 	else
915 		dev_set_msi_domain(&vmd->bus->dev,
916 				   dev_get_msi_domain(&vmd->dev->dev));
917 
918 	WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj,
919 			       "domain"), "Can't create symlink to domain\n");
920 
921 	vmd_acpi_begin();
922 
923 	pci_scan_child_bus(vmd->bus);
924 	vmd_domain_reset(vmd);
925 
926 	/* When Intel VMD is enabled, the OS does not discover the Root Ports
927 	 * owned by Intel VMD within the MMCFG space. pci_reset_bus() applies
928 	 * a reset to the parent of the PCI device supplied as argument. This
929 	 * is why we pass a child device, so the reset can be triggered at
930 	 * the Intel bridge level and propagated to all the children in the
931 	 * hierarchy.
932 	 */
933 	list_for_each_entry(child, &vmd->bus->children, node) {
934 		if (!list_empty(&child->devices)) {
935 			dev = list_first_entry(&child->devices,
936 					       struct pci_dev, bus_list);
937 			ret = pci_reset_bus(dev);
938 			if (ret)
939 				pci_warn(dev, "can't reset device: %d\n", ret);
940 
941 			break;
942 		}
943 	}
944 
945 	pci_assign_unassigned_bus_resources(vmd->bus);
946 
947 	pci_walk_bus(vmd->bus, vmd_pm_enable_quirk, &features);
948 
949 	/*
950 	 * VMD root buses are virtual and don't return true on pci_is_pcie()
951 	 * and will fail pcie_bus_configure_settings() early. It can instead be
952 	 * run on each of the real root ports.
953 	 */
954 	list_for_each_entry(child, &vmd->bus->children, node)
955 		pcie_bus_configure_settings(child);
956 
957 	pci_bus_add_devices(vmd->bus);
958 
959 	vmd_acpi_end();
960 	return 0;
961 }
962 
vmd_probe(struct pci_dev * dev,const struct pci_device_id * id)963 static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id)
964 {
965 	unsigned long features = (unsigned long) id->driver_data;
966 	struct vmd_dev *vmd;
967 	int err;
968 
969 	if (xen_domain()) {
970 		/*
971 		 * Xen doesn't have knowledge about devices in the VMD bus
972 		 * because the config space of devices behind the VMD bridge is
973 		 * not known to Xen, and hence Xen cannot discover or configure
974 		 * them in any way.
975 		 *
976 		 * Bypass of MSI remapping won't work in that case as direct
977 		 * write by Linux to the MSI entries won't result in functional
978 		 * interrupts, as Xen is the entity that manages the host
979 		 * interrupt controller and must configure interrupts.  However
980 		 * multiplexing of interrupts by the VMD bridge will work under
981 		 * Xen, so force the usage of that mode which must always be
982 		 * supported by VMD bridges.
983 		 */
984 		features &= ~VMD_FEAT_CAN_BYPASS_MSI_REMAP;
985 	}
986 
987 	if (resource_size(&dev->resource[VMD_CFGBAR]) < (1 << 20))
988 		return -ENOMEM;
989 
990 	vmd = devm_kzalloc(&dev->dev, sizeof(*vmd), GFP_KERNEL);
991 	if (!vmd)
992 		return -ENOMEM;
993 
994 	vmd->dev = dev;
995 	vmd->instance = ida_alloc(&vmd_instance_ida, GFP_KERNEL);
996 	if (vmd->instance < 0)
997 		return vmd->instance;
998 
999 	vmd->name = devm_kasprintf(&dev->dev, GFP_KERNEL, "vmd%d",
1000 				   vmd->instance);
1001 	if (!vmd->name) {
1002 		err = -ENOMEM;
1003 		goto out_release_instance;
1004 	}
1005 
1006 	err = pcim_enable_device(dev);
1007 	if (err < 0)
1008 		goto out_release_instance;
1009 
1010 	vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0);
1011 	if (!vmd->cfgbar) {
1012 		err = -ENOMEM;
1013 		goto out_release_instance;
1014 	}
1015 
1016 	pci_set_master(dev);
1017 	if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) &&
1018 	    dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32))) {
1019 		err = -ENODEV;
1020 		goto out_release_instance;
1021 	}
1022 
1023 	if (features & VMD_FEAT_OFFSET_FIRST_VECTOR)
1024 		vmd->first_vec = 1;
1025 
1026 	raw_spin_lock_init(&vmd->cfg_lock);
1027 	pci_set_drvdata(dev, vmd);
1028 	err = vmd_enable_domain(vmd, features);
1029 	if (err)
1030 		goto out_release_instance;
1031 
1032 	dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n",
1033 		 vmd->sysdata.domain);
1034 	return 0;
1035 
1036  out_release_instance:
1037 	ida_free(&vmd_instance_ida, vmd->instance);
1038 	return err;
1039 }
1040 
vmd_cleanup_srcu(struct vmd_dev * vmd)1041 static void vmd_cleanup_srcu(struct vmd_dev *vmd)
1042 {
1043 	int i;
1044 
1045 	for (i = 0; i < vmd->msix_count; i++)
1046 		cleanup_srcu_struct(&vmd->irqs[i].srcu);
1047 }
1048 
vmd_remove(struct pci_dev * dev)1049 static void vmd_remove(struct pci_dev *dev)
1050 {
1051 	struct vmd_dev *vmd = pci_get_drvdata(dev);
1052 
1053 	pci_stop_root_bus(vmd->bus);
1054 	sysfs_remove_link(&vmd->dev->dev.kobj, "domain");
1055 	pci_remove_root_bus(vmd->bus);
1056 	vmd_cleanup_srcu(vmd);
1057 	vmd_detach_resources(vmd);
1058 	vmd_remove_irq_domain(vmd);
1059 	ida_free(&vmd_instance_ida, vmd->instance);
1060 }
1061 
vmd_shutdown(struct pci_dev * dev)1062 static void vmd_shutdown(struct pci_dev *dev)
1063 {
1064 	struct vmd_dev *vmd = pci_get_drvdata(dev);
1065 
1066 	vmd_remove_irq_domain(vmd);
1067 }
1068 
1069 #ifdef CONFIG_PM_SLEEP
vmd_suspend(struct device * dev)1070 static int vmd_suspend(struct device *dev)
1071 {
1072 	struct pci_dev *pdev = to_pci_dev(dev);
1073 	struct vmd_dev *vmd = pci_get_drvdata(pdev);
1074 	int i;
1075 
1076 	for (i = 0; i < vmd->msix_count; i++)
1077 		devm_free_irq(dev, vmd->irqs[i].virq, &vmd->irqs[i]);
1078 
1079 	return 0;
1080 }
1081 
vmd_resume(struct device * dev)1082 static int vmd_resume(struct device *dev)
1083 {
1084 	struct pci_dev *pdev = to_pci_dev(dev);
1085 	struct vmd_dev *vmd = pci_get_drvdata(pdev);
1086 	int err, i;
1087 
1088 	vmd_set_msi_remapping(vmd, !!vmd->irq_domain);
1089 
1090 	for (i = 0; i < vmd->msix_count; i++) {
1091 		err = devm_request_irq(dev, vmd->irqs[i].virq,
1092 				       vmd_irq, IRQF_NO_THREAD,
1093 				       vmd->name, &vmd->irqs[i]);
1094 		if (err)
1095 			return err;
1096 	}
1097 
1098 	return 0;
1099 }
1100 #endif
1101 static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume);
1102 
1103 static const struct pci_device_id vmd_ids[] = {
1104 	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_201D),
1105 		.driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP,},
1106 	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0),
1107 		.driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW |
1108 				VMD_FEAT_HAS_BUS_RESTRICTIONS |
1109 				VMD_FEAT_CAN_BYPASS_MSI_REMAP,},
1110 	{PCI_VDEVICE(INTEL, 0x467f),
1111 		.driver_data = VMD_FEATS_CLIENT,},
1112 	{PCI_VDEVICE(INTEL, 0x4c3d),
1113 		.driver_data = VMD_FEATS_CLIENT,},
1114 	{PCI_VDEVICE(INTEL, 0xa77f),
1115 		.driver_data = VMD_FEATS_CLIENT,},
1116 	{PCI_VDEVICE(INTEL, 0x7d0b),
1117 		.driver_data = VMD_FEATS_CLIENT,},
1118 	{PCI_VDEVICE(INTEL, 0xad0b),
1119 		.driver_data = VMD_FEATS_CLIENT,},
1120 	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
1121 		.driver_data = VMD_FEATS_CLIENT,},
1122 	{PCI_VDEVICE(INTEL, 0xb60b),
1123                 .driver_data = VMD_FEATS_CLIENT,},
1124 	{PCI_VDEVICE(INTEL, 0xb06f),
1125                 .driver_data = VMD_FEATS_CLIENT,},
1126 	{PCI_VDEVICE(INTEL, 0xb07f),
1127                 .driver_data = VMD_FEATS_CLIENT,},
1128 	{0,}
1129 };
1130 MODULE_DEVICE_TABLE(pci, vmd_ids);
1131 
1132 static struct pci_driver vmd_drv = {
1133 	.name		= "vmd",
1134 	.id_table	= vmd_ids,
1135 	.probe		= vmd_probe,
1136 	.remove		= vmd_remove,
1137 	.shutdown	= vmd_shutdown,
1138 	.driver		= {
1139 		.pm	= &vmd_dev_pm_ops,
1140 	},
1141 };
1142 module_pci_driver(vmd_drv);
1143 
1144 MODULE_AUTHOR("Intel Corporation");
1145 MODULE_DESCRIPTION("Volume Management Device driver");
1146 MODULE_LICENSE("GPL v2");
1147 MODULE_VERSION("0.6");
1148