1 /*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_damage_helper.h>
28 #include <drm/drm_fourcc.h>
29 #include <drm/drm_gem_atomic_helper.h>
30 #include <linux/virtio_dma_buf.h>
31 #include <drm/drm_managed.h>
32 #include <drm/drm_panic.h>
33 #include <drm/drm_print.h>
34
35 #include "virtgpu_drv.h"
36
37 static const uint32_t virtio_gpu_formats[] = {
38 DRM_FORMAT_HOST_XRGB8888,
39 };
40
41 static const uint32_t virtio_gpu_cursor_formats[] = {
42 DRM_FORMAT_HOST_ARGB8888,
43 };
44
virtio_gpu_translate_format(uint32_t drm_fourcc)45 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
46 {
47 uint32_t format;
48
49 switch (drm_fourcc) {
50 case DRM_FORMAT_XRGB8888:
51 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
52 break;
53 case DRM_FORMAT_ARGB8888:
54 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
55 break;
56 case DRM_FORMAT_BGRX8888:
57 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
58 break;
59 case DRM_FORMAT_BGRA8888:
60 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
61 break;
62 default:
63 /*
64 * This should not happen, we handle everything listed
65 * in virtio_gpu_formats[].
66 */
67 format = 0;
68 break;
69 }
70 WARN_ON(format == 0);
71 return format;
72 }
73
74 static struct
virtio_gpu_plane_duplicate_state(struct drm_plane * plane)75 drm_plane_state *virtio_gpu_plane_duplicate_state(struct drm_plane *plane)
76 {
77 struct virtio_gpu_plane_state *new;
78
79 if (WARN_ON(!plane->state))
80 return NULL;
81
82 new = kzalloc_obj(*new);
83 if (!new)
84 return NULL;
85
86 __drm_atomic_helper_plane_duplicate_state(plane, &new->base);
87
88 return &new->base;
89 }
90
91 static const struct drm_plane_funcs virtio_gpu_plane_funcs = {
92 .update_plane = drm_atomic_helper_update_plane,
93 .disable_plane = drm_atomic_helper_disable_plane,
94 .reset = drm_atomic_helper_plane_reset,
95 .atomic_duplicate_state = virtio_gpu_plane_duplicate_state,
96 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
97 };
98
virtio_gpu_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)99 static int virtio_gpu_plane_atomic_check(struct drm_plane *plane,
100 struct drm_atomic_state *state)
101 {
102 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
103 plane);
104 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
105 plane);
106 bool is_cursor = plane->type == DRM_PLANE_TYPE_CURSOR;
107 struct drm_crtc_state *crtc_state;
108 int ret;
109
110 if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc))
111 return 0;
112
113 /*
114 * Ignore damage clips if the framebuffer attached to the plane's state
115 * has changed since the last plane update (page-flip). In this case, a
116 * full plane update should happen because uploads are done per-buffer.
117 */
118 if (old_plane_state->fb != new_plane_state->fb)
119 new_plane_state->ignore_damage_clips = true;
120
121 crtc_state = drm_atomic_get_crtc_state(state,
122 new_plane_state->crtc);
123 if (IS_ERR(crtc_state))
124 return PTR_ERR(crtc_state);
125
126 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
127 DRM_PLANE_NO_SCALING,
128 DRM_PLANE_NO_SCALING,
129 is_cursor, true);
130 return ret;
131 }
132
133 /* For drm panic */
virtio_gpu_panic_update_dumb_bo(struct virtio_gpu_device * vgdev,struct drm_plane_state * state,struct drm_rect * rect)134 static int virtio_gpu_panic_update_dumb_bo(struct virtio_gpu_device *vgdev,
135 struct drm_plane_state *state,
136 struct drm_rect *rect)
137 {
138 struct virtio_gpu_object *bo =
139 gem_to_virtio_gpu_obj(state->fb->obj[0]);
140 struct virtio_gpu_object_array *objs;
141 uint32_t w = rect->x2 - rect->x1;
142 uint32_t h = rect->y2 - rect->y1;
143 uint32_t x = rect->x1;
144 uint32_t y = rect->y1;
145 uint32_t off = x * state->fb->format->cpp[0] +
146 y * state->fb->pitches[0];
147
148 objs = virtio_gpu_panic_array_alloc();
149 if (!objs)
150 return -ENOMEM;
151 virtio_gpu_array_add_obj(objs, &bo->base.base);
152
153 return virtio_gpu_panic_cmd_transfer_to_host_2d(vgdev, off, w, h, x, y,
154 objs);
155 }
156
virtio_gpu_update_dumb_bo(struct virtio_gpu_device * vgdev,struct drm_plane_state * state,struct drm_rect * rect)157 static void virtio_gpu_update_dumb_bo(struct virtio_gpu_device *vgdev,
158 struct drm_plane_state *state,
159 struct drm_rect *rect)
160 {
161 struct virtio_gpu_object *bo =
162 gem_to_virtio_gpu_obj(state->fb->obj[0]);
163 struct virtio_gpu_object_array *objs;
164 uint32_t w = rect->x2 - rect->x1;
165 uint32_t h = rect->y2 - rect->y1;
166 uint32_t x = rect->x1;
167 uint32_t y = rect->y1;
168 uint32_t off = x * state->fb->format->cpp[0] +
169 y * state->fb->pitches[0];
170
171 objs = virtio_gpu_array_alloc(1);
172 if (!objs)
173 return;
174 virtio_gpu_array_add_obj(objs, &bo->base.base);
175
176 virtio_gpu_cmd_transfer_to_host_2d(vgdev, off, w, h, x, y,
177 objs, NULL);
178 }
179
180 /* For drm_panic */
virtio_gpu_panic_resource_flush(struct drm_plane * plane,uint32_t x,uint32_t y,uint32_t width,uint32_t height)181 static void virtio_gpu_panic_resource_flush(struct drm_plane *plane,
182 uint32_t x, uint32_t y,
183 uint32_t width, uint32_t height)
184 {
185 struct drm_device *dev = plane->dev;
186 struct virtio_gpu_device *vgdev = dev->dev_private;
187 struct virtio_gpu_framebuffer *vgfb;
188 struct virtio_gpu_object *bo;
189
190 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
191 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
192
193 virtio_gpu_panic_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
194 width, height);
195 virtio_gpu_panic_notify(vgdev);
196 }
197
virtio_gpu_resource_flush(struct drm_plane * plane,uint32_t x,uint32_t y,uint32_t width,uint32_t height)198 static void virtio_gpu_resource_flush(struct drm_plane *plane,
199 uint32_t x, uint32_t y,
200 uint32_t width, uint32_t height)
201 {
202 struct drm_device *dev = plane->dev;
203 struct virtio_gpu_device *vgdev = dev->dev_private;
204 struct virtio_gpu_framebuffer *vgfb;
205 struct virtio_gpu_plane_state *vgplane_st;
206 struct virtio_gpu_object *bo;
207
208 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
209 vgplane_st = to_virtio_gpu_plane_state(plane->state);
210 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
211 if (vgplane_st->fence) {
212 struct virtio_gpu_object_array *objs;
213
214 objs = virtio_gpu_array_alloc(1);
215 if (!objs)
216 return;
217 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
218 if (virtio_gpu_lock_one_resv_uninterruptible(objs)) {
219 virtio_gpu_array_put_free(objs);
220 return;
221 }
222 virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
223 width, height, objs,
224 vgplane_st->fence);
225 virtio_gpu_notify(vgdev);
226 dma_fence_wait_timeout(&vgplane_st->fence->f, true,
227 msecs_to_jiffies(50));
228 } else {
229 virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
230 width, height, NULL, NULL);
231 virtio_gpu_notify(vgdev);
232 }
233 }
234
virtio_gpu_primary_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)235 static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
236 struct drm_atomic_state *state)
237 {
238 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
239 plane);
240 struct drm_device *dev = plane->dev;
241 struct virtio_gpu_device *vgdev = dev->dev_private;
242 struct virtio_gpu_output *output = NULL;
243 struct virtio_gpu_object *bo;
244 struct drm_rect rect;
245
246 if (plane->state->crtc)
247 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
248 if (old_state->crtc)
249 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
250 if (WARN_ON(!output))
251 return;
252
253 if (!plane->state->fb || !output->crtc.state->active) {
254 DRM_DEBUG("nofb\n");
255 virtio_gpu_cmd_set_scanout(vgdev, output->index, 0,
256 plane->state->src_w >> 16,
257 plane->state->src_h >> 16,
258 0, 0);
259 virtio_gpu_notify(vgdev);
260 return;
261 }
262
263 if (!drm_atomic_helper_damage_merged(old_state, plane->state, &rect))
264 return;
265
266 bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]);
267 if (bo->dumb)
268 virtio_gpu_update_dumb_bo(vgdev, plane->state, &rect);
269
270 if (plane->state->fb != old_state->fb ||
271 plane->state->src_w != old_state->src_w ||
272 plane->state->src_h != old_state->src_h ||
273 plane->state->src_x != old_state->src_x ||
274 plane->state->src_y != old_state->src_y ||
275 output->needs_modeset) {
276 output->needs_modeset = false;
277 DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n",
278 bo->hw_res_handle,
279 plane->state->crtc_w, plane->state->crtc_h,
280 plane->state->crtc_x, plane->state->crtc_y,
281 plane->state->src_w >> 16,
282 plane->state->src_h >> 16,
283 plane->state->src_x >> 16,
284 plane->state->src_y >> 16);
285
286 if (bo->host3d_blob || bo->guest_blob) {
287 virtio_gpu_cmd_set_scanout_blob
288 (vgdev, output->index, bo,
289 plane->state->fb,
290 plane->state->src_w >> 16,
291 plane->state->src_h >> 16,
292 plane->state->src_x >> 16,
293 plane->state->src_y >> 16);
294 } else {
295 virtio_gpu_cmd_set_scanout(vgdev, output->index,
296 bo->hw_res_handle,
297 plane->state->src_w >> 16,
298 plane->state->src_h >> 16,
299 plane->state->src_x >> 16,
300 plane->state->src_y >> 16);
301 }
302 }
303
304 virtio_gpu_resource_flush(plane,
305 rect.x1,
306 rect.y1,
307 rect.x2 - rect.x1,
308 rect.y2 - rect.y1);
309 }
310
virtio_gpu_prepare_imported_obj(struct drm_plane * plane,struct drm_plane_state * new_state,struct drm_gem_object * obj)311 static int virtio_gpu_prepare_imported_obj(struct drm_plane *plane,
312 struct drm_plane_state *new_state,
313 struct drm_gem_object *obj)
314 {
315 struct virtio_gpu_device *vgdev = plane->dev->dev_private;
316 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(obj);
317 struct dma_buf_attachment *attach = obj->import_attach;
318 struct dma_resv *resv = attach->dmabuf->resv;
319 struct virtio_gpu_mem_entry *ents = NULL;
320 unsigned int nents;
321 int ret;
322
323 dma_resv_lock(resv, NULL);
324
325 ret = dma_buf_pin(attach);
326 if (ret) {
327 dma_resv_unlock(resv);
328 return ret;
329 }
330
331 if (!bo->sgt) {
332 ret = virtgpu_dma_buf_import_sgt(&ents, &nents,
333 bo, attach);
334 if (ret)
335 goto err;
336
337 virtio_gpu_object_attach(vgdev, bo, ents, nents);
338 }
339
340 dma_resv_unlock(resv);
341 return 0;
342
343 err:
344 dma_buf_unpin(attach);
345 dma_resv_unlock(resv);
346 return ret;
347 }
348
virtio_gpu_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)349 static int virtio_gpu_plane_prepare_fb(struct drm_plane *plane,
350 struct drm_plane_state *new_state)
351 {
352 struct drm_device *dev = plane->dev;
353 struct virtio_gpu_device *vgdev = dev->dev_private;
354 struct virtio_gpu_framebuffer *vgfb;
355 struct virtio_gpu_plane_state *vgplane_st;
356 struct virtio_gpu_object *bo;
357 struct drm_gem_object *obj;
358 int ret;
359
360 if (!new_state->fb)
361 return 0;
362
363 vgfb = to_virtio_gpu_framebuffer(new_state->fb);
364 vgplane_st = to_virtio_gpu_plane_state(new_state);
365 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
366
367 drm_gem_plane_helper_prepare_fb(plane, new_state);
368
369 if (!bo || (plane->type == DRM_PLANE_TYPE_PRIMARY && !bo->guest_blob))
370 return 0;
371
372 obj = new_state->fb->obj[0];
373 if (bo->dumb || drm_gem_is_imported(obj)) {
374 vgplane_st->fence = virtio_gpu_fence_alloc(vgdev,
375 vgdev->fence_drv.context,
376 0);
377 if (!vgplane_st->fence)
378 return -ENOMEM;
379 }
380
381 if (drm_gem_is_imported(obj)) {
382 ret = virtio_gpu_prepare_imported_obj(plane, new_state, obj);
383 if (ret)
384 goto err_fence;
385 }
386
387 return 0;
388
389 err_fence:
390 if (vgplane_st->fence) {
391 dma_fence_put(&vgplane_st->fence->f);
392 vgplane_st->fence = NULL;
393 }
394
395 return ret;
396 }
397
virtio_gpu_cleanup_imported_obj(struct drm_gem_object * obj)398 static void virtio_gpu_cleanup_imported_obj(struct drm_gem_object *obj)
399 {
400 struct dma_buf_attachment *attach = obj->import_attach;
401 struct dma_resv *resv = attach->dmabuf->resv;
402
403 dma_resv_lock(resv, NULL);
404 dma_buf_unpin(attach);
405 dma_resv_unlock(resv);
406 }
407
virtio_gpu_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * state)408 static void virtio_gpu_plane_cleanup_fb(struct drm_plane *plane,
409 struct drm_plane_state *state)
410 {
411 struct virtio_gpu_plane_state *vgplane_st;
412 struct drm_gem_object *obj;
413
414 if (!state->fb)
415 return;
416
417 vgplane_st = to_virtio_gpu_plane_state(state);
418 if (vgplane_st->fence) {
419 dma_fence_put(&vgplane_st->fence->f);
420 vgplane_st->fence = NULL;
421 }
422
423 obj = state->fb->obj[0];
424 if (drm_gem_is_imported(obj))
425 virtio_gpu_cleanup_imported_obj(obj);
426 }
427
virtio_gpu_cursor_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)428 static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
429 struct drm_atomic_state *state)
430 {
431 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
432 plane);
433 struct drm_device *dev = plane->dev;
434 struct virtio_gpu_device *vgdev = dev->dev_private;
435 struct virtio_gpu_output *output = NULL;
436 struct virtio_gpu_framebuffer *vgfb;
437 struct virtio_gpu_plane_state *vgplane_st;
438 struct virtio_gpu_object *bo = NULL;
439 uint32_t handle;
440
441 if (plane->state->crtc)
442 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
443 if (old_state->crtc)
444 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
445 if (WARN_ON(!output))
446 return;
447
448 if (plane->state->fb) {
449 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
450 vgplane_st = to_virtio_gpu_plane_state(plane->state);
451 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
452 handle = bo->hw_res_handle;
453 } else {
454 handle = 0;
455 }
456
457 if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
458 /* new cursor -- update & wait */
459 struct virtio_gpu_object_array *objs;
460
461 objs = virtio_gpu_array_alloc(1);
462 if (!objs)
463 return;
464 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
465 if (virtio_gpu_lock_one_resv_uninterruptible(objs)) {
466 virtio_gpu_array_put_free(objs);
467 return;
468 }
469 virtio_gpu_cmd_transfer_to_host_2d
470 (vgdev, 0,
471 plane->state->crtc_w,
472 plane->state->crtc_h,
473 0, 0, objs, vgplane_st->fence);
474 virtio_gpu_notify(vgdev);
475 dma_fence_wait(&vgplane_st->fence->f, true);
476 }
477
478 if (plane->state->fb != old_state->fb) {
479 DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle,
480 plane->state->crtc_x,
481 plane->state->crtc_y,
482 plane->state->hotspot_x,
483 plane->state->hotspot_y);
484 output->cursor.hdr.type =
485 cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR);
486 output->cursor.resource_id = cpu_to_le32(handle);
487 if (plane->state->fb) {
488 output->cursor.hot_x =
489 cpu_to_le32(plane->state->hotspot_x);
490 output->cursor.hot_y =
491 cpu_to_le32(plane->state->hotspot_y);
492 } else {
493 output->cursor.hot_x = cpu_to_le32(0);
494 output->cursor.hot_y = cpu_to_le32(0);
495 }
496 } else {
497 DRM_DEBUG("move +%d+%d\n",
498 plane->state->crtc_x,
499 plane->state->crtc_y);
500 output->cursor.hdr.type =
501 cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR);
502 }
503 output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x);
504 output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y);
505 virtio_gpu_cursor_ping(vgdev, output);
506 }
507
virtio_drm_get_scanout_buffer(struct drm_plane * plane,struct drm_scanout_buffer * sb)508 static int virtio_drm_get_scanout_buffer(struct drm_plane *plane,
509 struct drm_scanout_buffer *sb)
510 {
511 struct virtio_gpu_object *bo;
512
513 if (!plane->state || !plane->state->fb || !plane->state->visible)
514 return -ENODEV;
515
516 bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]);
517
518 if (virtio_gpu_is_vram(bo) || drm_gem_is_imported(&bo->base.base))
519 return -ENODEV;
520
521 if (bo->base.vaddr) {
522 iosys_map_set_vaddr(&sb->map[0], bo->base.vaddr);
523 } else {
524 struct drm_gem_shmem_object *shmem = &bo->base;
525
526 if (!shmem->pages)
527 return -ENODEV;
528 /* map scanout buffer later */
529 sb->pages = shmem->pages;
530 }
531
532 sb->format = plane->state->fb->format;
533 sb->height = plane->state->fb->height;
534 sb->width = plane->state->fb->width;
535 sb->pitch[0] = plane->state->fb->pitches[0];
536 return 0;
537 }
538
virtio_panic_flush(struct drm_plane * plane)539 static void virtio_panic_flush(struct drm_plane *plane)
540 {
541 struct virtio_gpu_object *bo;
542 struct drm_device *dev = plane->dev;
543 struct virtio_gpu_device *vgdev = dev->dev_private;
544 struct drm_rect rect;
545
546 rect.x1 = 0;
547 rect.y1 = 0;
548 rect.x2 = plane->state->fb->width;
549 rect.y2 = plane->state->fb->height;
550
551 bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]);
552
553 if (bo->dumb) {
554 if (virtio_gpu_panic_update_dumb_bo(vgdev, plane->state,
555 &rect))
556 return;
557 }
558
559 virtio_gpu_panic_resource_flush(plane,
560 plane->state->src_x >> 16,
561 plane->state->src_y >> 16,
562 plane->state->src_w >> 16,
563 plane->state->src_h >> 16);
564 }
565
566 static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = {
567 .prepare_fb = virtio_gpu_plane_prepare_fb,
568 .cleanup_fb = virtio_gpu_plane_cleanup_fb,
569 .atomic_check = virtio_gpu_plane_atomic_check,
570 .atomic_update = virtio_gpu_primary_plane_update,
571 .get_scanout_buffer = virtio_drm_get_scanout_buffer,
572 .panic_flush = virtio_panic_flush,
573 };
574
575 static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = {
576 .prepare_fb = virtio_gpu_plane_prepare_fb,
577 .cleanup_fb = virtio_gpu_plane_cleanup_fb,
578 .atomic_check = virtio_gpu_plane_atomic_check,
579 .atomic_update = virtio_gpu_cursor_plane_update,
580 };
581
virtio_gpu_plane_init(struct virtio_gpu_device * vgdev,enum drm_plane_type type,int index)582 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
583 enum drm_plane_type type,
584 int index)
585 {
586 struct drm_device *dev = vgdev->ddev;
587 const struct drm_plane_helper_funcs *funcs;
588 struct drm_plane *plane;
589 const uint32_t *formats;
590 int nformats;
591
592 if (type == DRM_PLANE_TYPE_CURSOR) {
593 formats = virtio_gpu_cursor_formats;
594 nformats = ARRAY_SIZE(virtio_gpu_cursor_formats);
595 funcs = &virtio_gpu_cursor_helper_funcs;
596 } else {
597 formats = virtio_gpu_formats;
598 nformats = ARRAY_SIZE(virtio_gpu_formats);
599 funcs = &virtio_gpu_primary_helper_funcs;
600 }
601
602 plane = drmm_universal_plane_alloc(dev, struct drm_plane, dev,
603 1 << index, &virtio_gpu_plane_funcs,
604 formats, nformats, NULL, type, NULL);
605 if (IS_ERR(plane))
606 return plane;
607
608 drm_plane_helper_add(plane, funcs);
609
610 if (type == DRM_PLANE_TYPE_PRIMARY)
611 drm_plane_enable_fb_damage_clips(plane);
612
613 return plane;
614 }
615