1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/dmi.h>
28
29 #include <drm/drm_fixed.h>
30 #include <drm/drm_fourcc.h>
31 #include <drm/drm_framebuffer.h>
32 #include <drm/drm_modeset_helper_vtables.h>
33 #include <drm/drm_vblank.h>
34 #include <drm/radeon_drm.h>
35
36 #include "radeon.h"
37 #include "atom.h"
38 #include "atom-bits.h"
39
atombios_overscan_setup(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)40 static void atombios_overscan_setup(struct drm_crtc *crtc,
41 struct drm_display_mode *mode,
42 struct drm_display_mode *adjusted_mode)
43 {
44 struct drm_device *dev = crtc->dev;
45 struct radeon_device *rdev = dev->dev_private;
46 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
47 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
48 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
49 int a1, a2;
50
51 memset(&args, 0, sizeof(args));
52
53 args.ucCRTC = radeon_crtc->crtc_id;
54
55 switch (radeon_crtc->rmx_type) {
56 case RMX_CENTER:
57 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
58 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
59 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
60 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
61 break;
62 case RMX_ASPECT:
63 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
64 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
65
66 if (a1 > a2) {
67 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
68 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
69 } else if (a2 > a1) {
70 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
71 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
72 }
73 break;
74 case RMX_FULL:
75 default:
76 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
77 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
78 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
79 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
80 break;
81 }
82 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
83 }
84
atombios_scaler_setup(struct drm_crtc * crtc)85 static void atombios_scaler_setup(struct drm_crtc *crtc)
86 {
87 struct drm_device *dev = crtc->dev;
88 struct radeon_device *rdev = dev->dev_private;
89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
90 ENABLE_SCALER_PS_ALLOCATION args;
91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
92 struct radeon_encoder *radeon_encoder =
93 to_radeon_encoder(radeon_crtc->encoder);
94 /* fixme - fill in enc_priv for atom dac */
95 enum radeon_tv_std tv_std = TV_STD_NTSC;
96 bool is_tv = false, is_cv = false;
97
98 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
99 return;
100
101 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
102 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
103 tv_std = tv_dac->tv_std;
104 is_tv = true;
105 }
106
107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
111 if (is_tv) {
112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
140 } else if (is_cv) {
141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
166 }
167 }
168
atombios_lock_crtc(struct drm_crtc * crtc,int lock)169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170 {
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
184 }
185
atombios_enable_crtc(struct drm_crtc * crtc,int state)186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187 {
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
200 }
201
atombios_enable_crtc_memreq(struct drm_crtc * crtc,int state)202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203 {
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
216 }
217
218 static const u32 vga_control_regs[6] =
219 {
220 AVIVO_D1VGA_CONTROL,
221 AVIVO_D2VGA_CONTROL,
222 EVERGREEN_D3VGA_CONTROL,
223 EVERGREEN_D4VGA_CONTROL,
224 EVERGREEN_D5VGA_CONTROL,
225 EVERGREEN_D6VGA_CONTROL,
226 };
227
atombios_blank_crtc(struct drm_crtc * crtc,int state)228 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
229 {
230 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
231 struct drm_device *dev = crtc->dev;
232 struct radeon_device *rdev = dev->dev_private;
233 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
234 BLANK_CRTC_PS_ALLOCATION args;
235 u32 vga_control = 0;
236
237 memset(&args, 0, sizeof(args));
238
239 if (ASIC_IS_DCE8(rdev)) {
240 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
241 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
242 }
243
244 args.ucCRTC = radeon_crtc->crtc_id;
245 args.ucBlanking = state;
246
247 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
248
249 if (ASIC_IS_DCE8(rdev))
250 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
251 }
252
atombios_powergate_crtc(struct drm_crtc * crtc,int state)253 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
254 {
255 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
256 struct drm_device *dev = crtc->dev;
257 struct radeon_device *rdev = dev->dev_private;
258 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
259 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
260
261 memset(&args, 0, sizeof(args));
262
263 args.ucDispPipeId = radeon_crtc->crtc_id;
264 args.ucEnable = state;
265
266 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
267 }
268
atombios_crtc_dpms(struct drm_crtc * crtc,int mode)269 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
270 {
271 struct drm_device *dev = crtc->dev;
272 struct radeon_device *rdev = dev->dev_private;
273 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
274
275 switch (mode) {
276 case DRM_MODE_DPMS_ON:
277 radeon_crtc->enabled = true;
278 atombios_enable_crtc(crtc, ATOM_ENABLE);
279 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
280 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
281 atombios_blank_crtc(crtc, ATOM_DISABLE);
282 if (dev->num_crtcs > radeon_crtc->crtc_id)
283 drm_crtc_vblank_on(crtc);
284 radeon_crtc_load_lut(crtc);
285 break;
286 case DRM_MODE_DPMS_STANDBY:
287 case DRM_MODE_DPMS_SUSPEND:
288 case DRM_MODE_DPMS_OFF:
289 if (dev->num_crtcs > radeon_crtc->crtc_id)
290 drm_crtc_vblank_off(crtc);
291 if (radeon_crtc->enabled)
292 atombios_blank_crtc(crtc, ATOM_ENABLE);
293 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
294 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
295 atombios_enable_crtc(crtc, ATOM_DISABLE);
296 radeon_crtc->enabled = false;
297 break;
298 }
299 /* adjust pm to dpms */
300 radeon_pm_compute_clocks(rdev);
301 }
302
303 static void
atombios_set_crtc_dtd_timing(struct drm_crtc * crtc,struct drm_display_mode * mode)304 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
305 struct drm_display_mode *mode)
306 {
307 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
308 struct drm_device *dev = crtc->dev;
309 struct radeon_device *rdev = dev->dev_private;
310 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
311 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
312 u16 misc = 0;
313
314 memset(&args, 0, sizeof(args));
315 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
316 args.usH_Blanking_Time =
317 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
318 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
319 args.usV_Blanking_Time =
320 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
321 args.usH_SyncOffset =
322 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
323 args.usH_SyncWidth =
324 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
325 args.usV_SyncOffset =
326 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
327 args.usV_SyncWidth =
328 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
329 args.ucH_Border = radeon_crtc->h_border;
330 args.ucV_Border = radeon_crtc->v_border;
331
332 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
333 misc |= ATOM_VSYNC_POLARITY;
334 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
335 misc |= ATOM_HSYNC_POLARITY;
336 if (mode->flags & DRM_MODE_FLAG_CSYNC)
337 misc |= ATOM_COMPOSITESYNC;
338 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
339 misc |= ATOM_INTERLACE;
340 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
341 misc |= ATOM_DOUBLE_CLOCK_MODE;
342 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
343 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
344
345 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
346 args.ucCRTC = radeon_crtc->crtc_id;
347
348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
349 }
350
atombios_crtc_set_timing(struct drm_crtc * crtc,struct drm_display_mode * mode)351 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
352 struct drm_display_mode *mode)
353 {
354 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
355 struct drm_device *dev = crtc->dev;
356 struct radeon_device *rdev = dev->dev_private;
357 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
358 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
359 u16 misc = 0;
360
361 memset(&args, 0, sizeof(args));
362 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
363 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
364 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
365 args.usH_SyncWidth =
366 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
367 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
368 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
369 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
370 args.usV_SyncWidth =
371 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
372
373 args.ucOverscanRight = radeon_crtc->h_border;
374 args.ucOverscanLeft = radeon_crtc->h_border;
375 args.ucOverscanBottom = radeon_crtc->v_border;
376 args.ucOverscanTop = radeon_crtc->v_border;
377
378 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
379 misc |= ATOM_VSYNC_POLARITY;
380 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
381 misc |= ATOM_HSYNC_POLARITY;
382 if (mode->flags & DRM_MODE_FLAG_CSYNC)
383 misc |= ATOM_COMPOSITESYNC;
384 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
385 misc |= ATOM_INTERLACE;
386 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
387 misc |= ATOM_DOUBLE_CLOCK_MODE;
388 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
389 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
390
391 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
392 args.ucCRTC = radeon_crtc->crtc_id;
393
394 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
395 }
396
atombios_disable_ss(struct radeon_device * rdev,int pll_id)397 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
398 {
399 u32 ss_cntl;
400
401 if (ASIC_IS_DCE4(rdev)) {
402 switch (pll_id) {
403 case ATOM_PPLL1:
404 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
405 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
406 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
407 break;
408 case ATOM_PPLL2:
409 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
410 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
411 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
412 break;
413 case ATOM_DCPLL:
414 case ATOM_PPLL_INVALID:
415 return;
416 }
417 } else if (ASIC_IS_AVIVO(rdev)) {
418 switch (pll_id) {
419 case ATOM_PPLL1:
420 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
421 ss_cntl &= ~1;
422 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
423 break;
424 case ATOM_PPLL2:
425 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
426 ss_cntl &= ~1;
427 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
428 break;
429 case ATOM_DCPLL:
430 case ATOM_PPLL_INVALID:
431 return;
432 }
433 }
434 }
435
436
437 union atom_enable_ss {
438 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
439 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
440 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
441 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
442 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
443 };
444
atombios_crtc_program_ss(struct radeon_device * rdev,int enable,int pll_id,int crtc_id,struct radeon_atom_ss * ss)445 static void atombios_crtc_program_ss(struct radeon_device *rdev,
446 int enable,
447 int pll_id,
448 int crtc_id,
449 struct radeon_atom_ss *ss)
450 {
451 unsigned i;
452 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
453 union atom_enable_ss args;
454
455 if (enable) {
456 /* Don't mess with SS if percentage is 0 or external ss.
457 * SS is already disabled previously, and disabling it
458 * again can cause display problems if the pll is already
459 * programmed.
460 */
461 if (ss->percentage == 0)
462 return;
463 if (ss->type & ATOM_EXTERNAL_SS_MASK)
464 return;
465 } else {
466 for (i = 0; i < rdev->num_crtc; i++) {
467 if (rdev->mode_info.crtcs[i] &&
468 rdev->mode_info.crtcs[i]->enabled &&
469 i != crtc_id &&
470 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
471 /* one other crtc is using this pll don't turn
472 * off spread spectrum as it might turn off
473 * display on active crtc
474 */
475 return;
476 }
477 }
478 }
479
480 memset(&args, 0, sizeof(args));
481
482 if (ASIC_IS_DCE5(rdev)) {
483 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
484 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
485 switch (pll_id) {
486 case ATOM_PPLL1:
487 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
488 break;
489 case ATOM_PPLL2:
490 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
491 break;
492 case ATOM_DCPLL:
493 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
494 break;
495 case ATOM_PPLL_INVALID:
496 return;
497 }
498 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
499 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
500 args.v3.ucEnable = enable;
501 } else if (ASIC_IS_DCE4(rdev)) {
502 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
503 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
504 switch (pll_id) {
505 case ATOM_PPLL1:
506 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
507 break;
508 case ATOM_PPLL2:
509 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
510 break;
511 case ATOM_DCPLL:
512 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
513 break;
514 case ATOM_PPLL_INVALID:
515 return;
516 }
517 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
518 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
519 args.v2.ucEnable = enable;
520 } else if (ASIC_IS_DCE3(rdev)) {
521 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
522 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
523 args.v1.ucSpreadSpectrumStep = ss->step;
524 args.v1.ucSpreadSpectrumDelay = ss->delay;
525 args.v1.ucSpreadSpectrumRange = ss->range;
526 args.v1.ucPpll = pll_id;
527 args.v1.ucEnable = enable;
528 } else if (ASIC_IS_AVIVO(rdev)) {
529 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
530 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
531 atombios_disable_ss(rdev, pll_id);
532 return;
533 }
534 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
535 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
536 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
537 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
538 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
539 args.lvds_ss_2.ucEnable = enable;
540 } else {
541 if (enable == ATOM_DISABLE) {
542 atombios_disable_ss(rdev, pll_id);
543 return;
544 }
545 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
546 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
547 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
548 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
549 args.lvds_ss.ucEnable = enable;
550 }
551 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
552 }
553
554 union adjust_pixel_clock {
555 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
556 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
557 };
558
atombios_adjust_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)559 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
560 struct drm_display_mode *mode)
561 {
562 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
563 struct drm_device *dev = crtc->dev;
564 struct radeon_device *rdev = dev->dev_private;
565 struct drm_encoder *encoder = radeon_crtc->encoder;
566 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
567 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
568 u32 adjusted_clock = mode->clock;
569 int encoder_mode = atombios_get_encoder_mode(encoder);
570 u32 dp_clock = mode->clock;
571 u32 clock = mode->clock;
572 int bpc = radeon_crtc->bpc;
573 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
574
575 /* reset the pll flags */
576 radeon_crtc->pll_flags = 0;
577
578 if (ASIC_IS_AVIVO(rdev)) {
579 if ((rdev->family == CHIP_RS600) ||
580 (rdev->family == CHIP_RS690) ||
581 (rdev->family == CHIP_RS740))
582 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
583 RADEON_PLL_PREFER_CLOSEST_LOWER);
584
585 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
586 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
587 else
588 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
589
590 if (rdev->family < CHIP_RV770)
591 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
592 /* use frac fb div on APUs */
593 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
594 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
595 /* use frac fb div on RS780/RS880 */
596 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
597 && !radeon_crtc->ss_enabled)
598 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
599 if ((ASIC_IS_DCE32(rdev) || dmi_match(DMI_PRODUCT_NAME, "iMac11,1"))
600 && mode->clock > 165000)
601 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
602 } else {
603 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
604
605 if (mode->clock > 200000) /* range limits??? */
606 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
607 else
608 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
609 }
610
611 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
612 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
613 if (connector) {
614 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
615 struct radeon_connector_atom_dig *dig_connector =
616 radeon_connector->con_priv;
617
618 dp_clock = dig_connector->dp_clock;
619 }
620 }
621
622 /* use recommended ref_div for ss */
623 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
624 if (radeon_crtc->ss_enabled) {
625 if (radeon_crtc->ss.refdiv) {
626 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
627 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
628 if (ASIC_IS_AVIVO(rdev) &&
629 rdev->family != CHIP_RS780 &&
630 rdev->family != CHIP_RS880)
631 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
632 }
633 }
634 }
635
636 if (ASIC_IS_AVIVO(rdev)) {
637 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
638 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
639 adjusted_clock = mode->clock * 2;
640 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
641 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
642 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
643 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
644 } else {
645 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
646 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
647 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
648 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
649 }
650
651 /* adjust pll for deep color modes */
652 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
653 switch (bpc) {
654 case 8:
655 default:
656 break;
657 case 10:
658 clock = (clock * 5) / 4;
659 break;
660 case 12:
661 clock = (clock * 3) / 2;
662 break;
663 case 16:
664 clock = clock * 2;
665 break;
666 }
667 }
668
669 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
670 * accordingly based on the encoder/transmitter to work around
671 * special hw requirements.
672 */
673 if (ASIC_IS_DCE3(rdev)) {
674 union adjust_pixel_clock args;
675 u8 frev, crev;
676 int index;
677
678 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
679 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
680 &crev))
681 return adjusted_clock;
682
683 memset(&args, 0, sizeof(args));
684
685 switch (frev) {
686 case 1:
687 switch (crev) {
688 case 1:
689 case 2:
690 args.v1.usPixelClock = cpu_to_le16(clock / 10);
691 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
692 args.v1.ucEncodeMode = encoder_mode;
693 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
694 args.v1.ucConfig |=
695 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
696
697 atom_execute_table(rdev->mode_info.atom_context,
698 index, (uint32_t *)&args, sizeof(args));
699 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
700 break;
701 case 3:
702 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
703 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
704 args.v3.sInput.ucEncodeMode = encoder_mode;
705 args.v3.sInput.ucDispPllConfig = 0;
706 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
707 args.v3.sInput.ucDispPllConfig |=
708 DISPPLL_CONFIG_SS_ENABLE;
709 if (ENCODER_MODE_IS_DP(encoder_mode)) {
710 args.v3.sInput.ucDispPllConfig |=
711 DISPPLL_CONFIG_COHERENT_MODE;
712 /* 16200 or 27000 */
713 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
714 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
715 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
716 if (dig->coherent_mode)
717 args.v3.sInput.ucDispPllConfig |=
718 DISPPLL_CONFIG_COHERENT_MODE;
719 if (is_duallink)
720 args.v3.sInput.ucDispPllConfig |=
721 DISPPLL_CONFIG_DUAL_LINK;
722 }
723 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
724 ENCODER_OBJECT_ID_NONE)
725 args.v3.sInput.ucExtTransmitterID =
726 radeon_encoder_get_dp_bridge_encoder_id(encoder);
727 else
728 args.v3.sInput.ucExtTransmitterID = 0;
729
730 atom_execute_table(rdev->mode_info.atom_context,
731 index, (uint32_t *)&args, sizeof(args));
732 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
733 if (args.v3.sOutput.ucRefDiv) {
734 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
735 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
736 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
737 }
738 if (args.v3.sOutput.ucPostDiv) {
739 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
740 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
741 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
742 }
743 break;
744 default:
745 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
746 return adjusted_clock;
747 }
748 break;
749 default:
750 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
751 return adjusted_clock;
752 }
753 }
754 return adjusted_clock;
755 }
756
757 union set_pixel_clock {
758 SET_PIXEL_CLOCK_PS_ALLOCATION base;
759 PIXEL_CLOCK_PARAMETERS v1;
760 PIXEL_CLOCK_PARAMETERS_V2 v2;
761 PIXEL_CLOCK_PARAMETERS_V3 v3;
762 PIXEL_CLOCK_PARAMETERS_V5 v5;
763 PIXEL_CLOCK_PARAMETERS_V6 v6;
764 };
765
766 /* on DCE5, make sure the voltage is high enough to support the
767 * required disp clk.
768 */
atombios_crtc_set_disp_eng_pll(struct radeon_device * rdev,u32 dispclk)769 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
770 u32 dispclk)
771 {
772 u8 frev, crev;
773 int index;
774 union set_pixel_clock args;
775
776 memset(&args, 0, sizeof(args));
777
778 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
779 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
780 &crev))
781 return;
782
783 switch (frev) {
784 case 1:
785 switch (crev) {
786 case 5:
787 /* if the default dcpll clock is specified,
788 * SetPixelClock provides the dividers
789 */
790 args.v5.ucCRTC = ATOM_CRTC_INVALID;
791 args.v5.usPixelClock = cpu_to_le16(dispclk);
792 args.v5.ucPpll = ATOM_DCPLL;
793 break;
794 case 6:
795 /* if the default dcpll clock is specified,
796 * SetPixelClock provides the dividers
797 */
798 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
799 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
800 args.v6.ucPpll = ATOM_EXT_PLL1;
801 else if (ASIC_IS_DCE6(rdev))
802 args.v6.ucPpll = ATOM_PPLL0;
803 else
804 args.v6.ucPpll = ATOM_DCPLL;
805 break;
806 default:
807 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
808 return;
809 }
810 break;
811 default:
812 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
813 return;
814 }
815 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
816 }
817
atombios_crtc_program_pll(struct drm_crtc * crtc,u32 crtc_id,int pll_id,u32 encoder_mode,u32 encoder_id,u32 clock,u32 ref_div,u32 fb_div,u32 frac_fb_div,u32 post_div,int bpc,bool ss_enabled,struct radeon_atom_ss * ss)818 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
819 u32 crtc_id,
820 int pll_id,
821 u32 encoder_mode,
822 u32 encoder_id,
823 u32 clock,
824 u32 ref_div,
825 u32 fb_div,
826 u32 frac_fb_div,
827 u32 post_div,
828 int bpc,
829 bool ss_enabled,
830 struct radeon_atom_ss *ss)
831 {
832 struct drm_device *dev = crtc->dev;
833 struct radeon_device *rdev = dev->dev_private;
834 u8 frev, crev;
835 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
836 union set_pixel_clock args;
837
838 memset(&args, 0, sizeof(args));
839
840 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
841 &crev))
842 return;
843
844 switch (frev) {
845 case 1:
846 switch (crev) {
847 case 1:
848 if (clock == ATOM_DISABLE)
849 return;
850 args.v1.usPixelClock = cpu_to_le16(clock / 10);
851 args.v1.usRefDiv = cpu_to_le16(ref_div);
852 args.v1.usFbDiv = cpu_to_le16(fb_div);
853 args.v1.ucFracFbDiv = frac_fb_div;
854 args.v1.ucPostDiv = post_div;
855 args.v1.ucPpll = pll_id;
856 args.v1.ucCRTC = crtc_id;
857 args.v1.ucRefDivSrc = 1;
858 break;
859 case 2:
860 args.v2.usPixelClock = cpu_to_le16(clock / 10);
861 args.v2.usRefDiv = cpu_to_le16(ref_div);
862 args.v2.usFbDiv = cpu_to_le16(fb_div);
863 args.v2.ucFracFbDiv = frac_fb_div;
864 args.v2.ucPostDiv = post_div;
865 args.v2.ucPpll = pll_id;
866 args.v2.ucCRTC = crtc_id;
867 args.v2.ucRefDivSrc = 1;
868 break;
869 case 3:
870 args.v3.usPixelClock = cpu_to_le16(clock / 10);
871 args.v3.usRefDiv = cpu_to_le16(ref_div);
872 args.v3.usFbDiv = cpu_to_le16(fb_div);
873 args.v3.ucFracFbDiv = frac_fb_div;
874 args.v3.ucPostDiv = post_div;
875 args.v3.ucPpll = pll_id;
876 if (crtc_id == ATOM_CRTC2)
877 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
878 else
879 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
880 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
881 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
882 args.v3.ucTransmitterId = encoder_id;
883 args.v3.ucEncoderMode = encoder_mode;
884 break;
885 case 5:
886 args.v5.ucCRTC = crtc_id;
887 args.v5.usPixelClock = cpu_to_le16(clock / 10);
888 args.v5.ucRefDiv = ref_div;
889 args.v5.usFbDiv = cpu_to_le16(fb_div);
890 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
891 args.v5.ucPostDiv = post_div;
892 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
893 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
894 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
895 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
896 switch (bpc) {
897 case 8:
898 default:
899 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
900 break;
901 case 10:
902 /* yes this is correct, the atom define is wrong */
903 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
904 break;
905 case 12:
906 /* yes this is correct, the atom define is wrong */
907 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
908 break;
909 }
910 }
911 args.v5.ucTransmitterID = encoder_id;
912 args.v5.ucEncoderMode = encoder_mode;
913 args.v5.ucPpll = pll_id;
914 break;
915 case 6:
916 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
917 args.v6.ucRefDiv = ref_div;
918 args.v6.usFbDiv = cpu_to_le16(fb_div);
919 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
920 args.v6.ucPostDiv = post_div;
921 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
922 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
923 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
924 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
925 switch (bpc) {
926 case 8:
927 default:
928 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
929 break;
930 case 10:
931 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
932 break;
933 case 12:
934 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
935 break;
936 case 16:
937 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
938 break;
939 }
940 }
941 args.v6.ucTransmitterID = encoder_id;
942 args.v6.ucEncoderMode = encoder_mode;
943 args.v6.ucPpll = pll_id;
944 break;
945 default:
946 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
947 return;
948 }
949 break;
950 default:
951 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
952 return;
953 }
954
955 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
956 }
957
atombios_crtc_prepare_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)958 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
959 {
960 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
961 struct drm_device *dev = crtc->dev;
962 struct radeon_device *rdev = dev->dev_private;
963 struct radeon_encoder *radeon_encoder =
964 to_radeon_encoder(radeon_crtc->encoder);
965 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
966
967 radeon_crtc->bpc = 8;
968 radeon_crtc->ss_enabled = false;
969
970 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
971 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
972 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
973 struct drm_connector *connector =
974 radeon_get_connector_for_encoder(radeon_crtc->encoder);
975 struct radeon_connector *radeon_connector =
976 to_radeon_connector(connector);
977 struct radeon_connector_atom_dig *dig_connector =
978 radeon_connector->con_priv;
979 int dp_clock;
980
981 /* Assign mode clock for hdmi deep color max clock limit check */
982 radeon_connector->pixelclock_for_modeset = mode->clock;
983 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
984
985 switch (encoder_mode) {
986 case ATOM_ENCODER_MODE_DP_MST:
987 case ATOM_ENCODER_MODE_DP:
988 /* DP/eDP */
989 dp_clock = dig_connector->dp_clock / 10;
990 if (ASIC_IS_DCE4(rdev))
991 radeon_crtc->ss_enabled =
992 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
993 ASIC_INTERNAL_SS_ON_DP,
994 dp_clock);
995 else {
996 if (dp_clock == 16200) {
997 radeon_crtc->ss_enabled =
998 radeon_atombios_get_ppll_ss_info(rdev,
999 &radeon_crtc->ss,
1000 ATOM_DP_SS_ID2);
1001 if (!radeon_crtc->ss_enabled)
1002 radeon_crtc->ss_enabled =
1003 radeon_atombios_get_ppll_ss_info(rdev,
1004 &radeon_crtc->ss,
1005 ATOM_DP_SS_ID1);
1006 } else {
1007 radeon_crtc->ss_enabled =
1008 radeon_atombios_get_ppll_ss_info(rdev,
1009 &radeon_crtc->ss,
1010 ATOM_DP_SS_ID1);
1011 }
1012 /* disable spread spectrum on DCE3 DP */
1013 radeon_crtc->ss_enabled = false;
1014 }
1015 break;
1016 case ATOM_ENCODER_MODE_LVDS:
1017 if (ASIC_IS_DCE4(rdev))
1018 radeon_crtc->ss_enabled =
1019 radeon_atombios_get_asic_ss_info(rdev,
1020 &radeon_crtc->ss,
1021 dig->lcd_ss_id,
1022 mode->clock / 10);
1023 else
1024 radeon_crtc->ss_enabled =
1025 radeon_atombios_get_ppll_ss_info(rdev,
1026 &radeon_crtc->ss,
1027 dig->lcd_ss_id);
1028 break;
1029 case ATOM_ENCODER_MODE_DVI:
1030 if (ASIC_IS_DCE4(rdev))
1031 radeon_crtc->ss_enabled =
1032 radeon_atombios_get_asic_ss_info(rdev,
1033 &radeon_crtc->ss,
1034 ASIC_INTERNAL_SS_ON_TMDS,
1035 mode->clock / 10);
1036 break;
1037 case ATOM_ENCODER_MODE_HDMI:
1038 if (ASIC_IS_DCE4(rdev))
1039 radeon_crtc->ss_enabled =
1040 radeon_atombios_get_asic_ss_info(rdev,
1041 &radeon_crtc->ss,
1042 ASIC_INTERNAL_SS_ON_HDMI,
1043 mode->clock / 10);
1044 break;
1045 default:
1046 break;
1047 }
1048 }
1049
1050 /* adjust pixel clock as needed */
1051 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1052
1053 return true;
1054 }
1055
atombios_crtc_set_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)1056 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1057 {
1058 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1059 struct drm_device *dev = crtc->dev;
1060 struct radeon_device *rdev = dev->dev_private;
1061 struct radeon_encoder *radeon_encoder =
1062 to_radeon_encoder(radeon_crtc->encoder);
1063 u32 pll_clock = mode->clock;
1064 u32 clock = mode->clock;
1065 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1066 struct radeon_pll *pll;
1067 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1068
1069 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1070 if (ASIC_IS_DCE5(rdev) &&
1071 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1072 (radeon_crtc->bpc > 8))
1073 clock = radeon_crtc->adjusted_clock;
1074
1075 switch (radeon_crtc->pll_id) {
1076 case ATOM_PPLL1:
1077 pll = &rdev->clock.p1pll;
1078 break;
1079 case ATOM_PPLL2:
1080 pll = &rdev->clock.p2pll;
1081 break;
1082 case ATOM_DCPLL:
1083 case ATOM_PPLL_INVALID:
1084 default:
1085 pll = &rdev->clock.dcpll;
1086 break;
1087 }
1088
1089 /* update pll params */
1090 pll->flags = radeon_crtc->pll_flags;
1091 pll->reference_div = radeon_crtc->pll_reference_div;
1092 pll->post_div = radeon_crtc->pll_post_div;
1093
1094 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1095 /* TV seems to prefer the legacy algo on some boards */
1096 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1097 &fb_div, &frac_fb_div, &ref_div, &post_div);
1098 else if (ASIC_IS_AVIVO(rdev))
1099 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1100 &fb_div, &frac_fb_div, &ref_div, &post_div);
1101 else
1102 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1103 &fb_div, &frac_fb_div, &ref_div, &post_div);
1104
1105 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1106 radeon_crtc->crtc_id, &radeon_crtc->ss);
1107
1108 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1109 encoder_mode, radeon_encoder->encoder_id, clock,
1110 ref_div, fb_div, frac_fb_div, post_div,
1111 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1112
1113 if (radeon_crtc->ss_enabled) {
1114 /* calculate ss amount and step size */
1115 if (ASIC_IS_DCE4(rdev)) {
1116 u32 step_size;
1117 u32 amount = (((fb_div * 10) + frac_fb_div) *
1118 (u32)radeon_crtc->ss.percentage) /
1119 (100 * (u32)radeon_crtc->ss.percentage_divider);
1120 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1121 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1122 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1123 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1124 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1125 (125 * 25 * pll->reference_freq / 100);
1126 else
1127 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1128 (125 * 25 * pll->reference_freq / 100);
1129 radeon_crtc->ss.step = step_size;
1130 }
1131
1132 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1133 radeon_crtc->crtc_id, &radeon_crtc->ss);
1134 }
1135 }
1136
dce4_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y)1137 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1138 struct drm_framebuffer *fb,
1139 int x, int y)
1140 {
1141 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1142 struct drm_device *dev = crtc->dev;
1143 struct radeon_device *rdev = dev->dev_private;
1144 struct drm_framebuffer *target_fb;
1145 struct drm_gem_object *obj;
1146 struct radeon_bo *rbo;
1147 uint64_t fb_location;
1148 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1149 unsigned bankw, bankh, mtaspect, tile_split;
1150 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1151 u32 tmp, viewport_w, viewport_h;
1152 int r;
1153 bool bypass_lut = false;
1154
1155 /* no fb bound */
1156 if (!crtc->primary->fb) {
1157 DRM_DEBUG_KMS("No FB bound\n");
1158 return 0;
1159 }
1160
1161 target_fb = crtc->primary->fb;
1162
1163 obj = target_fb->obj[0];
1164 rbo = gem_to_radeon_bo(obj);
1165 r = radeon_bo_reserve(rbo, false);
1166 if (unlikely(r != 0))
1167 return r;
1168
1169 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1170 if (unlikely(r != 0)) {
1171 radeon_bo_unreserve(rbo);
1172 return -EINVAL;
1173 }
1174
1175 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1176 radeon_bo_unreserve(rbo);
1177
1178 switch (target_fb->format->format) {
1179 case DRM_FORMAT_C8:
1180 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1181 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1182 break;
1183 case DRM_FORMAT_XRGB4444:
1184 case DRM_FORMAT_ARGB4444:
1185 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1186 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1187 #ifdef __BIG_ENDIAN
1188 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1189 #endif
1190 break;
1191 case DRM_FORMAT_XRGB1555:
1192 case DRM_FORMAT_ARGB1555:
1193 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1194 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1195 #ifdef __BIG_ENDIAN
1196 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1197 #endif
1198 break;
1199 case DRM_FORMAT_BGRX5551:
1200 case DRM_FORMAT_BGRA5551:
1201 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1202 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1203 #ifdef __BIG_ENDIAN
1204 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1205 #endif
1206 break;
1207 case DRM_FORMAT_RGB565:
1208 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1209 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1210 #ifdef __BIG_ENDIAN
1211 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1212 #endif
1213 break;
1214 case DRM_FORMAT_XRGB8888:
1215 case DRM_FORMAT_ARGB8888:
1216 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1217 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1218 #ifdef __BIG_ENDIAN
1219 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1220 #endif
1221 break;
1222 case DRM_FORMAT_XRGB2101010:
1223 case DRM_FORMAT_ARGB2101010:
1224 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1225 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1226 #ifdef __BIG_ENDIAN
1227 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1228 #endif
1229 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1230 bypass_lut = true;
1231 break;
1232 case DRM_FORMAT_BGRX1010102:
1233 case DRM_FORMAT_BGRA1010102:
1234 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1235 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1236 #ifdef __BIG_ENDIAN
1237 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1238 #endif
1239 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1240 bypass_lut = true;
1241 break;
1242 case DRM_FORMAT_XBGR8888:
1243 case DRM_FORMAT_ABGR8888:
1244 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1245 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1246 fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) |
1247 EVERGREEN_GRPH_BLUE_CROSSBAR(EVERGREEN_GRPH_BLUE_SEL_R));
1248 #ifdef __BIG_ENDIAN
1249 fb_swap |= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1250 #endif
1251 break;
1252 default:
1253 DRM_ERROR("Unsupported screen format %p4cc\n",
1254 &target_fb->format->format);
1255 return -EINVAL;
1256 }
1257
1258 if (tiling_flags & RADEON_TILING_MACRO) {
1259 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1260
1261 /* Set NUM_BANKS. */
1262 if (rdev->family >= CHIP_TAHITI) {
1263 unsigned index, num_banks;
1264
1265 if (rdev->family >= CHIP_BONAIRE) {
1266 unsigned tileb, tile_split_bytes;
1267
1268 /* Calculate the macrotile mode index. */
1269 tile_split_bytes = 64 << tile_split;
1270 tileb = 8 * 8 * target_fb->format->cpp[0];
1271 tileb = min(tile_split_bytes, tileb);
1272
1273 for (index = 0; tileb > 64; index++)
1274 tileb >>= 1;
1275
1276 if (index >= 16) {
1277 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1278 target_fb->format->cpp[0] * 8,
1279 tile_split);
1280 return -EINVAL;
1281 }
1282
1283 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1284 } else {
1285 switch (target_fb->format->cpp[0] * 8) {
1286 case 8:
1287 index = 10;
1288 break;
1289 case 16:
1290 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1291 break;
1292 default:
1293 case 32:
1294 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1295 break;
1296 }
1297
1298 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1299 }
1300
1301 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1302 } else {
1303 /* NI and older. */
1304 if (rdev->family >= CHIP_CAYMAN)
1305 tmp = rdev->config.cayman.tile_config;
1306 else
1307 tmp = rdev->config.evergreen.tile_config;
1308
1309 switch ((tmp & 0xf0) >> 4) {
1310 case 0: /* 4 banks */
1311 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1312 break;
1313 case 1: /* 8 banks */
1314 default:
1315 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1316 break;
1317 case 2: /* 16 banks */
1318 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1319 break;
1320 }
1321 }
1322
1323 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1324 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1325 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1326 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1327 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1328 if (rdev->family >= CHIP_BONAIRE) {
1329 /* XXX need to know more about the surface tiling mode */
1330 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1331 }
1332 } else if (tiling_flags & RADEON_TILING_MICRO)
1333 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1334
1335 if (rdev->family >= CHIP_BONAIRE) {
1336 /* Read the pipe config from the 2D TILED SCANOUT mode.
1337 * It should be the same for the other modes too, but not all
1338 * modes set the pipe config field. */
1339 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1340
1341 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1342 } else if ((rdev->family == CHIP_TAHITI) ||
1343 (rdev->family == CHIP_PITCAIRN))
1344 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1345 else if ((rdev->family == CHIP_VERDE) ||
1346 (rdev->family == CHIP_OLAND) ||
1347 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1348 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1349
1350 switch (radeon_crtc->crtc_id) {
1351 case 0:
1352 WREG32(AVIVO_D1VGA_CONTROL, 0);
1353 break;
1354 case 1:
1355 WREG32(AVIVO_D2VGA_CONTROL, 0);
1356 break;
1357 case 2:
1358 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1359 break;
1360 case 3:
1361 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1362 break;
1363 case 4:
1364 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1365 break;
1366 case 5:
1367 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1368 break;
1369 default:
1370 break;
1371 }
1372
1373 /* Make sure surface address is updated at vertical blank rather than
1374 * horizontal blank
1375 */
1376 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1377
1378 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1379 upper_32_bits(fb_location));
1380 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1381 upper_32_bits(fb_location));
1382 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1383 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1384 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1385 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1386 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1387 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1388
1389 /*
1390 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1391 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1392 * retain the full precision throughout the pipeline.
1393 */
1394 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1395 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1396 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1397
1398 if (bypass_lut)
1399 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1400
1401 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1402 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1403 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1404 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1405 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1406 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1407
1408 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1409 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1410 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1411
1412 if (rdev->family >= CHIP_BONAIRE)
1413 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1414 target_fb->height);
1415 else
1416 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1417 target_fb->height);
1418 x &= ~3;
1419 y &= ~1;
1420 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1421 (x << 16) | y);
1422 viewport_w = crtc->mode.hdisplay;
1423 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1424 if ((rdev->family >= CHIP_BONAIRE) &&
1425 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1426 viewport_h *= 2;
1427 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1428 (viewport_w << 16) | viewport_h);
1429
1430 /* set pageflip to happen anywhere in vblank interval */
1431 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1432
1433 if (fb && fb != crtc->primary->fb) {
1434 rbo = gem_to_radeon_bo(fb->obj[0]);
1435 r = radeon_bo_reserve(rbo, false);
1436 if (unlikely(r != 0))
1437 return r;
1438 radeon_bo_unpin(rbo);
1439 radeon_bo_unreserve(rbo);
1440 }
1441
1442 /* Bytes per pixel may have changed */
1443 radeon_bandwidth_update(rdev);
1444
1445 return 0;
1446 }
1447
avivo_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y)1448 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1449 struct drm_framebuffer *fb,
1450 int x, int y)
1451 {
1452 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1453 struct drm_device *dev = crtc->dev;
1454 struct radeon_device *rdev = dev->dev_private;
1455 struct drm_gem_object *obj;
1456 struct radeon_bo *rbo;
1457 struct drm_framebuffer *target_fb;
1458 uint64_t fb_location;
1459 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1460 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1461 u32 viewport_w, viewport_h;
1462 int r;
1463 bool bypass_lut = false;
1464
1465 /* no fb bound */
1466 if (!crtc->primary->fb) {
1467 DRM_DEBUG_KMS("No FB bound\n");
1468 return 0;
1469 }
1470
1471 target_fb = crtc->primary->fb;
1472
1473 obj = target_fb->obj[0];
1474 rbo = gem_to_radeon_bo(obj);
1475 r = radeon_bo_reserve(rbo, false);
1476 if (unlikely(r != 0))
1477 return r;
1478
1479 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1480 if (unlikely(r != 0)) {
1481 radeon_bo_unreserve(rbo);
1482 return -EINVAL;
1483 }
1484 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1485 radeon_bo_unreserve(rbo);
1486
1487 switch (target_fb->format->format) {
1488 case DRM_FORMAT_C8:
1489 fb_format =
1490 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1491 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1492 break;
1493 case DRM_FORMAT_XRGB4444:
1494 case DRM_FORMAT_ARGB4444:
1495 fb_format =
1496 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1497 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1498 #ifdef __BIG_ENDIAN
1499 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1500 #endif
1501 break;
1502 case DRM_FORMAT_XRGB1555:
1503 fb_format =
1504 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1505 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1506 #ifdef __BIG_ENDIAN
1507 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1508 #endif
1509 break;
1510 case DRM_FORMAT_RGB565:
1511 fb_format =
1512 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1513 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1514 #ifdef __BIG_ENDIAN
1515 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1516 #endif
1517 break;
1518 case DRM_FORMAT_XRGB8888:
1519 case DRM_FORMAT_ARGB8888:
1520 fb_format =
1521 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1522 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1523 #ifdef __BIG_ENDIAN
1524 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1525 #endif
1526 break;
1527 case DRM_FORMAT_XRGB2101010:
1528 case DRM_FORMAT_ARGB2101010:
1529 fb_format =
1530 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1531 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1532 #ifdef __BIG_ENDIAN
1533 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1534 #endif
1535 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1536 bypass_lut = true;
1537 break;
1538 case DRM_FORMAT_XBGR8888:
1539 case DRM_FORMAT_ABGR8888:
1540 fb_format =
1541 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1542 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1543 if (rdev->family >= CHIP_R600)
1544 fb_swap =
1545 (R600_D1GRPH_RED_CROSSBAR(R600_D1GRPH_RED_SEL_B) |
1546 R600_D1GRPH_BLUE_CROSSBAR(R600_D1GRPH_BLUE_SEL_R));
1547 else /* DCE1 (R5xx) */
1548 fb_format |= AVIVO_D1GRPH_SWAP_RB;
1549 #ifdef __BIG_ENDIAN
1550 fb_swap |= R600_D1GRPH_SWAP_ENDIAN_32BIT;
1551 #endif
1552 break;
1553 default:
1554 DRM_ERROR("Unsupported screen format %p4cc\n",
1555 &target_fb->format->format);
1556 return -EINVAL;
1557 }
1558
1559 if (rdev->family >= CHIP_R600) {
1560 if (tiling_flags & RADEON_TILING_MACRO)
1561 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1562 else if (tiling_flags & RADEON_TILING_MICRO)
1563 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1564 } else {
1565 if (tiling_flags & RADEON_TILING_MACRO)
1566 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1567
1568 if (tiling_flags & RADEON_TILING_MICRO)
1569 fb_format |= AVIVO_D1GRPH_TILED;
1570 }
1571
1572 if (radeon_crtc->crtc_id == 0)
1573 WREG32(AVIVO_D1VGA_CONTROL, 0);
1574 else
1575 WREG32(AVIVO_D2VGA_CONTROL, 0);
1576
1577 /* Make sure surface address is update at vertical blank rather than
1578 * horizontal blank
1579 */
1580 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1581
1582 if (rdev->family >= CHIP_RV770) {
1583 if (radeon_crtc->crtc_id) {
1584 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1585 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1586 } else {
1587 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1588 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1589 }
1590 }
1591 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1592 (u32) fb_location);
1593 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1594 radeon_crtc->crtc_offset, (u32) fb_location);
1595 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1596 if (rdev->family >= CHIP_R600)
1597 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1598
1599 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1600 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1601 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1602
1603 if (bypass_lut)
1604 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1605
1606 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1607 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1608 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1609 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1610 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1611 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1612
1613 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1614 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1615 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1616
1617 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1618 target_fb->height);
1619 x &= ~3;
1620 y &= ~1;
1621 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1622 (x << 16) | y);
1623 viewport_w = crtc->mode.hdisplay;
1624 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1625 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1626 (viewport_w << 16) | viewport_h);
1627
1628 /* set pageflip to happen only at start of vblank interval (front porch) */
1629 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1630
1631 if (fb && fb != crtc->primary->fb) {
1632 rbo = gem_to_radeon_bo(fb->obj[0]);
1633 r = radeon_bo_reserve(rbo, false);
1634 if (unlikely(r != 0))
1635 return r;
1636 radeon_bo_unpin(rbo);
1637 radeon_bo_unreserve(rbo);
1638 }
1639
1640 /* Bytes per pixel may have changed */
1641 radeon_bandwidth_update(rdev);
1642
1643 return 0;
1644 }
1645
atombios_crtc_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)1646 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1647 struct drm_framebuffer *old_fb)
1648 {
1649 struct drm_device *dev = crtc->dev;
1650 struct radeon_device *rdev = dev->dev_private;
1651
1652 if (ASIC_IS_DCE4(rdev))
1653 return dce4_crtc_do_set_base(crtc, old_fb, x, y);
1654 else if (ASIC_IS_AVIVO(rdev))
1655 return avivo_crtc_do_set_base(crtc, old_fb, x, y);
1656 else
1657 return radeon_crtc_do_set_base(crtc, old_fb, x, y);
1658 }
1659
1660 /* properly set additional regs when using atombios */
radeon_legacy_atom_fixup(struct drm_crtc * crtc)1661 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1662 {
1663 struct drm_device *dev = crtc->dev;
1664 struct radeon_device *rdev = dev->dev_private;
1665 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1666 u32 disp_merge_cntl;
1667
1668 switch (radeon_crtc->crtc_id) {
1669 case 0:
1670 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1671 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1672 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1673 break;
1674 case 1:
1675 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1676 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1677 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1678 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1679 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1680 break;
1681 }
1682 }
1683
1684 /**
1685 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1686 *
1687 * @crtc: drm crtc
1688 *
1689 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1690 */
radeon_get_pll_use_mask(struct drm_crtc * crtc)1691 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1692 {
1693 struct drm_device *dev = crtc->dev;
1694 struct drm_crtc *test_crtc;
1695 struct radeon_crtc *test_radeon_crtc;
1696 u32 pll_in_use = 0;
1697
1698 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1699 if (crtc == test_crtc)
1700 continue;
1701
1702 test_radeon_crtc = to_radeon_crtc(test_crtc);
1703 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1704 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1705 }
1706 return pll_in_use;
1707 }
1708
1709 /**
1710 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1711 *
1712 * @crtc: drm crtc
1713 *
1714 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1715 * also in DP mode. For DP, a single PPLL can be used for all DP
1716 * crtcs/encoders.
1717 */
radeon_get_shared_dp_ppll(struct drm_crtc * crtc)1718 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1719 {
1720 struct drm_device *dev = crtc->dev;
1721 struct radeon_device *rdev = dev->dev_private;
1722 struct drm_crtc *test_crtc;
1723 struct radeon_crtc *test_radeon_crtc;
1724
1725 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1726 if (crtc == test_crtc)
1727 continue;
1728 test_radeon_crtc = to_radeon_crtc(test_crtc);
1729 if (test_radeon_crtc->encoder &&
1730 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1731 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1732 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1733 test_radeon_crtc->pll_id == ATOM_PPLL2)
1734 continue;
1735 /* for DP use the same PLL for all */
1736 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1737 return test_radeon_crtc->pll_id;
1738 }
1739 }
1740 return ATOM_PPLL_INVALID;
1741 }
1742
1743 /**
1744 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1745 *
1746 * @crtc: drm crtc
1747 *
1748 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1749 * be shared (i.e., same clock).
1750 */
radeon_get_shared_nondp_ppll(struct drm_crtc * crtc)1751 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1752 {
1753 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1754 struct drm_device *dev = crtc->dev;
1755 struct radeon_device *rdev = dev->dev_private;
1756 struct drm_crtc *test_crtc;
1757 struct radeon_crtc *test_radeon_crtc;
1758 u32 adjusted_clock, test_adjusted_clock;
1759
1760 adjusted_clock = radeon_crtc->adjusted_clock;
1761
1762 if (adjusted_clock == 0)
1763 return ATOM_PPLL_INVALID;
1764
1765 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1766 if (crtc == test_crtc)
1767 continue;
1768 test_radeon_crtc = to_radeon_crtc(test_crtc);
1769 if (test_radeon_crtc->encoder &&
1770 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1771 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1772 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1773 test_radeon_crtc->pll_id == ATOM_PPLL2)
1774 continue;
1775 /* check if we are already driving this connector with another crtc */
1776 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1777 /* if we are, return that pll */
1778 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1779 return test_radeon_crtc->pll_id;
1780 }
1781 /* for non-DP check the clock */
1782 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1783 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1784 (adjusted_clock == test_adjusted_clock) &&
1785 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1786 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1787 return test_radeon_crtc->pll_id;
1788 }
1789 }
1790 return ATOM_PPLL_INVALID;
1791 }
1792
1793 /**
1794 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1795 *
1796 * @crtc: drm crtc
1797 *
1798 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1799 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1800 * monitors a dedicated PPLL must be used. If a particular board has
1801 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1802 * as there is no need to program the PLL itself. If we are not able to
1803 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1804 * avoid messing up an existing monitor.
1805 *
1806 * Asic specific PLL information
1807 *
1808 * DCE 8.x
1809 * KB/KV
1810 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1811 * CI
1812 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1813 *
1814 * DCE 6.1
1815 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1816 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1817 *
1818 * DCE 6.0
1819 * - PPLL0 is available to all UNIPHY (DP only)
1820 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1821 *
1822 * DCE 5.0
1823 * - DCPLL is available to all UNIPHY (DP only)
1824 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1825 *
1826 * DCE 3.0/4.0/4.1
1827 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1828 *
1829 */
radeon_atom_pick_pll(struct drm_crtc * crtc)1830 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1831 {
1832 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1833 struct drm_device *dev = crtc->dev;
1834 struct radeon_device *rdev = dev->dev_private;
1835 struct radeon_encoder *radeon_encoder =
1836 to_radeon_encoder(radeon_crtc->encoder);
1837 u32 pll_in_use;
1838 int pll;
1839
1840 if (ASIC_IS_DCE8(rdev)) {
1841 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1842 if (rdev->clock.dp_extclk)
1843 /* skip PPLL programming if using ext clock */
1844 return ATOM_PPLL_INVALID;
1845 else {
1846 /* use the same PPLL for all DP monitors */
1847 pll = radeon_get_shared_dp_ppll(crtc);
1848 if (pll != ATOM_PPLL_INVALID)
1849 return pll;
1850 }
1851 } else {
1852 /* use the same PPLL for all monitors with the same clock */
1853 pll = radeon_get_shared_nondp_ppll(crtc);
1854 if (pll != ATOM_PPLL_INVALID)
1855 return pll;
1856 }
1857 /* otherwise, pick one of the plls */
1858 if ((rdev->family == CHIP_KABINI) ||
1859 (rdev->family == CHIP_MULLINS)) {
1860 /* KB/ML has PPLL1 and PPLL2 */
1861 pll_in_use = radeon_get_pll_use_mask(crtc);
1862 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1863 return ATOM_PPLL2;
1864 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1865 return ATOM_PPLL1;
1866 DRM_ERROR("unable to allocate a PPLL\n");
1867 return ATOM_PPLL_INVALID;
1868 } else {
1869 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
1870 pll_in_use = radeon_get_pll_use_mask(crtc);
1871 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1872 return ATOM_PPLL2;
1873 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1874 return ATOM_PPLL1;
1875 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1876 return ATOM_PPLL0;
1877 DRM_ERROR("unable to allocate a PPLL\n");
1878 return ATOM_PPLL_INVALID;
1879 }
1880 } else if (ASIC_IS_DCE61(rdev)) {
1881 struct radeon_encoder_atom_dig *dig =
1882 radeon_encoder->enc_priv;
1883
1884 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1885 (dig->linkb == false))
1886 /* UNIPHY A uses PPLL2 */
1887 return ATOM_PPLL2;
1888 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1889 /* UNIPHY B/C/D/E/F */
1890 if (rdev->clock.dp_extclk)
1891 /* skip PPLL programming if using ext clock */
1892 return ATOM_PPLL_INVALID;
1893 else {
1894 /* use the same PPLL for all DP monitors */
1895 pll = radeon_get_shared_dp_ppll(crtc);
1896 if (pll != ATOM_PPLL_INVALID)
1897 return pll;
1898 }
1899 } else {
1900 /* use the same PPLL for all monitors with the same clock */
1901 pll = radeon_get_shared_nondp_ppll(crtc);
1902 if (pll != ATOM_PPLL_INVALID)
1903 return pll;
1904 }
1905 /* UNIPHY B/C/D/E/F */
1906 pll_in_use = radeon_get_pll_use_mask(crtc);
1907 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1908 return ATOM_PPLL0;
1909 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1910 return ATOM_PPLL1;
1911 DRM_ERROR("unable to allocate a PPLL\n");
1912 return ATOM_PPLL_INVALID;
1913 } else if (ASIC_IS_DCE41(rdev)) {
1914 /* Don't share PLLs on DCE4.1 chips */
1915 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1916 if (rdev->clock.dp_extclk)
1917 /* skip PPLL programming if using ext clock */
1918 return ATOM_PPLL_INVALID;
1919 }
1920 pll_in_use = radeon_get_pll_use_mask(crtc);
1921 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1922 return ATOM_PPLL1;
1923 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1924 return ATOM_PPLL2;
1925 DRM_ERROR("unable to allocate a PPLL\n");
1926 return ATOM_PPLL_INVALID;
1927 } else if (ASIC_IS_DCE4(rdev)) {
1928 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1929 * depending on the asic:
1930 * DCE4: PPLL or ext clock
1931 * DCE5: PPLL, DCPLL, or ext clock
1932 * DCE6: PPLL, PPLL0, or ext clock
1933 *
1934 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1935 * PPLL/DCPLL programming and only program the DP DTO for the
1936 * crtc virtual pixel clock.
1937 */
1938 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1939 if (rdev->clock.dp_extclk)
1940 /* skip PPLL programming if using ext clock */
1941 return ATOM_PPLL_INVALID;
1942 else if (ASIC_IS_DCE6(rdev))
1943 /* use PPLL0 for all DP */
1944 return ATOM_PPLL0;
1945 else if (ASIC_IS_DCE5(rdev))
1946 /* use DCPLL for all DP */
1947 return ATOM_DCPLL;
1948 else {
1949 /* use the same PPLL for all DP monitors */
1950 pll = radeon_get_shared_dp_ppll(crtc);
1951 if (pll != ATOM_PPLL_INVALID)
1952 return pll;
1953 }
1954 } else {
1955 /* use the same PPLL for all monitors with the same clock */
1956 pll = radeon_get_shared_nondp_ppll(crtc);
1957 if (pll != ATOM_PPLL_INVALID)
1958 return pll;
1959 }
1960 /* all other cases */
1961 pll_in_use = radeon_get_pll_use_mask(crtc);
1962 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1963 return ATOM_PPLL1;
1964 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1965 return ATOM_PPLL2;
1966 DRM_ERROR("unable to allocate a PPLL\n");
1967 return ATOM_PPLL_INVALID;
1968 } else {
1969 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1970 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1971 * the matching btw pll and crtc is done through
1972 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1973 * pll (1 or 2) to select which register to write. ie if using
1974 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1975 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1976 * choose which value to write. Which is reverse order from
1977 * register logic. So only case that works is when pllid is
1978 * same as crtcid or when both pll and crtc are enabled and
1979 * both use same clock.
1980 *
1981 * So just return crtc id as if crtc and pll were hard linked
1982 * together even if they aren't
1983 */
1984 return radeon_crtc->crtc_id;
1985 }
1986 }
1987
radeon_atom_disp_eng_pll_init(struct radeon_device * rdev)1988 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1989 {
1990 /* always set DCPLL */
1991 if (ASIC_IS_DCE6(rdev))
1992 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1993 else if (ASIC_IS_DCE4(rdev)) {
1994 struct radeon_atom_ss ss;
1995 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1996 ASIC_INTERNAL_SS_ON_DCPLL,
1997 rdev->clock.default_dispclk);
1998 if (ss_enabled)
1999 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2000 /* XXX: DCE5, make sure voltage, dispclk is high enough */
2001 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2002 if (ss_enabled)
2003 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2004 }
2005
2006 }
2007
atombios_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)2008 int atombios_crtc_mode_set(struct drm_crtc *crtc,
2009 struct drm_display_mode *mode,
2010 struct drm_display_mode *adjusted_mode,
2011 int x, int y, struct drm_framebuffer *old_fb)
2012 {
2013 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2014 struct drm_device *dev = crtc->dev;
2015 struct radeon_device *rdev = dev->dev_private;
2016 struct radeon_encoder *radeon_encoder =
2017 to_radeon_encoder(radeon_crtc->encoder);
2018 bool is_tvcv = false;
2019
2020 if (radeon_encoder->active_device &
2021 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2022 is_tvcv = true;
2023
2024 if (!radeon_crtc->adjusted_clock)
2025 return -EINVAL;
2026
2027 atombios_crtc_set_pll(crtc, adjusted_mode);
2028
2029 if (ASIC_IS_DCE4(rdev))
2030 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2031 else if (ASIC_IS_AVIVO(rdev)) {
2032 if (is_tvcv)
2033 atombios_crtc_set_timing(crtc, adjusted_mode);
2034 else
2035 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2036 } else {
2037 atombios_crtc_set_timing(crtc, adjusted_mode);
2038 if (radeon_crtc->crtc_id == 0)
2039 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2040 radeon_legacy_atom_fixup(crtc);
2041 }
2042 atombios_crtc_set_base(crtc, x, y, old_fb);
2043 atombios_overscan_setup(crtc, mode, adjusted_mode);
2044 atombios_scaler_setup(crtc);
2045 radeon_cursor_reset(crtc);
2046 /* update the hw version fpr dpm */
2047 radeon_crtc->hw_mode = *adjusted_mode;
2048
2049 return 0;
2050 }
2051
atombios_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2052 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2053 const struct drm_display_mode *mode,
2054 struct drm_display_mode *adjusted_mode)
2055 {
2056 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2057 struct drm_device *dev = crtc->dev;
2058 struct drm_encoder *encoder;
2059
2060 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
2061 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2062 if (encoder->crtc == crtc) {
2063 radeon_crtc->encoder = encoder;
2064 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
2065 break;
2066 }
2067 }
2068 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2069 radeon_crtc->encoder = NULL;
2070 radeon_crtc->connector = NULL;
2071 return false;
2072 }
2073 if (radeon_crtc->encoder) {
2074 struct radeon_encoder *radeon_encoder =
2075 to_radeon_encoder(radeon_crtc->encoder);
2076
2077 radeon_crtc->output_csc = radeon_encoder->output_csc;
2078 }
2079 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2080 return false;
2081 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2082 return false;
2083 /* pick pll */
2084 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2085 /* if we can't get a PPLL for a non-DP encoder, fail */
2086 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2087 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2088 return false;
2089
2090 return true;
2091 }
2092
atombios_crtc_prepare(struct drm_crtc * crtc)2093 static void atombios_crtc_prepare(struct drm_crtc *crtc)
2094 {
2095 struct drm_device *dev = crtc->dev;
2096 struct radeon_device *rdev = dev->dev_private;
2097
2098 /* disable crtc pair power gating before programming */
2099 if (ASIC_IS_DCE6(rdev))
2100 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2101
2102 atombios_lock_crtc(crtc, ATOM_ENABLE);
2103 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2104 }
2105
atombios_crtc_commit(struct drm_crtc * crtc)2106 static void atombios_crtc_commit(struct drm_crtc *crtc)
2107 {
2108 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2109 atombios_lock_crtc(crtc, ATOM_DISABLE);
2110 }
2111
atombios_crtc_disable(struct drm_crtc * crtc)2112 static void atombios_crtc_disable(struct drm_crtc *crtc)
2113 {
2114 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2115 struct drm_device *dev = crtc->dev;
2116 struct radeon_device *rdev = dev->dev_private;
2117 struct radeon_atom_ss ss;
2118 int i;
2119
2120 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2121 if (crtc->primary->fb) {
2122 int r;
2123 struct radeon_bo *rbo;
2124
2125 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]);
2126 r = radeon_bo_reserve(rbo, false);
2127 if (unlikely(r))
2128 DRM_ERROR("failed to reserve rbo before unpin\n");
2129 else {
2130 radeon_bo_unpin(rbo);
2131 radeon_bo_unreserve(rbo);
2132 }
2133 }
2134 /* disable the GRPH */
2135 if (ASIC_IS_DCE4(rdev))
2136 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2137 else if (ASIC_IS_AVIVO(rdev))
2138 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2139
2140 if (ASIC_IS_DCE6(rdev))
2141 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2142
2143 for (i = 0; i < rdev->num_crtc; i++) {
2144 if (rdev->mode_info.crtcs[i] &&
2145 rdev->mode_info.crtcs[i]->enabled &&
2146 i != radeon_crtc->crtc_id &&
2147 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2148 /* one other crtc is using this pll don't turn
2149 * off the pll
2150 */
2151 goto done;
2152 }
2153 }
2154
2155 switch (radeon_crtc->pll_id) {
2156 case ATOM_PPLL1:
2157 case ATOM_PPLL2:
2158 /* disable the ppll */
2159 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2160 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2161 break;
2162 case ATOM_PPLL0:
2163 /* disable the ppll */
2164 if ((rdev->family == CHIP_ARUBA) ||
2165 (rdev->family == CHIP_KAVERI) ||
2166 (rdev->family == CHIP_BONAIRE) ||
2167 (rdev->family == CHIP_HAWAII))
2168 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2169 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2170 break;
2171 default:
2172 break;
2173 }
2174 done:
2175 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2176 radeon_crtc->adjusted_clock = 0;
2177 radeon_crtc->encoder = NULL;
2178 radeon_crtc->connector = NULL;
2179 }
2180
2181 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2182 .dpms = atombios_crtc_dpms,
2183 .mode_fixup = atombios_crtc_mode_fixup,
2184 .mode_set = atombios_crtc_mode_set,
2185 .mode_set_base = atombios_crtc_set_base,
2186 .prepare = atombios_crtc_prepare,
2187 .commit = atombios_crtc_commit,
2188 .disable = atombios_crtc_disable,
2189 .get_scanout_position = radeon_get_crtc_scanout_position,
2190 };
2191
radeon_atombios_init_crtc(struct drm_device * dev,struct radeon_crtc * radeon_crtc)2192 void radeon_atombios_init_crtc(struct drm_device *dev,
2193 struct radeon_crtc *radeon_crtc)
2194 {
2195 struct radeon_device *rdev = dev->dev_private;
2196
2197 if (ASIC_IS_DCE4(rdev)) {
2198 switch (radeon_crtc->crtc_id) {
2199 case 0:
2200 default:
2201 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2202 break;
2203 case 1:
2204 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2205 break;
2206 case 2:
2207 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2208 break;
2209 case 3:
2210 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2211 break;
2212 case 4:
2213 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2214 break;
2215 case 5:
2216 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2217 break;
2218 }
2219 } else {
2220 if (radeon_crtc->crtc_id == 1)
2221 radeon_crtc->crtc_offset =
2222 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2223 else
2224 radeon_crtc->crtc_offset = 0;
2225 }
2226 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2227 radeon_crtc->adjusted_clock = 0;
2228 radeon_crtc->encoder = NULL;
2229 radeon_crtc->connector = NULL;
2230 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2231 }
2232