1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/pci.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/gcd.h>
30
31 #include <asm/div64.h>
32
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_device.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_fourcc.h>
38 #include <drm/drm_framebuffer.h>
39 #include <drm/drm_gem_framebuffer_helper.h>
40 #include <drm/drm_modeset_helper.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/radeon_drm.h>
44 #include <drm/drm_print.h>
45
46 #include "atom.h"
47 #include "radeon.h"
48 #include "radeon_kms.h"
49
avivo_crtc_load_lut(struct drm_crtc * crtc)50 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
51 {
52 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
53 struct drm_device *dev = crtc->dev;
54 struct radeon_device *rdev = dev->dev_private;
55 u16 *r, *g, *b;
56 int i;
57
58 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
59 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
60
61 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
62 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
63 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
64
65 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
66 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
67 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
68
69 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
70 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
71 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
72
73 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
74 r = crtc->gamma_store;
75 g = r + crtc->gamma_size;
76 b = g + crtc->gamma_size;
77 for (i = 0; i < 256; i++) {
78 WREG32(AVIVO_DC_LUT_30_COLOR,
79 ((*r++ & 0xffc0) << 14) |
80 ((*g++ & 0xffc0) << 4) |
81 (*b++ >> 6));
82 }
83
84 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
85 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
86 }
87
dce4_crtc_load_lut(struct drm_crtc * crtc)88 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
89 {
90 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
91 struct drm_device *dev = crtc->dev;
92 struct radeon_device *rdev = dev->dev_private;
93 u16 *r, *g, *b;
94 int i;
95
96 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
97 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
98
99 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
100 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
101 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
102
103 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
104 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
105 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
106
107 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
108 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
109
110 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
111 r = crtc->gamma_store;
112 g = r + crtc->gamma_size;
113 b = g + crtc->gamma_size;
114 for (i = 0; i < 256; i++) {
115 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
116 ((*r++ & 0xffc0) << 14) |
117 ((*g++ & 0xffc0) << 4) |
118 (*b++ >> 6));
119 }
120 }
121
dce5_crtc_load_lut(struct drm_crtc * crtc)122 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
123 {
124 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
125 struct drm_device *dev = crtc->dev;
126 struct radeon_device *rdev = dev->dev_private;
127 u16 *r, *g, *b;
128 int i;
129
130 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
131
132 msleep(10);
133
134 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
135 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
136 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
137 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
138 NI_GRPH_PRESCALE_BYPASS);
139 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
140 NI_OVL_PRESCALE_BYPASS);
141 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
142 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
143 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
144
145 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
146
147 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
148 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
149 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
150
151 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
152 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
153 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
154
155 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
156 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
157
158 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
159 r = crtc->gamma_store;
160 g = r + crtc->gamma_size;
161 b = g + crtc->gamma_size;
162 for (i = 0; i < 256; i++) {
163 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
164 ((*r++ & 0xffc0) << 14) |
165 ((*g++ & 0xffc0) << 4) |
166 (*b++ >> 6));
167 }
168
169 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
170 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
171 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
172 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
173 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
174 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
175 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
176 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
177 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
178 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
179 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
180 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
181 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
182 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
183 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
184 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
185 if (ASIC_IS_DCE8(rdev)) {
186 /* XXX this only needs to be programmed once per crtc at startup,
187 * not sure where the best place for it is
188 */
189 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
190 CIK_CURSOR_ALPHA_BLND_ENA);
191 }
192 }
193
legacy_crtc_load_lut(struct drm_crtc * crtc)194 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
195 {
196 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
197 struct drm_device *dev = crtc->dev;
198 struct radeon_device *rdev = dev->dev_private;
199 u16 *r, *g, *b;
200 int i;
201 uint32_t dac2_cntl;
202
203 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
204 if (radeon_crtc->crtc_id == 0)
205 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
206 else
207 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
208 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
209
210 WREG8(RADEON_PALETTE_INDEX, 0);
211 r = crtc->gamma_store;
212 g = r + crtc->gamma_size;
213 b = g + crtc->gamma_size;
214 for (i = 0; i < 256; i++) {
215 WREG32(RADEON_PALETTE_30_DATA,
216 ((*r++ & 0xffc0) << 14) |
217 ((*g++ & 0xffc0) << 4) |
218 (*b++ >> 6));
219 }
220 }
221
radeon_crtc_load_lut(struct drm_crtc * crtc)222 void radeon_crtc_load_lut(struct drm_crtc *crtc)
223 {
224 struct drm_device *dev = crtc->dev;
225 struct radeon_device *rdev = dev->dev_private;
226
227 if (!crtc->enabled)
228 return;
229
230 if (ASIC_IS_DCE5(rdev))
231 dce5_crtc_load_lut(crtc);
232 else if (ASIC_IS_DCE4(rdev))
233 dce4_crtc_load_lut(crtc);
234 else if (ASIC_IS_AVIVO(rdev))
235 avivo_crtc_load_lut(crtc);
236 else
237 legacy_crtc_load_lut(crtc);
238 }
239
radeon_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t size,struct drm_modeset_acquire_ctx * ctx)240 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
241 u16 *blue, uint32_t size,
242 struct drm_modeset_acquire_ctx *ctx)
243 {
244 radeon_crtc_load_lut(crtc);
245
246 return 0;
247 }
248
radeon_crtc_destroy(struct drm_crtc * crtc)249 static void radeon_crtc_destroy(struct drm_crtc *crtc)
250 {
251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
252
253 drm_crtc_cleanup(crtc);
254 destroy_workqueue(radeon_crtc->flip_queue);
255 kfree(radeon_crtc);
256 }
257
258 /**
259 * radeon_unpin_work_func - unpin old buffer object
260 *
261 * @__work: kernel work item
262 *
263 * Unpin the old frame buffer object outside of the interrupt handler
264 */
radeon_unpin_work_func(struct work_struct * __work)265 static void radeon_unpin_work_func(struct work_struct *__work)
266 {
267 struct radeon_flip_work *work =
268 container_of(__work, struct radeon_flip_work, unpin_work);
269 int r;
270
271 /* unpin of the old buffer */
272 r = radeon_bo_reserve(work->old_rbo, false);
273 if (likely(r == 0)) {
274 radeon_bo_unpin(work->old_rbo);
275 radeon_bo_unreserve(work->old_rbo);
276 } else
277 drm_err(&work->rdev->ddev, "failed to reserve buffer after flip\n");
278
279 drm_gem_object_put(&work->old_rbo->tbo.base);
280 kfree(work);
281 }
282
radeon_crtc_handle_vblank(struct radeon_device * rdev,int crtc_id)283 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
284 {
285 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
286 unsigned long flags;
287 u32 update_pending;
288 int vpos, hpos;
289
290 /* can happen during initialization */
291 if (radeon_crtc == NULL)
292 return;
293
294 /* Skip the pageflip completion check below (based on polling) on
295 * asics which reliably support hw pageflip completion irqs. pflip
296 * irqs are a reliable and race-free method of handling pageflip
297 * completion detection. A use_pflipirq module parameter < 2 allows
298 * to override this in case of asics with faulty pflip irqs.
299 * A module parameter of 0 would only use this polling based path,
300 * a parameter of 1 would use pflip irq only as a backup to this
301 * path, as in Linux 3.16.
302 */
303 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
304 return;
305
306 spin_lock_irqsave(&rdev_to_drm(rdev)->event_lock, flags);
307 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
308 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
309 "RADEON_FLIP_SUBMITTED(%d)\n",
310 radeon_crtc->flip_status,
311 RADEON_FLIP_SUBMITTED);
312 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags);
313 return;
314 }
315
316 update_pending = radeon_page_flip_pending(rdev, crtc_id);
317
318 /* Has the pageflip already completed in crtc, or is it certain
319 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
320 * distance to start of "fudged earlier" vblank in vpos, distance to
321 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
322 * the last few scanlines before start of real vblank, where the vblank
323 * irq can fire, so we have sampled update_pending a bit too early and
324 * know the flip will complete at leading edge of the upcoming real
325 * vblank. On pre-AVIVO hardware, flips also complete inside the real
326 * vblank, not only at leading edge, so if update_pending for hpos >= 0
327 * == inside real vblank, the flip will complete almost immediately.
328 * Note that this method of completion handling is still not 100% race
329 * free, as we could execute before the radeon_flip_work_func managed
330 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
331 * but the flip still gets programmed into hw and completed during
332 * vblank, leading to a delayed emission of the flip completion event.
333 * This applies at least to pre-AVIVO hardware, where flips are always
334 * completing inside vblank, not only at leading edge of vblank.
335 */
336 if (update_pending &&
337 (DRM_SCANOUTPOS_VALID &
338 radeon_get_crtc_scanoutpos(rdev_to_drm(rdev), crtc_id,
339 GET_DISTANCE_TO_VBLANKSTART,
340 &vpos, &hpos, NULL, NULL,
341 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
342 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
343 /* crtc didn't flip in this target vblank interval,
344 * but flip is pending in crtc. Based on the current
345 * scanout position we know that the current frame is
346 * (nearly) complete and the flip will (likely)
347 * complete before the start of the next frame.
348 */
349 update_pending = 0;
350 }
351 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags);
352 if (!update_pending)
353 radeon_crtc_handle_flip(rdev, crtc_id);
354 }
355
356 /**
357 * radeon_crtc_handle_flip - page flip completed
358 *
359 * @rdev: radeon device pointer
360 * @crtc_id: crtc number this event is for
361 *
362 * Called when we are sure that a page flip for this crtc is completed.
363 */
radeon_crtc_handle_flip(struct radeon_device * rdev,int crtc_id)364 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
365 {
366 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
367 struct radeon_flip_work *work;
368 unsigned long flags;
369
370 /* this can happen at init */
371 if (radeon_crtc == NULL)
372 return;
373
374 spin_lock_irqsave(&rdev_to_drm(rdev)->event_lock, flags);
375 work = radeon_crtc->flip_work;
376 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
377 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
378 "RADEON_FLIP_SUBMITTED(%d)\n",
379 radeon_crtc->flip_status,
380 RADEON_FLIP_SUBMITTED);
381 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags);
382 return;
383 }
384
385 /* Pageflip completed. Clean up. */
386 radeon_crtc->flip_status = RADEON_FLIP_NONE;
387 radeon_crtc->flip_work = NULL;
388
389 /* wakeup userspace */
390 if (work->event)
391 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
392
393 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags);
394
395 drm_crtc_vblank_put(&radeon_crtc->base);
396 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
397 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
398 }
399
400 /**
401 * radeon_flip_work_func - page flip framebuffer
402 *
403 * @__work: kernel work item
404 *
405 * Wait for the buffer object to become idle and do the actual page flip
406 */
radeon_flip_work_func(struct work_struct * __work)407 static void radeon_flip_work_func(struct work_struct *__work)
408 {
409 struct radeon_flip_work *work =
410 container_of(__work, struct radeon_flip_work, flip_work);
411 struct radeon_device *rdev = work->rdev;
412 struct drm_device *dev = rdev_to_drm(rdev);
413 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
414
415 struct drm_crtc *crtc = &radeon_crtc->base;
416 unsigned long flags;
417 int r;
418 int vpos, hpos;
419
420 down_read(&rdev->exclusive_lock);
421 if (work->fence) {
422 struct radeon_fence *fence;
423
424 fence = to_radeon_fence(work->fence);
425 if (fence && fence->rdev == rdev) {
426 r = radeon_fence_wait(fence, false);
427 if (r == -EDEADLK) {
428 up_read(&rdev->exclusive_lock);
429 do {
430 r = radeon_gpu_reset(rdev);
431 } while (r == -EAGAIN);
432 down_read(&rdev->exclusive_lock);
433 }
434 } else
435 r = dma_fence_wait(work->fence, false);
436
437 if (r)
438 drm_err(dev, "failed to wait on page flip fence (%d)!\n", r);
439
440 /* We continue with the page flip even if we failed to wait on
441 * the fence, otherwise the DRM core and userspace will be
442 * confused about which BO the CRTC is scanning out
443 */
444
445 dma_fence_put(work->fence);
446 work->fence = NULL;
447 }
448
449 /* Wait until we're out of the vertical blank period before the one
450 * targeted by the flip. Always wait on pre DCE4 to avoid races with
451 * flip completion handling from vblank irq, as these old asics don't
452 * have reliable pageflip completion interrupts.
453 */
454 while (radeon_crtc->enabled &&
455 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
456 &vpos, &hpos, NULL, NULL,
457 &crtc->hwmode)
458 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
459 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
460 (!ASIC_IS_AVIVO(rdev) ||
461 ((int) (work->target_vblank -
462 crtc->funcs->get_vblank_counter(crtc)) > 0)))
463 usleep_range(1000, 2000);
464
465 /* We borrow the event spin lock for protecting flip_status */
466 spin_lock_irqsave(&crtc->dev->event_lock, flags);
467
468 /* set the proper interrupt */
469 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
470
471 /* do the flip (mmio) */
472 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
473
474 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
475 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
476 up_read(&rdev->exclusive_lock);
477 }
478
radeon_crtc_page_flip_target(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags,uint32_t target,struct drm_modeset_acquire_ctx * ctx)479 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
480 struct drm_framebuffer *fb,
481 struct drm_pending_vblank_event *event,
482 uint32_t page_flip_flags,
483 uint32_t target,
484 struct drm_modeset_acquire_ctx *ctx)
485 {
486 struct drm_device *dev = crtc->dev;
487 struct radeon_device *rdev = dev->dev_private;
488 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
489 struct drm_gem_object *obj;
490 struct radeon_flip_work *work;
491 struct radeon_bo *new_rbo;
492 uint32_t tiling_flags, pitch_pixels;
493 uint64_t base;
494 unsigned long flags;
495 int r;
496
497 work = kzalloc_obj(*work);
498 if (work == NULL)
499 return -ENOMEM;
500
501 INIT_WORK(&work->flip_work, radeon_flip_work_func);
502 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
503
504 work->rdev = rdev;
505 work->crtc_id = radeon_crtc->crtc_id;
506 work->event = event;
507 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
508
509 /* schedule unpin of the old buffer */
510 obj = crtc->primary->fb->obj[0];
511
512 /* take a reference to the old object */
513 drm_gem_object_get(obj);
514 work->old_rbo = gem_to_radeon_bo(obj);
515
516 obj = fb->obj[0];
517 new_rbo = gem_to_radeon_bo(obj);
518
519 /* pin the new buffer */
520 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
521 work->old_rbo, new_rbo);
522
523 r = radeon_bo_reserve(new_rbo, false);
524 if (unlikely(r != 0)) {
525 drm_err(dev, "failed to reserve new rbo buffer before flip\n");
526 goto cleanup;
527 }
528 /* Only 27 bit offset for legacy CRTC */
529 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
530 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
531 if (unlikely(r != 0)) {
532 radeon_bo_unreserve(new_rbo);
533 r = -EINVAL;
534 drm_err(dev, "failed to pin new rbo buffer before flip\n");
535 goto cleanup;
536 }
537 r = dma_resv_get_singleton(new_rbo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
538 &work->fence);
539 if (r) {
540 radeon_bo_unreserve(new_rbo);
541 drm_err(dev, "failed to get new rbo buffer fences\n");
542 goto cleanup;
543 }
544 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
545 radeon_bo_unreserve(new_rbo);
546
547 if (!ASIC_IS_AVIVO(rdev)) {
548 /* crtc offset is from display base addr not FB location */
549 base -= radeon_crtc->legacy_display_base_addr;
550 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
551
552 if (tiling_flags & RADEON_TILING_MACRO) {
553 if (ASIC_IS_R300(rdev)) {
554 base &= ~0x7ff;
555 } else {
556 int byteshift = fb->format->cpp[0] * 8 >> 4;
557 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
558 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
559 }
560 } else {
561 int offset = crtc->y * pitch_pixels + crtc->x;
562 switch (fb->format->cpp[0] * 8) {
563 case 8:
564 default:
565 offset *= 1;
566 break;
567 case 15:
568 case 16:
569 offset *= 2;
570 break;
571 case 24:
572 offset *= 3;
573 break;
574 case 32:
575 offset *= 4;
576 break;
577 }
578 base += offset;
579 }
580 base &= ~7;
581 }
582 work->base = base;
583 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
584 crtc->funcs->get_vblank_counter(crtc);
585
586 /* We borrow the event spin lock for protecting flip_work */
587 spin_lock_irqsave(&crtc->dev->event_lock, flags);
588
589 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
590 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
591 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
592 r = -EBUSY;
593 goto pflip_cleanup;
594 }
595 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
596 radeon_crtc->flip_work = work;
597
598 /* update crtc fb */
599 crtc->primary->fb = fb;
600
601 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
602
603 queue_work(radeon_crtc->flip_queue, &work->flip_work);
604 return 0;
605
606 pflip_cleanup:
607 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
608 drm_err(dev, "failed to reserve new rbo in error path\n");
609 goto cleanup;
610 }
611 radeon_bo_unpin(new_rbo);
612 radeon_bo_unreserve(new_rbo);
613
614 cleanup:
615 drm_gem_object_put(&work->old_rbo->tbo.base);
616 dma_fence_put(work->fence);
617 kfree(work);
618 return r;
619 }
620
621 static int
radeon_crtc_set_config(struct drm_mode_set * set,struct drm_modeset_acquire_ctx * ctx)622 radeon_crtc_set_config(struct drm_mode_set *set,
623 struct drm_modeset_acquire_ctx *ctx)
624 {
625 struct drm_device *dev;
626 struct radeon_device *rdev;
627 struct drm_crtc *crtc;
628 bool active = false;
629 int ret;
630
631 if (!set || !set->crtc)
632 return -EINVAL;
633
634 dev = set->crtc->dev;
635
636 ret = pm_runtime_get_sync(dev->dev);
637 if (ret < 0) {
638 pm_runtime_put_autosuspend(dev->dev);
639 return ret;
640 }
641
642 ret = drm_crtc_helper_set_config(set, ctx);
643
644 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
645 if (crtc->enabled)
646 active = true;
647
648 rdev = dev->dev_private;
649 /* if we have active crtcs and we don't have a power ref,
650 take the current one */
651 if (active && !rdev->have_disp_power_ref) {
652 rdev->have_disp_power_ref = true;
653 return ret;
654 }
655 /* if we have no active crtcs, then drop the power ref
656 we got before */
657 if (!active && rdev->have_disp_power_ref) {
658 pm_runtime_put_autosuspend(dev->dev);
659 rdev->have_disp_power_ref = false;
660 }
661
662 /* drop the power reference we got coming in here */
663 pm_runtime_put_autosuspend(dev->dev);
664 return ret;
665 }
666
667 static const struct drm_crtc_funcs radeon_crtc_funcs = {
668 .cursor_set2 = radeon_crtc_cursor_set2,
669 .cursor_move = radeon_crtc_cursor_move,
670 .gamma_set = radeon_crtc_gamma_set,
671 .set_config = radeon_crtc_set_config,
672 .destroy = radeon_crtc_destroy,
673 .page_flip_target = radeon_crtc_page_flip_target,
674 .get_vblank_counter = radeon_get_vblank_counter_kms,
675 .enable_vblank = radeon_enable_vblank_kms,
676 .disable_vblank = radeon_disable_vblank_kms,
677 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
678 };
679
radeon_crtc_init(struct drm_device * dev,int index)680 static void radeon_crtc_init(struct drm_device *dev, int index)
681 {
682 struct radeon_device *rdev = dev->dev_private;
683 struct radeon_crtc *radeon_crtc;
684
685 radeon_crtc = kzalloc_obj(*radeon_crtc);
686 if (radeon_crtc == NULL)
687 return;
688
689 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
690 if (!radeon_crtc->flip_queue) {
691 kfree(radeon_crtc);
692 return;
693 }
694
695 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
696
697 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
698 radeon_crtc->crtc_id = index;
699 rdev->mode_info.crtcs[index] = radeon_crtc;
700
701 if (rdev->family >= CHIP_BONAIRE) {
702 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
703 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
704 } else {
705 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
706 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
707 }
708 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
709 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
710
711 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
712 radeon_atombios_init_crtc(dev, radeon_crtc);
713 else
714 radeon_legacy_init_crtc(dev, radeon_crtc);
715 }
716
717 static const char *encoder_names[38] = {
718 "NONE",
719 "INTERNAL_LVDS",
720 "INTERNAL_TMDS1",
721 "INTERNAL_TMDS2",
722 "INTERNAL_DAC1",
723 "INTERNAL_DAC2",
724 "INTERNAL_SDVOA",
725 "INTERNAL_SDVOB",
726 "SI170B",
727 "CH7303",
728 "CH7301",
729 "INTERNAL_DVO1",
730 "EXTERNAL_SDVOA",
731 "EXTERNAL_SDVOB",
732 "TITFP513",
733 "INTERNAL_LVTM1",
734 "VT1623",
735 "HDMI_SI1930",
736 "HDMI_INTERNAL",
737 "INTERNAL_KLDSCP_TMDS1",
738 "INTERNAL_KLDSCP_DVO1",
739 "INTERNAL_KLDSCP_DAC1",
740 "INTERNAL_KLDSCP_DAC2",
741 "SI178",
742 "MVPU_FPGA",
743 "INTERNAL_DDI",
744 "VT1625",
745 "HDMI_SI1932",
746 "DP_AN9801",
747 "DP_DP501",
748 "INTERNAL_UNIPHY",
749 "INTERNAL_KLDSCP_LVTMA",
750 "INTERNAL_UNIPHY1",
751 "INTERNAL_UNIPHY2",
752 "NUTMEG",
753 "TRAVIS",
754 "INTERNAL_VCE",
755 "INTERNAL_UNIPHY3",
756 };
757
758 static const char *hpd_names[6] = {
759 "HPD1",
760 "HPD2",
761 "HPD3",
762 "HPD4",
763 "HPD5",
764 "HPD6",
765 };
766
radeon_print_display_setup(struct drm_device * dev)767 static void radeon_print_display_setup(struct drm_device *dev)
768 {
769 struct drm_connector *connector;
770 struct radeon_connector *radeon_connector;
771 struct drm_encoder *encoder;
772 struct radeon_encoder *radeon_encoder;
773 uint32_t devices;
774 int i = 0;
775
776 drm_info(dev, "Radeon Display Connectors\n");
777 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
778 radeon_connector = to_radeon_connector(connector);
779 drm_info(dev, "Connector %d:\n", i);
780 drm_info(dev, " %s\n", connector->name);
781 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
782 drm_info(dev, " %s\n", hpd_names[radeon_connector->hpd.hpd]);
783 if (radeon_connector->ddc_bus) {
784 drm_info(dev, " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
785 radeon_connector->ddc_bus->rec.mask_clk_reg,
786 radeon_connector->ddc_bus->rec.mask_data_reg,
787 radeon_connector->ddc_bus->rec.a_clk_reg,
788 radeon_connector->ddc_bus->rec.a_data_reg,
789 radeon_connector->ddc_bus->rec.en_clk_reg,
790 radeon_connector->ddc_bus->rec.en_data_reg,
791 radeon_connector->ddc_bus->rec.y_clk_reg,
792 radeon_connector->ddc_bus->rec.y_data_reg);
793 if (radeon_connector->router.ddc_valid)
794 drm_info(dev, " DDC Router 0x%x/0x%x\n",
795 radeon_connector->router.ddc_mux_control_pin,
796 radeon_connector->router.ddc_mux_state);
797 if (radeon_connector->router.cd_valid)
798 drm_info(dev, " Clock/Data Router 0x%x/0x%x\n",
799 radeon_connector->router.cd_mux_control_pin,
800 radeon_connector->router.cd_mux_state);
801 } else {
802 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
803 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
804 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
805 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
806 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
807 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
808 drm_info(dev, " DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
809 }
810 drm_info(dev, " Encoders:\n");
811 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
812 radeon_encoder = to_radeon_encoder(encoder);
813 devices = radeon_encoder->devices & radeon_connector->devices;
814 if (devices) {
815 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
816 drm_info(dev, " CRT1: %s\n",
817 encoder_names[radeon_encoder->encoder_id]);
818 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
819 drm_info(dev, " CRT2: %s\n",
820 encoder_names[radeon_encoder->encoder_id]);
821 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
822 drm_info(dev, " LCD1: %s\n",
823 encoder_names[radeon_encoder->encoder_id]);
824 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
825 drm_info(dev, " DFP1: %s\n",
826 encoder_names[radeon_encoder->encoder_id]);
827 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
828 drm_info(dev, " DFP2: %s\n",
829 encoder_names[radeon_encoder->encoder_id]);
830 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
831 drm_info(dev, " DFP3: %s\n",
832 encoder_names[radeon_encoder->encoder_id]);
833 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
834 drm_info(dev, " DFP4: %s\n",
835 encoder_names[radeon_encoder->encoder_id]);
836 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
837 drm_info(dev, " DFP5: %s\n",
838 encoder_names[radeon_encoder->encoder_id]);
839 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
840 drm_info(dev, " DFP6: %s\n",
841 encoder_names[radeon_encoder->encoder_id]);
842 if (devices & ATOM_DEVICE_TV1_SUPPORT)
843 drm_info(dev, " TV1: %s\n",
844 encoder_names[radeon_encoder->encoder_id]);
845 if (devices & ATOM_DEVICE_CV_SUPPORT)
846 drm_info(dev, " CV: %s\n",
847 encoder_names[radeon_encoder->encoder_id]);
848 }
849 }
850 i++;
851 }
852 }
853
radeon_setup_enc_conn(struct drm_device * dev)854 static bool radeon_setup_enc_conn(struct drm_device *dev)
855 {
856 struct radeon_device *rdev = dev->dev_private;
857 bool ret = false;
858
859 if (rdev->bios) {
860 if (rdev->is_atom_bios) {
861 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
862 if (!ret)
863 ret = radeon_get_atom_connector_info_from_object_table(dev);
864 } else {
865 ret = radeon_get_legacy_connector_info_from_bios(dev);
866 if (!ret)
867 ret = radeon_get_legacy_connector_info_from_table(dev);
868 }
869 } else {
870 if (!ASIC_IS_AVIVO(rdev))
871 ret = radeon_get_legacy_connector_info_from_table(dev);
872 }
873 if (ret) {
874 radeon_setup_encoder_clones(dev);
875 radeon_print_display_setup(dev);
876 }
877
878 return ret;
879 }
880
881 /* avivo */
882
883 /**
884 * avivo_reduce_ratio - fractional number reduction
885 *
886 * @nom: nominator
887 * @den: denominator
888 * @nom_min: minimum value for nominator
889 * @den_min: minimum value for denominator
890 *
891 * Find the greatest common divisor and apply it on both nominator and
892 * denominator, but make nominator and denominator are at least as large
893 * as their minimum values.
894 */
avivo_reduce_ratio(unsigned * nom,unsigned * den,unsigned nom_min,unsigned den_min)895 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
896 unsigned nom_min, unsigned den_min)
897 {
898 unsigned tmp;
899
900 /* reduce the numbers to a simpler ratio */
901 tmp = gcd(*nom, *den);
902 *nom /= tmp;
903 *den /= tmp;
904
905 /* make sure nominator is large enough */
906 if (*nom < nom_min) {
907 tmp = DIV_ROUND_UP(nom_min, *nom);
908 *nom *= tmp;
909 *den *= tmp;
910 }
911
912 /* make sure the denominator is large enough */
913 if (*den < den_min) {
914 tmp = DIV_ROUND_UP(den_min, *den);
915 *nom *= tmp;
916 *den *= tmp;
917 }
918 }
919
920 /**
921 * avivo_get_fb_ref_div - feedback and ref divider calculation
922 *
923 * @nom: nominator
924 * @den: denominator
925 * @post_div: post divider
926 * @fb_div_max: feedback divider maximum
927 * @ref_div_max: reference divider maximum
928 * @fb_div: resulting feedback divider
929 * @ref_div: resulting reference divider
930 *
931 * Calculate feedback and reference divider for a given post divider. Makes
932 * sure we stay within the limits.
933 */
avivo_get_fb_ref_div(unsigned nom,unsigned den,unsigned post_div,unsigned fb_div_max,unsigned ref_div_max,unsigned * fb_div,unsigned * ref_div)934 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
935 unsigned fb_div_max, unsigned ref_div_max,
936 unsigned *fb_div, unsigned *ref_div)
937 {
938 /* limit reference * post divider to a maximum */
939 ref_div_max = clamp(100 / post_div, 1u, ref_div_max);
940
941 /* get matching reference and feedback divider */
942 *ref_div = clamp(den / post_div, 1u, ref_div_max);
943 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
944
945 /* limit fb divider to its maximum */
946 if (*fb_div > fb_div_max) {
947 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
948 *fb_div = fb_div_max;
949 }
950 }
951
952 /**
953 * radeon_compute_pll_avivo - compute PLL paramaters
954 *
955 * @pll: information about the PLL
956 * @freq: target frequency
957 * @dot_clock_p: resulting pixel clock
958 * @fb_div_p: resulting feedback divider
959 * @frac_fb_div_p: fractional part of the feedback divider
960 * @ref_div_p: resulting reference divider
961 * @post_div_p: resulting reference divider
962 *
963 * Try to calculate the PLL parameters to generate the given frequency:
964 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
965 */
radeon_compute_pll_avivo(struct radeon_pll * pll,u32 freq,u32 * dot_clock_p,u32 * fb_div_p,u32 * frac_fb_div_p,u32 * ref_div_p,u32 * post_div_p)966 void radeon_compute_pll_avivo(struct radeon_pll *pll,
967 u32 freq,
968 u32 *dot_clock_p,
969 u32 *fb_div_p,
970 u32 *frac_fb_div_p,
971 u32 *ref_div_p,
972 u32 *post_div_p)
973 {
974 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
975 freq : freq / 10;
976
977 unsigned fb_div_min, fb_div_max, fb_div;
978 unsigned post_div_min, post_div_max, post_div;
979 unsigned ref_div_min, ref_div_max, ref_div;
980 unsigned post_div_best, diff_best;
981 unsigned nom, den;
982
983 /* determine allowed feedback divider range */
984 fb_div_min = pll->min_feedback_div;
985 fb_div_max = pll->max_feedback_div;
986
987 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
988 fb_div_min *= 10;
989 fb_div_max *= 10;
990 }
991
992 /* determine allowed ref divider range */
993 if (pll->flags & RADEON_PLL_USE_REF_DIV)
994 ref_div_min = pll->reference_div;
995 else
996 ref_div_min = pll->min_ref_div;
997
998 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
999 pll->flags & RADEON_PLL_USE_REF_DIV)
1000 ref_div_max = pll->reference_div;
1001 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1002 /* fix for problems on RS880 */
1003 ref_div_max = min(pll->max_ref_div, 7u);
1004 else
1005 ref_div_max = pll->max_ref_div;
1006
1007 /* determine allowed post divider range */
1008 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1009 post_div_min = pll->post_div;
1010 post_div_max = pll->post_div;
1011 } else {
1012 unsigned vco_min, vco_max;
1013
1014 if (pll->flags & RADEON_PLL_IS_LCD) {
1015 vco_min = pll->lcd_pll_out_min;
1016 vco_max = pll->lcd_pll_out_max;
1017 } else {
1018 vco_min = pll->pll_out_min;
1019 vco_max = pll->pll_out_max;
1020 }
1021
1022 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1023 vco_min *= 10;
1024 vco_max *= 10;
1025 }
1026
1027 post_div_min = vco_min / target_clock;
1028 if ((target_clock * post_div_min) < vco_min)
1029 ++post_div_min;
1030 if (post_div_min < pll->min_post_div)
1031 post_div_min = pll->min_post_div;
1032
1033 post_div_max = vco_max / target_clock;
1034 if ((target_clock * post_div_max) > vco_max)
1035 --post_div_max;
1036 if (post_div_max > pll->max_post_div)
1037 post_div_max = pll->max_post_div;
1038 }
1039
1040 /* represent the searched ratio as fractional number */
1041 nom = target_clock;
1042 den = pll->reference_freq;
1043
1044 /* reduce the numbers to a simpler ratio */
1045 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1046
1047 /* now search for a post divider */
1048 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1049 post_div_best = post_div_min;
1050 else
1051 post_div_best = post_div_max;
1052 diff_best = ~0;
1053
1054 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1055 unsigned diff;
1056 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1057 ref_div_max, &fb_div, &ref_div);
1058 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1059 (ref_div * post_div));
1060
1061 if (diff < diff_best || (diff == diff_best &&
1062 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1063
1064 post_div_best = post_div;
1065 diff_best = diff;
1066 }
1067 }
1068 post_div = post_div_best;
1069
1070 /* get the feedback and reference divider for the optimal value */
1071 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1072 &fb_div, &ref_div);
1073
1074 /* reduce the numbers to a simpler ratio once more */
1075 /* this also makes sure that the reference divider is large enough */
1076 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1077
1078 /* avoid high jitter with small fractional dividers */
1079 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1080 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1081 if (fb_div < fb_div_min) {
1082 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1083 fb_div *= tmp;
1084 ref_div *= tmp;
1085 }
1086 }
1087
1088 /* and finally save the result */
1089 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1090 *fb_div_p = fb_div / 10;
1091 *frac_fb_div_p = fb_div % 10;
1092 } else {
1093 *fb_div_p = fb_div;
1094 *frac_fb_div_p = 0;
1095 }
1096
1097 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1098 (pll->reference_freq * *frac_fb_div_p)) /
1099 (ref_div * post_div * 10);
1100 *ref_div_p = ref_div;
1101 *post_div_p = post_div;
1102
1103 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1104 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1105 ref_div, post_div);
1106 }
1107
1108 /* pre-avivo */
radeon_div(uint64_t n,uint32_t d)1109 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1110 {
1111 n += d / 2;
1112
1113 do_div(n, d);
1114 return n;
1115 }
1116
radeon_compute_pll_legacy(struct radeon_pll * pll,uint64_t freq,uint32_t * dot_clock_p,uint32_t * fb_div_p,uint32_t * frac_fb_div_p,uint32_t * ref_div_p,uint32_t * post_div_p)1117 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1118 uint64_t freq,
1119 uint32_t *dot_clock_p,
1120 uint32_t *fb_div_p,
1121 uint32_t *frac_fb_div_p,
1122 uint32_t *ref_div_p,
1123 uint32_t *post_div_p)
1124 {
1125 uint32_t min_ref_div = pll->min_ref_div;
1126 uint32_t max_ref_div = pll->max_ref_div;
1127 uint32_t min_post_div = pll->min_post_div;
1128 uint32_t max_post_div = pll->max_post_div;
1129 uint32_t min_fractional_feed_div = 0;
1130 uint32_t max_fractional_feed_div = 0;
1131 uint32_t best_vco = pll->best_vco;
1132 uint32_t best_post_div = 1;
1133 uint32_t best_ref_div = 1;
1134 uint32_t best_feedback_div = 1;
1135 uint32_t best_frac_feedback_div = 0;
1136 uint32_t best_freq = -1;
1137 uint32_t best_error = 0xffffffff;
1138 uint32_t best_vco_diff = 1;
1139 uint32_t post_div;
1140 u32 pll_out_min, pll_out_max;
1141
1142 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1143 freq = freq * 1000;
1144
1145 if (pll->flags & RADEON_PLL_IS_LCD) {
1146 pll_out_min = pll->lcd_pll_out_min;
1147 pll_out_max = pll->lcd_pll_out_max;
1148 } else {
1149 pll_out_min = pll->pll_out_min;
1150 pll_out_max = pll->pll_out_max;
1151 }
1152
1153 if (pll_out_min > 64800)
1154 pll_out_min = 64800;
1155
1156 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1157 min_ref_div = max_ref_div = pll->reference_div;
1158 else {
1159 while (min_ref_div < max_ref_div-1) {
1160 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1161 uint32_t pll_in = pll->reference_freq / mid;
1162 if (pll_in < pll->pll_in_min)
1163 max_ref_div = mid;
1164 else if (pll_in > pll->pll_in_max)
1165 min_ref_div = mid;
1166 else
1167 break;
1168 }
1169 }
1170
1171 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1172 min_post_div = max_post_div = pll->post_div;
1173
1174 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1175 min_fractional_feed_div = pll->min_frac_feedback_div;
1176 max_fractional_feed_div = pll->max_frac_feedback_div;
1177 }
1178
1179 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1180 uint32_t ref_div;
1181
1182 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1183 continue;
1184
1185 /* legacy radeons only have a few post_divs */
1186 if (pll->flags & RADEON_PLL_LEGACY) {
1187 if ((post_div == 5) ||
1188 (post_div == 7) ||
1189 (post_div == 9) ||
1190 (post_div == 10) ||
1191 (post_div == 11) ||
1192 (post_div == 13) ||
1193 (post_div == 14) ||
1194 (post_div == 15))
1195 continue;
1196 }
1197
1198 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1199 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1200 uint32_t pll_in = pll->reference_freq / ref_div;
1201 uint32_t min_feed_div = pll->min_feedback_div;
1202 uint32_t max_feed_div = pll->max_feedback_div + 1;
1203
1204 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1205 continue;
1206
1207 while (min_feed_div < max_feed_div) {
1208 uint32_t vco;
1209 uint32_t min_frac_feed_div = min_fractional_feed_div;
1210 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1211 uint32_t frac_feedback_div;
1212 uint64_t tmp;
1213
1214 feedback_div = (min_feed_div + max_feed_div) / 2;
1215
1216 tmp = (uint64_t)pll->reference_freq * feedback_div;
1217 vco = radeon_div(tmp, ref_div);
1218
1219 if (vco < pll_out_min) {
1220 min_feed_div = feedback_div + 1;
1221 continue;
1222 } else if (vco > pll_out_max) {
1223 max_feed_div = feedback_div;
1224 continue;
1225 }
1226
1227 while (min_frac_feed_div < max_frac_feed_div) {
1228 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1229 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1230 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1231 current_freq = radeon_div(tmp, ref_div * post_div);
1232
1233 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1234 if (freq < current_freq)
1235 error = 0xffffffff;
1236 else
1237 error = freq - current_freq;
1238 } else
1239 error = abs(current_freq - freq);
1240 vco_diff = abs(vco - best_vco);
1241
1242 if ((best_vco == 0 && error < best_error) ||
1243 (best_vco != 0 &&
1244 ((best_error > 100 && error < best_error - 100) ||
1245 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1246 best_post_div = post_div;
1247 best_ref_div = ref_div;
1248 best_feedback_div = feedback_div;
1249 best_frac_feedback_div = frac_feedback_div;
1250 best_freq = current_freq;
1251 best_error = error;
1252 best_vco_diff = vco_diff;
1253 } else if (current_freq == freq) {
1254 if (best_freq == -1) {
1255 best_post_div = post_div;
1256 best_ref_div = ref_div;
1257 best_feedback_div = feedback_div;
1258 best_frac_feedback_div = frac_feedback_div;
1259 best_freq = current_freq;
1260 best_error = error;
1261 best_vco_diff = vco_diff;
1262 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1263 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1264 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1265 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1266 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1267 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1268 best_post_div = post_div;
1269 best_ref_div = ref_div;
1270 best_feedback_div = feedback_div;
1271 best_frac_feedback_div = frac_feedback_div;
1272 best_freq = current_freq;
1273 best_error = error;
1274 best_vco_diff = vco_diff;
1275 }
1276 }
1277 if (current_freq < freq)
1278 min_frac_feed_div = frac_feedback_div + 1;
1279 else
1280 max_frac_feed_div = frac_feedback_div;
1281 }
1282 if (current_freq < freq)
1283 min_feed_div = feedback_div + 1;
1284 else
1285 max_feed_div = feedback_div;
1286 }
1287 }
1288 }
1289
1290 *dot_clock_p = best_freq / 10000;
1291 *fb_div_p = best_feedback_div;
1292 *frac_fb_div_p = best_frac_feedback_div;
1293 *ref_div_p = best_ref_div;
1294 *post_div_p = best_post_div;
1295 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1296 (long long)freq,
1297 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1298 best_ref_div, best_post_div);
1299
1300 }
1301
1302 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1303 .destroy = drm_gem_fb_destroy,
1304 .create_handle = drm_gem_fb_create_handle,
1305 };
1306
1307 int
radeon_framebuffer_init(struct drm_device * dev,struct drm_framebuffer * fb,const struct drm_format_info * info,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1308 radeon_framebuffer_init(struct drm_device *dev,
1309 struct drm_framebuffer *fb,
1310 const struct drm_format_info *info,
1311 const struct drm_mode_fb_cmd2 *mode_cmd,
1312 struct drm_gem_object *obj)
1313 {
1314 int ret;
1315 fb->obj[0] = obj;
1316 drm_helper_mode_fill_fb_struct(dev, fb, info, mode_cmd);
1317 ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs);
1318 if (ret) {
1319 fb->obj[0] = NULL;
1320 return ret;
1321 }
1322 return 0;
1323 }
1324
1325 static struct drm_framebuffer *
radeon_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_format_info * info,const struct drm_mode_fb_cmd2 * mode_cmd)1326 radeon_user_framebuffer_create(struct drm_device *dev,
1327 struct drm_file *file_priv,
1328 const struct drm_format_info *info,
1329 const struct drm_mode_fb_cmd2 *mode_cmd)
1330 {
1331 struct drm_gem_object *obj;
1332 struct drm_framebuffer *fb;
1333 int ret;
1334
1335 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1336 if (obj == NULL) {
1337 dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1338 "can't create framebuffer\n", mode_cmd->handles[0]);
1339 return ERR_PTR(-ENOENT);
1340 }
1341
1342 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1343 if (obj->import_attach) {
1344 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1345 drm_gem_object_put(obj);
1346 return ERR_PTR(-EINVAL);
1347 }
1348
1349 fb = kzalloc_obj(*fb);
1350 if (fb == NULL) {
1351 drm_gem_object_put(obj);
1352 return ERR_PTR(-ENOMEM);
1353 }
1354
1355 ret = radeon_framebuffer_init(dev, fb, info, mode_cmd, obj);
1356 if (ret) {
1357 kfree(fb);
1358 drm_gem_object_put(obj);
1359 return ERR_PTR(ret);
1360 }
1361
1362 return fb;
1363 }
1364
1365 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1366 .fb_create = radeon_user_framebuffer_create,
1367 };
1368
1369 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1370 { { 0, "driver" },
1371 { 1, "bios" },
1372 };
1373
1374 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1375 { { TV_STD_NTSC, "ntsc" },
1376 { TV_STD_PAL, "pal" },
1377 { TV_STD_PAL_M, "pal-m" },
1378 { TV_STD_PAL_60, "pal-60" },
1379 { TV_STD_NTSC_J, "ntsc-j" },
1380 { TV_STD_SCART_PAL, "scart-pal" },
1381 { TV_STD_PAL_CN, "pal-cn" },
1382 { TV_STD_SECAM, "secam" },
1383 };
1384
1385 static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1386 { { UNDERSCAN_OFF, "off" },
1387 { UNDERSCAN_ON, "on" },
1388 { UNDERSCAN_AUTO, "auto" },
1389 };
1390
1391 static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1392 { { RADEON_AUDIO_DISABLE, "off" },
1393 { RADEON_AUDIO_ENABLE, "on" },
1394 { RADEON_AUDIO_AUTO, "auto" },
1395 };
1396
1397 /* XXX support different dither options? spatial, temporal, both, etc. */
1398 static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1399 { { RADEON_FMT_DITHER_DISABLE, "off" },
1400 { RADEON_FMT_DITHER_ENABLE, "on" },
1401 };
1402
1403 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1404 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1405 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1406 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1407 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1408 };
1409
radeon_modeset_create_props(struct radeon_device * rdev)1410 static int radeon_modeset_create_props(struct radeon_device *rdev)
1411 {
1412 int sz;
1413
1414 if (rdev->is_atom_bios) {
1415 rdev->mode_info.coherent_mode_property =
1416 drm_property_create_range(rdev_to_drm(rdev), 0, "coherent", 0, 1);
1417 if (!rdev->mode_info.coherent_mode_property)
1418 return -ENOMEM;
1419 }
1420
1421 if (!ASIC_IS_AVIVO(rdev)) {
1422 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1423 rdev->mode_info.tmds_pll_property =
1424 drm_property_create_enum(rdev_to_drm(rdev), 0,
1425 "tmds_pll",
1426 radeon_tmds_pll_enum_list, sz);
1427 }
1428
1429 rdev->mode_info.load_detect_property =
1430 drm_property_create_range(rdev_to_drm(rdev), 0, "load detection", 0, 1);
1431 if (!rdev->mode_info.load_detect_property)
1432 return -ENOMEM;
1433
1434 drm_mode_create_scaling_mode_property(rdev_to_drm(rdev));
1435
1436 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1437 rdev->mode_info.tv_std_property =
1438 drm_property_create_enum(rdev_to_drm(rdev), 0,
1439 "tv standard",
1440 radeon_tv_std_enum_list, sz);
1441
1442 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1443 rdev->mode_info.underscan_property =
1444 drm_property_create_enum(rdev_to_drm(rdev), 0,
1445 "underscan",
1446 radeon_underscan_enum_list, sz);
1447
1448 rdev->mode_info.underscan_hborder_property =
1449 drm_property_create_range(rdev_to_drm(rdev), 0,
1450 "underscan hborder", 0, 128);
1451 if (!rdev->mode_info.underscan_hborder_property)
1452 return -ENOMEM;
1453
1454 rdev->mode_info.underscan_vborder_property =
1455 drm_property_create_range(rdev_to_drm(rdev), 0,
1456 "underscan vborder", 0, 128);
1457 if (!rdev->mode_info.underscan_vborder_property)
1458 return -ENOMEM;
1459
1460 sz = ARRAY_SIZE(radeon_audio_enum_list);
1461 rdev->mode_info.audio_property =
1462 drm_property_create_enum(rdev_to_drm(rdev), 0,
1463 "audio",
1464 radeon_audio_enum_list, sz);
1465
1466 sz = ARRAY_SIZE(radeon_dither_enum_list);
1467 rdev->mode_info.dither_property =
1468 drm_property_create_enum(rdev_to_drm(rdev), 0,
1469 "dither",
1470 radeon_dither_enum_list, sz);
1471
1472 sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1473 rdev->mode_info.output_csc_property =
1474 drm_property_create_enum(rdev_to_drm(rdev), 0,
1475 "output_csc",
1476 radeon_output_csc_enum_list, sz);
1477
1478 return 0;
1479 }
1480
radeon_update_display_priority(struct radeon_device * rdev)1481 void radeon_update_display_priority(struct radeon_device *rdev)
1482 {
1483 /* adjustment options for the display watermarks */
1484 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1485 /* set display priority to high for r3xx, rv515 chips
1486 * this avoids flickering due to underflow to the
1487 * display controllers during heavy acceleration.
1488 * Don't force high on rs4xx igp chips as it seems to
1489 * affect the sound card. See kernel bug 15982.
1490 */
1491 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1492 !(rdev->flags & RADEON_IS_IGP))
1493 rdev->disp_priority = 2;
1494 else
1495 rdev->disp_priority = 0;
1496 } else
1497 rdev->disp_priority = radeon_disp_priority;
1498
1499 }
1500
1501 /*
1502 * Allocate hdmi structs and determine register offsets
1503 */
radeon_afmt_init(struct radeon_device * rdev)1504 static void radeon_afmt_init(struct radeon_device *rdev)
1505 {
1506 int i;
1507
1508 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1509 rdev->mode_info.afmt[i] = NULL;
1510
1511 if (ASIC_IS_NODCE(rdev)) {
1512 /* nothing to do */
1513 } else if (ASIC_IS_DCE4(rdev)) {
1514 static uint32_t eg_offsets[] = {
1515 EVERGREEN_CRTC0_REGISTER_OFFSET,
1516 EVERGREEN_CRTC1_REGISTER_OFFSET,
1517 EVERGREEN_CRTC2_REGISTER_OFFSET,
1518 EVERGREEN_CRTC3_REGISTER_OFFSET,
1519 EVERGREEN_CRTC4_REGISTER_OFFSET,
1520 EVERGREEN_CRTC5_REGISTER_OFFSET,
1521 0x13830 - 0x7030,
1522 };
1523 int num_afmt;
1524
1525 /* DCE8 has 7 audio blocks tied to DIG encoders */
1526 /* DCE6 has 6 audio blocks tied to DIG encoders */
1527 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1528 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1529 if (ASIC_IS_DCE8(rdev))
1530 num_afmt = 7;
1531 else if (ASIC_IS_DCE6(rdev))
1532 num_afmt = 6;
1533 else if (ASIC_IS_DCE5(rdev))
1534 num_afmt = 6;
1535 else if (ASIC_IS_DCE41(rdev))
1536 num_afmt = 2;
1537 else /* DCE4 */
1538 num_afmt = 6;
1539
1540 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1541 for (i = 0; i < num_afmt; i++) {
1542 rdev->mode_info.afmt[i] = kzalloc_obj(struct radeon_afmt);
1543 if (rdev->mode_info.afmt[i]) {
1544 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1545 rdev->mode_info.afmt[i]->id = i;
1546 }
1547 }
1548 } else if (ASIC_IS_DCE3(rdev)) {
1549 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1550 rdev->mode_info.afmt[0] = kzalloc_obj(struct radeon_afmt);
1551 if (rdev->mode_info.afmt[0]) {
1552 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1553 rdev->mode_info.afmt[0]->id = 0;
1554 }
1555 rdev->mode_info.afmt[1] = kzalloc_obj(struct radeon_afmt);
1556 if (rdev->mode_info.afmt[1]) {
1557 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1558 rdev->mode_info.afmt[1]->id = 1;
1559 }
1560 } else if (ASIC_IS_DCE2(rdev)) {
1561 /* DCE2 has at least 1 routable audio block */
1562 rdev->mode_info.afmt[0] = kzalloc_obj(struct radeon_afmt);
1563 if (rdev->mode_info.afmt[0]) {
1564 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1565 rdev->mode_info.afmt[0]->id = 0;
1566 }
1567 /* r6xx has 2 routable audio blocks */
1568 if (rdev->family >= CHIP_R600) {
1569 rdev->mode_info.afmt[1] = kzalloc_obj(struct radeon_afmt);
1570 if (rdev->mode_info.afmt[1]) {
1571 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1572 rdev->mode_info.afmt[1]->id = 1;
1573 }
1574 }
1575 }
1576 }
1577
radeon_afmt_fini(struct radeon_device * rdev)1578 static void radeon_afmt_fini(struct radeon_device *rdev)
1579 {
1580 int i;
1581
1582 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1583 kfree(rdev->mode_info.afmt[i]);
1584 rdev->mode_info.afmt[i] = NULL;
1585 }
1586 }
1587
radeon_modeset_init(struct radeon_device * rdev)1588 int radeon_modeset_init(struct radeon_device *rdev)
1589 {
1590 int i;
1591 int ret;
1592
1593 drm_mode_config_init(rdev_to_drm(rdev));
1594 rdev->mode_info.mode_config_initialized = true;
1595
1596 rdev_to_drm(rdev)->mode_config.funcs = &radeon_mode_funcs;
1597
1598 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1599 rdev_to_drm(rdev)->mode_config.async_page_flip = true;
1600
1601 if (ASIC_IS_DCE5(rdev)) {
1602 rdev_to_drm(rdev)->mode_config.max_width = 16384;
1603 rdev_to_drm(rdev)->mode_config.max_height = 16384;
1604 } else if (ASIC_IS_AVIVO(rdev)) {
1605 rdev_to_drm(rdev)->mode_config.max_width = 8192;
1606 rdev_to_drm(rdev)->mode_config.max_height = 8192;
1607 } else {
1608 rdev_to_drm(rdev)->mode_config.max_width = 4096;
1609 rdev_to_drm(rdev)->mode_config.max_height = 4096;
1610 }
1611
1612 rdev_to_drm(rdev)->mode_config.preferred_depth = 24;
1613 rdev_to_drm(rdev)->mode_config.prefer_shadow = 1;
1614
1615 rdev_to_drm(rdev)->mode_config.fb_modifiers_not_supported = true;
1616
1617 ret = radeon_modeset_create_props(rdev);
1618 if (ret) {
1619 return ret;
1620 }
1621
1622 /* init i2c buses */
1623 radeon_i2c_init(rdev);
1624
1625 /* check combios for a valid hardcoded EDID - Sun servers */
1626 if (!rdev->is_atom_bios) {
1627 /* check for hardcoded EDID in BIOS */
1628 radeon_combios_check_hardcoded_edid(rdev);
1629 }
1630
1631 /* allocate crtcs */
1632 for (i = 0; i < rdev->num_crtc; i++) {
1633 radeon_crtc_init(rdev_to_drm(rdev), i);
1634 }
1635
1636 /* okay we should have all the bios connectors */
1637 ret = radeon_setup_enc_conn(rdev_to_drm(rdev));
1638 if (!ret) {
1639 return ret;
1640 }
1641
1642 /* init dig PHYs, disp eng pll */
1643 if (rdev->is_atom_bios) {
1644 radeon_atom_encoder_init(rdev);
1645 radeon_atom_disp_eng_pll_init(rdev);
1646 }
1647
1648 /* initialize hpd */
1649 radeon_hpd_init(rdev);
1650
1651 /* setup afmt */
1652 radeon_afmt_init(rdev);
1653
1654 drm_kms_helper_poll_init(rdev_to_drm(rdev));
1655
1656 /* do pm late init */
1657 ret = radeon_pm_late_init(rdev);
1658
1659 return 0;
1660 }
1661
radeon_modeset_fini(struct radeon_device * rdev)1662 void radeon_modeset_fini(struct radeon_device *rdev)
1663 {
1664 if (rdev->mode_info.mode_config_initialized) {
1665 drm_kms_helper_poll_fini(rdev_to_drm(rdev));
1666 radeon_hpd_fini(rdev);
1667 drm_helper_force_disable_all(rdev_to_drm(rdev));
1668 radeon_afmt_fini(rdev);
1669 drm_mode_config_cleanup(rdev_to_drm(rdev));
1670 rdev->mode_info.mode_config_initialized = false;
1671 }
1672
1673 drm_edid_free(rdev->mode_info.bios_hardcoded_edid);
1674
1675 /* free i2c buses */
1676 radeon_i2c_fini(rdev);
1677 }
1678
is_hdtv_mode(const struct drm_display_mode * mode)1679 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1680 {
1681 /* try and guess if this is a tv or a monitor */
1682 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1683 (mode->vdisplay == 576) || /* 576p */
1684 (mode->vdisplay == 720) || /* 720p */
1685 (mode->vdisplay == 1080)) /* 1080p */
1686 return true;
1687 else
1688 return false;
1689 }
1690
radeon_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1691 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1692 const struct drm_display_mode *mode,
1693 struct drm_display_mode *adjusted_mode)
1694 {
1695 struct drm_device *dev = crtc->dev;
1696 struct radeon_device *rdev = dev->dev_private;
1697 struct drm_encoder *encoder;
1698 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1699 struct radeon_encoder *radeon_encoder;
1700 struct drm_connector *connector;
1701 bool first = true;
1702 u32 src_v = 1, dst_v = 1;
1703 u32 src_h = 1, dst_h = 1;
1704
1705 radeon_crtc->h_border = 0;
1706 radeon_crtc->v_border = 0;
1707
1708 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1709 if (encoder->crtc != crtc)
1710 continue;
1711 radeon_encoder = to_radeon_encoder(encoder);
1712 connector = radeon_get_connector_for_encoder(encoder);
1713
1714 if (first) {
1715 /* set scaling */
1716 if (radeon_encoder->rmx_type == RMX_OFF)
1717 radeon_crtc->rmx_type = RMX_OFF;
1718 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1719 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1720 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1721 else
1722 radeon_crtc->rmx_type = RMX_OFF;
1723 /* copy native mode */
1724 memcpy(&radeon_crtc->native_mode,
1725 &radeon_encoder->native_mode,
1726 sizeof(struct drm_display_mode));
1727 src_v = crtc->mode.vdisplay;
1728 dst_v = radeon_crtc->native_mode.vdisplay;
1729 src_h = crtc->mode.hdisplay;
1730 dst_h = radeon_crtc->native_mode.hdisplay;
1731
1732 /* fix up for overscan on hdmi */
1733 if (ASIC_IS_AVIVO(rdev) &&
1734 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1735 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1736 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1737 connector->display_info.is_hdmi &&
1738 is_hdtv_mode(mode)))) {
1739 if (radeon_encoder->underscan_hborder != 0)
1740 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1741 else
1742 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1743 if (radeon_encoder->underscan_vborder != 0)
1744 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1745 else
1746 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1747 radeon_crtc->rmx_type = RMX_FULL;
1748 src_v = crtc->mode.vdisplay;
1749 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1750 src_h = crtc->mode.hdisplay;
1751 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1752 }
1753 first = false;
1754 } else {
1755 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1756 /* WARNING: Right now this can't happen but
1757 * in the future we need to check that scaling
1758 * are consistent across different encoder
1759 * (ie all encoder can work with the same
1760 * scaling).
1761 */
1762 drm_err(dev, "Scaling not consistent across encoder.\n");
1763 return false;
1764 }
1765 }
1766 }
1767 if (radeon_crtc->rmx_type != RMX_OFF) {
1768 fixed20_12 a, b;
1769 a.full = dfixed_const(src_v);
1770 b.full = dfixed_const(dst_v);
1771 radeon_crtc->vsc.full = dfixed_div(a, b);
1772 a.full = dfixed_const(src_h);
1773 b.full = dfixed_const(dst_h);
1774 radeon_crtc->hsc.full = dfixed_div(a, b);
1775 } else {
1776 radeon_crtc->vsc.full = dfixed_const(1);
1777 radeon_crtc->hsc.full = dfixed_const(1);
1778 }
1779 return true;
1780 }
1781
1782 /*
1783 * Retrieve current video scanout position of crtc on a given gpu, and
1784 * an optional accurate timestamp of when query happened.
1785 *
1786 * \param dev Device to query.
1787 * \param crtc Crtc to query.
1788 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1789 * For driver internal use only also supports these flags:
1790 *
1791 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1792 * of a fudged earlier start of vblank.
1793 *
1794 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1795 * fudged earlier start of vblank in *vpos and the distance
1796 * to true start of vblank in *hpos.
1797 *
1798 * \param *vpos Location where vertical scanout position should be stored.
1799 * \param *hpos Location where horizontal scanout position should go.
1800 * \param *stime Target location for timestamp taken immediately before
1801 * scanout position query. Can be NULL to skip timestamp.
1802 * \param *etime Target location for timestamp taken immediately after
1803 * scanout position query. Can be NULL to skip timestamp.
1804 *
1805 * Returns vpos as a positive number while in active scanout area.
1806 * Returns vpos as a negative number inside vblank, counting the number
1807 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1808 * until start of active scanout / end of vblank."
1809 *
1810 * \return Flags, or'ed together as follows:
1811 *
1812 * DRM_SCANOUTPOS_VALID = Query successful.
1813 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1814 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1815 * this flag means that returned position may be offset by a constant but
1816 * unknown small number of scanlines wrt. real scanout position.
1817 *
1818 */
radeon_get_crtc_scanoutpos(struct drm_device * dev,unsigned int pipe,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1819 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1820 unsigned int flags, int *vpos, int *hpos,
1821 ktime_t *stime, ktime_t *etime,
1822 const struct drm_display_mode *mode)
1823 {
1824 u32 stat_crtc = 0, vbl = 0, position = 0;
1825 int vbl_start, vbl_end, vtotal, ret = 0;
1826 bool in_vbl = true;
1827
1828 struct radeon_device *rdev = dev->dev_private;
1829
1830 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1831
1832 /* Get optional system timestamp before query. */
1833 if (stime)
1834 *stime = ktime_get();
1835
1836 if (ASIC_IS_DCE4(rdev)) {
1837 if (pipe == 0) {
1838 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1839 EVERGREEN_CRTC0_REGISTER_OFFSET);
1840 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1841 EVERGREEN_CRTC0_REGISTER_OFFSET);
1842 ret |= DRM_SCANOUTPOS_VALID;
1843 }
1844 if (pipe == 1) {
1845 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1846 EVERGREEN_CRTC1_REGISTER_OFFSET);
1847 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1848 EVERGREEN_CRTC1_REGISTER_OFFSET);
1849 ret |= DRM_SCANOUTPOS_VALID;
1850 }
1851 if (pipe == 2) {
1852 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1853 EVERGREEN_CRTC2_REGISTER_OFFSET);
1854 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1855 EVERGREEN_CRTC2_REGISTER_OFFSET);
1856 ret |= DRM_SCANOUTPOS_VALID;
1857 }
1858 if (pipe == 3) {
1859 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1860 EVERGREEN_CRTC3_REGISTER_OFFSET);
1861 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1862 EVERGREEN_CRTC3_REGISTER_OFFSET);
1863 ret |= DRM_SCANOUTPOS_VALID;
1864 }
1865 if (pipe == 4) {
1866 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1867 EVERGREEN_CRTC4_REGISTER_OFFSET);
1868 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1869 EVERGREEN_CRTC4_REGISTER_OFFSET);
1870 ret |= DRM_SCANOUTPOS_VALID;
1871 }
1872 if (pipe == 5) {
1873 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1874 EVERGREEN_CRTC5_REGISTER_OFFSET);
1875 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1876 EVERGREEN_CRTC5_REGISTER_OFFSET);
1877 ret |= DRM_SCANOUTPOS_VALID;
1878 }
1879 } else if (ASIC_IS_AVIVO(rdev)) {
1880 if (pipe == 0) {
1881 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1882 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1883 ret |= DRM_SCANOUTPOS_VALID;
1884 }
1885 if (pipe == 1) {
1886 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1887 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1888 ret |= DRM_SCANOUTPOS_VALID;
1889 }
1890 } else {
1891 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1892 if (pipe == 0) {
1893 /* Assume vbl_end == 0, get vbl_start from
1894 * upper 16 bits.
1895 */
1896 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1897 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1898 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1899 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1900 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1901 if (!(stat_crtc & 1))
1902 in_vbl = false;
1903
1904 ret |= DRM_SCANOUTPOS_VALID;
1905 }
1906 if (pipe == 1) {
1907 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1908 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1909 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1910 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1911 if (!(stat_crtc & 1))
1912 in_vbl = false;
1913
1914 ret |= DRM_SCANOUTPOS_VALID;
1915 }
1916 }
1917
1918 /* Get optional system timestamp after query. */
1919 if (etime)
1920 *etime = ktime_get();
1921
1922 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1923
1924 /* Decode into vertical and horizontal scanout position. */
1925 *vpos = position & 0x1fff;
1926 *hpos = (position >> 16) & 0x1fff;
1927
1928 /* Valid vblank area boundaries from gpu retrieved? */
1929 if (vbl > 0) {
1930 /* Yes: Decode. */
1931 ret |= DRM_SCANOUTPOS_ACCURATE;
1932 vbl_start = vbl & 0x1fff;
1933 vbl_end = (vbl >> 16) & 0x1fff;
1934 }
1935 else {
1936 /* No: Fake something reasonable which gives at least ok results. */
1937 vbl_start = mode->crtc_vdisplay;
1938 vbl_end = 0;
1939 }
1940
1941 /* Called from driver internal vblank counter query code? */
1942 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1943 /* Caller wants distance from real vbl_start in *hpos */
1944 *hpos = *vpos - vbl_start;
1945 }
1946
1947 /* Fudge vblank to start a few scanlines earlier to handle the
1948 * problem that vblank irqs fire a few scanlines before start
1949 * of vblank. Some driver internal callers need the true vblank
1950 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1951 *
1952 * The cause of the "early" vblank irq is that the irq is triggered
1953 * by the line buffer logic when the line buffer read position enters
1954 * the vblank, whereas our crtc scanout position naturally lags the
1955 * line buffer read position.
1956 */
1957 if (!(flags & USE_REAL_VBLANKSTART))
1958 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1959
1960 /* Test scanout position against vblank region. */
1961 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1962 in_vbl = false;
1963
1964 /* In vblank? */
1965 if (in_vbl)
1966 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1967
1968 /* Called from driver internal vblank counter query code? */
1969 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1970 /* Caller wants distance from fudged earlier vbl_start */
1971 *vpos -= vbl_start;
1972 return ret;
1973 }
1974
1975 /* Check if inside vblank area and apply corrective offsets:
1976 * vpos will then be >=0 in video scanout area, but negative
1977 * within vblank area, counting down the number of lines until
1978 * start of scanout.
1979 */
1980
1981 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1982 if (in_vbl && (*vpos >= vbl_start)) {
1983 vtotal = mode->crtc_vtotal;
1984 *vpos = *vpos - vtotal;
1985 }
1986
1987 /* Correct for shifted end of vbl at vbl_end. */
1988 *vpos = *vpos - vbl_end;
1989
1990 return ret;
1991 }
1992
1993 bool
radeon_get_crtc_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1994 radeon_get_crtc_scanout_position(struct drm_crtc *crtc,
1995 bool in_vblank_irq, int *vpos, int *hpos,
1996 ktime_t *stime, ktime_t *etime,
1997 const struct drm_display_mode *mode)
1998 {
1999 struct drm_device *dev = crtc->dev;
2000 unsigned int pipe = crtc->index;
2001
2002 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
2003 stime, etime, mode);
2004 }
2005