1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for the Nuvoton NAU7802 ADC
4 *
5 * Copyright 2013 Free Electrons
6 */
7
8 #include <linux/delay.h>
9 #include <linux/i2c.h>
10 #include <linux/interrupt.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/property.h>
14 #include <linux/wait.h>
15 #include <linux/log2.h>
16
17 #include <linux/iio/iio.h>
18 #include <linux/iio/sysfs.h>
19
20 #define NAU7802_REG_PUCTRL 0x00
21 #define NAU7802_PUCTRL_RR(x) (x << 0)
22 #define NAU7802_PUCTRL_RR_BIT NAU7802_PUCTRL_RR(1)
23 #define NAU7802_PUCTRL_PUD(x) (x << 1)
24 #define NAU7802_PUCTRL_PUD_BIT NAU7802_PUCTRL_PUD(1)
25 #define NAU7802_PUCTRL_PUA(x) (x << 2)
26 #define NAU7802_PUCTRL_PUA_BIT NAU7802_PUCTRL_PUA(1)
27 #define NAU7802_PUCTRL_PUR(x) (x << 3)
28 #define NAU7802_PUCTRL_PUR_BIT NAU7802_PUCTRL_PUR(1)
29 #define NAU7802_PUCTRL_CS(x) (x << 4)
30 #define NAU7802_PUCTRL_CS_BIT NAU7802_PUCTRL_CS(1)
31 #define NAU7802_PUCTRL_CR(x) (x << 5)
32 #define NAU7802_PUCTRL_CR_BIT NAU7802_PUCTRL_CR(1)
33 #define NAU7802_PUCTRL_AVDDS(x) (x << 7)
34 #define NAU7802_PUCTRL_AVDDS_BIT NAU7802_PUCTRL_AVDDS(1)
35 #define NAU7802_REG_CTRL1 0x01
36 #define NAU7802_CTRL1_VLDO(x) (x << 3)
37 #define NAU7802_CTRL1_GAINS(x) (x)
38 #define NAU7802_CTRL1_GAINS_BITS 0x07
39 #define NAU7802_REG_CTRL2 0x02
40 #define NAU7802_CTRL2_CHS(x) (x << 7)
41 #define NAU7802_CTRL2_CRS(x) (x << 4)
42 #define NAU7802_SAMP_FREQ_320 0x07
43 #define NAU7802_CTRL2_CHS_BIT NAU7802_CTRL2_CHS(1)
44 #define NAU7802_REG_ADC_B2 0x12
45 #define NAU7802_REG_ADC_B1 0x13
46 #define NAU7802_REG_ADC_B0 0x14
47 #define NAU7802_REG_ADC_CTRL 0x15
48
49 #define NAU7802_MIN_CONVERSIONS 6
50
51 struct nau7802_state {
52 struct i2c_client *client;
53 s32 last_value;
54 struct mutex lock;
55 struct mutex data_lock;
56 u32 vref_mv;
57 u32 conversion_count;
58 u8 sample_rate;
59 u32 scale_avail[8];
60 struct completion value_ok;
61 };
62
63 #define NAU7802_CHANNEL(chan) { \
64 .type = IIO_VOLTAGE, \
65 .indexed = 1, \
66 .channel = (chan), \
67 .scan_index = (chan), \
68 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
69 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
70 BIT(IIO_CHAN_INFO_SAMP_FREQ) \
71 }
72
73 static const struct iio_chan_spec nau7802_chan_array[] = {
74 NAU7802_CHANNEL(0),
75 NAU7802_CHANNEL(1),
76 };
77
78 static const u16 nau7802_sample_freq_avail[] = {10, 20, 40, 80,
79 10, 10, 10, 320};
80
nau7802_show_scales(struct device * dev,struct device_attribute * attr,char * buf)81 static ssize_t nau7802_show_scales(struct device *dev,
82 struct device_attribute *attr, char *buf)
83 {
84 struct nau7802_state *st = iio_priv(dev_to_iio_dev(dev));
85 int i, len = 0;
86
87 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
88 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09d ",
89 st->scale_avail[i]);
90
91 buf[len-1] = '\n';
92
93 return len;
94 }
95
96 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 40 80 320");
97
98 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, nau7802_show_scales,
99 NULL, 0);
100
101 static struct attribute *nau7802_attributes[] = {
102 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
103 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
104 NULL
105 };
106
107 static const struct attribute_group nau7802_attribute_group = {
108 .attrs = nau7802_attributes,
109 };
110
nau7802_set_gain(struct nau7802_state * st,int gain)111 static int nau7802_set_gain(struct nau7802_state *st, int gain)
112 {
113 int ret;
114
115 mutex_lock(&st->lock);
116 st->conversion_count = 0;
117
118 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
119 if (ret < 0)
120 goto nau7802_sysfs_set_gain_out;
121 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
122 (ret & (~NAU7802_CTRL1_GAINS_BITS)) |
123 gain);
124
125 nau7802_sysfs_set_gain_out:
126 mutex_unlock(&st->lock);
127
128 return ret;
129 }
130
nau7802_read_conversion(struct nau7802_state * st)131 static int nau7802_read_conversion(struct nau7802_state *st)
132 {
133 int data;
134
135 mutex_lock(&st->data_lock);
136 data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B2);
137 if (data < 0)
138 goto nau7802_read_conversion_out;
139 st->last_value = data << 16;
140
141 data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B1);
142 if (data < 0)
143 goto nau7802_read_conversion_out;
144 st->last_value |= data << 8;
145
146 data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B0);
147 if (data < 0)
148 goto nau7802_read_conversion_out;
149 st->last_value |= data;
150
151 st->last_value = sign_extend32(st->last_value, 23);
152
153 nau7802_read_conversion_out:
154 mutex_unlock(&st->data_lock);
155
156 return data;
157 }
158
159 /*
160 * Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT
161 */
nau7802_sync(struct nau7802_state * st)162 static int nau7802_sync(struct nau7802_state *st)
163 {
164 int ret;
165
166 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
167 if (ret < 0)
168 return ret;
169 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
170 ret | NAU7802_PUCTRL_CS_BIT);
171
172 return ret;
173 }
174
nau7802_eoc_trigger(int irq,void * private)175 static irqreturn_t nau7802_eoc_trigger(int irq, void *private)
176 {
177 struct iio_dev *indio_dev = private;
178 struct nau7802_state *st = iio_priv(indio_dev);
179 int status;
180
181 status = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
182 if (status < 0)
183 return IRQ_HANDLED;
184
185 if (!(status & NAU7802_PUCTRL_CR_BIT))
186 return IRQ_NONE;
187
188 if (nau7802_read_conversion(st) < 0)
189 return IRQ_HANDLED;
190
191 /*
192 * Because there is actually only one ADC for both channels, we have to
193 * wait for enough conversions to happen before getting a significant
194 * value when changing channels and the values are far apart.
195 */
196 if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
197 st->conversion_count++;
198 if (st->conversion_count >= NAU7802_MIN_CONVERSIONS)
199 complete(&st->value_ok);
200
201 return IRQ_HANDLED;
202 }
203
nau7802_read_irq(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)204 static int nau7802_read_irq(struct iio_dev *indio_dev,
205 struct iio_chan_spec const *chan,
206 int *val)
207 {
208 struct nau7802_state *st = iio_priv(indio_dev);
209 int ret;
210
211 reinit_completion(&st->value_ok);
212 enable_irq(st->client->irq);
213
214 nau7802_sync(st);
215
216 /* read registers to ensure we flush everything */
217 ret = nau7802_read_conversion(st);
218 if (ret < 0)
219 goto read_chan_info_failure;
220
221 /* Wait for a conversion to finish */
222 ret = wait_for_completion_interruptible_timeout(&st->value_ok,
223 msecs_to_jiffies(1000));
224 if (ret == 0)
225 ret = -ETIMEDOUT;
226
227 if (ret < 0)
228 goto read_chan_info_failure;
229
230 disable_irq(st->client->irq);
231
232 *val = st->last_value;
233
234 return IIO_VAL_INT;
235
236 read_chan_info_failure:
237 disable_irq(st->client->irq);
238
239 return ret;
240 }
241
nau7802_read_poll(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)242 static int nau7802_read_poll(struct iio_dev *indio_dev,
243 struct iio_chan_spec const *chan,
244 int *val)
245 {
246 struct nau7802_state *st = iio_priv(indio_dev);
247 int ret;
248
249 nau7802_sync(st);
250
251 /* read registers to ensure we flush everything */
252 ret = nau7802_read_conversion(st);
253 if (ret < 0)
254 return ret;
255
256 /*
257 * Because there is actually only one ADC for both channels, we have to
258 * wait for enough conversions to happen before getting a significant
259 * value when changing channels and the values are far apart.
260 */
261 do {
262 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
263 if (ret < 0)
264 return ret;
265
266 while (!(ret & NAU7802_PUCTRL_CR_BIT)) {
267 if (st->sample_rate != NAU7802_SAMP_FREQ_320)
268 msleep(20);
269 else
270 mdelay(4);
271 ret = i2c_smbus_read_byte_data(st->client,
272 NAU7802_REG_PUCTRL);
273 if (ret < 0)
274 return ret;
275 }
276
277 ret = nau7802_read_conversion(st);
278 if (ret < 0)
279 return ret;
280 if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
281 st->conversion_count++;
282 } while (st->conversion_count < NAU7802_MIN_CONVERSIONS);
283
284 *val = st->last_value;
285
286 return IIO_VAL_INT;
287 }
288
nau7802_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)289 static int nau7802_read_raw(struct iio_dev *indio_dev,
290 struct iio_chan_spec const *chan,
291 int *val, int *val2, long mask)
292 {
293 struct nau7802_state *st = iio_priv(indio_dev);
294 int ret;
295
296 switch (mask) {
297 case IIO_CHAN_INFO_RAW:
298 mutex_lock(&st->lock);
299 /*
300 * Select the channel to use
301 * - Channel 1 is value 0 in the CHS register
302 * - Channel 2 is value 1 in the CHS register
303 */
304 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL2);
305 if (ret < 0) {
306 mutex_unlock(&st->lock);
307 return ret;
308 }
309
310 if (((ret & NAU7802_CTRL2_CHS_BIT) && !chan->channel) ||
311 (!(ret & NAU7802_CTRL2_CHS_BIT) &&
312 chan->channel)) {
313 st->conversion_count = 0;
314 ret = i2c_smbus_write_byte_data(st->client,
315 NAU7802_REG_CTRL2,
316 NAU7802_CTRL2_CHS(chan->channel) |
317 NAU7802_CTRL2_CRS(st->sample_rate));
318
319 if (ret < 0) {
320 mutex_unlock(&st->lock);
321 return ret;
322 }
323 }
324
325 if (st->client->irq)
326 ret = nau7802_read_irq(indio_dev, chan, val);
327 else
328 ret = nau7802_read_poll(indio_dev, chan, val);
329
330 mutex_unlock(&st->lock);
331 return ret;
332
333 case IIO_CHAN_INFO_SCALE:
334 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
335 if (ret < 0)
336 return ret;
337
338 /*
339 * We have 24 bits of signed data, that means 23 bits of data
340 * plus the sign bit
341 */
342 *val = st->vref_mv;
343 *val2 = 23 + (ret & NAU7802_CTRL1_GAINS_BITS);
344
345 return IIO_VAL_FRACTIONAL_LOG2;
346
347 case IIO_CHAN_INFO_SAMP_FREQ:
348 *val = nau7802_sample_freq_avail[st->sample_rate];
349 *val2 = 0;
350 return IIO_VAL_INT;
351
352 default:
353 break;
354 }
355
356 return -EINVAL;
357 }
358
nau7802_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)359 static int nau7802_write_raw(struct iio_dev *indio_dev,
360 struct iio_chan_spec const *chan,
361 int val, int val2, long mask)
362 {
363 struct nau7802_state *st = iio_priv(indio_dev);
364 int i, ret;
365
366 switch (mask) {
367 case IIO_CHAN_INFO_SCALE:
368 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
369 if (val2 == st->scale_avail[i])
370 return nau7802_set_gain(st, i);
371
372 break;
373
374 case IIO_CHAN_INFO_SAMP_FREQ:
375 for (i = 0; i < ARRAY_SIZE(nau7802_sample_freq_avail); i++)
376 if (val == nau7802_sample_freq_avail[i]) {
377 mutex_lock(&st->lock);
378 st->sample_rate = i;
379 st->conversion_count = 0;
380 ret = i2c_smbus_write_byte_data(st->client,
381 NAU7802_REG_CTRL2,
382 NAU7802_CTRL2_CRS(st->sample_rate));
383 mutex_unlock(&st->lock);
384 return ret;
385 }
386
387 break;
388
389 default:
390 break;
391 }
392
393 return -EINVAL;
394 }
395
nau7802_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)396 static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev,
397 struct iio_chan_spec const *chan,
398 long mask)
399 {
400 return IIO_VAL_INT_PLUS_NANO;
401 }
402
403 static const struct iio_info nau7802_info = {
404 .read_raw = &nau7802_read_raw,
405 .write_raw = &nau7802_write_raw,
406 .write_raw_get_fmt = nau7802_write_raw_get_fmt,
407 .attrs = &nau7802_attribute_group,
408 };
409
nau7802_probe(struct i2c_client * client)410 static int nau7802_probe(struct i2c_client *client)
411 {
412 struct iio_dev *indio_dev;
413 struct nau7802_state *st;
414 int i, ret;
415 u8 data;
416 u32 tmp = 0;
417
418 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
419 if (indio_dev == NULL)
420 return -ENOMEM;
421
422 st = iio_priv(indio_dev);
423
424 indio_dev->name = dev_name(&client->dev);
425 indio_dev->modes = INDIO_DIRECT_MODE;
426 indio_dev->info = &nau7802_info;
427
428 st->client = client;
429
430 /* Reset the device */
431 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
432 NAU7802_PUCTRL_RR_BIT);
433 if (ret < 0)
434 return ret;
435
436 /* Enter normal operation mode */
437 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
438 NAU7802_PUCTRL_PUD_BIT);
439 if (ret < 0)
440 return ret;
441
442 /*
443 * After about 200 usecs, the device should be ready and then
444 * the Power Up bit will be set to 1. If not, wait for it.
445 */
446 udelay(210);
447 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
448 if (ret < 0)
449 return ret;
450 if (!(ret & NAU7802_PUCTRL_PUR_BIT))
451 return ret;
452
453 device_property_read_u32(&client->dev, "nuvoton,vldo", &tmp);
454 st->vref_mv = tmp;
455
456 data = NAU7802_PUCTRL_PUD_BIT | NAU7802_PUCTRL_PUA_BIT |
457 NAU7802_PUCTRL_CS_BIT;
458 if (tmp >= 2400)
459 data |= NAU7802_PUCTRL_AVDDS_BIT;
460
461 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, data);
462 if (ret < 0)
463 return ret;
464 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_ADC_CTRL, 0x30);
465 if (ret < 0)
466 return ret;
467
468 if (tmp >= 2400) {
469 data = NAU7802_CTRL1_VLDO((4500 - tmp) / 300);
470 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
471 data);
472 if (ret < 0)
473 return ret;
474 }
475
476 /* Populate available ADC input ranges */
477 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
478 st->scale_avail[i] = (((u64)st->vref_mv) * 1000000000ULL)
479 >> (23 + i);
480
481 init_completion(&st->value_ok);
482
483 /*
484 * The ADC fires continuously and we can't do anything about
485 * it. So we need to have the IRQ disabled by default, and we
486 * will enable them back when we will need them..
487 */
488 if (client->irq) {
489 ret = devm_request_threaded_irq(&client->dev, client->irq,
490 NULL,
491 nau7802_eoc_trigger,
492 IRQF_TRIGGER_HIGH | IRQF_ONESHOT |
493 IRQF_NO_AUTOEN,
494 client->dev.driver->name,
495 indio_dev);
496 if (ret) {
497 /*
498 * What may happen here is that our IRQ controller is
499 * not able to get level interrupt but this is required
500 * by this ADC as when going over 40 sample per second,
501 * the interrupt line may stay high between conversions.
502 * So, we continue no matter what but we switch to
503 * polling mode.
504 */
505 dev_info(&client->dev,
506 "Failed to allocate IRQ, using polling mode\n");
507 client->irq = 0;
508 }
509 }
510
511 if (!client->irq) {
512 /*
513 * We are polling, use the fastest sample rate by
514 * default
515 */
516 st->sample_rate = NAU7802_SAMP_FREQ_320;
517 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL2,
518 NAU7802_CTRL2_CRS(st->sample_rate));
519 if (ret)
520 return ret;
521 }
522
523 /* Setup the ADC channels available on the board */
524 indio_dev->num_channels = ARRAY_SIZE(nau7802_chan_array);
525 indio_dev->channels = nau7802_chan_array;
526
527 mutex_init(&st->lock);
528 mutex_init(&st->data_lock);
529
530 return devm_iio_device_register(&client->dev, indio_dev);
531 }
532
533 static const struct i2c_device_id nau7802_i2c_id[] = {
534 { "nau7802" },
535 { }
536 };
537 MODULE_DEVICE_TABLE(i2c, nau7802_i2c_id);
538
539 static const struct of_device_id nau7802_dt_ids[] = {
540 { .compatible = "nuvoton,nau7802" },
541 { }
542 };
543 MODULE_DEVICE_TABLE(of, nau7802_dt_ids);
544
545 static struct i2c_driver nau7802_driver = {
546 .probe = nau7802_probe,
547 .id_table = nau7802_i2c_id,
548 .driver = {
549 .name = "nau7802",
550 .of_match_table = nau7802_dt_ids,
551 },
552 };
553
554 module_i2c_driver(nau7802_driver);
555
556 MODULE_LICENSE("GPL");
557 MODULE_DESCRIPTION("Nuvoton NAU7802 ADC Driver");
558 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
559 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
560