1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17 #include <linux/kvm_host.h>
18
19 #include <asm/cpufeature.h>
20 #include <asm/cpuid/api.h>
21 #include <asm/debugreg.h>
22 #include <asm/hardirq.h>
23 #include <asm/intel-family.h>
24 #include <asm/intel_pt.h>
25 #include <asm/apic.h>
26 #include <asm/cpu_device_id.h>
27 #include <asm/msr.h>
28
29 #include "../perf_event.h"
30
31 /*
32 * Intel PerfMon, used on Core and later.
33 */
34 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
35 {
36 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
37 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
38 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
39 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
40 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
41 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
42 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
43 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
44 };
45
46 static struct event_constraint intel_core_event_constraints[] __read_mostly =
47 {
48 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
49 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
50 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
51 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
52 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
53 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
54 EVENT_CONSTRAINT_END
55 };
56
57 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
58 {
59 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
60 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
61 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
62 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
63 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
64 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
65 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
66 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
67 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
68 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
69 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
70 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
71 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
72 EVENT_CONSTRAINT_END
73 };
74
75 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
76 {
77 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
78 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
79 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
80 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
81 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
82 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
83 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
84 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
85 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
86 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
87 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
88 EVENT_CONSTRAINT_END
89 };
90
91 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
92 {
93 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
94 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
95 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
96 EVENT_EXTRA_END
97 };
98
99 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
100 {
101 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
102 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
103 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
104 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
105 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
106 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
107 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
108 EVENT_CONSTRAINT_END
109 };
110
111 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
112 {
113 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
114 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
115 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
117 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
118 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
119 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
120 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
121 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
122 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
123 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
124 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
125
126 /*
127 * When HT is off these events can only run on the bottom 4 counters
128 * When HT is on, they are impacted by the HT bug and require EXCL access
129 */
130 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
131 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
132 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
133 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
134
135 EVENT_CONSTRAINT_END
136 };
137
138 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
139 {
140 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
141 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
142 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
143 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
144 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
145 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
146 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
148 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
149 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
150 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
151 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
152 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
153
154 /*
155 * When HT is off these events can only run on the bottom 4 counters
156 * When HT is on, they are impacted by the HT bug and require EXCL access
157 */
158 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
159 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
160 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
161 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
162
163 EVENT_CONSTRAINT_END
164 };
165
166 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
167 {
168 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
169 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
170 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
171 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
172 EVENT_EXTRA_END
173 };
174
175 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
176 {
177 EVENT_CONSTRAINT_END
178 };
179
180 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
181 {
182 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
183 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
184 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
185 EVENT_CONSTRAINT_END
186 };
187
188 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
189 {
190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
193 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
194 FIXED_EVENT_CONSTRAINT(0x0500, 4),
195 FIXED_EVENT_CONSTRAINT(0x0600, 5),
196 FIXED_EVENT_CONSTRAINT(0x0700, 6),
197 FIXED_EVENT_CONSTRAINT(0x0800, 7),
198 FIXED_EVENT_CONSTRAINT(0x0900, 8),
199 FIXED_EVENT_CONSTRAINT(0x0a00, 9),
200 FIXED_EVENT_CONSTRAINT(0x0b00, 10),
201 FIXED_EVENT_CONSTRAINT(0x0c00, 11),
202 FIXED_EVENT_CONSTRAINT(0x0d00, 12),
203 FIXED_EVENT_CONSTRAINT(0x0e00, 13),
204 FIXED_EVENT_CONSTRAINT(0x0f00, 14),
205 FIXED_EVENT_CONSTRAINT(0x1000, 15),
206 EVENT_CONSTRAINT_END
207 };
208
209 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
210 {
211 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
212 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
213 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
214 EVENT_CONSTRAINT_END
215 };
216
217 static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
218 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
219 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
220 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
221 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
222 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
223 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
224 EVENT_CONSTRAINT_END
225 };
226
227 static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
228 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
229 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
230 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
231 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
232 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
233 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
234 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
235 FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
236 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
237 FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
238 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
239 FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
240 EVENT_CONSTRAINT_END
241 };
242
243 static struct event_constraint intel_arw_event_constraints[] __read_mostly = {
244 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
245 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
246 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
247 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
248 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
249 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
250 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
251 FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
252 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
253 FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
254 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
255 FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
256 INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),
257 INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2),
258 INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4),
259 INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8),
260 INTEL_UEVENT_CONSTRAINT(0x0175, 0x1),
261 INTEL_UEVENT_CONSTRAINT(0x0275, 0x2),
262 INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1),
263 INTEL_UEVENT_CONSTRAINT(0x22d3, 0x1),
264 EVENT_CONSTRAINT_END
265 };
266
267 static struct event_constraint intel_skl_event_constraints[] = {
268 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
269 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
270 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
271 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
272
273 /*
274 * when HT is off, these can only run on the bottom 4 counters
275 */
276 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
277 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
278 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
279 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
280 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
281
282 EVENT_CONSTRAINT_END
283 };
284
285 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
286 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
287 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
288 EVENT_EXTRA_END
289 };
290
291 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
292 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
293 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
294 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
295 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
296 EVENT_EXTRA_END
297 };
298
299 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
300 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
301 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
302 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
303 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
304 EVENT_EXTRA_END
305 };
306
307 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
308 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
309 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
310 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
311 /*
312 * Note the low 8 bits eventsel code is not a continuous field, containing
313 * some #GPing bits. These are masked out.
314 */
315 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
316 EVENT_EXTRA_END
317 };
318
319 static struct event_constraint intel_icl_event_constraints[] = {
320 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
321 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
322 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
323 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
324 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
325 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
326 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
327 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
328 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
329 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
330 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
331 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
332 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
333 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
334 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
335 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
336 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
337 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
338 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
339 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
340 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
341 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
342 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
343 INTEL_EVENT_CONSTRAINT(0xef, 0xf),
344 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
345 EVENT_CONSTRAINT_END
346 };
347
348 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
349 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
350 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
351 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
352 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
353 EVENT_EXTRA_END
354 };
355
356 static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
357 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
358 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
359 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
360 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
361 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
362 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
363 EVENT_EXTRA_END
364 };
365
366 static struct event_constraint intel_glc_event_constraints[] = {
367 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
368 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
369 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
370 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
371 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
372 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
373 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
374 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
375 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
376 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
377 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
378 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
379 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
380 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
381 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
382
383 INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
384 INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
385 /*
386 * Generally event codes < 0x90 are restricted to counters 0-3.
387 * The 0x2E and 0x3C are exception, which has no restriction.
388 */
389 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
390
391 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
392 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
393 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf),
394 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf),
395 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
396 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0xf),
397 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
398 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
399 INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfe),
400 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
401 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
402 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
403 /*
404 * Generally event codes >= 0x90 are likely to have no restrictions.
405 * The exception are defined as above.
406 */
407 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
408
409 EVENT_CONSTRAINT_END
410 };
411
412 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {
413 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
414 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
415 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
416 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
417 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
418 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
419 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
420 EVENT_EXTRA_END
421 };
422
423 static struct event_constraint intel_lnc_event_constraints[] = {
424 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
425 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
426 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
427 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
428 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
429 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
430 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
431 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
432 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
433 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
434 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
435 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
436 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
437 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
438 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
439
440 INTEL_EVENT_CONSTRAINT(0x20, 0xf),
441
442 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
443 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
444
445 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff),
446 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff),
447
448 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
449 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
450 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
451 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
452 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x8),
453 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
454 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),
455 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
456
457 INTEL_UEVENT_CONSTRAINT(0x87d0, 0x3ff),
458 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
459
460 EVENT_CONSTRAINT_END
461 };
462
463 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
464 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0),
465 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1),
466 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
467 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
468 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
469 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
470 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
471 EVENT_EXTRA_END
472 };
473
474 static struct event_constraint intel_pnc_event_constraints[] = {
475 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
476 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
477 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
478 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
479 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
480 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
481 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
482 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
483 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
484 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
485 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
486 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
487 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
488 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
489 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
490
491 INTEL_EVENT_CONSTRAINT(0x20, 0xf),
492 INTEL_EVENT_CONSTRAINT(0x79, 0xf),
493
494 INTEL_UEVENT_CONSTRAINT(0x0275, 0xf),
495 INTEL_UEVENT_CONSTRAINT(0x0176, 0xf),
496 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
497 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
498 INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfc),
499 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
500
501 INTEL_EVENT_CONSTRAINT(0xd0, 0xf),
502 INTEL_EVENT_CONSTRAINT(0xd1, 0xf),
503 INTEL_EVENT_CONSTRAINT(0xd4, 0xf),
504 INTEL_EVENT_CONSTRAINT(0xd6, 0xf),
505 INTEL_EVENT_CONSTRAINT(0xdf, 0xf),
506 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
507
508 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
509 INTEL_UEVENT_CONSTRAINT(0x0847, 0xf),
510 INTEL_UEVENT_CONSTRAINT(0x0446, 0xf),
511 INTEL_UEVENT_CONSTRAINT(0x0846, 0xf),
512 INTEL_UEVENT_CONSTRAINT(0x0148, 0xf),
513
514 EVENT_CONSTRAINT_END
515 };
516
517 static struct extra_reg intel_pnc_extra_regs[] __read_mostly = {
518 /* must define OMR_X first, see intel_alt_er() */
519 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
520 INTEL_UEVENT_EXTRA_REG(0x022a, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
521 INTEL_UEVENT_EXTRA_REG(0x042a, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
522 INTEL_UEVENT_EXTRA_REG(0x082a, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
523 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
524 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
525 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
526 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
527 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
528 EVENT_EXTRA_END
529 };
530
531 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
532 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
533 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
534
535 static struct attribute *nhm_mem_events_attrs[] = {
536 EVENT_PTR(mem_ld_nhm),
537 NULL,
538 };
539
540 /*
541 * topdown events for Intel Core CPUs.
542 *
543 * The events are all in slots, which is a free slot in a 4 wide
544 * pipeline. Some events are already reported in slots, for cycle
545 * events we multiply by the pipeline width (4).
546 *
547 * With Hyper Threading on, topdown metrics are either summed or averaged
548 * between the threads of a core: (count_t0 + count_t1).
549 *
550 * For the average case the metric is always scaled to pipeline width,
551 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
552 */
553
554 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
555 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
556 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
557 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
558 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
559 "event=0xe,umask=0x1"); /* uops_issued.any */
560 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
561 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
562 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
563 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
564 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
565 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
566 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
567 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
568 "4", "2");
569
570 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
571 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
572 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
573 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
574 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
575 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84");
576 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85");
577 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
578 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87");
579
580 static struct attribute *snb_events_attrs[] = {
581 EVENT_PTR(td_slots_issued),
582 EVENT_PTR(td_slots_retired),
583 EVENT_PTR(td_fetch_bubbles),
584 EVENT_PTR(td_total_slots),
585 EVENT_PTR(td_total_slots_scale),
586 EVENT_PTR(td_recovery_bubbles),
587 EVENT_PTR(td_recovery_bubbles_scale),
588 NULL,
589 };
590
591 static struct attribute *snb_mem_events_attrs[] = {
592 EVENT_PTR(mem_ld_snb),
593 EVENT_PTR(mem_st_snb),
594 NULL,
595 };
596
597 static struct event_constraint intel_hsw_event_constraints[] = {
598 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
599 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
600 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
601 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
602 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
603 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
604 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
605 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
606 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
607 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
608 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
609 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
610
611 /*
612 * When HT is off these events can only run on the bottom 4 counters
613 * When HT is on, they are impacted by the HT bug and require EXCL access
614 */
615 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
616 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
617 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
618 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
619
620 EVENT_CONSTRAINT_END
621 };
622
623 static struct event_constraint intel_bdw_event_constraints[] = {
624 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
625 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
626 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
627 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
628 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
629 /*
630 * when HT is off, these can only run on the bottom 4 counters
631 */
632 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
633 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
634 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
635 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
636 EVENT_CONSTRAINT_END
637 };
638
intel_pmu_event_map(int hw_event)639 static u64 intel_pmu_event_map(int hw_event)
640 {
641 return intel_perfmon_event_map[hw_event];
642 }
643
644 static __initconst const u64 glc_hw_cache_event_ids
645 [PERF_COUNT_HW_CACHE_MAX]
646 [PERF_COUNT_HW_CACHE_OP_MAX]
647 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
648 {
649 [ C(L1D ) ] = {
650 [ C(OP_READ) ] = {
651 [ C(RESULT_ACCESS) ] = 0x81d0,
652 [ C(RESULT_MISS) ] = 0xe124,
653 },
654 [ C(OP_WRITE) ] = {
655 [ C(RESULT_ACCESS) ] = 0x82d0,
656 },
657 },
658 [ C(L1I ) ] = {
659 [ C(OP_READ) ] = {
660 [ C(RESULT_MISS) ] = 0xe424,
661 },
662 [ C(OP_WRITE) ] = {
663 [ C(RESULT_ACCESS) ] = -1,
664 [ C(RESULT_MISS) ] = -1,
665 },
666 },
667 [ C(LL ) ] = {
668 [ C(OP_READ) ] = {
669 [ C(RESULT_ACCESS) ] = 0x12a,
670 [ C(RESULT_MISS) ] = 0x12a,
671 },
672 [ C(OP_WRITE) ] = {
673 [ C(RESULT_ACCESS) ] = 0x12a,
674 [ C(RESULT_MISS) ] = 0x12a,
675 },
676 },
677 [ C(DTLB) ] = {
678 [ C(OP_READ) ] = {
679 [ C(RESULT_ACCESS) ] = 0x81d0,
680 [ C(RESULT_MISS) ] = 0xe12,
681 },
682 [ C(OP_WRITE) ] = {
683 [ C(RESULT_ACCESS) ] = 0x82d0,
684 [ C(RESULT_MISS) ] = 0xe13,
685 },
686 },
687 [ C(ITLB) ] = {
688 [ C(OP_READ) ] = {
689 [ C(RESULT_ACCESS) ] = -1,
690 [ C(RESULT_MISS) ] = 0xe11,
691 },
692 [ C(OP_WRITE) ] = {
693 [ C(RESULT_ACCESS) ] = -1,
694 [ C(RESULT_MISS) ] = -1,
695 },
696 [ C(OP_PREFETCH) ] = {
697 [ C(RESULT_ACCESS) ] = -1,
698 [ C(RESULT_MISS) ] = -1,
699 },
700 },
701 [ C(BPU ) ] = {
702 [ C(OP_READ) ] = {
703 [ C(RESULT_ACCESS) ] = 0x4c4,
704 [ C(RESULT_MISS) ] = 0x4c5,
705 },
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = -1,
708 [ C(RESULT_MISS) ] = -1,
709 },
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = -1,
712 [ C(RESULT_MISS) ] = -1,
713 },
714 },
715 [ C(NODE) ] = {
716 [ C(OP_READ) ] = {
717 [ C(RESULT_ACCESS) ] = 0x12a,
718 [ C(RESULT_MISS) ] = 0x12a,
719 },
720 },
721 };
722
723 /* ADL P-core (Golden cove) specific event code. */
724 static __initconst const u64 adl_glc_hw_cache_event_ids
725 [PERF_COUNT_HW_CACHE_MAX]
726 [PERF_COUNT_HW_CACHE_OP_MAX]
727 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
728 {
729 [ C(L1D ) ] = {
730 [ C(OP_READ) ] = {
731 [ C(RESULT_ACCESS) ] = 0x81d0,
732 [ C(RESULT_MISS) ] = 0xe124,
733 },
734 [ C(OP_WRITE) ] = {
735 [ C(RESULT_ACCESS) ] = 0x82d0,
736 },
737 },
738 [ C(L1I ) ] = {
739 [ C(OP_READ) ] = {
740 [ C(RESULT_MISS) ] = 0xe424,
741 },
742 [ C(OP_WRITE) ] = {
743 [ C(RESULT_ACCESS) ] = -1,
744 [ C(RESULT_MISS) ] = -1,
745 },
746 },
747 [ C(LL ) ] = {
748 [ C(OP_READ) ] = {
749 [ C(RESULT_ACCESS) ] = 0x12a,
750 [ C(RESULT_MISS) ] = 0x12a,
751 },
752 [ C(OP_WRITE) ] = {
753 [ C(RESULT_ACCESS) ] = 0x12a,
754 [ C(RESULT_MISS) ] = 0x12a,
755 },
756 },
757 [ C(DTLB) ] = {
758 [ C(OP_READ) ] = {
759 [ C(RESULT_ACCESS) ] = 0x81d0,
760 [ C(RESULT_MISS) ] = 0xe12,
761 },
762 [ C(OP_WRITE) ] = {
763 [ C(RESULT_ACCESS) ] = 0x82d0,
764 [ C(RESULT_MISS) ] = 0xe13,
765 },
766 },
767 [ C(ITLB) ] = {
768 [ C(OP_READ) ] = {
769 [ C(RESULT_ACCESS) ] = -1,
770 [ C(RESULT_MISS) ] = 0xe11,
771 },
772 [ C(OP_WRITE) ] = {
773 [ C(RESULT_ACCESS) ] = -1,
774 [ C(RESULT_MISS) ] = -1,
775 },
776 [ C(OP_PREFETCH) ] = {
777 [ C(RESULT_ACCESS) ] = -1,
778 [ C(RESULT_MISS) ] = -1,
779 },
780 },
781 [ C(BPU ) ] = {
782 [ C(OP_READ) ] = {
783 [ C(RESULT_ACCESS) ] = 0x4c4,
784 [ C(RESULT_MISS) ] = 0x4c5,
785 },
786 [ C(OP_WRITE) ] = {
787 [ C(RESULT_ACCESS) ] = -1,
788 [ C(RESULT_MISS) ] = -1,
789 },
790 [ C(OP_PREFETCH) ] = {
791 [ C(RESULT_ACCESS) ] = -1,
792 [ C(RESULT_MISS) ] = -1,
793 },
794 },
795 };
796
797 static __initconst const u64 glc_hw_cache_extra_regs
798 [PERF_COUNT_HW_CACHE_MAX]
799 [PERF_COUNT_HW_CACHE_OP_MAX]
800 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
801 {
802 [ C(LL ) ] = {
803 [ C(OP_READ) ] = {
804 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
805 [ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
806 },
807 [ C(OP_WRITE) ] = {
808 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
809 [ C(RESULT_MISS) ] = 0x3f3fc00002, /* OCR.DEMAND_RFO.L3_MISS */
810 },
811 },
812 [ C(NODE) ] = {
813 [ C(OP_READ) ] = {
814 [ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
815 [ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
816 },
817 },
818 };
819
820 /* ADL P-core (Golden cove) specific extra regs value. */
821 static __initconst const u64 adl_glc_hw_cache_extra_regs
822 [PERF_COUNT_HW_CACHE_MAX]
823 [PERF_COUNT_HW_CACHE_OP_MAX]
824 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
825 {
826 [ C(LL ) ] = {
827 [ C(OP_READ) ] = {
828 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
829 [ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
830 },
831 [ C(OP_WRITE) ] = {
832 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
833 [ C(RESULT_MISS) ] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */
834 },
835 },
836 };
837
838 static __initconst const u64 lnc_hw_cache_extra_regs
839 [PERF_COUNT_HW_CACHE_MAX]
840 [PERF_COUNT_HW_CACHE_OP_MAX]
841 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
842 {
843 [ C(LL ) ] = {
844 [ C(OP_READ) ] = {
845 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
846 [ C(RESULT_MISS) ] = 0x9E7FA000001, /* OCR.DEMAND_DATA_RD.L3_MISS */
847 },
848 [ C(OP_WRITE) ] = {
849 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
850 [ C(RESULT_MISS) ] = 0x9E7FA000002, /* OCR.DEMAND_RFO.L3_MISS */
851 },
852 },
853 };
854
855 /* ARL specific lioncove hw_cache_extra_regs[] variant. */
856 static __initconst const u64 arl_lnc_hw_cache_extra_regs
857 [PERF_COUNT_HW_CACHE_MAX]
858 [PERF_COUNT_HW_CACHE_OP_MAX]
859 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
860 {
861 [ C(LL ) ] = {
862 [ C(OP_READ) ] = {
863 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
864 [ C(RESULT_MISS) ] = 0xFE7F8000001, /* OCR.DEMAND_DATA_RD.L3_MISS */
865 },
866 [ C(OP_WRITE) ] = {
867 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
868 [ C(RESULT_MISS) ] = 0xFE7F8000002, /* OCR.DEMAND_RFO.L3_MISS */
869 },
870 },
871 };
872
873 static __initconst const u64 pnc_hw_cache_event_ids
874 [PERF_COUNT_HW_CACHE_MAX]
875 [PERF_COUNT_HW_CACHE_OP_MAX]
876 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
877 {
878 [ C(L1D ) ] = {
879 [ C(OP_READ) ] = {
880 [ C(RESULT_ACCESS) ] = 0x81d0,
881 [ C(RESULT_MISS) ] = 0xe124,
882 },
883 [ C(OP_WRITE) ] = {
884 [ C(RESULT_ACCESS) ] = 0x82d0,
885 },
886 },
887 [ C(L1I ) ] = {
888 [ C(OP_READ) ] = {
889 [ C(RESULT_MISS) ] = 0xe424,
890 },
891 [ C(OP_WRITE) ] = {
892 [ C(RESULT_ACCESS) ] = -1,
893 [ C(RESULT_MISS) ] = -1,
894 },
895 },
896 [ C(LL ) ] = {
897 [ C(OP_READ) ] = {
898 [ C(RESULT_ACCESS) ] = 0x12a,
899 [ C(RESULT_MISS) ] = 0x12a,
900 },
901 [ C(OP_WRITE) ] = {
902 [ C(RESULT_ACCESS) ] = 0x12a,
903 [ C(RESULT_MISS) ] = 0x12a,
904 },
905 },
906 [ C(DTLB) ] = {
907 [ C(OP_READ) ] = {
908 [ C(RESULT_ACCESS) ] = 0x81d0,
909 [ C(RESULT_MISS) ] = 0xe12,
910 },
911 [ C(OP_WRITE) ] = {
912 [ C(RESULT_ACCESS) ] = 0x82d0,
913 [ C(RESULT_MISS) ] = 0xe13,
914 },
915 },
916 [ C(ITLB) ] = {
917 [ C(OP_READ) ] = {
918 [ C(RESULT_ACCESS) ] = -1,
919 [ C(RESULT_MISS) ] = 0xe11,
920 },
921 [ C(OP_WRITE) ] = {
922 [ C(RESULT_ACCESS) ] = -1,
923 [ C(RESULT_MISS) ] = -1,
924 },
925 [ C(OP_PREFETCH) ] = {
926 [ C(RESULT_ACCESS) ] = -1,
927 [ C(RESULT_MISS) ] = -1,
928 },
929 },
930 [ C(BPU ) ] = {
931 [ C(OP_READ) ] = {
932 [ C(RESULT_ACCESS) ] = 0x4c4,
933 [ C(RESULT_MISS) ] = 0x4c5,
934 },
935 [ C(OP_WRITE) ] = {
936 [ C(RESULT_ACCESS) ] = -1,
937 [ C(RESULT_MISS) ] = -1,
938 },
939 [ C(OP_PREFETCH) ] = {
940 [ C(RESULT_ACCESS) ] = -1,
941 [ C(RESULT_MISS) ] = -1,
942 },
943 },
944 [ C(NODE) ] = {
945 [ C(OP_READ) ] = {
946 [ C(RESULT_ACCESS) ] = -1,
947 [ C(RESULT_MISS) ] = -1,
948 },
949 },
950 };
951
952 static __initconst const u64 pnc_hw_cache_extra_regs
953 [PERF_COUNT_HW_CACHE_MAX]
954 [PERF_COUNT_HW_CACHE_OP_MAX]
955 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
956 {
957 [ C(LL ) ] = {
958 [ C(OP_READ) ] = {
959 [ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
960 [ C(RESULT_MISS) ] = 0xFFFFF000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */
961 },
962 [ C(OP_WRITE) ] = {
963 [ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */
964 [ C(RESULT_MISS) ] = 0xFFFFF000000002, /* OMR.DEMAND_RFO.L3_MISS */
965 },
966 },
967 };
968
969 static __initconst const u64 cyc_hw_cache_extra_regs
970 [PERF_COUNT_HW_CACHE_MAX]
971 [PERF_COUNT_HW_CACHE_OP_MAX]
972 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
973 {
974 [ C(LL ) ] = {
975 [ C(OP_READ) ] = {
976 [ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
977 [ C(RESULT_MISS) ] = 0xFF03F000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */
978 },
979 [ C(OP_WRITE) ] = {
980 [ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */
981 [ C(RESULT_MISS) ] = 0xFF03F000000002, /* OMR.DEMAND_RFO.L3_MISS */
982 },
983 },
984 };
985
986 /*
987 * Notes on the events:
988 * - data reads do not include code reads (comparable to earlier tables)
989 * - data counts include speculative execution (except L1 write, dtlb, bpu)
990 * - remote node access includes remote memory, remote cache, remote mmio.
991 * - prefetches are not included in the counts.
992 * - icache miss does not include decoded icache
993 */
994
995 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
996 #define SKL_DEMAND_RFO BIT_ULL(1)
997 #define SKL_ANY_RESPONSE BIT_ULL(16)
998 #define SKL_SUPPLIER_NONE BIT_ULL(17)
999 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
1000 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
1001 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
1002 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
1003 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
1004 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
1005 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
1006 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
1007 #define SKL_SPL_HIT BIT_ULL(30)
1008 #define SKL_SNOOP_NONE BIT_ULL(31)
1009 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
1010 #define SKL_SNOOP_MISS BIT_ULL(33)
1011 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
1012 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
1013 #define SKL_SNOOP_HITM BIT_ULL(36)
1014 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
1015 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
1016 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
1017 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
1018 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
1019 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
1020 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
1021 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
1022 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
1023 SKL_SNOOP_HITM|SKL_SPL_HIT)
1024 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
1025 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
1026 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
1027 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
1028 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
1029
1030 static __initconst const u64 skl_hw_cache_event_ids
1031 [PERF_COUNT_HW_CACHE_MAX]
1032 [PERF_COUNT_HW_CACHE_OP_MAX]
1033 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1034 {
1035 [ C(L1D ) ] = {
1036 [ C(OP_READ) ] = {
1037 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
1038 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1039 },
1040 [ C(OP_WRITE) ] = {
1041 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
1042 [ C(RESULT_MISS) ] = 0x0,
1043 },
1044 [ C(OP_PREFETCH) ] = {
1045 [ C(RESULT_ACCESS) ] = 0x0,
1046 [ C(RESULT_MISS) ] = 0x0,
1047 },
1048 },
1049 [ C(L1I ) ] = {
1050 [ C(OP_READ) ] = {
1051 [ C(RESULT_ACCESS) ] = 0x0,
1052 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
1053 },
1054 [ C(OP_WRITE) ] = {
1055 [ C(RESULT_ACCESS) ] = -1,
1056 [ C(RESULT_MISS) ] = -1,
1057 },
1058 [ C(OP_PREFETCH) ] = {
1059 [ C(RESULT_ACCESS) ] = 0x0,
1060 [ C(RESULT_MISS) ] = 0x0,
1061 },
1062 },
1063 [ C(LL ) ] = {
1064 [ C(OP_READ) ] = {
1065 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1066 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1067 },
1068 [ C(OP_WRITE) ] = {
1069 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1070 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1071 },
1072 [ C(OP_PREFETCH) ] = {
1073 [ C(RESULT_ACCESS) ] = 0x0,
1074 [ C(RESULT_MISS) ] = 0x0,
1075 },
1076 },
1077 [ C(DTLB) ] = {
1078 [ C(OP_READ) ] = {
1079 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
1080 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1081 },
1082 [ C(OP_WRITE) ] = {
1083 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
1084 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1085 },
1086 [ C(OP_PREFETCH) ] = {
1087 [ C(RESULT_ACCESS) ] = 0x0,
1088 [ C(RESULT_MISS) ] = 0x0,
1089 },
1090 },
1091 [ C(ITLB) ] = {
1092 [ C(OP_READ) ] = {
1093 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
1094 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
1095 },
1096 [ C(OP_WRITE) ] = {
1097 [ C(RESULT_ACCESS) ] = -1,
1098 [ C(RESULT_MISS) ] = -1,
1099 },
1100 [ C(OP_PREFETCH) ] = {
1101 [ C(RESULT_ACCESS) ] = -1,
1102 [ C(RESULT_MISS) ] = -1,
1103 },
1104 },
1105 [ C(BPU ) ] = {
1106 [ C(OP_READ) ] = {
1107 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1108 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1109 },
1110 [ C(OP_WRITE) ] = {
1111 [ C(RESULT_ACCESS) ] = -1,
1112 [ C(RESULT_MISS) ] = -1,
1113 },
1114 [ C(OP_PREFETCH) ] = {
1115 [ C(RESULT_ACCESS) ] = -1,
1116 [ C(RESULT_MISS) ] = -1,
1117 },
1118 },
1119 [ C(NODE) ] = {
1120 [ C(OP_READ) ] = {
1121 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1122 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1123 },
1124 [ C(OP_WRITE) ] = {
1125 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1126 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1127 },
1128 [ C(OP_PREFETCH) ] = {
1129 [ C(RESULT_ACCESS) ] = 0x0,
1130 [ C(RESULT_MISS) ] = 0x0,
1131 },
1132 },
1133 };
1134
1135 static __initconst const u64 skl_hw_cache_extra_regs
1136 [PERF_COUNT_HW_CACHE_MAX]
1137 [PERF_COUNT_HW_CACHE_OP_MAX]
1138 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1139 {
1140 [ C(LL ) ] = {
1141 [ C(OP_READ) ] = {
1142 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
1143 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
1144 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
1145 SKL_L3_MISS|SKL_ANY_SNOOP|
1146 SKL_SUPPLIER_NONE,
1147 },
1148 [ C(OP_WRITE) ] = {
1149 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
1150 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
1151 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
1152 SKL_L3_MISS|SKL_ANY_SNOOP|
1153 SKL_SUPPLIER_NONE,
1154 },
1155 [ C(OP_PREFETCH) ] = {
1156 [ C(RESULT_ACCESS) ] = 0x0,
1157 [ C(RESULT_MISS) ] = 0x0,
1158 },
1159 },
1160 [ C(NODE) ] = {
1161 [ C(OP_READ) ] = {
1162 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
1163 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
1164 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
1165 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
1166 },
1167 [ C(OP_WRITE) ] = {
1168 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
1169 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
1170 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
1171 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
1172 },
1173 [ C(OP_PREFETCH) ] = {
1174 [ C(RESULT_ACCESS) ] = 0x0,
1175 [ C(RESULT_MISS) ] = 0x0,
1176 },
1177 },
1178 };
1179
1180 static __initconst const u64 snc_hw_cache_extra_regs
1181 [PERF_COUNT_HW_CACHE_MAX]
1182 [PERF_COUNT_HW_CACHE_OP_MAX]
1183 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1184 {
1185 [ C(LL ) ] = {
1186 [ C(OP_READ) ] = {
1187 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
1188 [ C(RESULT_MISS) ] = 0x3FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
1189 },
1190 [ C(OP_WRITE) ] = {
1191 [ C(RESULT_ACCESS) ] = 0x3F3FFC0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
1192 [ C(RESULT_MISS) ] = 0x3F3FC00002, /* OCR.DEMAND_RFO.L3_MISS */
1193 },
1194 [ C(OP_PREFETCH) ] = {
1195 [ C(RESULT_ACCESS) ] = 0x0,
1196 [ C(RESULT_MISS) ] = 0x0,
1197 },
1198 },
1199 [ C(NODE) ] = {
1200 [ C(OP_READ) ] = {
1201 [ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
1202 [ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
1203 },
1204 [ C(OP_WRITE) ] = {
1205 [ C(RESULT_ACCESS) ] = 0x104000002, /* OCR.DEMAND_RFO.LOCAL_DRAM */
1206 [ C(RESULT_MISS) ] = 0x730000002, /* OCR.DEMAND_RFO.REMOTE_DRAM */
1207 },
1208 [ C(OP_PREFETCH) ] = {
1209 [ C(RESULT_ACCESS) ] = 0x0,
1210 [ C(RESULT_MISS) ] = 0x0,
1211 },
1212 },
1213 };
1214
1215 #define SNB_DMND_DATA_RD (1ULL << 0)
1216 #define SNB_DMND_RFO (1ULL << 1)
1217 #define SNB_DMND_IFETCH (1ULL << 2)
1218 #define SNB_DMND_WB (1ULL << 3)
1219 #define SNB_PF_DATA_RD (1ULL << 4)
1220 #define SNB_PF_RFO (1ULL << 5)
1221 #define SNB_PF_IFETCH (1ULL << 6)
1222 #define SNB_LLC_DATA_RD (1ULL << 7)
1223 #define SNB_LLC_RFO (1ULL << 8)
1224 #define SNB_LLC_IFETCH (1ULL << 9)
1225 #define SNB_BUS_LOCKS (1ULL << 10)
1226 #define SNB_STRM_ST (1ULL << 11)
1227 #define SNB_OTHER (1ULL << 15)
1228 #define SNB_RESP_ANY (1ULL << 16)
1229 #define SNB_NO_SUPP (1ULL << 17)
1230 #define SNB_LLC_HITM (1ULL << 18)
1231 #define SNB_LLC_HITE (1ULL << 19)
1232 #define SNB_LLC_HITS (1ULL << 20)
1233 #define SNB_LLC_HITF (1ULL << 21)
1234 #define SNB_LOCAL (1ULL << 22)
1235 #define SNB_REMOTE (0xffULL << 23)
1236 #define SNB_SNP_NONE (1ULL << 31)
1237 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
1238 #define SNB_SNP_MISS (1ULL << 33)
1239 #define SNB_NO_FWD (1ULL << 34)
1240 #define SNB_SNP_FWD (1ULL << 35)
1241 #define SNB_HITM (1ULL << 36)
1242 #define SNB_NON_DRAM (1ULL << 37)
1243
1244 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
1245 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
1246 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1247
1248 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
1249 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
1250 SNB_HITM)
1251
1252 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
1253 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
1254
1255 #define SNB_L3_ACCESS SNB_RESP_ANY
1256 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
1257
1258 static __initconst const u64 snb_hw_cache_extra_regs
1259 [PERF_COUNT_HW_CACHE_MAX]
1260 [PERF_COUNT_HW_CACHE_OP_MAX]
1261 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1262 {
1263 [ C(LL ) ] = {
1264 [ C(OP_READ) ] = {
1265 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
1266 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
1267 },
1268 [ C(OP_WRITE) ] = {
1269 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
1270 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
1271 },
1272 [ C(OP_PREFETCH) ] = {
1273 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
1274 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
1275 },
1276 },
1277 [ C(NODE) ] = {
1278 [ C(OP_READ) ] = {
1279 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
1280 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
1281 },
1282 [ C(OP_WRITE) ] = {
1283 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
1284 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
1285 },
1286 [ C(OP_PREFETCH) ] = {
1287 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
1288 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
1289 },
1290 },
1291 };
1292
1293 static __initconst const u64 snb_hw_cache_event_ids
1294 [PERF_COUNT_HW_CACHE_MAX]
1295 [PERF_COUNT_HW_CACHE_OP_MAX]
1296 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1297 {
1298 [ C(L1D) ] = {
1299 [ C(OP_READ) ] = {
1300 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
1301 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
1302 },
1303 [ C(OP_WRITE) ] = {
1304 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
1305 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
1306 },
1307 [ C(OP_PREFETCH) ] = {
1308 [ C(RESULT_ACCESS) ] = 0x0,
1309 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
1310 },
1311 },
1312 [ C(L1I ) ] = {
1313 [ C(OP_READ) ] = {
1314 [ C(RESULT_ACCESS) ] = 0x0,
1315 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
1316 },
1317 [ C(OP_WRITE) ] = {
1318 [ C(RESULT_ACCESS) ] = -1,
1319 [ C(RESULT_MISS) ] = -1,
1320 },
1321 [ C(OP_PREFETCH) ] = {
1322 [ C(RESULT_ACCESS) ] = 0x0,
1323 [ C(RESULT_MISS) ] = 0x0,
1324 },
1325 },
1326 [ C(LL ) ] = {
1327 [ C(OP_READ) ] = {
1328 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1329 [ C(RESULT_ACCESS) ] = 0x01b7,
1330 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1331 [ C(RESULT_MISS) ] = 0x01b7,
1332 },
1333 [ C(OP_WRITE) ] = {
1334 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1335 [ C(RESULT_ACCESS) ] = 0x01b7,
1336 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1337 [ C(RESULT_MISS) ] = 0x01b7,
1338 },
1339 [ C(OP_PREFETCH) ] = {
1340 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1341 [ C(RESULT_ACCESS) ] = 0x01b7,
1342 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1343 [ C(RESULT_MISS) ] = 0x01b7,
1344 },
1345 },
1346 [ C(DTLB) ] = {
1347 [ C(OP_READ) ] = {
1348 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
1349 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
1350 },
1351 [ C(OP_WRITE) ] = {
1352 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
1353 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1354 },
1355 [ C(OP_PREFETCH) ] = {
1356 [ C(RESULT_ACCESS) ] = 0x0,
1357 [ C(RESULT_MISS) ] = 0x0,
1358 },
1359 },
1360 [ C(ITLB) ] = {
1361 [ C(OP_READ) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
1363 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
1364 },
1365 [ C(OP_WRITE) ] = {
1366 [ C(RESULT_ACCESS) ] = -1,
1367 [ C(RESULT_MISS) ] = -1,
1368 },
1369 [ C(OP_PREFETCH) ] = {
1370 [ C(RESULT_ACCESS) ] = -1,
1371 [ C(RESULT_MISS) ] = -1,
1372 },
1373 },
1374 [ C(BPU ) ] = {
1375 [ C(OP_READ) ] = {
1376 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1377 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1378 },
1379 [ C(OP_WRITE) ] = {
1380 [ C(RESULT_ACCESS) ] = -1,
1381 [ C(RESULT_MISS) ] = -1,
1382 },
1383 [ C(OP_PREFETCH) ] = {
1384 [ C(RESULT_ACCESS) ] = -1,
1385 [ C(RESULT_MISS) ] = -1,
1386 },
1387 },
1388 [ C(NODE) ] = {
1389 [ C(OP_READ) ] = {
1390 [ C(RESULT_ACCESS) ] = 0x01b7,
1391 [ C(RESULT_MISS) ] = 0x01b7,
1392 },
1393 [ C(OP_WRITE) ] = {
1394 [ C(RESULT_ACCESS) ] = 0x01b7,
1395 [ C(RESULT_MISS) ] = 0x01b7,
1396 },
1397 [ C(OP_PREFETCH) ] = {
1398 [ C(RESULT_ACCESS) ] = 0x01b7,
1399 [ C(RESULT_MISS) ] = 0x01b7,
1400 },
1401 },
1402
1403 };
1404
1405 /*
1406 * Notes on the events:
1407 * - data reads do not include code reads (comparable to earlier tables)
1408 * - data counts include speculative execution (except L1 write, dtlb, bpu)
1409 * - remote node access includes remote memory, remote cache, remote mmio.
1410 * - prefetches are not included in the counts because they are not
1411 * reliably counted.
1412 */
1413
1414 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
1415 #define HSW_DEMAND_RFO BIT_ULL(1)
1416 #define HSW_ANY_RESPONSE BIT_ULL(16)
1417 #define HSW_SUPPLIER_NONE BIT_ULL(17)
1418 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
1419 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
1420 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
1421 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
1422 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
1423 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1424 HSW_L3_MISS_REMOTE_HOP2P)
1425 #define HSW_SNOOP_NONE BIT_ULL(31)
1426 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
1427 #define HSW_SNOOP_MISS BIT_ULL(33)
1428 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
1429 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
1430 #define HSW_SNOOP_HITM BIT_ULL(36)
1431 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
1432 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
1433 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
1434 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
1435 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
1436 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
1437 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
1438 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
1439 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
1440 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
1441 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
1442
1443 #define BDW_L3_MISS_LOCAL BIT(26)
1444 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
1445 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1446 HSW_L3_MISS_REMOTE_HOP2P)
1447
1448
1449 static __initconst const u64 hsw_hw_cache_event_ids
1450 [PERF_COUNT_HW_CACHE_MAX]
1451 [PERF_COUNT_HW_CACHE_OP_MAX]
1452 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1453 {
1454 [ C(L1D ) ] = {
1455 [ C(OP_READ) ] = {
1456 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1457 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1458 },
1459 [ C(OP_WRITE) ] = {
1460 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1461 [ C(RESULT_MISS) ] = 0x0,
1462 },
1463 [ C(OP_PREFETCH) ] = {
1464 [ C(RESULT_ACCESS) ] = 0x0,
1465 [ C(RESULT_MISS) ] = 0x0,
1466 },
1467 },
1468 [ C(L1I ) ] = {
1469 [ C(OP_READ) ] = {
1470 [ C(RESULT_ACCESS) ] = 0x0,
1471 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1472 },
1473 [ C(OP_WRITE) ] = {
1474 [ C(RESULT_ACCESS) ] = -1,
1475 [ C(RESULT_MISS) ] = -1,
1476 },
1477 [ C(OP_PREFETCH) ] = {
1478 [ C(RESULT_ACCESS) ] = 0x0,
1479 [ C(RESULT_MISS) ] = 0x0,
1480 },
1481 },
1482 [ C(LL ) ] = {
1483 [ C(OP_READ) ] = {
1484 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1485 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1486 },
1487 [ C(OP_WRITE) ] = {
1488 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1489 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1490 },
1491 [ C(OP_PREFETCH) ] = {
1492 [ C(RESULT_ACCESS) ] = 0x0,
1493 [ C(RESULT_MISS) ] = 0x0,
1494 },
1495 },
1496 [ C(DTLB) ] = {
1497 [ C(OP_READ) ] = {
1498 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1499 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1500 },
1501 [ C(OP_WRITE) ] = {
1502 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1503 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1504 },
1505 [ C(OP_PREFETCH) ] = {
1506 [ C(RESULT_ACCESS) ] = 0x0,
1507 [ C(RESULT_MISS) ] = 0x0,
1508 },
1509 },
1510 [ C(ITLB) ] = {
1511 [ C(OP_READ) ] = {
1512 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1513 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1514 },
1515 [ C(OP_WRITE) ] = {
1516 [ C(RESULT_ACCESS) ] = -1,
1517 [ C(RESULT_MISS) ] = -1,
1518 },
1519 [ C(OP_PREFETCH) ] = {
1520 [ C(RESULT_ACCESS) ] = -1,
1521 [ C(RESULT_MISS) ] = -1,
1522 },
1523 },
1524 [ C(BPU ) ] = {
1525 [ C(OP_READ) ] = {
1526 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1527 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1528 },
1529 [ C(OP_WRITE) ] = {
1530 [ C(RESULT_ACCESS) ] = -1,
1531 [ C(RESULT_MISS) ] = -1,
1532 },
1533 [ C(OP_PREFETCH) ] = {
1534 [ C(RESULT_ACCESS) ] = -1,
1535 [ C(RESULT_MISS) ] = -1,
1536 },
1537 },
1538 [ C(NODE) ] = {
1539 [ C(OP_READ) ] = {
1540 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1541 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1542 },
1543 [ C(OP_WRITE) ] = {
1544 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1545 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1546 },
1547 [ C(OP_PREFETCH) ] = {
1548 [ C(RESULT_ACCESS) ] = 0x0,
1549 [ C(RESULT_MISS) ] = 0x0,
1550 },
1551 },
1552 };
1553
1554 static __initconst const u64 hsw_hw_cache_extra_regs
1555 [PERF_COUNT_HW_CACHE_MAX]
1556 [PERF_COUNT_HW_CACHE_OP_MAX]
1557 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1558 {
1559 [ C(LL ) ] = {
1560 [ C(OP_READ) ] = {
1561 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1562 HSW_LLC_ACCESS,
1563 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1564 HSW_L3_MISS|HSW_ANY_SNOOP,
1565 },
1566 [ C(OP_WRITE) ] = {
1567 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1568 HSW_LLC_ACCESS,
1569 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1570 HSW_L3_MISS|HSW_ANY_SNOOP,
1571 },
1572 [ C(OP_PREFETCH) ] = {
1573 [ C(RESULT_ACCESS) ] = 0x0,
1574 [ C(RESULT_MISS) ] = 0x0,
1575 },
1576 },
1577 [ C(NODE) ] = {
1578 [ C(OP_READ) ] = {
1579 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1580 HSW_L3_MISS_LOCAL_DRAM|
1581 HSW_SNOOP_DRAM,
1582 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1583 HSW_L3_MISS_REMOTE|
1584 HSW_SNOOP_DRAM,
1585 },
1586 [ C(OP_WRITE) ] = {
1587 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1588 HSW_L3_MISS_LOCAL_DRAM|
1589 HSW_SNOOP_DRAM,
1590 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1591 HSW_L3_MISS_REMOTE|
1592 HSW_SNOOP_DRAM,
1593 },
1594 [ C(OP_PREFETCH) ] = {
1595 [ C(RESULT_ACCESS) ] = 0x0,
1596 [ C(RESULT_MISS) ] = 0x0,
1597 },
1598 },
1599 };
1600
1601 static __initconst const u64 westmere_hw_cache_event_ids
1602 [PERF_COUNT_HW_CACHE_MAX]
1603 [PERF_COUNT_HW_CACHE_OP_MAX]
1604 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1605 {
1606 [ C(L1D) ] = {
1607 [ C(OP_READ) ] = {
1608 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1609 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1610 },
1611 [ C(OP_WRITE) ] = {
1612 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1613 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1614 },
1615 [ C(OP_PREFETCH) ] = {
1616 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1617 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1618 },
1619 },
1620 [ C(L1I ) ] = {
1621 [ C(OP_READ) ] = {
1622 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1623 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1624 },
1625 [ C(OP_WRITE) ] = {
1626 [ C(RESULT_ACCESS) ] = -1,
1627 [ C(RESULT_MISS) ] = -1,
1628 },
1629 [ C(OP_PREFETCH) ] = {
1630 [ C(RESULT_ACCESS) ] = 0x0,
1631 [ C(RESULT_MISS) ] = 0x0,
1632 },
1633 },
1634 [ C(LL ) ] = {
1635 [ C(OP_READ) ] = {
1636 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1637 [ C(RESULT_ACCESS) ] = 0x01b7,
1638 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1639 [ C(RESULT_MISS) ] = 0x01b7,
1640 },
1641 /*
1642 * Use RFO, not WRITEBACK, because a write miss would typically occur
1643 * on RFO.
1644 */
1645 [ C(OP_WRITE) ] = {
1646 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1647 [ C(RESULT_ACCESS) ] = 0x01b7,
1648 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1649 [ C(RESULT_MISS) ] = 0x01b7,
1650 },
1651 [ C(OP_PREFETCH) ] = {
1652 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1653 [ C(RESULT_ACCESS) ] = 0x01b7,
1654 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1655 [ C(RESULT_MISS) ] = 0x01b7,
1656 },
1657 },
1658 [ C(DTLB) ] = {
1659 [ C(OP_READ) ] = {
1660 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1661 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1662 },
1663 [ C(OP_WRITE) ] = {
1664 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1665 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1666 },
1667 [ C(OP_PREFETCH) ] = {
1668 [ C(RESULT_ACCESS) ] = 0x0,
1669 [ C(RESULT_MISS) ] = 0x0,
1670 },
1671 },
1672 [ C(ITLB) ] = {
1673 [ C(OP_READ) ] = {
1674 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1675 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1676 },
1677 [ C(OP_WRITE) ] = {
1678 [ C(RESULT_ACCESS) ] = -1,
1679 [ C(RESULT_MISS) ] = -1,
1680 },
1681 [ C(OP_PREFETCH) ] = {
1682 [ C(RESULT_ACCESS) ] = -1,
1683 [ C(RESULT_MISS) ] = -1,
1684 },
1685 },
1686 [ C(BPU ) ] = {
1687 [ C(OP_READ) ] = {
1688 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1689 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1690 },
1691 [ C(OP_WRITE) ] = {
1692 [ C(RESULT_ACCESS) ] = -1,
1693 [ C(RESULT_MISS) ] = -1,
1694 },
1695 [ C(OP_PREFETCH) ] = {
1696 [ C(RESULT_ACCESS) ] = -1,
1697 [ C(RESULT_MISS) ] = -1,
1698 },
1699 },
1700 [ C(NODE) ] = {
1701 [ C(OP_READ) ] = {
1702 [ C(RESULT_ACCESS) ] = 0x01b7,
1703 [ C(RESULT_MISS) ] = 0x01b7,
1704 },
1705 [ C(OP_WRITE) ] = {
1706 [ C(RESULT_ACCESS) ] = 0x01b7,
1707 [ C(RESULT_MISS) ] = 0x01b7,
1708 },
1709 [ C(OP_PREFETCH) ] = {
1710 [ C(RESULT_ACCESS) ] = 0x01b7,
1711 [ C(RESULT_MISS) ] = 0x01b7,
1712 },
1713 },
1714 };
1715
1716 /*
1717 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1718 * See IA32 SDM Vol 3B 30.6.1.3
1719 */
1720
1721 #define NHM_DMND_DATA_RD (1 << 0)
1722 #define NHM_DMND_RFO (1 << 1)
1723 #define NHM_DMND_IFETCH (1 << 2)
1724 #define NHM_DMND_WB (1 << 3)
1725 #define NHM_PF_DATA_RD (1 << 4)
1726 #define NHM_PF_DATA_RFO (1 << 5)
1727 #define NHM_PF_IFETCH (1 << 6)
1728 #define NHM_OFFCORE_OTHER (1 << 7)
1729 #define NHM_UNCORE_HIT (1 << 8)
1730 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1731 #define NHM_OTHER_CORE_HITM (1 << 10)
1732 /* reserved */
1733 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1734 #define NHM_REMOTE_DRAM (1 << 13)
1735 #define NHM_LOCAL_DRAM (1 << 14)
1736 #define NHM_NON_DRAM (1 << 15)
1737
1738 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1739 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1740
1741 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1742 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1743 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1744
1745 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1746 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1747 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1748
1749 static __initconst const u64 nehalem_hw_cache_extra_regs
1750 [PERF_COUNT_HW_CACHE_MAX]
1751 [PERF_COUNT_HW_CACHE_OP_MAX]
1752 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1753 {
1754 [ C(LL ) ] = {
1755 [ C(OP_READ) ] = {
1756 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1757 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1758 },
1759 [ C(OP_WRITE) ] = {
1760 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1761 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1762 },
1763 [ C(OP_PREFETCH) ] = {
1764 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1765 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1766 },
1767 },
1768 [ C(NODE) ] = {
1769 [ C(OP_READ) ] = {
1770 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1771 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1772 },
1773 [ C(OP_WRITE) ] = {
1774 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1775 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1776 },
1777 [ C(OP_PREFETCH) ] = {
1778 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1779 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1780 },
1781 },
1782 };
1783
1784 static __initconst const u64 nehalem_hw_cache_event_ids
1785 [PERF_COUNT_HW_CACHE_MAX]
1786 [PERF_COUNT_HW_CACHE_OP_MAX]
1787 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1788 {
1789 [ C(L1D) ] = {
1790 [ C(OP_READ) ] = {
1791 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1792 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1793 },
1794 [ C(OP_WRITE) ] = {
1795 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1796 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1797 },
1798 [ C(OP_PREFETCH) ] = {
1799 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1800 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1801 },
1802 },
1803 [ C(L1I ) ] = {
1804 [ C(OP_READ) ] = {
1805 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1806 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1807 },
1808 [ C(OP_WRITE) ] = {
1809 [ C(RESULT_ACCESS) ] = -1,
1810 [ C(RESULT_MISS) ] = -1,
1811 },
1812 [ C(OP_PREFETCH) ] = {
1813 [ C(RESULT_ACCESS) ] = 0x0,
1814 [ C(RESULT_MISS) ] = 0x0,
1815 },
1816 },
1817 [ C(LL ) ] = {
1818 [ C(OP_READ) ] = {
1819 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1820 [ C(RESULT_ACCESS) ] = 0x01b7,
1821 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1822 [ C(RESULT_MISS) ] = 0x01b7,
1823 },
1824 /*
1825 * Use RFO, not WRITEBACK, because a write miss would typically occur
1826 * on RFO.
1827 */
1828 [ C(OP_WRITE) ] = {
1829 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1830 [ C(RESULT_ACCESS) ] = 0x01b7,
1831 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1832 [ C(RESULT_MISS) ] = 0x01b7,
1833 },
1834 [ C(OP_PREFETCH) ] = {
1835 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1836 [ C(RESULT_ACCESS) ] = 0x01b7,
1837 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1838 [ C(RESULT_MISS) ] = 0x01b7,
1839 },
1840 },
1841 [ C(DTLB) ] = {
1842 [ C(OP_READ) ] = {
1843 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1844 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1845 },
1846 [ C(OP_WRITE) ] = {
1847 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1848 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1849 },
1850 [ C(OP_PREFETCH) ] = {
1851 [ C(RESULT_ACCESS) ] = 0x0,
1852 [ C(RESULT_MISS) ] = 0x0,
1853 },
1854 },
1855 [ C(ITLB) ] = {
1856 [ C(OP_READ) ] = {
1857 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1858 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1859 },
1860 [ C(OP_WRITE) ] = {
1861 [ C(RESULT_ACCESS) ] = -1,
1862 [ C(RESULT_MISS) ] = -1,
1863 },
1864 [ C(OP_PREFETCH) ] = {
1865 [ C(RESULT_ACCESS) ] = -1,
1866 [ C(RESULT_MISS) ] = -1,
1867 },
1868 },
1869 [ C(BPU ) ] = {
1870 [ C(OP_READ) ] = {
1871 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1872 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1873 },
1874 [ C(OP_WRITE) ] = {
1875 [ C(RESULT_ACCESS) ] = -1,
1876 [ C(RESULT_MISS) ] = -1,
1877 },
1878 [ C(OP_PREFETCH) ] = {
1879 [ C(RESULT_ACCESS) ] = -1,
1880 [ C(RESULT_MISS) ] = -1,
1881 },
1882 },
1883 [ C(NODE) ] = {
1884 [ C(OP_READ) ] = {
1885 [ C(RESULT_ACCESS) ] = 0x01b7,
1886 [ C(RESULT_MISS) ] = 0x01b7,
1887 },
1888 [ C(OP_WRITE) ] = {
1889 [ C(RESULT_ACCESS) ] = 0x01b7,
1890 [ C(RESULT_MISS) ] = 0x01b7,
1891 },
1892 [ C(OP_PREFETCH) ] = {
1893 [ C(RESULT_ACCESS) ] = 0x01b7,
1894 [ C(RESULT_MISS) ] = 0x01b7,
1895 },
1896 },
1897 };
1898
1899 static __initconst const u64 core2_hw_cache_event_ids
1900 [PERF_COUNT_HW_CACHE_MAX]
1901 [PERF_COUNT_HW_CACHE_OP_MAX]
1902 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1903 {
1904 [ C(L1D) ] = {
1905 [ C(OP_READ) ] = {
1906 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1907 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1908 },
1909 [ C(OP_WRITE) ] = {
1910 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1911 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1912 },
1913 [ C(OP_PREFETCH) ] = {
1914 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1915 [ C(RESULT_MISS) ] = 0,
1916 },
1917 },
1918 [ C(L1I ) ] = {
1919 [ C(OP_READ) ] = {
1920 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1921 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1922 },
1923 [ C(OP_WRITE) ] = {
1924 [ C(RESULT_ACCESS) ] = -1,
1925 [ C(RESULT_MISS) ] = -1,
1926 },
1927 [ C(OP_PREFETCH) ] = {
1928 [ C(RESULT_ACCESS) ] = 0,
1929 [ C(RESULT_MISS) ] = 0,
1930 },
1931 },
1932 [ C(LL ) ] = {
1933 [ C(OP_READ) ] = {
1934 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1935 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1936 },
1937 [ C(OP_WRITE) ] = {
1938 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1939 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1940 },
1941 [ C(OP_PREFETCH) ] = {
1942 [ C(RESULT_ACCESS) ] = 0,
1943 [ C(RESULT_MISS) ] = 0,
1944 },
1945 },
1946 [ C(DTLB) ] = {
1947 [ C(OP_READ) ] = {
1948 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1949 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1950 },
1951 [ C(OP_WRITE) ] = {
1952 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1953 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1954 },
1955 [ C(OP_PREFETCH) ] = {
1956 [ C(RESULT_ACCESS) ] = 0,
1957 [ C(RESULT_MISS) ] = 0,
1958 },
1959 },
1960 [ C(ITLB) ] = {
1961 [ C(OP_READ) ] = {
1962 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1963 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1964 },
1965 [ C(OP_WRITE) ] = {
1966 [ C(RESULT_ACCESS) ] = -1,
1967 [ C(RESULT_MISS) ] = -1,
1968 },
1969 [ C(OP_PREFETCH) ] = {
1970 [ C(RESULT_ACCESS) ] = -1,
1971 [ C(RESULT_MISS) ] = -1,
1972 },
1973 },
1974 [ C(BPU ) ] = {
1975 [ C(OP_READ) ] = {
1976 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1977 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1978 },
1979 [ C(OP_WRITE) ] = {
1980 [ C(RESULT_ACCESS) ] = -1,
1981 [ C(RESULT_MISS) ] = -1,
1982 },
1983 [ C(OP_PREFETCH) ] = {
1984 [ C(RESULT_ACCESS) ] = -1,
1985 [ C(RESULT_MISS) ] = -1,
1986 },
1987 },
1988 };
1989
1990 static __initconst const u64 atom_hw_cache_event_ids
1991 [PERF_COUNT_HW_CACHE_MAX]
1992 [PERF_COUNT_HW_CACHE_OP_MAX]
1993 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1994 {
1995 [ C(L1D) ] = {
1996 [ C(OP_READ) ] = {
1997 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1998 [ C(RESULT_MISS) ] = 0,
1999 },
2000 [ C(OP_WRITE) ] = {
2001 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
2002 [ C(RESULT_MISS) ] = 0,
2003 },
2004 [ C(OP_PREFETCH) ] = {
2005 [ C(RESULT_ACCESS) ] = 0x0,
2006 [ C(RESULT_MISS) ] = 0,
2007 },
2008 },
2009 [ C(L1I ) ] = {
2010 [ C(OP_READ) ] = {
2011 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
2012 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
2013 },
2014 [ C(OP_WRITE) ] = {
2015 [ C(RESULT_ACCESS) ] = -1,
2016 [ C(RESULT_MISS) ] = -1,
2017 },
2018 [ C(OP_PREFETCH) ] = {
2019 [ C(RESULT_ACCESS) ] = 0,
2020 [ C(RESULT_MISS) ] = 0,
2021 },
2022 },
2023 [ C(LL ) ] = {
2024 [ C(OP_READ) ] = {
2025 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
2026 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
2027 },
2028 [ C(OP_WRITE) ] = {
2029 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
2030 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
2031 },
2032 [ C(OP_PREFETCH) ] = {
2033 [ C(RESULT_ACCESS) ] = 0,
2034 [ C(RESULT_MISS) ] = 0,
2035 },
2036 },
2037 [ C(DTLB) ] = {
2038 [ C(OP_READ) ] = {
2039 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
2040 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
2041 },
2042 [ C(OP_WRITE) ] = {
2043 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
2044 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
2045 },
2046 [ C(OP_PREFETCH) ] = {
2047 [ C(RESULT_ACCESS) ] = 0,
2048 [ C(RESULT_MISS) ] = 0,
2049 },
2050 },
2051 [ C(ITLB) ] = {
2052 [ C(OP_READ) ] = {
2053 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
2054 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
2055 },
2056 [ C(OP_WRITE) ] = {
2057 [ C(RESULT_ACCESS) ] = -1,
2058 [ C(RESULT_MISS) ] = -1,
2059 },
2060 [ C(OP_PREFETCH) ] = {
2061 [ C(RESULT_ACCESS) ] = -1,
2062 [ C(RESULT_MISS) ] = -1,
2063 },
2064 },
2065 [ C(BPU ) ] = {
2066 [ C(OP_READ) ] = {
2067 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
2068 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
2069 },
2070 [ C(OP_WRITE) ] = {
2071 [ C(RESULT_ACCESS) ] = -1,
2072 [ C(RESULT_MISS) ] = -1,
2073 },
2074 [ C(OP_PREFETCH) ] = {
2075 [ C(RESULT_ACCESS) ] = -1,
2076 [ C(RESULT_MISS) ] = -1,
2077 },
2078 },
2079 };
2080
2081 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
2082 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
2083 /* no_alloc_cycles.not_delivered */
2084 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
2085 "event=0xca,umask=0x50");
2086 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
2087 /* uops_retired.all */
2088 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
2089 "event=0xc2,umask=0x10");
2090 /* uops_retired.all */
2091 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
2092 "event=0xc2,umask=0x10");
2093
2094 static struct attribute *slm_events_attrs[] = {
2095 EVENT_PTR(td_total_slots_slm),
2096 EVENT_PTR(td_total_slots_scale_slm),
2097 EVENT_PTR(td_fetch_bubbles_slm),
2098 EVENT_PTR(td_fetch_bubbles_scale_slm),
2099 EVENT_PTR(td_slots_issued_slm),
2100 EVENT_PTR(td_slots_retired_slm),
2101 NULL
2102 };
2103
2104 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
2105 {
2106 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2107 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
2108 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
2109 EVENT_EXTRA_END
2110 };
2111
2112 #define SLM_DMND_READ SNB_DMND_DATA_RD
2113 #define SLM_DMND_WRITE SNB_DMND_RFO
2114 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
2115
2116 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
2117 #define SLM_LLC_ACCESS SNB_RESP_ANY
2118 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
2119
2120 static __initconst const u64 slm_hw_cache_extra_regs
2121 [PERF_COUNT_HW_CACHE_MAX]
2122 [PERF_COUNT_HW_CACHE_OP_MAX]
2123 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
2124 {
2125 [ C(LL ) ] = {
2126 [ C(OP_READ) ] = {
2127 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
2128 [ C(RESULT_MISS) ] = 0,
2129 },
2130 [ C(OP_WRITE) ] = {
2131 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
2132 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
2133 },
2134 [ C(OP_PREFETCH) ] = {
2135 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
2136 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
2137 },
2138 },
2139 };
2140
2141 static __initconst const u64 slm_hw_cache_event_ids
2142 [PERF_COUNT_HW_CACHE_MAX]
2143 [PERF_COUNT_HW_CACHE_OP_MAX]
2144 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
2145 {
2146 [ C(L1D) ] = {
2147 [ C(OP_READ) ] = {
2148 [ C(RESULT_ACCESS) ] = 0,
2149 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
2150 },
2151 [ C(OP_WRITE) ] = {
2152 [ C(RESULT_ACCESS) ] = 0,
2153 [ C(RESULT_MISS) ] = 0,
2154 },
2155 [ C(OP_PREFETCH) ] = {
2156 [ C(RESULT_ACCESS) ] = 0,
2157 [ C(RESULT_MISS) ] = 0,
2158 },
2159 },
2160 [ C(L1I ) ] = {
2161 [ C(OP_READ) ] = {
2162 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
2163 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
2164 },
2165 [ C(OP_WRITE) ] = {
2166 [ C(RESULT_ACCESS) ] = -1,
2167 [ C(RESULT_MISS) ] = -1,
2168 },
2169 [ C(OP_PREFETCH) ] = {
2170 [ C(RESULT_ACCESS) ] = 0,
2171 [ C(RESULT_MISS) ] = 0,
2172 },
2173 },
2174 [ C(LL ) ] = {
2175 [ C(OP_READ) ] = {
2176 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
2177 [ C(RESULT_ACCESS) ] = 0x01b7,
2178 [ C(RESULT_MISS) ] = 0,
2179 },
2180 [ C(OP_WRITE) ] = {
2181 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
2182 [ C(RESULT_ACCESS) ] = 0x01b7,
2183 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
2184 [ C(RESULT_MISS) ] = 0x01b7,
2185 },
2186 [ C(OP_PREFETCH) ] = {
2187 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
2188 [ C(RESULT_ACCESS) ] = 0x01b7,
2189 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
2190 [ C(RESULT_MISS) ] = 0x01b7,
2191 },
2192 },
2193 [ C(DTLB) ] = {
2194 [ C(OP_READ) ] = {
2195 [ C(RESULT_ACCESS) ] = 0,
2196 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
2197 },
2198 [ C(OP_WRITE) ] = {
2199 [ C(RESULT_ACCESS) ] = 0,
2200 [ C(RESULT_MISS) ] = 0,
2201 },
2202 [ C(OP_PREFETCH) ] = {
2203 [ C(RESULT_ACCESS) ] = 0,
2204 [ C(RESULT_MISS) ] = 0,
2205 },
2206 },
2207 [ C(ITLB) ] = {
2208 [ C(OP_READ) ] = {
2209 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
2210 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
2211 },
2212 [ C(OP_WRITE) ] = {
2213 [ C(RESULT_ACCESS) ] = -1,
2214 [ C(RESULT_MISS) ] = -1,
2215 },
2216 [ C(OP_PREFETCH) ] = {
2217 [ C(RESULT_ACCESS) ] = -1,
2218 [ C(RESULT_MISS) ] = -1,
2219 },
2220 },
2221 [ C(BPU ) ] = {
2222 [ C(OP_READ) ] = {
2223 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
2224 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
2225 },
2226 [ C(OP_WRITE) ] = {
2227 [ C(RESULT_ACCESS) ] = -1,
2228 [ C(RESULT_MISS) ] = -1,
2229 },
2230 [ C(OP_PREFETCH) ] = {
2231 [ C(RESULT_ACCESS) ] = -1,
2232 [ C(RESULT_MISS) ] = -1,
2233 },
2234 },
2235 };
2236
2237 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
2238 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
2239 /* UOPS_NOT_DELIVERED.ANY */
2240 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
2241 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
2242 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
2243 /* UOPS_RETIRED.ANY */
2244 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
2245 /* UOPS_ISSUED.ANY */
2246 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
2247
2248 static struct attribute *glm_events_attrs[] = {
2249 EVENT_PTR(td_total_slots_glm),
2250 EVENT_PTR(td_total_slots_scale_glm),
2251 EVENT_PTR(td_fetch_bubbles_glm),
2252 EVENT_PTR(td_recovery_bubbles_glm),
2253 EVENT_PTR(td_slots_issued_glm),
2254 EVENT_PTR(td_slots_retired_glm),
2255 NULL
2256 };
2257
2258 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
2259 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2260 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
2261 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
2262 EVENT_EXTRA_END
2263 };
2264
2265 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
2266 #define GLM_DEMAND_RFO BIT_ULL(1)
2267 #define GLM_ANY_RESPONSE BIT_ULL(16)
2268 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
2269 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
2270 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
2271 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
2272 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
2273 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
2274 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
2275
2276 static __initconst const u64 glm_hw_cache_event_ids
2277 [PERF_COUNT_HW_CACHE_MAX]
2278 [PERF_COUNT_HW_CACHE_OP_MAX]
2279 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2280 [C(L1D)] = {
2281 [C(OP_READ)] = {
2282 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2283 [C(RESULT_MISS)] = 0x0,
2284 },
2285 [C(OP_WRITE)] = {
2286 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2287 [C(RESULT_MISS)] = 0x0,
2288 },
2289 [C(OP_PREFETCH)] = {
2290 [C(RESULT_ACCESS)] = 0x0,
2291 [C(RESULT_MISS)] = 0x0,
2292 },
2293 },
2294 [C(L1I)] = {
2295 [C(OP_READ)] = {
2296 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2297 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2298 },
2299 [C(OP_WRITE)] = {
2300 [C(RESULT_ACCESS)] = -1,
2301 [C(RESULT_MISS)] = -1,
2302 },
2303 [C(OP_PREFETCH)] = {
2304 [C(RESULT_ACCESS)] = 0x0,
2305 [C(RESULT_MISS)] = 0x0,
2306 },
2307 },
2308 [C(LL)] = {
2309 [C(OP_READ)] = {
2310 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2311 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2312 },
2313 [C(OP_WRITE)] = {
2314 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2315 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2316 },
2317 [C(OP_PREFETCH)] = {
2318 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2319 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2320 },
2321 },
2322 [C(DTLB)] = {
2323 [C(OP_READ)] = {
2324 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2325 [C(RESULT_MISS)] = 0x0,
2326 },
2327 [C(OP_WRITE)] = {
2328 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2329 [C(RESULT_MISS)] = 0x0,
2330 },
2331 [C(OP_PREFETCH)] = {
2332 [C(RESULT_ACCESS)] = 0x0,
2333 [C(RESULT_MISS)] = 0x0,
2334 },
2335 },
2336 [C(ITLB)] = {
2337 [C(OP_READ)] = {
2338 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2339 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2340 },
2341 [C(OP_WRITE)] = {
2342 [C(RESULT_ACCESS)] = -1,
2343 [C(RESULT_MISS)] = -1,
2344 },
2345 [C(OP_PREFETCH)] = {
2346 [C(RESULT_ACCESS)] = -1,
2347 [C(RESULT_MISS)] = -1,
2348 },
2349 },
2350 [C(BPU)] = {
2351 [C(OP_READ)] = {
2352 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2353 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2354 },
2355 [C(OP_WRITE)] = {
2356 [C(RESULT_ACCESS)] = -1,
2357 [C(RESULT_MISS)] = -1,
2358 },
2359 [C(OP_PREFETCH)] = {
2360 [C(RESULT_ACCESS)] = -1,
2361 [C(RESULT_MISS)] = -1,
2362 },
2363 },
2364 };
2365
2366 static __initconst const u64 glm_hw_cache_extra_regs
2367 [PERF_COUNT_HW_CACHE_MAX]
2368 [PERF_COUNT_HW_CACHE_OP_MAX]
2369 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2370 [C(LL)] = {
2371 [C(OP_READ)] = {
2372 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2373 GLM_LLC_ACCESS,
2374 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2375 GLM_LLC_MISS,
2376 },
2377 [C(OP_WRITE)] = {
2378 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2379 GLM_LLC_ACCESS,
2380 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2381 GLM_LLC_MISS,
2382 },
2383 [C(OP_PREFETCH)] = {
2384 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
2385 GLM_LLC_ACCESS,
2386 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
2387 GLM_LLC_MISS,
2388 },
2389 },
2390 };
2391
2392 static __initconst const u64 glp_hw_cache_event_ids
2393 [PERF_COUNT_HW_CACHE_MAX]
2394 [PERF_COUNT_HW_CACHE_OP_MAX]
2395 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2396 [C(L1D)] = {
2397 [C(OP_READ)] = {
2398 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2399 [C(RESULT_MISS)] = 0x0,
2400 },
2401 [C(OP_WRITE)] = {
2402 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2403 [C(RESULT_MISS)] = 0x0,
2404 },
2405 [C(OP_PREFETCH)] = {
2406 [C(RESULT_ACCESS)] = 0x0,
2407 [C(RESULT_MISS)] = 0x0,
2408 },
2409 },
2410 [C(L1I)] = {
2411 [C(OP_READ)] = {
2412 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2413 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2414 },
2415 [C(OP_WRITE)] = {
2416 [C(RESULT_ACCESS)] = -1,
2417 [C(RESULT_MISS)] = -1,
2418 },
2419 [C(OP_PREFETCH)] = {
2420 [C(RESULT_ACCESS)] = 0x0,
2421 [C(RESULT_MISS)] = 0x0,
2422 },
2423 },
2424 [C(LL)] = {
2425 [C(OP_READ)] = {
2426 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2427 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2428 },
2429 [C(OP_WRITE)] = {
2430 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2431 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2432 },
2433 [C(OP_PREFETCH)] = {
2434 [C(RESULT_ACCESS)] = 0x0,
2435 [C(RESULT_MISS)] = 0x0,
2436 },
2437 },
2438 [C(DTLB)] = {
2439 [C(OP_READ)] = {
2440 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2441 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
2442 },
2443 [C(OP_WRITE)] = {
2444 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2445 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
2446 },
2447 [C(OP_PREFETCH)] = {
2448 [C(RESULT_ACCESS)] = 0x0,
2449 [C(RESULT_MISS)] = 0x0,
2450 },
2451 },
2452 [C(ITLB)] = {
2453 [C(OP_READ)] = {
2454 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2455 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2456 },
2457 [C(OP_WRITE)] = {
2458 [C(RESULT_ACCESS)] = -1,
2459 [C(RESULT_MISS)] = -1,
2460 },
2461 [C(OP_PREFETCH)] = {
2462 [C(RESULT_ACCESS)] = -1,
2463 [C(RESULT_MISS)] = -1,
2464 },
2465 },
2466 [C(BPU)] = {
2467 [C(OP_READ)] = {
2468 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2469 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2470 },
2471 [C(OP_WRITE)] = {
2472 [C(RESULT_ACCESS)] = -1,
2473 [C(RESULT_MISS)] = -1,
2474 },
2475 [C(OP_PREFETCH)] = {
2476 [C(RESULT_ACCESS)] = -1,
2477 [C(RESULT_MISS)] = -1,
2478 },
2479 },
2480 };
2481
2482 static __initconst const u64 glp_hw_cache_extra_regs
2483 [PERF_COUNT_HW_CACHE_MAX]
2484 [PERF_COUNT_HW_CACHE_OP_MAX]
2485 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2486 [C(LL)] = {
2487 [C(OP_READ)] = {
2488 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2489 GLM_LLC_ACCESS,
2490 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2491 GLM_LLC_MISS,
2492 },
2493 [C(OP_WRITE)] = {
2494 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2495 GLM_LLC_ACCESS,
2496 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2497 GLM_LLC_MISS,
2498 },
2499 [C(OP_PREFETCH)] = {
2500 [C(RESULT_ACCESS)] = 0x0,
2501 [C(RESULT_MISS)] = 0x0,
2502 },
2503 },
2504 };
2505
2506 #define TNT_LOCAL_DRAM BIT_ULL(26)
2507 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
2508 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
2509 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
2510 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2511 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2512 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2513
2514 static __initconst const u64 tnt_hw_cache_extra_regs
2515 [PERF_COUNT_HW_CACHE_MAX]
2516 [PERF_COUNT_HW_CACHE_OP_MAX]
2517 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2518 [C(LL)] = {
2519 [C(OP_READ)] = {
2520 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2521 TNT_LLC_ACCESS,
2522 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2523 TNT_LLC_MISS,
2524 },
2525 [C(OP_WRITE)] = {
2526 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2527 TNT_LLC_ACCESS,
2528 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2529 TNT_LLC_MISS,
2530 },
2531 [C(OP_PREFETCH)] = {
2532 [C(RESULT_ACCESS)] = 0x0,
2533 [C(RESULT_MISS)] = 0x0,
2534 },
2535 },
2536 };
2537
2538 static __initconst const u64 grt_hw_cache_extra_regs
2539 [PERF_COUNT_HW_CACHE_MAX]
2540 [PERF_COUNT_HW_CACHE_OP_MAX]
2541 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2542 [C(LL)] = {
2543 [C(OP_READ)] = {
2544 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2545 [C(RESULT_MISS)] = 0x3F84400001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2546 },
2547 [C(OP_WRITE)] = {
2548 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2549 [C(RESULT_MISS)] = 0x3F84400002, /* OCR.DEMAND_RFO.L3_MISS */
2550 },
2551 },
2552 };
2553
2554 static __initconst const u64 cmt_hw_cache_extra_regs
2555 [PERF_COUNT_HW_CACHE_MAX]
2556 [PERF_COUNT_HW_CACHE_OP_MAX]
2557 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2558 [C(LL)] = {
2559 [C(OP_READ)] = {
2560 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2561 [C(RESULT_MISS)] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2562 },
2563 [C(OP_WRITE)] = {
2564 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2565 [C(RESULT_MISS)] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */
2566 },
2567 },
2568 };
2569
2570 static __initconst const u64 skt_hw_cache_extra_regs
2571 [PERF_COUNT_HW_CACHE_MAX]
2572 [PERF_COUNT_HW_CACHE_OP_MAX]
2573 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2574 [C(LL)] = {
2575 [C(OP_READ)] = {
2576 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2577 [C(RESULT_MISS)] = 0x13FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2578 },
2579 [C(OP_WRITE)] = {
2580 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2581 [C(RESULT_MISS)] = 0x13FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */
2582 },
2583 },
2584 };
2585
2586 static __initconst const u64 dkt_hw_cache_extra_regs
2587 [PERF_COUNT_HW_CACHE_MAX]
2588 [PERF_COUNT_HW_CACHE_OP_MAX]
2589 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2590 [C(LL)] = {
2591 [C(OP_READ)] = {
2592 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2593 [C(RESULT_MISS)] = 0x33FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2594 },
2595 [C(OP_WRITE)] = {
2596 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2597 [C(RESULT_MISS)] = 0x33FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */
2598 },
2599 },
2600 };
2601
2602 static __initconst const u64 arw_hw_cache_extra_regs
2603 [PERF_COUNT_HW_CACHE_MAX]
2604 [PERF_COUNT_HW_CACHE_OP_MAX]
2605 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2606 [C(LL)] = {
2607 [C(OP_READ)] = {
2608 [C(RESULT_ACCESS)] = 0x4000000000000009, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
2609 [C(RESULT_MISS)] = 0xFF03F000000009, /* OMR.DEMAND_DATA_RD.L3_MISS */
2610 },
2611 [C(OP_WRITE)] = {
2612 [C(RESULT_ACCESS)] = 0x400000000000000A, /* OMR.DEMAND_RFO.ANY_RESPONSE */
2613 [C(RESULT_MISS)] = 0xFF03F00000000A, /* OMR.DEMAND_RFO.L3_MISS */
2614 },
2615 },
2616 };
2617
2618 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
2619 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
2620 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
2621 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
2622
2623 static struct attribute *tnt_events_attrs[] = {
2624 EVENT_PTR(td_fe_bound_tnt),
2625 EVENT_PTR(td_retiring_tnt),
2626 EVENT_PTR(td_bad_spec_tnt),
2627 EVENT_PTR(td_be_bound_tnt),
2628 NULL,
2629 };
2630
2631 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2632 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2633 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2634 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2635 EVENT_EXTRA_END
2636 };
2637
2638 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3");
2639 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
2640
2641 static struct attribute *grt_mem_attrs[] = {
2642 EVENT_PTR(mem_ld_grt),
2643 EVENT_PTR(mem_st_grt),
2644 NULL
2645 };
2646
2647 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2648 /*
2649 * Must define OFFCORE_RSP_X first, see intel_fixup_er().
2650 * Bit 63 only valid on OFFCORE_RSP_0 MSR.
2651 */
2652 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x8003f03fffffffffull, RSP_0),
2653 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3f03fffffffffull, RSP_1),
2654 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2655 EVENT_EXTRA_END
2656 };
2657
2658 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0");
2659 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0");
2660
2661 static struct attribute *cmt_events_attrs[] = {
2662 EVENT_PTR(td_fe_bound_tnt),
2663 EVENT_PTR(td_retiring_cmt),
2664 EVENT_PTR(td_bad_spec_cmt),
2665 EVENT_PTR(td_be_bound_tnt),
2666 NULL
2667 };
2668
2669 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
2670 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2671 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
2672 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1),
2673 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2674 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2675 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2676 EVENT_EXTRA_END
2677 };
2678
2679 static struct extra_reg intel_arw_extra_regs[] __read_mostly = {
2680 /* must define OMR_X first, see intel_alt_er() */
2681 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0),
2682 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
2683 INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
2684 INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
2685 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2686 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2687 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2688 EVENT_EXTRA_END
2689 };
2690
2691 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_skt, "event=0x9c,umask=0x01");
2692 EVENT_ATTR_STR(topdown-retiring, td_retiring_skt, "event=0xc2,umask=0x02");
2693 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_skt, "event=0xa4,umask=0x02");
2694
2695 static struct attribute *skt_events_attrs[] = {
2696 EVENT_PTR(td_fe_bound_skt),
2697 EVENT_PTR(td_retiring_skt),
2698 EVENT_PTR(td_bad_spec_cmt),
2699 EVENT_PTR(td_be_bound_skt),
2700 NULL,
2701 };
2702
2703 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
2704 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
2705 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
2706 #define KNL_MCDRAM_FAR BIT_ULL(22)
2707 #define KNL_DDR_LOCAL BIT_ULL(23)
2708 #define KNL_DDR_FAR BIT_ULL(24)
2709 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2710 KNL_DDR_LOCAL | KNL_DDR_FAR)
2711 #define KNL_L2_READ SLM_DMND_READ
2712 #define KNL_L2_WRITE SLM_DMND_WRITE
2713 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
2714 #define KNL_L2_ACCESS SLM_LLC_ACCESS
2715 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2716 KNL_DRAM_ANY | SNB_SNP_ANY | \
2717 SNB_NON_DRAM)
2718
2719 static __initconst const u64 knl_hw_cache_extra_regs
2720 [PERF_COUNT_HW_CACHE_MAX]
2721 [PERF_COUNT_HW_CACHE_OP_MAX]
2722 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2723 [C(LL)] = {
2724 [C(OP_READ)] = {
2725 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2726 [C(RESULT_MISS)] = 0,
2727 },
2728 [C(OP_WRITE)] = {
2729 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2730 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2731 },
2732 [C(OP_PREFETCH)] = {
2733 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2734 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2735 },
2736 },
2737 };
2738
2739 /*
2740 * Used from PMIs where the LBRs are already disabled.
2741 *
2742 * This function could be called consecutively. It is required to remain in
2743 * disabled state if called consecutively.
2744 *
2745 * During consecutive calls, the same disable value will be written to related
2746 * registers, so the PMU state remains unchanged.
2747 *
2748 * intel_bts events don't coexist with intel PMU's BTS events because of
2749 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2750 * disabled around intel PMU's event batching etc, only inside the PMI handler.
2751 *
2752 * Avoid PEBS_ENABLE MSR access in PMIs.
2753 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2754 * It doesn't matter if the PEBS is enabled or not.
2755 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2756 * access PEBS_ENABLE MSR in disable_all()/enable_all().
2757 * However, there are some cases which may change PEBS status, e.g. PMI
2758 * throttle. The PEBS_ENABLE should be updated where the status changes.
2759 */
__intel_pmu_disable_all(bool bts)2760 static __always_inline void __intel_pmu_disable_all(bool bts)
2761 {
2762 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2763
2764 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2765
2766 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2767 intel_pmu_disable_bts();
2768 }
2769
intel_pmu_disable_all(void)2770 static __always_inline void intel_pmu_disable_all(void)
2771 {
2772 __intel_pmu_disable_all(true);
2773 static_call_cond(x86_pmu_pebs_disable_all)();
2774 intel_pmu_lbr_disable_all();
2775 }
2776
__intel_pmu_enable_all(int added,bool pmi)2777 static void __intel_pmu_enable_all(int added, bool pmi)
2778 {
2779 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2780 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2781
2782 intel_pmu_lbr_enable_all(pmi);
2783
2784 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) {
2785 wrmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val);
2786 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val;
2787 }
2788
2789 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL,
2790 intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2791
2792 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2793 struct perf_event *event =
2794 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2795
2796 if (WARN_ON_ONCE(!event))
2797 return;
2798
2799 intel_pmu_enable_bts(event->hw.config);
2800 }
2801 }
2802
intel_pmu_enable_all(int added)2803 static void intel_pmu_enable_all(int added)
2804 {
2805 static_call_cond(x86_pmu_pebs_enable_all)();
2806 __intel_pmu_enable_all(added, false);
2807 }
2808
2809 static noinline int
__intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt,unsigned long flags)2810 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries,
2811 unsigned int cnt, unsigned long flags)
2812 {
2813 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2814
2815 intel_pmu_lbr_read();
2816 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr);
2817
2818 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
2819 intel_pmu_enable_all(0);
2820 local_irq_restore(flags);
2821 return cnt;
2822 }
2823
2824 static int
intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2825 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2826 {
2827 unsigned long flags;
2828
2829 /* must not have branches... */
2830 local_irq_save(flags);
2831 __intel_pmu_disable_all(false); /* we don't care about BTS */
2832 __intel_pmu_lbr_disable();
2833 /* ... until here */
2834 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2835 }
2836
2837 static int
intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2838 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2839 {
2840 unsigned long flags;
2841
2842 /* must not have branches... */
2843 local_irq_save(flags);
2844 __intel_pmu_disable_all(false); /* we don't care about BTS */
2845 __intel_pmu_arch_lbr_disable();
2846 /* ... until here */
2847 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2848 }
2849
2850 /*
2851 * Workaround for:
2852 * Intel Errata AAK100 (model 26)
2853 * Intel Errata AAP53 (model 30)
2854 * Intel Errata BD53 (model 44)
2855 *
2856 * The official story:
2857 * These chips need to be 'reset' when adding counters by programming the
2858 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2859 * in sequence on the same PMC or on different PMCs.
2860 *
2861 * In practice it appears some of these events do in fact count, and
2862 * we need to program all 4 events.
2863 */
intel_pmu_nhm_workaround(void)2864 static void intel_pmu_nhm_workaround(void)
2865 {
2866 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2867 static const unsigned long nhm_magic[4] = {
2868 0x4300B5,
2869 0x4300D2,
2870 0x4300B1,
2871 0x4300B1
2872 };
2873 struct perf_event *event;
2874 int i;
2875
2876 /*
2877 * The Errata requires below steps:
2878 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2879 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2880 * the corresponding PMCx;
2881 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2882 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2883 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2884 */
2885
2886 /*
2887 * The real steps we choose are a little different from above.
2888 * A) To reduce MSR operations, we don't run step 1) as they
2889 * are already cleared before this function is called;
2890 * B) Call x86_perf_event_update to save PMCx before configuring
2891 * PERFEVTSELx with magic number;
2892 * C) With step 5), we do clear only when the PERFEVTSELx is
2893 * not used currently.
2894 * D) Call x86_perf_event_set_period to restore PMCx;
2895 */
2896
2897 /* We always operate 4 pairs of PERF Counters */
2898 for (i = 0; i < 4; i++) {
2899 event = cpuc->events[i];
2900 if (event)
2901 static_call(x86_pmu_update)(event);
2902 }
2903
2904 for (i = 0; i < 4; i++) {
2905 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2906 wrmsrq(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2907 }
2908
2909 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2910 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2911
2912 for (i = 0; i < 4; i++) {
2913 event = cpuc->events[i];
2914
2915 if (event) {
2916 static_call(x86_pmu_set_period)(event);
2917 __x86_pmu_enable_event(&event->hw,
2918 ARCH_PERFMON_EVENTSEL_ENABLE);
2919 } else
2920 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2921 }
2922 }
2923
intel_pmu_nhm_enable_all(int added)2924 static void intel_pmu_nhm_enable_all(int added)
2925 {
2926 if (added)
2927 intel_pmu_nhm_workaround();
2928 intel_pmu_enable_all(added);
2929 }
2930
intel_set_tfa(struct cpu_hw_events * cpuc,bool on)2931 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2932 {
2933 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2934
2935 if (cpuc->tfa_shadow != val) {
2936 cpuc->tfa_shadow = val;
2937 wrmsrq(MSR_TSX_FORCE_ABORT, val);
2938 }
2939 }
2940
intel_tfa_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)2941 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2942 {
2943 /*
2944 * We're going to use PMC3, make sure TFA is set before we touch it.
2945 */
2946 if (cntr == 3)
2947 intel_set_tfa(cpuc, true);
2948 }
2949
intel_tfa_pmu_enable_all(int added)2950 static void intel_tfa_pmu_enable_all(int added)
2951 {
2952 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2953
2954 /*
2955 * If we find PMC3 is no longer used when we enable the PMU, we can
2956 * clear TFA.
2957 */
2958 if (!test_bit(3, cpuc->active_mask))
2959 intel_set_tfa(cpuc, false);
2960
2961 intel_pmu_enable_all(added);
2962 }
2963
intel_pmu_get_status(void)2964 static inline u64 intel_pmu_get_status(void)
2965 {
2966 u64 status;
2967
2968 rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status);
2969
2970 return status;
2971 }
2972
intel_pmu_ack_status(u64 ack)2973 static inline void intel_pmu_ack_status(u64 ack)
2974 {
2975 wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2976 }
2977
event_is_checkpointed(struct perf_event * event)2978 static inline bool event_is_checkpointed(struct perf_event *event)
2979 {
2980 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2981 }
2982
intel_set_masks(struct perf_event * event,int idx)2983 static inline void intel_set_masks(struct perf_event *event, int idx)
2984 {
2985 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2986
2987 if (event->attr.exclude_host)
2988 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2989 if (event->attr.exclude_guest)
2990 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2991 if (event_is_checkpointed(event))
2992 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2993 }
2994
intel_clear_masks(struct perf_event * event,int idx)2995 static inline void intel_clear_masks(struct perf_event *event, int idx)
2996 {
2997 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2998
2999 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
3000 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
3001 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
3002 }
3003
intel_pmu_disable_fixed(struct perf_event * event)3004 static void intel_pmu_disable_fixed(struct perf_event *event)
3005 {
3006 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3007 struct hw_perf_event *hwc = &event->hw;
3008 int idx = hwc->idx;
3009 u64 mask;
3010
3011 if (is_topdown_idx(idx)) {
3012 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3013
3014 /*
3015 * When there are other active TopDown events,
3016 * don't disable the fixed counter 3.
3017 */
3018 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
3019 return;
3020 idx = INTEL_PMC_IDX_FIXED_SLOTS;
3021 }
3022
3023 intel_clear_masks(event, idx);
3024
3025 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);
3026 cpuc->fixed_ctrl_val &= ~mask;
3027 }
3028
__intel_pmu_update_event_ext(int idx,u64 ext)3029 static inline void __intel_pmu_update_event_ext(int idx, u64 ext)
3030 {
3031 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3032 u32 msr;
3033
3034 if (idx < INTEL_PMC_IDX_FIXED) {
3035 msr = MSR_IA32_PMC_V6_GP0_CFG_C +
3036 x86_pmu.addr_offset(idx, false);
3037 } else {
3038 msr = MSR_IA32_PMC_V6_FX0_CFG_C +
3039 x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
3040 }
3041
3042 cpuc->cfg_c_val[idx] = ext;
3043 wrmsrq(msr, ext);
3044 }
3045
intel_pmu_disable_event_ext(struct perf_event * event)3046 static void intel_pmu_disable_event_ext(struct perf_event *event)
3047 {
3048 /*
3049 * Only clear CFG_C MSR for PEBS counter group events,
3050 * it avoids the HW counter's value to be added into
3051 * other PEBS records incorrectly after PEBS counter
3052 * group events are disabled.
3053 *
3054 * For other events, it's unnecessary to clear CFG_C MSRs
3055 * since CFG_C doesn't take effect if counter is in
3056 * disabled state. That helps to reduce the WRMSR overhead
3057 * in context switches.
3058 */
3059 if (!is_pebs_counter_event_group(event))
3060 return;
3061
3062 __intel_pmu_update_event_ext(event->hw.idx, 0);
3063 }
3064
3065 DEFINE_STATIC_CALL_NULL(intel_pmu_disable_event_ext, intel_pmu_disable_event_ext);
3066
intel_pmu_disable_event(struct perf_event * event)3067 static void intel_pmu_disable_event(struct perf_event *event)
3068 {
3069 struct hw_perf_event *hwc = &event->hw;
3070 int idx = hwc->idx;
3071
3072 switch (idx) {
3073 case 0 ... INTEL_PMC_IDX_FIXED - 1:
3074 intel_clear_masks(event, idx);
3075 static_call_cond(intel_pmu_disable_event_ext)(event);
3076 x86_pmu_disable_event(event);
3077 break;
3078 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
3079 static_call_cond(intel_pmu_disable_event_ext)(event);
3080 fallthrough;
3081 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
3082 intel_pmu_disable_fixed(event);
3083 break;
3084 case INTEL_PMC_IDX_FIXED_BTS:
3085 intel_pmu_disable_bts();
3086 intel_pmu_drain_bts_buffer();
3087 return;
3088 case INTEL_PMC_IDX_FIXED_VLBR:
3089 intel_clear_masks(event, idx);
3090 break;
3091 default:
3092 intel_clear_masks(event, idx);
3093 pr_warn("Failed to disable the event with invalid index %d\n",
3094 idx);
3095 return;
3096 }
3097
3098 /*
3099 * Needs to be called after x86_pmu_disable_event,
3100 * so we don't trigger the event without PEBS bit set.
3101 */
3102 if (unlikely(event->attr.precise_ip))
3103 static_call(x86_pmu_pebs_disable)(event);
3104 }
3105
intel_pmu_assign_event(struct perf_event * event,int idx)3106 static void intel_pmu_assign_event(struct perf_event *event, int idx)
3107 {
3108 if (is_pebs_pt(event))
3109 perf_report_aux_output_id(event, idx);
3110 }
3111
intel_pmu_needs_branch_stack(struct perf_event * event)3112 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event)
3113 {
3114 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK;
3115 }
3116
intel_pmu_del_event(struct perf_event * event)3117 static void intel_pmu_del_event(struct perf_event *event)
3118 {
3119 if (intel_pmu_needs_branch_stack(event))
3120 intel_pmu_lbr_del(event);
3121 if (event->attr.precise_ip)
3122 intel_pmu_pebs_del(event);
3123 if (is_pebs_counter_event_group(event) ||
3124 is_acr_event_group(event))
3125 this_cpu_ptr(&cpu_hw_events)->n_late_setup--;
3126 }
3127
icl_set_topdown_event_period(struct perf_event * event)3128 static int icl_set_topdown_event_period(struct perf_event *event)
3129 {
3130 struct hw_perf_event *hwc = &event->hw;
3131 s64 left = local64_read(&hwc->period_left);
3132
3133 /*
3134 * The values in PERF_METRICS MSR are derived from fixed counter 3.
3135 * Software should start both registers, PERF_METRICS and fixed
3136 * counter 3, from zero.
3137 * Clear PERF_METRICS and Fixed counter 3 in initialization.
3138 * After that, both MSRs will be cleared for each read.
3139 * Don't need to clear them again.
3140 */
3141 if (left == x86_pmu.max_period) {
3142 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0);
3143 wrmsrq(MSR_PERF_METRICS, 0);
3144 hwc->saved_slots = 0;
3145 hwc->saved_metric = 0;
3146 }
3147
3148 if ((hwc->saved_slots) && is_slots_event(event)) {
3149 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
3150 wrmsrq(MSR_PERF_METRICS, hwc->saved_metric);
3151 }
3152
3153 perf_event_update_userpage(event);
3154
3155 return 0;
3156 }
3157
3158 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period);
3159
icl_get_metrics_event_value(u64 metric,u64 slots,int idx)3160 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
3161 {
3162 u32 val;
3163
3164 /*
3165 * The metric is reported as an 8bit integer fraction
3166 * summing up to 0xff.
3167 * slots-in-metric = (Metric / 0xff) * slots
3168 */
3169 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
3170 return mul_u64_u32_div(slots, val, 0xff);
3171 }
3172
icl_get_topdown_value(struct perf_event * event,u64 slots,u64 metrics)3173 static u64 icl_get_topdown_value(struct perf_event *event,
3174 u64 slots, u64 metrics)
3175 {
3176 int idx = event->hw.idx;
3177 u64 delta;
3178
3179 if (is_metric_idx(idx))
3180 delta = icl_get_metrics_event_value(metrics, slots, idx);
3181 else
3182 delta = slots;
3183
3184 return delta;
3185 }
3186
__icl_update_topdown_event(struct perf_event * event,u64 slots,u64 metrics,u64 last_slots,u64 last_metrics)3187 static void __icl_update_topdown_event(struct perf_event *event,
3188 u64 slots, u64 metrics,
3189 u64 last_slots, u64 last_metrics)
3190 {
3191 u64 delta, last = 0;
3192
3193 delta = icl_get_topdown_value(event, slots, metrics);
3194 if (last_slots)
3195 last = icl_get_topdown_value(event, last_slots, last_metrics);
3196
3197 /*
3198 * The 8bit integer fraction of metric may be not accurate,
3199 * especially when the changes is very small.
3200 * For example, if only a few bad_spec happens, the fraction
3201 * may be reduced from 1 to 0. If so, the bad_spec event value
3202 * will be 0 which is definitely less than the last value.
3203 * Avoid update event->count for this case.
3204 */
3205 if (delta > last) {
3206 delta -= last;
3207 local64_add(delta, &event->count);
3208 }
3209 }
3210
update_saved_topdown_regs(struct perf_event * event,u64 slots,u64 metrics,int metric_end)3211 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
3212 u64 metrics, int metric_end)
3213 {
3214 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3215 struct perf_event *other;
3216 int idx;
3217
3218 event->hw.saved_slots = slots;
3219 event->hw.saved_metric = metrics;
3220
3221 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
3222 if (!is_topdown_idx(idx))
3223 continue;
3224 other = cpuc->events[idx];
3225 other->hw.saved_slots = slots;
3226 other->hw.saved_metric = metrics;
3227 }
3228 }
3229
3230 /*
3231 * Update all active Topdown events.
3232 *
3233 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
3234 * modify by a NMI. PMU has to be disabled before calling this function.
3235 */
3236
intel_update_topdown_event(struct perf_event * event,int metric_end,u64 * val)3237 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end, u64 *val)
3238 {
3239 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3240 struct perf_event *other;
3241 u64 slots, metrics;
3242 bool reset = true;
3243 int idx;
3244
3245 if (!val) {
3246 /* read Fixed counter 3 */
3247 slots = rdpmc(3 | INTEL_PMC_FIXED_RDPMC_BASE);
3248 if (!slots)
3249 return 0;
3250
3251 /* read PERF_METRICS */
3252 metrics = rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS);
3253 } else {
3254 slots = val[0];
3255 metrics = val[1];
3256 /*
3257 * Don't reset the PERF_METRICS and Fixed counter 3
3258 * for each PEBS record read. Utilize the RDPMC metrics
3259 * clear mode.
3260 */
3261 reset = false;
3262 }
3263
3264 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
3265 if (!is_topdown_idx(idx))
3266 continue;
3267 other = cpuc->events[idx];
3268 __icl_update_topdown_event(other, slots, metrics,
3269 event ? event->hw.saved_slots : 0,
3270 event ? event->hw.saved_metric : 0);
3271 }
3272
3273 /*
3274 * Check and update this event, which may have been cleared
3275 * in active_mask e.g. x86_pmu_stop()
3276 */
3277 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
3278 __icl_update_topdown_event(event, slots, metrics,
3279 event->hw.saved_slots,
3280 event->hw.saved_metric);
3281
3282 /*
3283 * In x86_pmu_stop(), the event is cleared in active_mask first,
3284 * then drain the delta, which indicates context switch for
3285 * counting.
3286 * Save metric and slots for context switch.
3287 * Don't need to reset the PERF_METRICS and Fixed counter 3.
3288 * Because the values will be restored in next schedule in.
3289 */
3290 update_saved_topdown_regs(event, slots, metrics, metric_end);
3291 reset = false;
3292 }
3293
3294 if (reset) {
3295 /* The fixed counter 3 has to be written before the PERF_METRICS. */
3296 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0);
3297 wrmsrq(MSR_PERF_METRICS, 0);
3298 if (event)
3299 update_saved_topdown_regs(event, 0, 0, metric_end);
3300 }
3301
3302 return slots;
3303 }
3304
icl_update_topdown_event(struct perf_event * event,u64 * val)3305 static u64 icl_update_topdown_event(struct perf_event *event, u64 *val)
3306 {
3307 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
3308 x86_pmu.num_topdown_events - 1,
3309 val);
3310 }
3311
3312 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update);
3313
intel_pmu_read_event(struct perf_event * event)3314 static void intel_pmu_read_event(struct perf_event *event)
3315 {
3316 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN) ||
3317 is_pebs_counter_event_group(event)) {
3318 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3319 bool pmu_enabled = cpuc->enabled;
3320
3321 /* Only need to call update_topdown_event() once for group read. */
3322 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ))
3323 return;
3324
3325 cpuc->enabled = 0;
3326 if (pmu_enabled)
3327 intel_pmu_disable_all();
3328
3329 /*
3330 * If the PEBS counters snapshotting is enabled,
3331 * the topdown event is available in PEBS records.
3332 */
3333 if (is_topdown_count(event) && !is_pebs_counter_event_group(event))
3334 static_call(intel_pmu_update_topdown_event)(event, NULL);
3335 else
3336 intel_pmu_drain_pebs_buffer();
3337
3338 cpuc->enabled = pmu_enabled;
3339 if (pmu_enabled)
3340 intel_pmu_enable_all(0);
3341
3342 return;
3343 }
3344
3345 x86_perf_event_update(event);
3346 }
3347
intel_pmu_enable_fixed(struct perf_event * event)3348 static void intel_pmu_enable_fixed(struct perf_event *event)
3349 {
3350 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3351 struct hw_perf_event *hwc = &event->hw;
3352 int idx = hwc->idx;
3353 u64 bits = 0;
3354
3355 if (is_topdown_idx(idx)) {
3356 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3357 /*
3358 * When there are other active TopDown events,
3359 * don't enable the fixed counter 3 again.
3360 */
3361 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
3362 return;
3363
3364 idx = INTEL_PMC_IDX_FIXED_SLOTS;
3365
3366 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR)
3367 bits |= INTEL_FIXED_3_METRICS_CLEAR;
3368 }
3369
3370 intel_set_masks(event, idx);
3371
3372 /*
3373 * Enable IRQ generation (0x8), if not PEBS or self-reloaded
3374 * ACR event, and enable ring-3 counting (0x2) and ring-0
3375 * counting (0x1) if requested:
3376 */
3377 if (!event->attr.precise_ip && !is_acr_self_reload_event(event))
3378 bits |= INTEL_FIXED_0_ENABLE_PMI;
3379 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
3380 bits |= INTEL_FIXED_0_USER;
3381 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
3382 bits |= INTEL_FIXED_0_KERNEL;
3383 if (hwc->config & ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE)
3384 bits |= INTEL_FIXED_0_RDPMC_USER_DISABLE;
3385
3386 /*
3387 * ANY bit is supported in v3 and up
3388 */
3389 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
3390 bits |= INTEL_FIXED_0_ANYTHREAD;
3391
3392 idx -= INTEL_PMC_IDX_FIXED;
3393 bits = intel_fixed_bits_by_idx(idx, bits);
3394 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip)
3395 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
3396
3397 cpuc->fixed_ctrl_val &= ~intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK);
3398 cpuc->fixed_ctrl_val |= bits;
3399 }
3400
intel_pmu_config_acr(int idx,u64 mask,u32 reload)3401 static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
3402 {
3403 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3404 int msr_b, msr_c;
3405 int msr_offset;
3406
3407 if (!mask && !cpuc->acr_cfg_b[idx])
3408 return;
3409
3410 if (idx < INTEL_PMC_IDX_FIXED) {
3411 msr_b = MSR_IA32_PMC_V6_GP0_CFG_B;
3412 msr_c = MSR_IA32_PMC_V6_GP0_CFG_C;
3413 msr_offset = x86_pmu.addr_offset(idx, false);
3414 } else {
3415 msr_b = MSR_IA32_PMC_V6_FX0_CFG_B;
3416 msr_c = MSR_IA32_PMC_V6_FX0_CFG_C;
3417 msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
3418 }
3419
3420 if (cpuc->acr_cfg_b[idx] != mask) {
3421 wrmsrq(msr_b + msr_offset, mask);
3422 cpuc->acr_cfg_b[idx] = mask;
3423 }
3424 /* Only update CFG_C reload when ACR is actively enabled (mask != 0) */
3425 if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) != reload)) {
3426 wrmsrq(msr_c + msr_offset, reload);
3427 cpuc->cfg_c_val[idx] = reload;
3428 }
3429 }
3430
intel_pmu_enable_acr(struct perf_event * event)3431 static void intel_pmu_enable_acr(struct perf_event *event)
3432 {
3433 struct hw_perf_event *hwc = &event->hw;
3434
3435 if (!is_acr_event_group(event) || !event->attr.config2) {
3436 /*
3437 * The disable doesn't clear the ACR CFG register.
3438 * Check and clear the ACR CFG register.
3439 */
3440 intel_pmu_config_acr(hwc->idx, 0, 0);
3441 return;
3442 }
3443
3444 intel_pmu_config_acr(hwc->idx, hwc->config1, -hwc->sample_period);
3445 }
3446
3447 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
3448
intel_pmu_enable_event_ext(struct perf_event * event)3449 static void intel_pmu_enable_event_ext(struct perf_event *event)
3450 {
3451 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3452 struct hw_perf_event *hwc = &event->hw;
3453 u64 ext = 0;
3454
3455 if (is_acr_event_group(event))
3456 ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD;
3457
3458 if (event->attr.precise_ip) {
3459 u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event);
3460 struct arch_pebs_cap cap = hybrid(cpuc->pmu, arch_pebs_cap);
3461 union arch_pebs_index old, new;
3462
3463 ext |= ARCH_PEBS_EN;
3464 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD)
3465 ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD;
3466
3467 if (pebs_data_cfg && cap.caps) {
3468 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
3469 ext |= ARCH_PEBS_AUX & cap.caps;
3470
3471 if (pebs_data_cfg & PEBS_DATACFG_GP)
3472 ext |= ARCH_PEBS_GPR & cap.caps;
3473
3474 if (pebs_data_cfg & PEBS_DATACFG_XMMS)
3475 ext |= ARCH_PEBS_VECR_XMM & cap.caps;
3476
3477 if (pebs_data_cfg & PEBS_DATACFG_LBRS)
3478 ext |= ARCH_PEBS_LBR & cap.caps;
3479
3480 if (pebs_data_cfg &
3481 (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT))
3482 ext |= ARCH_PEBS_CNTR_GP & cap.caps;
3483
3484 if (pebs_data_cfg &
3485 (PEBS_DATACFG_FIX_MASK << PEBS_DATACFG_FIX_SHIFT))
3486 ext |= ARCH_PEBS_CNTR_FIXED & cap.caps;
3487
3488 if (pebs_data_cfg & PEBS_DATACFG_METRICS)
3489 ext |= ARCH_PEBS_CNTR_METRICS & cap.caps;
3490 }
3491
3492 if (cpuc->n_pebs == cpuc->n_large_pebs)
3493 new.thresh = ARCH_PEBS_THRESH_MULTI;
3494 else
3495 new.thresh = ARCH_PEBS_THRESH_SINGLE;
3496
3497 rdmsrq(MSR_IA32_PEBS_INDEX, old.whole);
3498 if (new.thresh != old.thresh || !old.en) {
3499 if (old.thresh == ARCH_PEBS_THRESH_MULTI && old.wr > 0) {
3500 /*
3501 * Large PEBS was enabled.
3502 * Drain PEBS buffer before applying the single PEBS.
3503 */
3504 intel_pmu_drain_pebs_buffer();
3505 } else {
3506 new.wr = 0;
3507 new.full = 0;
3508 new.en = 1;
3509 wrmsrq(MSR_IA32_PEBS_INDEX, new.whole);
3510 }
3511 }
3512 }
3513
3514 if (is_pebs_counter_event_group(event))
3515 ext |= ARCH_PEBS_CNTR_ALLOW;
3516
3517 if (cpuc->cfg_c_val[hwc->idx] != ext)
3518 __intel_pmu_update_event_ext(hwc->idx, ext);
3519 }
3520
intel_pmu_update_rdpmc_user_disable(struct perf_event * event)3521 static void intel_pmu_update_rdpmc_user_disable(struct perf_event *event)
3522 {
3523 if (!x86_pmu_has_rdpmc_user_disable(event->pmu))
3524 return;
3525
3526 /*
3527 * Counter scope's user-space rdpmc is disabled by default
3528 * except two cases.
3529 * a. rdpmc = 2 (user space rdpmc enabled unconditionally)
3530 * b. rdpmc = 1 and the event is not a system-wide event.
3531 * The count of non-system-wide events would be cleared when
3532 * context switches, so no count data is leaked.
3533 */
3534 if (x86_pmu.attr_rdpmc == X86_USER_RDPMC_ALWAYS_ENABLE ||
3535 (x86_pmu.attr_rdpmc == X86_USER_RDPMC_CONDITIONAL_ENABLE &&
3536 (event->attach_state & PERF_ATTACH_TASK)))
3537 event->hw.config &= ~ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
3538 else
3539 event->hw.config |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
3540 }
3541
3542 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_event_ext, intel_pmu_enable_event_ext);
3543
intel_pmu_enable_event(struct perf_event * event)3544 static void intel_pmu_enable_event(struct perf_event *event)
3545 {
3546 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE;
3547 struct hw_perf_event *hwc = &event->hw;
3548 int idx = hwc->idx;
3549
3550 if (unlikely(event->attr.precise_ip))
3551 static_call(x86_pmu_pebs_enable)(event);
3552
3553 switch (idx) {
3554 case 0 ... INTEL_PMC_IDX_FIXED - 1:
3555 if (branch_sample_counters(event))
3556 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR;
3557 intel_set_masks(event, idx);
3558 static_call_cond(intel_pmu_enable_acr_event)(event);
3559 static_call_cond(intel_pmu_enable_event_ext)(event);
3560 /*
3561 * For self-reloaded ACR event, don't enable PMI since
3562 * HW won't set overflow bit in GLOBAL_STATUS. Otherwise,
3563 * the PMI would be recognized as a suspicious NMI.
3564 */
3565 if (is_acr_self_reload_event(event))
3566 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
3567 else if (!event->attr.precise_ip)
3568 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
3569 __x86_pmu_enable_event(hwc, enable_mask);
3570 break;
3571 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
3572 static_call_cond(intel_pmu_enable_acr_event)(event);
3573 static_call_cond(intel_pmu_enable_event_ext)(event);
3574 fallthrough;
3575 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
3576 intel_pmu_enable_fixed(event);
3577 break;
3578 case INTEL_PMC_IDX_FIXED_BTS:
3579 if (!__this_cpu_read(cpu_hw_events.enabled))
3580 return;
3581 intel_pmu_enable_bts(hwc->config);
3582 break;
3583 case INTEL_PMC_IDX_FIXED_VLBR:
3584 intel_set_masks(event, idx);
3585 break;
3586 default:
3587 pr_warn("Failed to enable the event with invalid index %d\n",
3588 idx);
3589 }
3590 }
3591
intel_pmu_acr_late_setup(struct cpu_hw_events * cpuc)3592 static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc)
3593 {
3594 struct perf_event *event, *leader;
3595 int i, j, k, bit, idx;
3596
3597 /*
3598 * FIXME: ACR mask parsing relies on cpuc->event_list[] (active events only).
3599 * Disabling an ACR event causes bit-shifting errors in the acr_mask of
3600 * remaining group members. As ACR sampling requires all events to be active,
3601 * this limitation is acceptable for now. Revisit if independent event toggling
3602 * is required.
3603 */
3604 for (i = 0; i < cpuc->n_events; i++) {
3605 leader = cpuc->event_list[i];
3606 if (!is_acr_event_group(leader))
3607 continue;
3608
3609 /* Find the last event of the ACR group. */
3610 for (j = i; j < cpuc->n_events; j++) {
3611 event = cpuc->event_list[j];
3612 if (event->group_leader != leader->group_leader)
3613 break;
3614 }
3615
3616 /*
3617 * Translate the user-space ACR mask (attr.config2) into the physical
3618 * counter bitmask (hw.config1) for each ACR event in the group.
3619 * NOTE: ACR event contiguity is guaranteed by intel_pmu_hw_config().
3620 */
3621 for (k = i; k < j; k++) {
3622 event = cpuc->event_list[k];
3623 event->hw.config1 = 0;
3624 for_each_set_bit(bit, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) {
3625 idx = i + bit;
3626 /* Event index of ACR group must locate in [i, j). */
3627 if (idx >= j || !is_acr_event_group(cpuc->event_list[idx]))
3628 continue;
3629 __set_bit(cpuc->assign[idx], (unsigned long *)&event->hw.config1);
3630 }
3631 }
3632 i = j - 1;
3633 }
3634 }
3635
intel_pmu_late_setup(void)3636 void intel_pmu_late_setup(void)
3637 {
3638 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3639
3640 if (!cpuc->n_late_setup)
3641 return;
3642
3643 intel_pmu_pebs_late_setup(cpuc);
3644 intel_pmu_acr_late_setup(cpuc);
3645 }
3646
intel_pmu_add_event(struct perf_event * event)3647 static void intel_pmu_add_event(struct perf_event *event)
3648 {
3649 if (event->attr.precise_ip)
3650 intel_pmu_pebs_add(event);
3651 if (intel_pmu_needs_branch_stack(event))
3652 intel_pmu_lbr_add(event);
3653 if (is_pebs_counter_event_group(event) ||
3654 is_acr_event_group(event))
3655 this_cpu_ptr(&cpu_hw_events)->n_late_setup++;
3656 }
3657
3658 /*
3659 * Save and restart an expired event. Called by NMI contexts,
3660 * so it has to be careful about preempting normal event ops:
3661 */
intel_pmu_save_and_restart(struct perf_event * event)3662 int intel_pmu_save_and_restart(struct perf_event *event)
3663 {
3664 static_call(x86_pmu_update)(event);
3665 /*
3666 * For a checkpointed counter always reset back to 0. This
3667 * avoids a situation where the counter overflows, aborts the
3668 * transaction and is then set back to shortly before the
3669 * overflow, and overflows and aborts again.
3670 */
3671 if (unlikely(event_is_checkpointed(event))) {
3672 /* No race with NMIs because the counter should not be armed */
3673 wrmsrq(event->hw.event_base, 0);
3674 local64_set(&event->hw.prev_count, 0);
3675 }
3676 return static_call(x86_pmu_set_period)(event);
3677 }
3678
intel_pmu_set_period(struct perf_event * event)3679 static int intel_pmu_set_period(struct perf_event *event)
3680 {
3681 if (unlikely(is_topdown_count(event)))
3682 return static_call(intel_pmu_set_topdown_event_period)(event);
3683
3684 return x86_perf_event_set_period(event);
3685 }
3686
intel_pmu_update(struct perf_event * event)3687 static u64 intel_pmu_update(struct perf_event *event)
3688 {
3689 if (unlikely(is_topdown_count(event)))
3690 return static_call(intel_pmu_update_topdown_event)(event, NULL);
3691
3692 return x86_perf_event_update(event);
3693 }
3694
intel_pmu_reset(void)3695 static void intel_pmu_reset(void)
3696 {
3697 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
3698 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3699 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask);
3700 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);
3701 unsigned long flags;
3702 int idx;
3703
3704 if (!*(u64 *)cntr_mask)
3705 return;
3706
3707 local_irq_save(flags);
3708
3709 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
3710
3711 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) {
3712 wrmsrq_safe(x86_pmu_config_addr(idx), 0ull);
3713 wrmsrq_safe(x86_pmu_event_addr(idx), 0ull);
3714 }
3715 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) {
3716 wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull);
3717 }
3718
3719 if (ds)
3720 ds->bts_index = ds->bts_buffer_base;
3721
3722 /* Ack all overflows and disable fixed counters */
3723 if (x86_pmu.version >= 2) {
3724 intel_pmu_ack_status(intel_pmu_get_status());
3725 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0);
3726 }
3727
3728 /* Reset LBRs and LBR freezing */
3729 if (x86_pmu.lbr_nr) {
3730 update_debugctlmsr(get_debugctlmsr() &
3731 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
3732 }
3733
3734 local_irq_restore(flags);
3735 }
3736
3737 /*
3738 * We may be running with guest PEBS events created by KVM, and the
3739 * PEBS records are logged into the guest's DS and invisible to host.
3740 *
3741 * In the case of guest PEBS overflow, we only trigger a fake event
3742 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM.
3743 * The guest will then vm-entry and check the guest DS area to read
3744 * the guest PEBS records.
3745 *
3746 * The contents and other behavior of the guest event do not matter.
3747 */
x86_pmu_handle_guest_pebs(struct pt_regs * regs,struct perf_sample_data * data)3748 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs,
3749 struct perf_sample_data *data)
3750 {
3751 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3752 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
3753 struct perf_event *event = NULL;
3754 int bit;
3755
3756 if (!unlikely(perf_guest_state()))
3757 return;
3758
3759 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active ||
3760 !guest_pebs_idxs)
3761 return;
3762
3763 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) {
3764 event = cpuc->events[bit];
3765 if (!event->attr.precise_ip)
3766 continue;
3767
3768 perf_sample_data_init(data, 0, event->hw.last_period);
3769 perf_event_overflow(event, data, regs);
3770
3771 /* Inject one fake event is enough. */
3772 break;
3773 }
3774 }
3775
handle_pmi_common(struct pt_regs * regs,u64 status)3776 static int handle_pmi_common(struct pt_regs *regs, u64 status)
3777 {
3778 struct perf_sample_data data;
3779 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3780 int bit;
3781 int handled = 0;
3782
3783 inc_perf_irq_stat();
3784
3785 /*
3786 * Ignore a range of extra bits in status that do not indicate
3787 * overflow by themselves.
3788 */
3789 status &= ~(GLOBAL_STATUS_COND_CHG |
3790 GLOBAL_STATUS_ASIF |
3791 GLOBAL_STATUS_LBRS_FROZEN);
3792 if (!status)
3793 return 0;
3794 /*
3795 * In case multiple PEBS events are sampled at the same time,
3796 * it is possible to have GLOBAL_STATUS bit 62 set indicating
3797 * PEBS buffer overflow and also seeing at most 3 PEBS counters
3798 * having their bits set in the status register. This is a sign
3799 * that there was at least one PEBS record pending at the time
3800 * of the PMU interrupt. PEBS counters must only be processed
3801 * via the drain_pebs() calls and not via the regular sample
3802 * processing loop coming after that the function, otherwise
3803 * phony regular samples may be generated in the sampling buffer
3804 * not marked with the EXACT tag. Another possibility is to have
3805 * one PEBS event and at least one non-PEBS event which overflows
3806 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
3807 * not be set, yet the overflow status bit for the PEBS counter will
3808 * be on Skylake.
3809 *
3810 * To avoid this problem, we systematically ignore the PEBS-enabled
3811 * counters from the GLOBAL_STATUS mask and we always process PEBS
3812 * events via drain_pebs().
3813 */
3814 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
3815
3816 /*
3817 * PEBS overflow sets bit 62 in the global status register
3818 */
3819 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
3820 u64 pebs_enabled = cpuc->pebs_enabled;
3821
3822 handled++;
3823 x86_pmu_handle_guest_pebs(regs, &data);
3824 static_call(x86_pmu_drain_pebs)(regs, &data);
3825
3826 /*
3827 * PMI throttle may be triggered, which stops the PEBS event.
3828 * Although cpuc->pebs_enabled is updated accordingly, the
3829 * MSR_IA32_PEBS_ENABLE is not updated. Because the
3830 * cpuc->enabled has been forced to 0 in PMI.
3831 * Update the MSR if pebs_enabled is changed.
3832 */
3833 if (pebs_enabled != cpuc->pebs_enabled)
3834 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
3835
3836 /*
3837 * Above PEBS handler (PEBS counters snapshotting) has updated fixed
3838 * counter 3 and perf metrics counts if they are in counter group,
3839 * unnecessary to update again.
3840 */
3841 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&
3842 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))
3843 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
3844 }
3845
3846 /*
3847 * Arch PEBS sets bit 54 in the global status register
3848 */
3849 if (__test_and_clear_bit(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT,
3850 (unsigned long *)&status)) {
3851 handled++;
3852 static_call(x86_pmu_drain_pebs)(regs, &data);
3853
3854 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&
3855 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))
3856 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
3857 }
3858
3859 /*
3860 * Intel PT
3861 */
3862 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
3863 handled++;
3864 if (!perf_guest_handle_intel_pt_intr())
3865 intel_pt_interrupt();
3866 }
3867
3868 /*
3869 * Intel Perf metrics
3870 */
3871 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
3872 handled++;
3873 static_call(intel_pmu_update_topdown_event)(NULL, NULL);
3874 }
3875
3876 status &= hybrid(cpuc->pmu, intel_ctrl);
3877
3878 /*
3879 * Checkpointed counters can lead to 'spurious' PMIs because the
3880 * rollback caused by the PMI will have cleared the overflow status
3881 * bit. Therefore always force probe these counters.
3882 */
3883 status |= cpuc->intel_cp_status;
3884
3885 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
3886 struct perf_event *event = cpuc->events[bit];
3887 u64 last_period;
3888
3889 handled++;
3890
3891 if (!test_bit(bit, cpuc->active_mask))
3892 continue;
3893 /* Event may have already been cleared: */
3894 if (!event)
3895 continue;
3896
3897 /*
3898 * There may be unprocessed PEBS records in the PEBS buffer,
3899 * which still stores the previous values.
3900 * Process those records first before handling the latest value.
3901 * For example,
3902 * A is a regular counter
3903 * B is a PEBS event which reads A
3904 * C is a PEBS event
3905 *
3906 * The following can happen:
3907 * B-assist A=1
3908 * C A=2
3909 * B-assist A=3
3910 * A-overflow-PMI A=4
3911 * C-assist-PMI (PEBS buffer) A=5
3912 *
3913 * The PEBS buffer has to be drained before handling the A-PMI
3914 */
3915 if (is_pebs_counter_event_group(event))
3916 static_call(x86_pmu_drain_pebs)(regs, &data);
3917
3918 last_period = event->hw.last_period;
3919
3920 if (!intel_pmu_save_and_restart(event))
3921 continue;
3922
3923 perf_sample_data_init(&data, 0, last_period);
3924
3925 if (has_branch_stack(event))
3926 intel_pmu_lbr_save_brstack(&data, cpuc, event);
3927
3928 perf_event_overflow(event, &data, regs);
3929 }
3930
3931 return handled;
3932 }
3933
3934 /*
3935 * This handler is triggered by the local APIC, so the APIC IRQ handling
3936 * rules apply:
3937 */
intel_pmu_handle_irq(struct pt_regs * regs)3938 static int intel_pmu_handle_irq(struct pt_regs *regs)
3939 {
3940 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3941 bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
3942 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
3943 int loops;
3944 u64 status;
3945 int handled;
3946 int pmu_enabled;
3947
3948 /*
3949 * Save the PMU state.
3950 * It needs to be restored when leaving the handler.
3951 */
3952 pmu_enabled = cpuc->enabled;
3953 /*
3954 * In general, the early ACK is only applied for old platforms.
3955 * For the big core starts from Haswell, the late ACK should be
3956 * applied.
3957 * For the small core after Tremont, we have to do the ACK right
3958 * before re-enabling counters, which is in the middle of the
3959 * NMI handler.
3960 */
3961 if (!late_ack && !mid_ack)
3962 apic_write(APIC_LVTPC, APIC_DM_NMI);
3963 intel_bts_disable_local();
3964 cpuc->enabled = 0;
3965 __intel_pmu_disable_all(true);
3966 handled = intel_pmu_drain_bts_buffer();
3967 handled += intel_bts_interrupt();
3968 status = intel_pmu_get_status();
3969 if (!status)
3970 goto done;
3971
3972 loops = 0;
3973 again:
3974 intel_pmu_lbr_read();
3975 intel_pmu_ack_status(status);
3976 if (++loops > 100) {
3977 static bool warned;
3978
3979 if (!warned) {
3980 WARN(1, "perfevents: irq loop stuck!\n");
3981 perf_event_print_debug();
3982 warned = true;
3983 }
3984 intel_pmu_reset();
3985 goto done;
3986 }
3987
3988 handled += handle_pmi_common(regs, status);
3989
3990 /*
3991 * Repeat if there is more work to be done:
3992 */
3993 status = intel_pmu_get_status();
3994 if (status)
3995 goto again;
3996
3997 done:
3998 if (mid_ack)
3999 apic_write(APIC_LVTPC, APIC_DM_NMI);
4000 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
4001 cpuc->enabled = pmu_enabled;
4002 if (pmu_enabled)
4003 __intel_pmu_enable_all(0, true);
4004 intel_bts_enable_local();
4005
4006 /*
4007 * Only unmask the NMI after the overflow counters
4008 * have been reset. This avoids spurious NMIs on
4009 * Haswell CPUs.
4010 */
4011 if (late_ack)
4012 apic_write(APIC_LVTPC, APIC_DM_NMI);
4013 return handled;
4014 }
4015
4016 static struct event_constraint *
intel_bts_constraints(struct perf_event * event)4017 intel_bts_constraints(struct perf_event *event)
4018 {
4019 if (unlikely(intel_pmu_has_bts(event)))
4020 return &bts_constraint;
4021
4022 return NULL;
4023 }
4024
4025 /*
4026 * Note: matches a fake event, like Fixed2.
4027 */
4028 static struct event_constraint *
intel_vlbr_constraints(struct perf_event * event)4029 intel_vlbr_constraints(struct perf_event *event)
4030 {
4031 struct event_constraint *c = &vlbr_constraint;
4032
4033 if (unlikely(constraint_match(c, event->hw.config))) {
4034 event->hw.flags |= c->flags;
4035 return c;
4036 }
4037
4038 return NULL;
4039 }
4040
intel_alt_er(struct cpu_hw_events * cpuc,int idx,u64 config)4041 static int intel_alt_er(struct cpu_hw_events *cpuc,
4042 int idx, u64 config)
4043 {
4044 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
4045 int alt_idx = idx;
4046
4047 switch (idx) {
4048 case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1:
4049 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
4050 return idx;
4051 if (++alt_idx > EXTRA_REG_RSP_1)
4052 alt_idx = EXTRA_REG_RSP_0;
4053 if (config & ~extra_regs[alt_idx].valid_mask)
4054 return idx;
4055 break;
4056
4057 case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3:
4058 if (!(x86_pmu.flags & PMU_FL_HAS_OMR))
4059 return idx;
4060 if (++alt_idx > EXTRA_REG_OMR_3)
4061 alt_idx = EXTRA_REG_OMR_0;
4062 /*
4063 * Subtracting EXTRA_REG_OMR_0 ensures to get correct
4064 * OMR extra_reg entries which start from 0.
4065 */
4066 if (config & ~extra_regs[alt_idx - EXTRA_REG_OMR_0].valid_mask)
4067 return idx;
4068 break;
4069
4070 default:
4071 break;
4072 }
4073
4074 return alt_idx;
4075 }
4076
intel_fixup_er(struct perf_event * event,int idx)4077 static void intel_fixup_er(struct perf_event *event, int idx)
4078 {
4079 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
4080 int er_idx;
4081
4082 event->hw.extra_reg.idx = idx;
4083 switch (idx) {
4084 case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1:
4085 er_idx = idx - EXTRA_REG_RSP_0;
4086 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
4087 event->hw.config |= extra_regs[er_idx].event;
4088 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0 + er_idx;
4089 break;
4090
4091 case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3:
4092 er_idx = idx - EXTRA_REG_OMR_0;
4093 event->hw.config &= ~ARCH_PERFMON_EVENTSEL_UMASK;
4094 event->hw.config |= 1ULL << (8 + er_idx);
4095 event->hw.extra_reg.reg = MSR_OMR_0 + er_idx;
4096 break;
4097
4098 default:
4099 pr_warn("The extra reg idx %d is not supported.\n", idx);
4100 }
4101 }
4102
4103 /*
4104 * manage allocation of shared extra msr for certain events
4105 *
4106 * sharing can be:
4107 * per-cpu: to be shared between the various events on a single PMU
4108 * per-core: per-cpu + shared by HT threads
4109 */
4110 static struct event_constraint *
__intel_shared_reg_get_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct hw_perf_event_extra * reg)4111 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
4112 struct perf_event *event,
4113 struct hw_perf_event_extra *reg)
4114 {
4115 struct event_constraint *c = &emptyconstraint;
4116 struct er_account *era;
4117 unsigned long flags;
4118 int idx = reg->idx;
4119
4120 /*
4121 * reg->alloc can be set due to existing state, so for fake cpuc we
4122 * need to ignore this, otherwise we might fail to allocate proper fake
4123 * state for this extra reg constraint. Also see the comment below.
4124 */
4125 if (reg->alloc && !cpuc->is_fake)
4126 return NULL; /* call x86_get_event_constraint() */
4127
4128 again:
4129 era = &cpuc->shared_regs->regs[idx];
4130 /*
4131 * we use spin_lock_irqsave() to avoid lockdep issues when
4132 * passing a fake cpuc
4133 */
4134 raw_spin_lock_irqsave(&era->lock, flags);
4135
4136 if (!atomic_read(&era->ref) || era->config == reg->config) {
4137
4138 /*
4139 * If its a fake cpuc -- as per validate_{group,event}() we
4140 * shouldn't touch event state and we can avoid doing so
4141 * since both will only call get_event_constraints() once
4142 * on each event, this avoids the need for reg->alloc.
4143 *
4144 * Not doing the ER fixup will only result in era->reg being
4145 * wrong, but since we won't actually try and program hardware
4146 * this isn't a problem either.
4147 */
4148 if (!cpuc->is_fake) {
4149 if (idx != reg->idx)
4150 intel_fixup_er(event, idx);
4151
4152 /*
4153 * x86_schedule_events() can call get_event_constraints()
4154 * multiple times on events in the case of incremental
4155 * scheduling(). reg->alloc ensures we only do the ER
4156 * allocation once.
4157 */
4158 reg->alloc = 1;
4159 }
4160
4161 /* lock in msr value */
4162 era->config = reg->config;
4163 era->reg = reg->reg;
4164
4165 /* one more user */
4166 atomic_inc(&era->ref);
4167
4168 /*
4169 * need to call x86_get_event_constraint()
4170 * to check if associated event has constraints
4171 */
4172 c = NULL;
4173 } else {
4174 idx = intel_alt_er(cpuc, idx, reg->config);
4175 if (idx != reg->idx) {
4176 raw_spin_unlock_irqrestore(&era->lock, flags);
4177 goto again;
4178 }
4179 }
4180 raw_spin_unlock_irqrestore(&era->lock, flags);
4181
4182 return c;
4183 }
4184
4185 static void
__intel_shared_reg_put_constraints(struct cpu_hw_events * cpuc,struct hw_perf_event_extra * reg)4186 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
4187 struct hw_perf_event_extra *reg)
4188 {
4189 struct er_account *era;
4190
4191 /*
4192 * Only put constraint if extra reg was actually allocated. Also takes
4193 * care of event which do not use an extra shared reg.
4194 *
4195 * Also, if this is a fake cpuc we shouldn't touch any event state
4196 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
4197 * either since it'll be thrown out.
4198 */
4199 if (!reg->alloc || cpuc->is_fake)
4200 return;
4201
4202 era = &cpuc->shared_regs->regs[reg->idx];
4203
4204 /* one fewer user */
4205 atomic_dec(&era->ref);
4206
4207 /* allocate again next time */
4208 reg->alloc = 0;
4209 }
4210
4211 static struct event_constraint *
intel_shared_regs_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4212 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
4213 struct perf_event *event)
4214 {
4215 struct event_constraint *c = NULL, *d;
4216 struct hw_perf_event_extra *xreg, *breg;
4217
4218 xreg = &event->hw.extra_reg;
4219 if (xreg->idx != EXTRA_REG_NONE) {
4220 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
4221 if (c == &emptyconstraint)
4222 return c;
4223 }
4224 breg = &event->hw.branch_reg;
4225 if (breg->idx != EXTRA_REG_NONE) {
4226 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
4227 if (d == &emptyconstraint) {
4228 __intel_shared_reg_put_constraints(cpuc, xreg);
4229 c = d;
4230 }
4231 }
4232 return c;
4233 }
4234
4235 struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4236 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4237 struct perf_event *event)
4238 {
4239 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
4240 struct event_constraint *c;
4241
4242 if (event_constraints) {
4243 for_each_event_constraint(c, event_constraints) {
4244 if (constraint_match(c, event->hw.config)) {
4245 event->hw.flags |= c->flags;
4246 return c;
4247 }
4248 }
4249 }
4250
4251 return &hybrid_var(cpuc->pmu, unconstrained);
4252 }
4253
4254 static struct event_constraint *
__intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4255 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4256 struct perf_event *event)
4257 {
4258 struct event_constraint *c;
4259
4260 c = intel_vlbr_constraints(event);
4261 if (c)
4262 return c;
4263
4264 c = intel_bts_constraints(event);
4265 if (c)
4266 return c;
4267
4268 c = intel_shared_regs_constraints(cpuc, event);
4269 if (c)
4270 return c;
4271
4272 c = intel_pebs_constraints(event);
4273 if (c)
4274 return c;
4275
4276 return x86_get_event_constraints(cpuc, idx, event);
4277 }
4278
4279 static void
intel_start_scheduling(struct cpu_hw_events * cpuc)4280 intel_start_scheduling(struct cpu_hw_events *cpuc)
4281 {
4282 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4283 struct intel_excl_states *xl;
4284 int tid = cpuc->excl_thread_id;
4285
4286 /*
4287 * nothing needed if in group validation mode
4288 */
4289 if (cpuc->is_fake || !is_ht_workaround_enabled())
4290 return;
4291
4292 /*
4293 * no exclusion needed
4294 */
4295 if (WARN_ON_ONCE(!excl_cntrs))
4296 return;
4297
4298 xl = &excl_cntrs->states[tid];
4299
4300 xl->sched_started = true;
4301 /*
4302 * lock shared state until we are done scheduling
4303 * in stop_event_scheduling()
4304 * makes scheduling appear as a transaction
4305 */
4306 raw_spin_lock(&excl_cntrs->lock);
4307 }
4308
intel_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)4309 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
4310 {
4311 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4312 struct event_constraint *c = cpuc->event_constraint[idx];
4313 struct intel_excl_states *xl;
4314 int tid = cpuc->excl_thread_id;
4315
4316 if (cpuc->is_fake || !is_ht_workaround_enabled())
4317 return;
4318
4319 if (WARN_ON_ONCE(!excl_cntrs))
4320 return;
4321
4322 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
4323 return;
4324
4325 xl = &excl_cntrs->states[tid];
4326
4327 lockdep_assert_held(&excl_cntrs->lock);
4328
4329 if (c->flags & PERF_X86_EVENT_EXCL)
4330 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
4331 else
4332 xl->state[cntr] = INTEL_EXCL_SHARED;
4333 }
4334
4335 static void
intel_stop_scheduling(struct cpu_hw_events * cpuc)4336 intel_stop_scheduling(struct cpu_hw_events *cpuc)
4337 {
4338 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4339 struct intel_excl_states *xl;
4340 int tid = cpuc->excl_thread_id;
4341
4342 /*
4343 * nothing needed if in group validation mode
4344 */
4345 if (cpuc->is_fake || !is_ht_workaround_enabled())
4346 return;
4347 /*
4348 * no exclusion needed
4349 */
4350 if (WARN_ON_ONCE(!excl_cntrs))
4351 return;
4352
4353 xl = &excl_cntrs->states[tid];
4354
4355 xl->sched_started = false;
4356 /*
4357 * release shared state lock (acquired in intel_start_scheduling())
4358 */
4359 raw_spin_unlock(&excl_cntrs->lock);
4360 }
4361
4362 static struct event_constraint *
dyn_constraint(struct cpu_hw_events * cpuc,struct event_constraint * c,int idx)4363 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
4364 {
4365 WARN_ON_ONCE(!cpuc->constraint_list);
4366
4367 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
4368 struct event_constraint *cx;
4369
4370 /*
4371 * grab pre-allocated constraint entry
4372 */
4373 cx = &cpuc->constraint_list[idx];
4374
4375 /*
4376 * initialize dynamic constraint
4377 * with static constraint
4378 */
4379 *cx = *c;
4380
4381 /*
4382 * mark constraint as dynamic
4383 */
4384 cx->flags |= PERF_X86_EVENT_DYNAMIC;
4385 c = cx;
4386 }
4387
4388 return c;
4389 }
4390
4391 static struct event_constraint *
intel_get_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,int idx,struct event_constraint * c)4392 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
4393 int idx, struct event_constraint *c)
4394 {
4395 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4396 struct intel_excl_states *xlo;
4397 int tid = cpuc->excl_thread_id;
4398 int is_excl, i, w;
4399
4400 /*
4401 * validating a group does not require
4402 * enforcing cross-thread exclusion
4403 */
4404 if (cpuc->is_fake || !is_ht_workaround_enabled())
4405 return c;
4406
4407 /*
4408 * no exclusion needed
4409 */
4410 if (WARN_ON_ONCE(!excl_cntrs))
4411 return c;
4412
4413 /*
4414 * because we modify the constraint, we need
4415 * to make a copy. Static constraints come
4416 * from static const tables.
4417 *
4418 * only needed when constraint has not yet
4419 * been cloned (marked dynamic)
4420 */
4421 c = dyn_constraint(cpuc, c, idx);
4422
4423 /*
4424 * From here on, the constraint is dynamic.
4425 * Either it was just allocated above, or it
4426 * was allocated during a earlier invocation
4427 * of this function
4428 */
4429
4430 /*
4431 * state of sibling HT
4432 */
4433 xlo = &excl_cntrs->states[tid ^ 1];
4434
4435 /*
4436 * event requires exclusive counter access
4437 * across HT threads
4438 */
4439 is_excl = c->flags & PERF_X86_EVENT_EXCL;
4440 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
4441 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
4442 if (!cpuc->n_excl++)
4443 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
4444 }
4445
4446 /*
4447 * Modify static constraint with current dynamic
4448 * state of thread
4449 *
4450 * EXCLUSIVE: sibling counter measuring exclusive event
4451 * SHARED : sibling counter measuring non-exclusive event
4452 * UNUSED : sibling counter unused
4453 */
4454 w = c->weight;
4455 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
4456 /*
4457 * exclusive event in sibling counter
4458 * our corresponding counter cannot be used
4459 * regardless of our event
4460 */
4461 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
4462 __clear_bit(i, c->idxmsk);
4463 w--;
4464 continue;
4465 }
4466 /*
4467 * if measuring an exclusive event, sibling
4468 * measuring non-exclusive, then counter cannot
4469 * be used
4470 */
4471 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
4472 __clear_bit(i, c->idxmsk);
4473 w--;
4474 continue;
4475 }
4476 }
4477
4478 /*
4479 * if we return an empty mask, then switch
4480 * back to static empty constraint to avoid
4481 * the cost of freeing later on
4482 */
4483 if (!w)
4484 c = &emptyconstraint;
4485
4486 c->weight = w;
4487
4488 return c;
4489 }
4490
4491 static struct event_constraint *
intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4492 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4493 struct perf_event *event)
4494 {
4495 struct event_constraint *c1, *c2;
4496
4497 c1 = cpuc->event_constraint[idx];
4498
4499 /*
4500 * first time only
4501 * - static constraint: no change across incremental scheduling calls
4502 * - dynamic constraint: handled by intel_get_excl_constraints()
4503 */
4504 c2 = __intel_get_event_constraints(cpuc, idx, event);
4505 if (c1) {
4506 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
4507 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
4508 c1->weight = c2->weight;
4509 c2 = c1;
4510 }
4511
4512 if (cpuc->excl_cntrs)
4513 return intel_get_excl_constraints(cpuc, event, idx, c2);
4514
4515 if (event->hw.dyn_constraint != ~0ULL) {
4516 c2 = dyn_constraint(cpuc, c2, idx);
4517 c2->idxmsk64 &= event->hw.dyn_constraint;
4518 c2->weight = hweight64(c2->idxmsk64);
4519 }
4520
4521 return c2;
4522 }
4523
intel_put_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4524 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
4525 struct perf_event *event)
4526 {
4527 struct hw_perf_event *hwc = &event->hw;
4528 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4529 int tid = cpuc->excl_thread_id;
4530 struct intel_excl_states *xl;
4531
4532 /*
4533 * nothing needed if in group validation mode
4534 */
4535 if (cpuc->is_fake)
4536 return;
4537
4538 if (WARN_ON_ONCE(!excl_cntrs))
4539 return;
4540
4541 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
4542 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
4543 if (!--cpuc->n_excl)
4544 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
4545 }
4546
4547 /*
4548 * If event was actually assigned, then mark the counter state as
4549 * unused now.
4550 */
4551 if (hwc->idx >= 0) {
4552 xl = &excl_cntrs->states[tid];
4553
4554 /*
4555 * put_constraint may be called from x86_schedule_events()
4556 * which already has the lock held so here make locking
4557 * conditional.
4558 */
4559 if (!xl->sched_started)
4560 raw_spin_lock(&excl_cntrs->lock);
4561
4562 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
4563
4564 if (!xl->sched_started)
4565 raw_spin_unlock(&excl_cntrs->lock);
4566 }
4567 }
4568
4569 static void
intel_put_shared_regs_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4570 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
4571 struct perf_event *event)
4572 {
4573 struct hw_perf_event_extra *reg;
4574
4575 reg = &event->hw.extra_reg;
4576 if (reg->idx != EXTRA_REG_NONE)
4577 __intel_shared_reg_put_constraints(cpuc, reg);
4578
4579 reg = &event->hw.branch_reg;
4580 if (reg->idx != EXTRA_REG_NONE)
4581 __intel_shared_reg_put_constraints(cpuc, reg);
4582 }
4583
intel_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4584 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
4585 struct perf_event *event)
4586 {
4587 intel_put_shared_regs_event_constraints(cpuc, event);
4588
4589 /*
4590 * is PMU has exclusive counter restrictions, then
4591 * all events are subject to and must call the
4592 * put_excl_constraints() routine
4593 */
4594 if (cpuc->excl_cntrs)
4595 intel_put_excl_constraints(cpuc, event);
4596 }
4597
intel_pebs_aliases_core2(struct perf_event * event)4598 static void intel_pebs_aliases_core2(struct perf_event *event)
4599 {
4600 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4601 /*
4602 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4603 * (0x003c) so that we can use it with PEBS.
4604 *
4605 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4606 * PEBS capable. However we can use INST_RETIRED.ANY_P
4607 * (0x00c0), which is a PEBS capable event, to get the same
4608 * count.
4609 *
4610 * INST_RETIRED.ANY_P counts the number of cycles that retires
4611 * CNTMASK instructions. By setting CNTMASK to a value (16)
4612 * larger than the maximum number of instructions that can be
4613 * retired per cycle (4) and then inverting the condition, we
4614 * count all cycles that retire 16 or less instructions, which
4615 * is every cycle.
4616 *
4617 * Thereby we gain a PEBS capable cycle counter.
4618 */
4619 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
4620
4621 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4622 event->hw.config = alt_config;
4623 }
4624 }
4625
intel_pebs_aliases_snb(struct perf_event * event)4626 static void intel_pebs_aliases_snb(struct perf_event *event)
4627 {
4628 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4629 /*
4630 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4631 * (0x003c) so that we can use it with PEBS.
4632 *
4633 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4634 * PEBS capable. However we can use UOPS_RETIRED.ALL
4635 * (0x01c2), which is a PEBS capable event, to get the same
4636 * count.
4637 *
4638 * UOPS_RETIRED.ALL counts the number of cycles that retires
4639 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
4640 * larger than the maximum number of micro-ops that can be
4641 * retired per cycle (4) and then inverting the condition, we
4642 * count all cycles that retire 16 or less micro-ops, which
4643 * is every cycle.
4644 *
4645 * Thereby we gain a PEBS capable cycle counter.
4646 */
4647 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
4648
4649 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4650 event->hw.config = alt_config;
4651 }
4652 }
4653
intel_pebs_aliases_precdist(struct perf_event * event)4654 static void intel_pebs_aliases_precdist(struct perf_event *event)
4655 {
4656 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4657 /*
4658 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4659 * (0x003c) so that we can use it with PEBS.
4660 *
4661 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4662 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
4663 * (0x01c0), which is a PEBS capable event, to get the same
4664 * count.
4665 *
4666 * The PREC_DIST event has special support to minimize sample
4667 * shadowing effects. One drawback is that it can be
4668 * only programmed on counter 1, but that seems like an
4669 * acceptable trade off.
4670 */
4671 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
4672
4673 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4674 event->hw.config = alt_config;
4675 }
4676 }
4677
intel_pebs_aliases_ivb(struct perf_event * event)4678 static void intel_pebs_aliases_ivb(struct perf_event *event)
4679 {
4680 if (event->attr.precise_ip < 3)
4681 return intel_pebs_aliases_snb(event);
4682 return intel_pebs_aliases_precdist(event);
4683 }
4684
intel_pebs_aliases_skl(struct perf_event * event)4685 static void intel_pebs_aliases_skl(struct perf_event *event)
4686 {
4687 if (event->attr.precise_ip < 3)
4688 return intel_pebs_aliases_core2(event);
4689 return intel_pebs_aliases_precdist(event);
4690 }
4691
intel_pmu_large_pebs_flags(struct perf_event * event)4692 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
4693 {
4694 unsigned long flags = x86_pmu.large_pebs_flags;
4695
4696 if (event->attr.use_clockid)
4697 flags &= ~PERF_SAMPLE_TIME;
4698 if (!event->attr.exclude_kernel)
4699 flags &= ~PERF_SAMPLE_REGS_USER;
4700 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
4701 flags &= ~PERF_SAMPLE_REGS_USER;
4702 if (event->attr.sample_regs_intr & ~PEBS_GP_REGS)
4703 flags &= ~PERF_SAMPLE_REGS_INTR;
4704 return flags;
4705 }
4706
intel_pmu_bts_config(struct perf_event * event)4707 static int intel_pmu_bts_config(struct perf_event *event)
4708 {
4709 struct perf_event_attr *attr = &event->attr;
4710
4711 if (unlikely(intel_pmu_has_bts(event))) {
4712 /* BTS is not supported by this architecture. */
4713 if (!x86_pmu.bts_active)
4714 return -EOPNOTSUPP;
4715
4716 /* BTS is currently only allowed for user-mode. */
4717 if (!attr->exclude_kernel)
4718 return -EOPNOTSUPP;
4719
4720 /* BTS is not allowed for precise events. */
4721 if (attr->precise_ip)
4722 return -EOPNOTSUPP;
4723
4724 /* disallow bts if conflicting events are present */
4725 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
4726 return -EBUSY;
4727
4728 event->destroy = hw_perf_lbr_event_destroy;
4729 }
4730
4731 return 0;
4732 }
4733
core_pmu_hw_config(struct perf_event * event)4734 static int core_pmu_hw_config(struct perf_event *event)
4735 {
4736 int ret = x86_pmu_hw_config(event);
4737
4738 if (ret)
4739 return ret;
4740
4741 return intel_pmu_bts_config(event);
4742 }
4743
4744 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \
4745 ((x86_pmu.num_topdown_events - 1) << 8))
4746
is_available_metric_event(struct perf_event * event)4747 static bool is_available_metric_event(struct perf_event *event)
4748 {
4749 return is_metric_event(event) &&
4750 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
4751 }
4752
is_mem_loads_event(struct perf_event * event)4753 static inline bool is_mem_loads_event(struct perf_event *event)
4754 {
4755 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
4756 }
4757
is_mem_loads_aux_event(struct perf_event * event)4758 static inline bool is_mem_loads_aux_event(struct perf_event *event)
4759 {
4760 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
4761 }
4762
require_mem_loads_aux_event(struct perf_event * event)4763 static inline bool require_mem_loads_aux_event(struct perf_event *event)
4764 {
4765 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
4766 return false;
4767
4768 if (is_hybrid())
4769 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big;
4770
4771 return true;
4772 }
4773
intel_pmu_has_cap(struct perf_event * event,int idx)4774 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
4775 {
4776 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
4777
4778 return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
4779 }
4780
intel_pmu_freq_start_period(struct perf_event * event)4781 static u64 intel_pmu_freq_start_period(struct perf_event *event)
4782 {
4783 int type = event->attr.type;
4784 u64 config, factor;
4785 s64 start;
4786
4787 /*
4788 * The 127 is the lowest possible recommended SAV (sample after value)
4789 * for a 4000 freq (default freq), according to the event list JSON file.
4790 * Also, assume the workload is idle 50% time.
4791 */
4792 factor = 64 * 4000;
4793 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE)
4794 goto end;
4795
4796 /*
4797 * The estimation of the start period in the freq mode is
4798 * based on the below assumption.
4799 *
4800 * For a cycles or an instructions event, 1GHZ of the
4801 * underlying platform, 1 IPC. The workload is idle 50% time.
4802 * The start period = 1,000,000,000 * 1 / freq / 2.
4803 * = 500,000,000 / freq
4804 *
4805 * Usually, the branch-related events occur less than the
4806 * instructions event. According to the Intel event list JSON
4807 * file, the SAV (sample after value) of a branch-related event
4808 * is usually 1/4 of an instruction event.
4809 * The start period of branch-related events = 125,000,000 / freq.
4810 *
4811 * The cache-related events occurs even less. The SAV is usually
4812 * 1/20 of an instruction event.
4813 * The start period of cache-related events = 25,000,000 / freq.
4814 */
4815 config = event->attr.config & PERF_HW_EVENT_MASK;
4816 if (type == PERF_TYPE_HARDWARE) {
4817 switch (config) {
4818 case PERF_COUNT_HW_CPU_CYCLES:
4819 case PERF_COUNT_HW_INSTRUCTIONS:
4820 case PERF_COUNT_HW_BUS_CYCLES:
4821 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND:
4822 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND:
4823 case PERF_COUNT_HW_REF_CPU_CYCLES:
4824 factor = 500000000;
4825 break;
4826 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS:
4827 case PERF_COUNT_HW_BRANCH_MISSES:
4828 factor = 125000000;
4829 break;
4830 case PERF_COUNT_HW_CACHE_REFERENCES:
4831 case PERF_COUNT_HW_CACHE_MISSES:
4832 factor = 25000000;
4833 break;
4834 default:
4835 goto end;
4836 }
4837 }
4838
4839 if (type == PERF_TYPE_HW_CACHE)
4840 factor = 25000000;
4841 end:
4842 /*
4843 * Usually, a prime or a number with less factors (close to prime)
4844 * is chosen as an SAV, which makes it less likely that the sampling
4845 * period synchronizes with some periodic event in the workload.
4846 * Minus 1 to make it at least avoiding values near power of twos
4847 * for the default freq.
4848 */
4849 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1;
4850
4851 if (start > x86_pmu.max_period)
4852 start = x86_pmu.max_period;
4853
4854 if (x86_pmu.limit_period)
4855 x86_pmu.limit_period(event, &start);
4856
4857 return start;
4858 }
4859
intel_pmu_has_acr(struct pmu * pmu)4860 static inline bool intel_pmu_has_acr(struct pmu *pmu)
4861 {
4862 return !!hybrid(pmu, acr_cause_mask64);
4863 }
4864
intel_pmu_is_acr_group(struct perf_event * event)4865 static bool intel_pmu_is_acr_group(struct perf_event *event)
4866 {
4867 /* The group leader has the ACR flag set */
4868 if (is_acr_event_group(event))
4869 return true;
4870
4871 /* The acr_mask is set */
4872 if (event->attr.config2)
4873 return true;
4874
4875 return false;
4876 }
4877
intel_pmu_has_pebs_counter_group(struct pmu * pmu)4878 static inline bool intel_pmu_has_pebs_counter_group(struct pmu *pmu)
4879 {
4880 u64 caps;
4881
4882 if (x86_pmu.intel_cap.pebs_format >= 6 && x86_pmu.intel_cap.pebs_baseline)
4883 return true;
4884
4885 caps = hybrid(pmu, arch_pebs_cap).caps;
4886 if (x86_pmu.arch_pebs && (caps & ARCH_PEBS_CNTR_MASK))
4887 return true;
4888
4889 return false;
4890 }
4891
intel_pmu_set_acr_cntr_constr(struct perf_event * event,u64 * cause_mask,int * num)4892 static inline void intel_pmu_set_acr_cntr_constr(struct perf_event *event,
4893 u64 *cause_mask, int *num)
4894 {
4895 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cntr_mask64);
4896 *cause_mask |= event->attr.config2;
4897 *num += 1;
4898 }
4899
intel_pmu_set_acr_caused_constr(struct perf_event * event,int idx,u64 cause_mask)4900 static inline void intel_pmu_set_acr_caused_constr(struct perf_event *event,
4901 int idx, u64 cause_mask)
4902 {
4903 if (test_bit(idx, (unsigned long *)&cause_mask))
4904 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cause_mask64);
4905 }
4906
intel_set_branch_counter_constr(struct perf_event * event,int * num)4907 static inline int intel_set_branch_counter_constr(struct perf_event *event,
4908 int *num)
4909 {
4910 if (branch_sample_call_stack(event))
4911 return -EINVAL;
4912 if (branch_sample_counters(event)) {
4913 (*num)++;
4914 event->hw.dyn_constraint &= x86_pmu.lbr_counters;
4915 }
4916
4917 return 0;
4918 }
4919
intel_pmu_hw_config(struct perf_event * event)4920 static int intel_pmu_hw_config(struct perf_event *event)
4921 {
4922 int ret = x86_pmu_hw_config(event);
4923
4924 if (ret)
4925 return ret;
4926
4927 ret = intel_pmu_bts_config(event);
4928 if (ret)
4929 return ret;
4930
4931 if (event->attr.freq && event->attr.sample_freq) {
4932 event->hw.sample_period = intel_pmu_freq_start_period(event);
4933 event->hw.last_period = event->hw.sample_period;
4934 local64_set(&event->hw.period_left, event->hw.sample_period);
4935 }
4936
4937 if (event->attr.precise_ip) {
4938 struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap);
4939
4940 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
4941 return -EINVAL;
4942
4943 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
4944 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
4945 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) &&
4946 !has_aux_action(event)) {
4947 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
4948 event->attach_state |= PERF_ATTACH_SCHED_CB;
4949 }
4950 }
4951 if (x86_pmu.pebs_aliases)
4952 x86_pmu.pebs_aliases(event);
4953
4954 if (x86_pmu.arch_pebs) {
4955 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) &
4956 ~GLOBAL_CTRL_EN_PERF_METRICS;
4957 u64 pebs_mask = event->attr.precise_ip >= 3 ?
4958 pebs_cap.pdists : pebs_cap.counters;
4959 if (cntr_mask != pebs_mask)
4960 event->hw.dyn_constraint &= pebs_mask;
4961 }
4962 }
4963
4964 if (needs_branch_stack(event)) {
4965 /* Avoid branch stack setup for counting events in SAMPLE READ */
4966 if (is_sampling_event(event) ||
4967 !(event->attr.sample_type & PERF_SAMPLE_READ))
4968 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK;
4969 }
4970
4971 if (branch_sample_counters(event)) {
4972 struct perf_event *leader, *sibling;
4973 int num = 0;
4974
4975 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) ||
4976 (event->attr.config & ~INTEL_ARCH_EVENT_MASK))
4977 return -EINVAL;
4978
4979 /*
4980 * The branch counter logging is not supported in the call stack
4981 * mode yet, since we cannot simply flush the LBR during e.g.,
4982 * multiplexing. Also, there is no obvious usage with the call
4983 * stack mode. Simply forbids it for now.
4984 *
4985 * If any events in the group enable the branch counter logging
4986 * feature, the group is treated as a branch counter logging
4987 * group, which requires the extra space to store the counters.
4988 */
4989 leader = event->group_leader;
4990 if (intel_set_branch_counter_constr(leader, &num))
4991 return -EINVAL;
4992 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS;
4993
4994 for_each_sibling_event(sibling, leader) {
4995 if (intel_set_branch_counter_constr(sibling, &num))
4996 return -EINVAL;
4997 }
4998
4999 /* event isn't installed as a sibling yet. */
5000 if (event != leader) {
5001 if (intel_set_branch_counter_constr(event, &num))
5002 return -EINVAL;
5003 }
5004
5005 if (num > fls(x86_pmu.lbr_counters))
5006 return -EINVAL;
5007 /*
5008 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't
5009 * require any branch stack setup.
5010 * Clear the bit to avoid unnecessary branch stack setup.
5011 */
5012 if (0 == (event->attr.branch_sample_type &
5013 ~(PERF_SAMPLE_BRANCH_PLM_ALL |
5014 PERF_SAMPLE_BRANCH_COUNTERS)))
5015 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK;
5016
5017 /*
5018 * Force the leader to be a LBR event. So LBRs can be reset
5019 * with the leader event. See intel_pmu_lbr_del() for details.
5020 */
5021 if (!intel_pmu_needs_branch_stack(leader))
5022 return -EINVAL;
5023 }
5024
5025 if (intel_pmu_needs_branch_stack(event)) {
5026 ret = intel_pmu_setup_lbr_filter(event);
5027 if (ret)
5028 return ret;
5029 event->attach_state |= PERF_ATTACH_SCHED_CB;
5030
5031 /*
5032 * BTS is set up earlier in this path, so don't account twice
5033 */
5034 if (!unlikely(intel_pmu_has_bts(event))) {
5035 /* disallow lbr if conflicting events are present */
5036 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
5037 return -EBUSY;
5038
5039 event->destroy = hw_perf_lbr_event_destroy;
5040 }
5041 }
5042
5043 if (event->attr.aux_output) {
5044 if (!event->attr.precise_ip)
5045 return -EINVAL;
5046
5047 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
5048 }
5049
5050 if ((event->attr.sample_type & PERF_SAMPLE_READ) &&
5051 intel_pmu_has_pebs_counter_group(event->pmu) &&
5052 is_sampling_event(event) &&
5053 event->attr.precise_ip)
5054 event->group_leader->hw.flags |= PERF_X86_EVENT_PEBS_CNTR;
5055
5056 if (intel_pmu_has_acr(event->pmu) && intel_pmu_is_acr_group(event)) {
5057 struct perf_event *sibling, *leader = event->group_leader;
5058 struct pmu *pmu = event->pmu;
5059 bool has_sw_event = false;
5060 int num = 0, idx = 0;
5061 u64 cause_mask = 0;
5062
5063 /* Not support perf metrics */
5064 if (is_metric_event(event))
5065 return -EINVAL;
5066
5067 /* Not support freq mode */
5068 if (event->attr.freq)
5069 return -EINVAL;
5070
5071 /* PDist is not supported */
5072 if (event->attr.config2 && event->attr.precise_ip > 2)
5073 return -EINVAL;
5074
5075 /* The reload value cannot exceeds the max period */
5076 if (event->attr.sample_period > x86_pmu.max_period)
5077 return -EINVAL;
5078 /*
5079 * The counter-constraints of each event cannot be finalized
5080 * unless the whole group is scanned. However, it's hard
5081 * to know whether the event is the last one of the group.
5082 * Recalculate the counter-constraints for each event when
5083 * adding a new event.
5084 *
5085 * The group is traversed twice, which may be optimized later.
5086 * In the first round,
5087 * - Find all events which do reload when other events
5088 * overflow and set the corresponding counter-constraints
5089 * - Add all events, which can cause other events reload,
5090 * in the cause_mask
5091 * - Error out if the number of events exceeds the HW limit
5092 * - The ACR events must be contiguous.
5093 * Error out if there are non-X86 events between ACR events.
5094 * This is not a HW limit, but a SW limit.
5095 * With the assumption, the intel_pmu_acr_late_setup() can
5096 * easily convert the event idx to counter idx without
5097 * traversing the whole event list.
5098 */
5099 if (!is_x86_event(leader))
5100 return -EINVAL;
5101
5102 if (leader->attr.config2)
5103 intel_pmu_set_acr_cntr_constr(leader, &cause_mask, &num);
5104
5105 if (leader->nr_siblings) {
5106 for_each_sibling_event(sibling, leader) {
5107 if (!is_x86_event(sibling)) {
5108 has_sw_event = true;
5109 continue;
5110 }
5111 if (!sibling->attr.config2)
5112 continue;
5113 if (has_sw_event)
5114 return -EINVAL;
5115 intel_pmu_set_acr_cntr_constr(sibling, &cause_mask, &num);
5116 }
5117 }
5118 if (leader != event && event->attr.config2) {
5119 if (has_sw_event)
5120 return -EINVAL;
5121 intel_pmu_set_acr_cntr_constr(event, &cause_mask, &num);
5122 }
5123
5124 if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) ||
5125 num > hweight64(hybrid(event->pmu, acr_cntr_mask64)))
5126 return -EINVAL;
5127 /*
5128 * In the second round, apply the counter-constraints for
5129 * the events which can cause other events reload.
5130 */
5131 intel_pmu_set_acr_caused_constr(leader, idx++, cause_mask);
5132
5133 if (leader->nr_siblings) {
5134 for_each_sibling_event(sibling, leader) {
5135 if (is_x86_event(sibling))
5136 intel_pmu_set_acr_caused_constr(sibling, idx++, cause_mask);
5137 }
5138 }
5139
5140 if (leader != event)
5141 intel_pmu_set_acr_caused_constr(event, idx, cause_mask);
5142
5143 leader->hw.flags |= PERF_X86_EVENT_ACR;
5144 }
5145
5146 intel_pmu_update_rdpmc_user_disable(event);
5147
5148 if ((event->attr.type == PERF_TYPE_HARDWARE) ||
5149 (event->attr.type == PERF_TYPE_HW_CACHE))
5150 return 0;
5151
5152 /*
5153 * Config Topdown slots and metric events
5154 *
5155 * The slots event on Fixed Counter 3 can support sampling,
5156 * which will be handled normally in x86_perf_event_update().
5157 *
5158 * Metric events don't support sampling and require being paired
5159 * with a slots event as group leader. When the slots event
5160 * is used in a metrics group, it too cannot support sampling.
5161 */
5162 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
5163 /* The metrics_clear can only be set for the slots event */
5164 if (event->attr.config1 &&
5165 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR)))
5166 return -EINVAL;
5167
5168 if (event->attr.config2)
5169 return -EINVAL;
5170
5171 /*
5172 * The TopDown metrics events and slots event don't
5173 * support any filters.
5174 */
5175 if (event->attr.config & X86_ALL_EVENT_FLAGS)
5176 return -EINVAL;
5177
5178 if (is_available_metric_event(event)) {
5179 struct perf_event *leader = event->group_leader;
5180
5181 /* The metric events don't support sampling. */
5182 if (is_sampling_event(event))
5183 return -EINVAL;
5184
5185 /* The metric events require a slots group leader. */
5186 if (!is_slots_event(leader))
5187 return -EINVAL;
5188
5189 /*
5190 * The leader/SLOTS must not be a sampling event for
5191 * metric use; hardware requires it starts at 0 when used
5192 * in conjunction with MSR_PERF_METRICS.
5193 */
5194 if (is_sampling_event(leader))
5195 return -EINVAL;
5196
5197 event->event_caps |= PERF_EV_CAP_SIBLING;
5198 /*
5199 * Only once we have a METRICs sibling do we
5200 * need TopDown magic.
5201 */
5202 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
5203 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
5204 }
5205 }
5206
5207 /*
5208 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
5209 * doesn't function quite right. As a work-around it needs to always be
5210 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
5211 * The actual count of this second event is irrelevant it just needs
5212 * to be active to make the first event function correctly.
5213 *
5214 * In a group, the auxiliary event must be in front of the load latency
5215 * event. The rule is to simplify the implementation of the check.
5216 * That's because perf cannot have a complete group at the moment.
5217 */
5218 if (require_mem_loads_aux_event(event) &&
5219 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
5220 is_mem_loads_event(event)) {
5221 struct perf_event *leader = event->group_leader;
5222 struct perf_event *sibling = NULL;
5223
5224 /*
5225 * When this memload event is also the first event (no group
5226 * exists yet), then there is no aux event before it.
5227 */
5228 if (leader == event)
5229 return -ENODATA;
5230
5231 if (!is_mem_loads_aux_event(leader)) {
5232 for_each_sibling_event(sibling, leader) {
5233 if (is_mem_loads_aux_event(sibling))
5234 break;
5235 }
5236 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
5237 return -ENODATA;
5238 }
5239 }
5240
5241 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
5242 return 0;
5243
5244 if (x86_pmu.version < 3)
5245 return -EINVAL;
5246
5247 ret = perf_allow_cpu();
5248 if (ret)
5249 return ret;
5250
5251 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
5252
5253 return 0;
5254 }
5255
5256 /*
5257 * Currently, the only caller of this function is the atomic_switch_perf_msrs().
5258 * The host perf context helps to prepare the values of the real hardware for
5259 * a set of msrs that need to be switched atomically in a vmx transaction.
5260 *
5261 * For example, the pseudocode needed to add a new msr should look like:
5262 *
5263 * arr[(*nr)++] = (struct perf_guest_switch_msr){
5264 * .msr = the hardware msr address,
5265 * .host = the value the hardware has when it doesn't run a guest,
5266 * .guest = the value the hardware has when it runs a guest,
5267 * };
5268 *
5269 * These values have nothing to do with the emulated values the guest sees
5270 * when it uses {RD,WR}MSR, which should be handled by the KVM context,
5271 * specifically in the intel_pmu_{get,set}_msr().
5272 */
intel_guest_get_msrs(int * nr,void * data)5273 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
5274 {
5275 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5276 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
5277 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data;
5278 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
5279 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
5280 int global_ctrl, pebs_enable;
5281
5282 /*
5283 * In addition to obeying exclude_guest/exclude_host, remove bits being
5284 * used for PEBS when running a guest, because PEBS writes to virtual
5285 * addresses (not physical addresses).
5286 */
5287 *nr = 0;
5288 global_ctrl = (*nr)++;
5289 arr[global_ctrl] = (struct perf_guest_switch_msr){
5290 .msr = MSR_CORE_PERF_GLOBAL_CTRL,
5291 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
5292 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask,
5293 };
5294
5295 if (!x86_pmu.ds_pebs)
5296 return arr;
5297
5298 /*
5299 * If PMU counter has PEBS enabled it is not enough to
5300 * disable counter on a guest entry since PEBS memory
5301 * write can overshoot guest entry and corrupt guest
5302 * memory. Disabling PEBS solves the problem.
5303 *
5304 * Don't do this if the CPU already enforces it.
5305 */
5306 if (x86_pmu.pebs_no_isolation) {
5307 arr[(*nr)++] = (struct perf_guest_switch_msr){
5308 .msr = MSR_IA32_PEBS_ENABLE,
5309 .host = cpuc->pebs_enabled,
5310 .guest = 0,
5311 };
5312 return arr;
5313 }
5314
5315 if (!kvm_pmu || !x86_pmu.pebs_ept)
5316 return arr;
5317
5318 arr[(*nr)++] = (struct perf_guest_switch_msr){
5319 .msr = MSR_IA32_DS_AREA,
5320 .host = (unsigned long)cpuc->ds,
5321 .guest = kvm_pmu->ds_area,
5322 };
5323
5324 if (x86_pmu.intel_cap.pebs_baseline) {
5325 arr[(*nr)++] = (struct perf_guest_switch_msr){
5326 .msr = MSR_PEBS_DATA_CFG,
5327 .host = cpuc->active_pebs_data_cfg,
5328 .guest = kvm_pmu->pebs_data_cfg,
5329 };
5330 }
5331
5332 pebs_enable = (*nr)++;
5333 arr[pebs_enable] = (struct perf_guest_switch_msr){
5334 .msr = MSR_IA32_PEBS_ENABLE,
5335 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
5336 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask & kvm_pmu->pebs_enable,
5337 };
5338
5339 if (arr[pebs_enable].host) {
5340 /* Disable guest PEBS if host PEBS is enabled. */
5341 arr[pebs_enable].guest = 0;
5342 } else {
5343 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */
5344 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
5345 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask;
5346 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
5347 arr[global_ctrl].guest |= arr[pebs_enable].guest;
5348 }
5349
5350 return arr;
5351 }
5352
core_guest_get_msrs(int * nr,void * data)5353 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data)
5354 {
5355 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5356 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
5357 int idx;
5358
5359 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
5360 struct perf_event *event = cpuc->events[idx];
5361
5362 arr[idx].msr = x86_pmu_config_addr(idx);
5363 arr[idx].host = arr[idx].guest = 0;
5364
5365 if (!test_bit(idx, cpuc->active_mask))
5366 continue;
5367
5368 arr[idx].host = arr[idx].guest =
5369 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
5370
5371 if (event->attr.exclude_host)
5372 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
5373 else if (event->attr.exclude_guest)
5374 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
5375 }
5376
5377 *nr = x86_pmu_max_num_counters(cpuc->pmu);
5378 return arr;
5379 }
5380
core_pmu_enable_event(struct perf_event * event)5381 static void core_pmu_enable_event(struct perf_event *event)
5382 {
5383 if (!event->attr.exclude_host)
5384 x86_pmu_enable_event(event);
5385 }
5386
core_pmu_enable_all(int added)5387 static void core_pmu_enable_all(int added)
5388 {
5389 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5390 int idx;
5391
5392 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
5393 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
5394
5395 if (!test_bit(idx, cpuc->active_mask) ||
5396 cpuc->events[idx]->attr.exclude_host)
5397 continue;
5398
5399 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
5400 }
5401 }
5402
hsw_hw_config(struct perf_event * event)5403 static int hsw_hw_config(struct perf_event *event)
5404 {
5405 int ret = intel_pmu_hw_config(event);
5406
5407 if (ret)
5408 return ret;
5409 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
5410 return 0;
5411 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
5412
5413 /*
5414 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
5415 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
5416 * this combination.
5417 */
5418 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
5419 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
5420 event->attr.precise_ip > 0))
5421 return -EOPNOTSUPP;
5422
5423 if (event_is_checkpointed(event)) {
5424 /*
5425 * Sampling of checkpointed events can cause situations where
5426 * the CPU constantly aborts because of a overflow, which is
5427 * then checkpointed back and ignored. Forbid checkpointing
5428 * for sampling.
5429 *
5430 * But still allow a long sampling period, so that perf stat
5431 * from KVM works.
5432 */
5433 if (event->attr.sample_period > 0 &&
5434 event->attr.sample_period < 0x7fffffff)
5435 return -EOPNOTSUPP;
5436 }
5437 return 0;
5438 }
5439
5440 static struct event_constraint counter0_constraint =
5441 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
5442
5443 static struct event_constraint counter1_constraint =
5444 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2);
5445
5446 static struct event_constraint counter0_1_constraint =
5447 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3);
5448
5449 static struct event_constraint counter2_constraint =
5450 EVENT_CONSTRAINT(0, 0x4, 0);
5451
5452 static struct event_constraint fixed0_constraint =
5453 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
5454
5455 static struct event_constraint fixed0_counter0_constraint =
5456 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
5457
5458 static struct event_constraint fixed0_counter0_1_constraint =
5459 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL);
5460
5461 static struct event_constraint counters_1_7_constraint =
5462 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL);
5463
5464 static struct event_constraint *
hsw_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5465 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5466 struct perf_event *event)
5467 {
5468 struct event_constraint *c;
5469
5470 c = intel_get_event_constraints(cpuc, idx, event);
5471
5472 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
5473 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
5474 if (c->idxmsk64 & (1U << 2))
5475 return &counter2_constraint;
5476 return &emptyconstraint;
5477 }
5478
5479 return c;
5480 }
5481
5482 static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5483 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5484 struct perf_event *event)
5485 {
5486 /*
5487 * Fixed counter 0 has less skid.
5488 * Force instruction:ppp in Fixed counter 0
5489 */
5490 if ((event->attr.precise_ip == 3) &&
5491 constraint_match(&fixed0_constraint, event->hw.config))
5492 return &fixed0_constraint;
5493
5494 return hsw_get_event_constraints(cpuc, idx, event);
5495 }
5496
5497 static struct event_constraint *
glc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5498 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5499 struct perf_event *event)
5500 {
5501 struct event_constraint *c;
5502
5503 c = icl_get_event_constraints(cpuc, idx, event);
5504
5505 /*
5506 * The :ppp indicates the Precise Distribution (PDist) facility, which
5507 * is only supported on the GP counter 0. If a :ppp event which is not
5508 * available on the GP counter 0, error out.
5509 * Exception: Instruction PDIR is only available on the fixed counter 0.
5510 */
5511 if ((event->attr.precise_ip == 3) &&
5512 !constraint_match(&fixed0_constraint, event->hw.config)) {
5513 if (c->idxmsk64 & BIT_ULL(0))
5514 return &counter0_constraint;
5515
5516 return &emptyconstraint;
5517 }
5518
5519 return c;
5520 }
5521
5522 static struct event_constraint *
glp_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5523 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5524 struct perf_event *event)
5525 {
5526 struct event_constraint *c;
5527
5528 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
5529 if (event->attr.precise_ip == 3)
5530 return &counter0_constraint;
5531
5532 c = intel_get_event_constraints(cpuc, idx, event);
5533
5534 return c;
5535 }
5536
5537 static struct event_constraint *
tnt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5538 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5539 struct perf_event *event)
5540 {
5541 struct event_constraint *c;
5542
5543 c = intel_get_event_constraints(cpuc, idx, event);
5544
5545 /*
5546 * :ppp means to do reduced skid PEBS,
5547 * which is available on PMC0 and fixed counter 0.
5548 */
5549 if (event->attr.precise_ip == 3) {
5550 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
5551 if (constraint_match(&fixed0_constraint, event->hw.config))
5552 return &fixed0_counter0_constraint;
5553
5554 return &counter0_constraint;
5555 }
5556
5557 return c;
5558 }
5559
5560 static bool allow_tsx_force_abort = true;
5561
5562 static struct event_constraint *
tfa_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5563 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5564 struct perf_event *event)
5565 {
5566 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
5567
5568 /*
5569 * Without TFA we must not use PMC3.
5570 */
5571 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
5572 c = dyn_constraint(cpuc, c, idx);
5573 c->idxmsk64 &= ~(1ULL << 3);
5574 c->weight--;
5575 }
5576
5577 return c;
5578 }
5579
5580 static struct event_constraint *
adl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5581 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5582 struct perf_event *event)
5583 {
5584 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5585
5586 if (pmu->pmu_type == hybrid_big)
5587 return glc_get_event_constraints(cpuc, idx, event);
5588 else if (pmu->pmu_type == hybrid_small)
5589 return tnt_get_event_constraints(cpuc, idx, event);
5590
5591 WARN_ON(1);
5592 return &emptyconstraint;
5593 }
5594
5595 static struct event_constraint *
cmt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5596 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5597 struct perf_event *event)
5598 {
5599 struct event_constraint *c;
5600
5601 c = intel_get_event_constraints(cpuc, idx, event);
5602
5603 /*
5604 * The :ppp indicates the Precise Distribution (PDist) facility, which
5605 * is only supported on the GP counter 0 & 1 and Fixed counter 0.
5606 * If a :ppp event which is not available on the above eligible counters,
5607 * error out.
5608 */
5609 if (event->attr.precise_ip == 3) {
5610 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */
5611 if (constraint_match(&fixed0_constraint, event->hw.config)) {
5612 /* The fixed counter 0 doesn't support LBR event logging. */
5613 if (branch_sample_counters(event))
5614 return &counter0_1_constraint;
5615 else
5616 return &fixed0_counter0_1_constraint;
5617 }
5618
5619 switch (c->idxmsk64 & 0x3ull) {
5620 case 0x1:
5621 return &counter0_constraint;
5622 case 0x2:
5623 return &counter1_constraint;
5624 case 0x3:
5625 return &counter0_1_constraint;
5626 }
5627 return &emptyconstraint;
5628 }
5629
5630 return c;
5631 }
5632
5633 static struct event_constraint *
rwc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5634 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5635 struct perf_event *event)
5636 {
5637 struct event_constraint *c;
5638
5639 c = glc_get_event_constraints(cpuc, idx, event);
5640
5641 /* The Retire Latency is not supported by the fixed counter 0. */
5642 if (event->attr.precise_ip &&
5643 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
5644 constraint_match(&fixed0_constraint, event->hw.config)) {
5645 /*
5646 * The Instruction PDIR is only available
5647 * on the fixed counter 0. Error out for this case.
5648 */
5649 if (event->attr.precise_ip == 3)
5650 return &emptyconstraint;
5651 return &counters_1_7_constraint;
5652 }
5653
5654 return c;
5655 }
5656
5657 static struct event_constraint *
mtl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5658 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5659 struct perf_event *event)
5660 {
5661 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5662
5663 if (pmu->pmu_type == hybrid_big)
5664 return rwc_get_event_constraints(cpuc, idx, event);
5665 if (pmu->pmu_type == hybrid_small)
5666 return cmt_get_event_constraints(cpuc, idx, event);
5667
5668 WARN_ON(1);
5669 return &emptyconstraint;
5670 }
5671
adl_hw_config(struct perf_event * event)5672 static int adl_hw_config(struct perf_event *event)
5673 {
5674 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5675
5676 if (pmu->pmu_type == hybrid_big)
5677 return hsw_hw_config(event);
5678 else if (pmu->pmu_type == hybrid_small)
5679 return intel_pmu_hw_config(event);
5680
5681 WARN_ON(1);
5682 return -EOPNOTSUPP;
5683 }
5684
adl_get_hybrid_cpu_type(void)5685 static enum intel_cpu_type adl_get_hybrid_cpu_type(void)
5686 {
5687 return INTEL_CPU_TYPE_CORE;
5688 }
5689
erratum_hsw11(struct perf_event * event)5690 static inline bool erratum_hsw11(struct perf_event *event)
5691 {
5692 return (event->hw.config & INTEL_ARCH_EVENT_MASK) ==
5693 X86_CONFIG(.event=0xc0, .umask=0x01);
5694 }
5695
5696 static struct event_constraint *
arl_h_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5697 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5698 struct perf_event *event)
5699 {
5700 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5701
5702 if (pmu->pmu_type == hybrid_tiny)
5703 return cmt_get_event_constraints(cpuc, idx, event);
5704
5705 return mtl_get_event_constraints(cpuc, idx, event);
5706 }
5707
arl_h_hw_config(struct perf_event * event)5708 static int arl_h_hw_config(struct perf_event *event)
5709 {
5710 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5711
5712 if (pmu->pmu_type == hybrid_tiny)
5713 return intel_pmu_hw_config(event);
5714
5715 return adl_hw_config(event);
5716 }
5717
5718 /*
5719 * The HSW11 requires a period larger than 100 which is the same as the BDM11.
5720 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL.
5721 *
5722 * The message 'interrupt took too long' can be observed on any counter which
5723 * was armed with a period < 32 and two events expired in the same NMI.
5724 * A minimum period of 32 is enforced for the rest of the events.
5725 */
hsw_limit_period(struct perf_event * event,s64 * left)5726 static void hsw_limit_period(struct perf_event *event, s64 *left)
5727 {
5728 *left = max(*left, erratum_hsw11(event) ? 128 : 32);
5729 }
5730
5731 /*
5732 * Broadwell:
5733 *
5734 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
5735 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
5736 * the two to enforce a minimum period of 128 (the smallest value that has bits
5737 * 0-5 cleared and >= 100).
5738 *
5739 * Because of how the code in x86_perf_event_set_period() works, the truncation
5740 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
5741 * to make up for the 'lost' events due to carrying the 'error' in period_left.
5742 *
5743 * Therefore the effective (average) period matches the requested period,
5744 * despite coarser hardware granularity.
5745 */
bdw_limit_period(struct perf_event * event,s64 * left)5746 static void bdw_limit_period(struct perf_event *event, s64 *left)
5747 {
5748 if (erratum_hsw11(event)) {
5749 if (*left < 128)
5750 *left = 128;
5751 *left &= ~0x3fULL;
5752 }
5753 }
5754
nhm_limit_period(struct perf_event * event,s64 * left)5755 static void nhm_limit_period(struct perf_event *event, s64 *left)
5756 {
5757 *left = max(*left, 32LL);
5758 }
5759
glc_limit_period(struct perf_event * event,s64 * left)5760 static void glc_limit_period(struct perf_event *event, s64 *left)
5761 {
5762 if (event->attr.precise_ip == 3)
5763 *left = max(*left, 128LL);
5764 }
5765
5766 PMU_FORMAT_ATTR(event, "config:0-7" );
5767 PMU_FORMAT_ATTR(umask, "config:8-15" );
5768 PMU_FORMAT_ATTR(edge, "config:18" );
5769 PMU_FORMAT_ATTR(pc, "config:19" );
5770 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
5771 PMU_FORMAT_ATTR(inv, "config:23" );
5772 PMU_FORMAT_ATTR(cmask, "config:24-31" );
5773 PMU_FORMAT_ATTR(in_tx, "config:32" );
5774 PMU_FORMAT_ATTR(in_tx_cp, "config:33" );
5775 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */
5776
5777 PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
5778
umask2_show(struct device * dev,struct device_attribute * attr,char * page)5779 static ssize_t umask2_show(struct device *dev,
5780 struct device_attribute *attr,
5781 char *page)
5782 {
5783 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2;
5784
5785 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2)
5786 return sprintf(page, "config:8-15,40-47\n");
5787
5788 /* Roll back to the old format if umask2 is not supported. */
5789 return sprintf(page, "config:8-15\n");
5790 }
5791
5792 static struct device_attribute format_attr_umask2 =
5793 __ATTR(umask, 0444, umask2_show, NULL);
5794
5795 static struct attribute *format_evtsel_ext_attrs[] = {
5796 &format_attr_umask2.attr,
5797 &format_attr_eq.attr,
5798 &format_attr_metrics_clear.attr,
5799 NULL
5800 };
5801
5802 static umode_t
evtsel_ext_is_visible(struct kobject * kobj,struct attribute * attr,int i)5803 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5804 {
5805 struct device *dev = kobj_to_dev(kobj);
5806 u64 mask;
5807
5808 /*
5809 * The umask and umask2 have different formats but share the
5810 * same attr name. In update mode, the previous value of the
5811 * umask is unconditionally removed before is_visible. If
5812 * umask2 format is not enumerated, it's impossible to roll
5813 * back to the old format.
5814 * Does the check in umask2_show rather than is_visible.
5815 */
5816 if (i == 0)
5817 return attr->mode;
5818
5819 mask = hybrid(dev_get_drvdata(dev), config_mask);
5820 if (i == 1)
5821 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0;
5822
5823 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
5824 if (i == 2) {
5825 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap);
5826
5827 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0;
5828 }
5829
5830 return 0;
5831 }
5832
5833 static struct attribute *intel_arch_formats_attr[] = {
5834 &format_attr_event.attr,
5835 &format_attr_umask.attr,
5836 &format_attr_edge.attr,
5837 &format_attr_pc.attr,
5838 &format_attr_inv.attr,
5839 &format_attr_cmask.attr,
5840 NULL,
5841 };
5842
intel_event_sysfs_show(char * page,u64 config)5843 ssize_t intel_event_sysfs_show(char *page, u64 config)
5844 {
5845 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
5846
5847 return x86_event_sysfs_show(page, config, event);
5848 }
5849
allocate_shared_regs(int cpu)5850 static struct intel_shared_regs *allocate_shared_regs(int cpu)
5851 {
5852 struct intel_shared_regs *regs;
5853 int i;
5854
5855 regs = kzalloc_node(sizeof(struct intel_shared_regs),
5856 GFP_KERNEL, cpu_to_node(cpu));
5857 if (regs) {
5858 /*
5859 * initialize the locks to keep lockdep happy
5860 */
5861 for (i = 0; i < EXTRA_REG_MAX; i++)
5862 raw_spin_lock_init(®s->regs[i].lock);
5863
5864 regs->core_id = -1;
5865 }
5866 return regs;
5867 }
5868
allocate_excl_cntrs(int cpu)5869 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
5870 {
5871 struct intel_excl_cntrs *c;
5872
5873 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
5874 GFP_KERNEL, cpu_to_node(cpu));
5875 if (c) {
5876 raw_spin_lock_init(&c->lock);
5877 c->core_id = -1;
5878 }
5879 return c;
5880 }
5881
5882
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)5883 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
5884 {
5885 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
5886
5887 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
5888 cpuc->shared_regs = allocate_shared_regs(cpu);
5889 if (!cpuc->shared_regs)
5890 goto err;
5891 }
5892
5893 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_DYN_CONSTRAINT)) {
5894 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
5895
5896 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
5897 if (!cpuc->constraint_list)
5898 goto err_shared_regs;
5899 }
5900
5901 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
5902 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
5903 if (!cpuc->excl_cntrs)
5904 goto err_constraint_list;
5905
5906 cpuc->excl_thread_id = 0;
5907 }
5908
5909 return 0;
5910
5911 err_constraint_list:
5912 kfree(cpuc->constraint_list);
5913 cpuc->constraint_list = NULL;
5914
5915 err_shared_regs:
5916 kfree(cpuc->shared_regs);
5917 cpuc->shared_regs = NULL;
5918
5919 err:
5920 return -ENOMEM;
5921 }
5922
intel_pmu_cpu_prepare(int cpu)5923 static int intel_pmu_cpu_prepare(int cpu)
5924 {
5925 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5926 int ret;
5927
5928 ret = intel_cpuc_prepare(cpuc, cpu);
5929 if (ret)
5930 return ret;
5931
5932 ret = alloc_arch_pebs_buf_on_cpu(cpu);
5933 if (ret) {
5934 intel_cpuc_finish(cpuc);
5935 return ret;
5936 }
5937
5938 return 0;
5939 }
5940
flip_smm_bit(void * data)5941 static void flip_smm_bit(void *data)
5942 {
5943 unsigned long set = *(unsigned long *)data;
5944
5945 if (set > 0) {
5946 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
5947 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
5948 } else {
5949 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
5950 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
5951 }
5952 }
5953
intel_pmu_check_counters_mask(u64 * cntr_mask,u64 * fixed_cntr_mask,u64 * intel_ctrl)5954 static void intel_pmu_check_counters_mask(u64 *cntr_mask,
5955 u64 *fixed_cntr_mask,
5956 u64 *intel_ctrl)
5957 {
5958 unsigned int bit;
5959
5960 bit = fls64(*cntr_mask);
5961 if (bit > INTEL_PMC_MAX_GENERIC) {
5962 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5963 bit, INTEL_PMC_MAX_GENERIC);
5964 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
5965 }
5966 *intel_ctrl = *cntr_mask;
5967
5968 bit = fls64(*fixed_cntr_mask);
5969 if (bit > INTEL_PMC_MAX_FIXED) {
5970 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5971 bit, INTEL_PMC_MAX_FIXED);
5972 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
5973 }
5974
5975 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED;
5976 }
5977
5978 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
5979 u64 cntr_mask,
5980 u64 fixed_cntr_mask,
5981 u64 intel_ctrl);
5982
5983 enum dyn_constr_type {
5984 DYN_CONSTR_NONE,
5985 DYN_CONSTR_BR_CNTR,
5986 DYN_CONSTR_ACR_CNTR,
5987 DYN_CONSTR_ACR_CAUSE,
5988 DYN_CONSTR_PEBS,
5989 DYN_CONSTR_PDIST,
5990
5991 DYN_CONSTR_MAX,
5992 };
5993
5994 static const char * const dyn_constr_type_name[] = {
5995 [DYN_CONSTR_NONE] = "a normal event",
5996 [DYN_CONSTR_BR_CNTR] = "a branch counter logging event",
5997 [DYN_CONSTR_ACR_CNTR] = "an auto-counter reload event",
5998 [DYN_CONSTR_ACR_CAUSE] = "an auto-counter reload cause event",
5999 [DYN_CONSTR_PEBS] = "a PEBS event",
6000 [DYN_CONSTR_PDIST] = "a PEBS PDIST event",
6001 };
6002
__intel_pmu_check_dyn_constr(struct event_constraint * constr,enum dyn_constr_type type,u64 mask)6003 static void __intel_pmu_check_dyn_constr(struct event_constraint *constr,
6004 enum dyn_constr_type type, u64 mask)
6005 {
6006 struct event_constraint *c1, *c2;
6007 int new_weight, check_weight;
6008 u64 new_mask, check_mask;
6009
6010 for_each_event_constraint(c1, constr) {
6011 new_mask = c1->idxmsk64 & mask;
6012 new_weight = hweight64(new_mask);
6013
6014 /* ignore topdown perf metrics event */
6015 if (c1->idxmsk64 & INTEL_PMC_MSK_TOPDOWN)
6016 continue;
6017
6018 if (!new_weight && fls64(c1->idxmsk64) < INTEL_PMC_IDX_FIXED) {
6019 pr_info("The event 0x%llx is not supported as %s.\n",
6020 c1->code, dyn_constr_type_name[type]);
6021 }
6022
6023 if (new_weight <= 1)
6024 continue;
6025
6026 for_each_event_constraint(c2, c1 + 1) {
6027 bool check_fail = false;
6028
6029 check_mask = c2->idxmsk64 & mask;
6030 check_weight = hweight64(check_mask);
6031
6032 if (c2->idxmsk64 & INTEL_PMC_MSK_TOPDOWN ||
6033 !check_weight)
6034 continue;
6035
6036 /* The same constraints or no overlap */
6037 if (new_mask == check_mask ||
6038 (new_mask ^ check_mask) == (new_mask | check_mask))
6039 continue;
6040
6041 /*
6042 * A scheduler issue may be triggered in the following cases.
6043 * - Two overlap constraints have the same weight.
6044 * E.g., A constraints: 0x3, B constraints: 0x6
6045 * event counter failure case
6046 * B PMC[2:1] 1
6047 * A PMC[1:0] 0
6048 * A PMC[1:0] FAIL
6049 * - Two overlap constraints have different weight.
6050 * The constraint has a low weight, but has high last bit.
6051 * E.g., A constraints: 0x7, B constraints: 0xC
6052 * event counter failure case
6053 * B PMC[3:2] 2
6054 * A PMC[2:0] 0
6055 * A PMC[2:0] 1
6056 * A PMC[2:0] FAIL
6057 */
6058 if (new_weight == check_weight) {
6059 check_fail = true;
6060 } else if (new_weight < check_weight) {
6061 if ((new_mask | check_mask) != check_mask &&
6062 fls64(new_mask) > fls64(check_mask))
6063 check_fail = true;
6064 } else {
6065 if ((new_mask | check_mask) != new_mask &&
6066 fls64(new_mask) < fls64(check_mask))
6067 check_fail = true;
6068 }
6069
6070 if (check_fail) {
6071 pr_warn("The two events 0x%llx and 0x%llx may not be "
6072 "fully scheduled under some circumstances as "
6073 "%s.\n",
6074 c1->code, c2->code, dyn_constr_type_name[type]);
6075 }
6076 }
6077 }
6078 }
6079
intel_pmu_check_dyn_constr(struct pmu * pmu,struct event_constraint * constr,u64 cntr_mask)6080 static void intel_pmu_check_dyn_constr(struct pmu *pmu,
6081 struct event_constraint *constr,
6082 u64 cntr_mask)
6083 {
6084 u64 gp_mask = GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
6085 enum dyn_constr_type i;
6086 u64 mask;
6087
6088 for (i = DYN_CONSTR_NONE; i < DYN_CONSTR_MAX; i++) {
6089 mask = 0;
6090 switch (i) {
6091 case DYN_CONSTR_NONE:
6092 mask = cntr_mask;
6093 break;
6094 case DYN_CONSTR_BR_CNTR:
6095 if (x86_pmu.flags & PMU_FL_BR_CNTR)
6096 mask = x86_pmu.lbr_counters;
6097 break;
6098 case DYN_CONSTR_ACR_CNTR:
6099 mask = hybrid(pmu, acr_cntr_mask64) & gp_mask;
6100 break;
6101 case DYN_CONSTR_ACR_CAUSE:
6102 if (hybrid(pmu, acr_cntr_mask64) ==
6103 hybrid(pmu, acr_cause_mask64))
6104 continue;
6105 mask = hybrid(pmu, acr_cause_mask64) & gp_mask;
6106 break;
6107 case DYN_CONSTR_PEBS:
6108 if (x86_pmu.arch_pebs) {
6109 mask = hybrid(pmu, arch_pebs_cap).counters &
6110 gp_mask;
6111 }
6112 break;
6113 case DYN_CONSTR_PDIST:
6114 if (x86_pmu.arch_pebs) {
6115 mask = hybrid(pmu, arch_pebs_cap).pdists &
6116 gp_mask;
6117 }
6118 break;
6119 default:
6120 pr_warn("Unsupported dynamic constraint type %d\n", i);
6121 }
6122
6123 if (mask)
6124 __intel_pmu_check_dyn_constr(constr, i, mask);
6125 }
6126 }
6127
intel_pmu_check_event_constraints_all(struct pmu * pmu)6128 static void intel_pmu_check_event_constraints_all(struct pmu *pmu)
6129 {
6130 struct event_constraint *event_constraints = hybrid(pmu, event_constraints);
6131 struct event_constraint *pebs_constraints = hybrid(pmu, pebs_constraints);
6132 u64 cntr_mask = hybrid(pmu, cntr_mask64);
6133 u64 fixed_cntr_mask = hybrid(pmu, fixed_cntr_mask64);
6134 u64 intel_ctrl = hybrid(pmu, intel_ctrl);
6135
6136 intel_pmu_check_event_constraints(event_constraints, cntr_mask,
6137 fixed_cntr_mask, intel_ctrl);
6138
6139 if (event_constraints)
6140 intel_pmu_check_dyn_constr(pmu, event_constraints, cntr_mask);
6141
6142 if (pebs_constraints)
6143 intel_pmu_check_dyn_constr(pmu, pebs_constraints, cntr_mask);
6144 }
6145
6146 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs);
6147
intel_pmu_broken_perf_cap(void)6148 static inline bool intel_pmu_broken_perf_cap(void)
6149 {
6150 /*
6151 * The Perf Metric (Bit 15) is always cleared on P-core of
6152 * RPL and MTL. Details can be found in RPL018 erratum.
6153 */
6154 if (boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE ||
6155 boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE_P ||
6156 boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE_S ||
6157 boot_cpu_data.x86_vfm == INTEL_METEORLAKE ||
6158 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L)
6159 return true;
6160
6161 return false;
6162 }
6163
__intel_update_pmu_caps(struct pmu * pmu)6164 static inline void __intel_update_pmu_caps(struct pmu *pmu)
6165 {
6166 struct pmu *dest_pmu = pmu ? pmu : x86_get_pmu(smp_processor_id());
6167
6168 if (hybrid(pmu, arch_pebs_cap).caps & ARCH_PEBS_VECR_XMM)
6169 dest_pmu->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
6170 }
6171
__intel_update_large_pebs_flags(struct pmu * pmu)6172 static inline void __intel_update_large_pebs_flags(struct pmu *pmu)
6173 {
6174 u64 caps = hybrid(pmu, arch_pebs_cap).caps;
6175
6176 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
6177 if (caps & ARCH_PEBS_LBR)
6178 x86_pmu.large_pebs_flags |= PERF_SAMPLE_BRANCH_STACK;
6179 if (caps & ARCH_PEBS_CNTR_MASK)
6180 x86_pmu.large_pebs_flags |= PERF_SAMPLE_READ;
6181
6182 if (!(caps & ARCH_PEBS_AUX))
6183 x86_pmu.large_pebs_flags &= ~PERF_SAMPLE_DATA_SRC;
6184 if (!(caps & ARCH_PEBS_GPR)) {
6185 x86_pmu.large_pebs_flags &=
6186 ~(PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
6187 }
6188 }
6189
6190 #define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX_FIXED))
6191
update_pmu_cap_from_perfmonext(struct pmu * pmu)6192 static void update_pmu_cap_from_perfmonext(struct pmu *pmu)
6193 {
6194 unsigned int eax, ebx, ecx, edx;
6195 union cpuid35_eax eax_0;
6196 union cpuid35_ebx ebx_0;
6197 u64 cntrs_mask = 0;
6198 u64 pebs_mask = 0;
6199 u64 pdists_mask = 0;
6200
6201 cpuid(ARCH_PERFMON_EXT_LEAF, &eax_0.full, &ebx_0.full, &ecx, &edx);
6202
6203 if (ebx_0.split.umask2)
6204 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2;
6205 if (ebx_0.split.eq)
6206 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ;
6207 if (ebx_0.split.rdpmc_user_disable)
6208 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
6209
6210 if (eax_0.split.cntr_subleaf) {
6211 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
6212 &eax, &ebx, &ecx, &edx);
6213 hybrid(pmu, cntr_mask64) = eax;
6214 hybrid(pmu, fixed_cntr_mask64) = ebx;
6215 cntrs_mask = counter_mask(eax, ebx);
6216 }
6217
6218 if (eax_0.split.acr_subleaf) {
6219 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_ACR_LEAF,
6220 &eax, &ebx, &ecx, &edx);
6221 /* The mask of the counters which can be reloaded */
6222 hybrid(pmu, acr_cntr_mask64) = counter_mask(eax, ebx);
6223 /* The mask of the counters which can cause a reload of reloadable counters */
6224 hybrid(pmu, acr_cause_mask64) = counter_mask(ecx, edx);
6225 }
6226
6227 /* Bits[5:4] should be set simultaneously if arch-PEBS is supported */
6228 if (eax_0.split.pebs_caps_subleaf && eax_0.split.pebs_cnts_subleaf) {
6229 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_CAP_LEAF,
6230 &eax, &ebx, &ecx, &edx);
6231 hybrid(pmu, arch_pebs_cap).caps = (u64)ebx << 32;
6232
6233 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_COUNTER_LEAF,
6234 &eax, &ebx, &ecx, &edx);
6235 pebs_mask = counter_mask(eax, ecx);
6236 pdists_mask = counter_mask(ebx, edx);
6237 hybrid(pmu, arch_pebs_cap).counters = pebs_mask;
6238 hybrid(pmu, arch_pebs_cap).pdists = pdists_mask;
6239
6240 if (WARN_ON((pebs_mask | pdists_mask) & ~cntrs_mask)) {
6241 x86_pmu.arch_pebs = 0;
6242 } else {
6243 __intel_update_pmu_caps(pmu);
6244 __intel_update_large_pebs_flags(pmu);
6245 }
6246 } else {
6247 WARN_ON(x86_pmu.arch_pebs == 1);
6248 x86_pmu.arch_pebs = 0;
6249 }
6250 }
6251
intel_update_pmu_caps(struct pmu * pmu)6252 static void intel_update_pmu_caps(struct pmu *pmu)
6253 {
6254 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
6255 update_pmu_cap_from_perfmonext(pmu);
6256
6257 if (is_hybrid() && this_cpu_has(X86_FEATURE_PDCM)) {
6258 rdmsrq(MSR_IA32_PERF_CAPABILITIES,
6259 hybrid(pmu, intel_cap).capabilities);
6260
6261 /*
6262 * Restore perf_metrics on platforms with broken
6263 * perf_capablities.
6264 */
6265 if (intel_pmu_broken_perf_cap() &&
6266 hybrid_pmu(pmu)->pmu_type == hybrid_big)
6267 hybrid(pmu, intel_cap).perf_metrics = 1;
6268 }
6269 }
6270
intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu * pmu)6271 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu)
6272 {
6273 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64,
6274 &pmu->intel_ctrl);
6275 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
6276 pmu->unconstrained = (struct event_constraint)
6277 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
6278 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
6279
6280 if (pmu->intel_cap.perf_metrics)
6281 pmu->intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS;
6282 else
6283 pmu->intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;
6284
6285 pmu->pmu.capabilities |= PERF_PMU_CAP_MEDIATED_VPMU;
6286
6287 intel_pmu_check_event_constraints_all(&pmu->pmu);
6288
6289 intel_pmu_check_extra_regs(pmu->extra_regs);
6290 }
6291
find_hybrid_pmu_for_cpu(void)6292 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void)
6293 {
6294 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
6295 enum intel_cpu_type cpu_type = c->topo.intel_type;
6296 int i;
6297
6298 /*
6299 * This is running on a CPU model that is known to have hybrid
6300 * configurations. But the CPU told us it is not hybrid, shame
6301 * on it. There should be a fixup function provided for these
6302 * troublesome CPUs (->get_hybrid_cpu_type).
6303 */
6304 if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) {
6305 if (x86_pmu.get_hybrid_cpu_type)
6306 cpu_type = x86_pmu.get_hybrid_cpu_type();
6307 else
6308 return NULL;
6309 }
6310
6311 /*
6312 * This essentially just maps between the 'hybrid_cpu_type'
6313 * and 'hybrid_pmu_type' enums except for ARL-H processor
6314 * which needs to compare atom uarch native id since ARL-H
6315 * contains two different atom uarchs.
6316 */
6317 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
6318 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type;
6319 u32 native_id;
6320
6321 if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big)
6322 return &x86_pmu.hybrid_pmu[i];
6323 if (cpu_type == INTEL_CPU_TYPE_ATOM) {
6324 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small)
6325 return &x86_pmu.hybrid_pmu[i];
6326
6327 native_id = c->topo.intel_native_model_id;
6328 if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small)
6329 return &x86_pmu.hybrid_pmu[i];
6330 if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny)
6331 return &x86_pmu.hybrid_pmu[i];
6332 }
6333 }
6334
6335 return NULL;
6336 }
6337
init_hybrid_pmu(int cpu)6338 static bool init_hybrid_pmu(int cpu)
6339 {
6340 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6341 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu();
6342
6343 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
6344 cpuc->pmu = NULL;
6345 return false;
6346 }
6347
6348 /* Only check and dump the PMU information for the first CPU */
6349 if (!cpumask_empty(&pmu->supported_cpus))
6350 goto end;
6351
6352 intel_update_pmu_caps(&pmu->pmu);
6353 intel_pmu_check_hybrid_pmus(pmu);
6354
6355 if (!check_hw_exists(pmu->cntr_mask, pmu->fixed_cntr_mask)) {
6356 cpuc->pmu = NULL;
6357 return false;
6358 }
6359
6360 pr_info("%s PMU driver: ", pmu->name);
6361
6362 pr_cont("\n");
6363
6364 x86_pmu_show_pmu_cap(&pmu->pmu);
6365
6366 end:
6367 cpumask_set_cpu(cpu, &pmu->supported_cpus);
6368 cpuc->pmu = &pmu->pmu;
6369
6370 return true;
6371 }
6372
intel_pmu_cpu_starting(int cpu)6373 static void intel_pmu_cpu_starting(int cpu)
6374 {
6375 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6376 int core_id = topology_core_id(cpu);
6377 int i;
6378
6379 if (is_hybrid() && !init_hybrid_pmu(cpu))
6380 return;
6381
6382 init_debug_store_on_cpu(cpu);
6383 init_arch_pebs_on_cpu(cpu);
6384 /*
6385 * Deal with CPUs that don't clear their LBRs on power-up, and that may
6386 * even boot with LBRs enabled.
6387 */
6388 if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr)
6389 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT);
6390 intel_pmu_lbr_reset();
6391
6392 cpuc->lbr_sel = NULL;
6393
6394 if (x86_pmu.flags & PMU_FL_TFA) {
6395 WARN_ON_ONCE(cpuc->tfa_shadow);
6396 cpuc->tfa_shadow = ~0ULL;
6397 intel_set_tfa(cpuc, false);
6398 }
6399
6400 if (x86_pmu.version > 1)
6401 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
6402
6403 /*
6404 * Disable perf metrics if any added CPU doesn't support it.
6405 *
6406 * Turn off the check for a hybrid architecture, because the
6407 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
6408 * the architecture features. The perf metrics is a model-specific
6409 * feature for now. The corresponding bit should always be 0 on
6410 * a hybrid platform, e.g., Alder Lake.
6411 */
6412 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
6413 union perf_capabilities perf_cap;
6414
6415 rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
6416 if (!perf_cap.perf_metrics) {
6417 x86_pmu.intel_cap.perf_metrics = 0;
6418 x86_pmu.intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;
6419 }
6420 }
6421
6422 __intel_update_pmu_caps(cpuc->pmu);
6423
6424 if (!cpuc->shared_regs)
6425 return;
6426
6427 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
6428 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
6429 struct intel_shared_regs *pc;
6430
6431 pc = per_cpu(cpu_hw_events, i).shared_regs;
6432 if (pc && pc->core_id == core_id) {
6433 cpuc->kfree_on_online[0] = cpuc->shared_regs;
6434 cpuc->shared_regs = pc;
6435 break;
6436 }
6437 }
6438 cpuc->shared_regs->core_id = core_id;
6439 cpuc->shared_regs->refcnt++;
6440 }
6441
6442 if (x86_pmu.lbr_sel_map)
6443 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
6444
6445 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
6446 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
6447 struct cpu_hw_events *sibling;
6448 struct intel_excl_cntrs *c;
6449
6450 sibling = &per_cpu(cpu_hw_events, i);
6451 c = sibling->excl_cntrs;
6452 if (c && c->core_id == core_id) {
6453 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
6454 cpuc->excl_cntrs = c;
6455 if (!sibling->excl_thread_id)
6456 cpuc->excl_thread_id = 1;
6457 break;
6458 }
6459 }
6460 cpuc->excl_cntrs->core_id = core_id;
6461 cpuc->excl_cntrs->refcnt++;
6462 }
6463 }
6464
free_excl_cntrs(struct cpu_hw_events * cpuc)6465 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
6466 {
6467 struct intel_excl_cntrs *c;
6468
6469 c = cpuc->excl_cntrs;
6470 if (c) {
6471 if (c->core_id == -1 || --c->refcnt == 0)
6472 kfree(c);
6473 cpuc->excl_cntrs = NULL;
6474 }
6475
6476 kfree(cpuc->constraint_list);
6477 cpuc->constraint_list = NULL;
6478 }
6479
intel_pmu_cpu_dying(int cpu)6480 static void intel_pmu_cpu_dying(int cpu)
6481 {
6482 fini_debug_store_on_cpu(cpu);
6483 fini_arch_pebs_on_cpu(cpu);
6484 }
6485
intel_cpuc_finish(struct cpu_hw_events * cpuc)6486 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
6487 {
6488 struct intel_shared_regs *pc;
6489
6490 pc = cpuc->shared_regs;
6491 if (pc) {
6492 if (pc->core_id == -1 || --pc->refcnt == 0)
6493 kfree(pc);
6494 cpuc->shared_regs = NULL;
6495 }
6496
6497 free_excl_cntrs(cpuc);
6498 }
6499
intel_pmu_cpu_dead(int cpu)6500 static void intel_pmu_cpu_dead(int cpu)
6501 {
6502 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6503 struct pmu *pmu = x86_get_static_pmu();
6504
6505 release_arch_pebs_buf_on_cpu(cpu);
6506 intel_cpuc_finish(cpuc);
6507
6508 if (is_hybrid() && cpuc->pmu && cpuc->pmu != pmu)
6509 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
6510 }
6511
intel_pmu_sched_task(struct perf_event_pmu_context * pmu_ctx,struct task_struct * task,bool sched_in)6512 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
6513 struct task_struct *task, bool sched_in)
6514 {
6515 intel_pmu_pebs_sched_task(pmu_ctx, sched_in);
6516 intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in);
6517 }
6518
intel_pmu_check_period(struct perf_event * event,u64 value)6519 static int intel_pmu_check_period(struct perf_event *event, u64 value)
6520 {
6521 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
6522 }
6523
intel_aux_output_init(void)6524 static void intel_aux_output_init(void)
6525 {
6526 /* Refer also intel_pmu_aux_output_match() */
6527 if (x86_pmu.intel_cap.pebs_output_pt_available)
6528 x86_pmu.assign = intel_pmu_assign_event;
6529 }
6530
intel_pmu_aux_output_match(struct perf_event * event)6531 static int intel_pmu_aux_output_match(struct perf_event *event)
6532 {
6533 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
6534 if (!x86_pmu.intel_cap.pebs_output_pt_available)
6535 return 0;
6536
6537 return is_intel_pt_event(event);
6538 }
6539
intel_pmu_filter(struct pmu * pmu,int cpu,bool * ret)6540 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
6541 {
6542 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu);
6543
6544 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus);
6545 }
6546
6547 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
6548
6549 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
6550
6551 PMU_FORMAT_ATTR(frontend, "config1:0-23");
6552
6553 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
6554
6555 static struct attribute *intel_arch3_formats_attr[] = {
6556 &format_attr_event.attr,
6557 &format_attr_umask.attr,
6558 &format_attr_edge.attr,
6559 &format_attr_pc.attr,
6560 &format_attr_any.attr,
6561 &format_attr_inv.attr,
6562 &format_attr_cmask.attr,
6563 NULL,
6564 };
6565
6566 static struct attribute *hsw_format_attr[] = {
6567 &format_attr_in_tx.attr,
6568 &format_attr_in_tx_cp.attr,
6569 &format_attr_offcore_rsp.attr,
6570 &format_attr_ldlat.attr,
6571 NULL
6572 };
6573
6574 static struct attribute *nhm_format_attr[] = {
6575 &format_attr_offcore_rsp.attr,
6576 &format_attr_ldlat.attr,
6577 NULL
6578 };
6579
6580 static struct attribute *slm_format_attr[] = {
6581 &format_attr_offcore_rsp.attr,
6582 NULL
6583 };
6584
6585 static struct attribute *cmt_format_attr[] = {
6586 &format_attr_offcore_rsp.attr,
6587 &format_attr_ldlat.attr,
6588 &format_attr_snoop_rsp.attr,
6589 NULL
6590 };
6591
6592 static struct attribute *skl_format_attr[] = {
6593 &format_attr_frontend.attr,
6594 NULL,
6595 };
6596
6597 static __initconst const struct x86_pmu core_pmu = {
6598 .name = "core",
6599 .handle_irq = x86_pmu_handle_irq,
6600 .disable_all = x86_pmu_disable_all,
6601 .enable_all = core_pmu_enable_all,
6602 .enable = core_pmu_enable_event,
6603 .disable = x86_pmu_disable_event,
6604 .hw_config = core_pmu_hw_config,
6605 .schedule_events = x86_schedule_events,
6606 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
6607 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
6608 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
6609 .event_map = intel_pmu_event_map,
6610 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
6611 .apic = 1,
6612 .large_pebs_flags = LARGE_PEBS_FLAGS,
6613
6614 /*
6615 * Intel PMCs cannot be accessed sanely above 32-bit width,
6616 * so we install an artificial 1<<31 period regardless of
6617 * the generic event period:
6618 */
6619 .max_period = (1ULL<<31) - 1,
6620 .get_event_constraints = intel_get_event_constraints,
6621 .put_event_constraints = intel_put_event_constraints,
6622 .event_constraints = intel_core_event_constraints,
6623 .guest_get_msrs = core_guest_get_msrs,
6624 .format_attrs = intel_arch_formats_attr,
6625 .events_sysfs_show = intel_event_sysfs_show,
6626
6627 /*
6628 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
6629 * together with PMU version 1 and thus be using core_pmu with
6630 * shared_regs. We need following callbacks here to allocate
6631 * it properly.
6632 */
6633 .cpu_prepare = intel_pmu_cpu_prepare,
6634 .cpu_starting = intel_pmu_cpu_starting,
6635 .cpu_dying = intel_pmu_cpu_dying,
6636 .cpu_dead = intel_pmu_cpu_dead,
6637
6638 .check_period = intel_pmu_check_period,
6639
6640 .lbr_reset = intel_pmu_lbr_reset_64,
6641 .lbr_read = intel_pmu_lbr_read_64,
6642 .lbr_save = intel_pmu_lbr_save,
6643 .lbr_restore = intel_pmu_lbr_restore,
6644 };
6645
6646 static __initconst const struct x86_pmu intel_pmu = {
6647 .name = "Intel",
6648 .handle_irq = intel_pmu_handle_irq,
6649 .disable_all = intel_pmu_disable_all,
6650 .enable_all = intel_pmu_enable_all,
6651 .enable = intel_pmu_enable_event,
6652 .disable = intel_pmu_disable_event,
6653 .add = intel_pmu_add_event,
6654 .del = intel_pmu_del_event,
6655 .read = intel_pmu_read_event,
6656 .set_period = intel_pmu_set_period,
6657 .update = intel_pmu_update,
6658 .hw_config = intel_pmu_hw_config,
6659 .schedule_events = x86_schedule_events,
6660 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
6661 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
6662 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
6663 .event_map = intel_pmu_event_map,
6664 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
6665 .apic = 1,
6666 .large_pebs_flags = LARGE_PEBS_FLAGS,
6667 /*
6668 * Intel PMCs cannot be accessed sanely above 32 bit width,
6669 * so we install an artificial 1<<31 period regardless of
6670 * the generic event period:
6671 */
6672 .max_period = (1ULL << 31) - 1,
6673 .get_event_constraints = intel_get_event_constraints,
6674 .put_event_constraints = intel_put_event_constraints,
6675 .pebs_aliases = intel_pebs_aliases_core2,
6676
6677 .format_attrs = intel_arch3_formats_attr,
6678 .events_sysfs_show = intel_event_sysfs_show,
6679
6680 .cpu_prepare = intel_pmu_cpu_prepare,
6681 .cpu_starting = intel_pmu_cpu_starting,
6682 .cpu_dying = intel_pmu_cpu_dying,
6683 .cpu_dead = intel_pmu_cpu_dead,
6684
6685 .guest_get_msrs = intel_guest_get_msrs,
6686 .sched_task = intel_pmu_sched_task,
6687
6688 .check_period = intel_pmu_check_period,
6689
6690 .aux_output_match = intel_pmu_aux_output_match,
6691
6692 .lbr_reset = intel_pmu_lbr_reset_64,
6693 .lbr_read = intel_pmu_lbr_read_64,
6694 .lbr_save = intel_pmu_lbr_save,
6695 .lbr_restore = intel_pmu_lbr_restore,
6696
6697 /*
6698 * SMM has access to all 4 rings and while traditionally SMM code only
6699 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
6700 *
6701 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
6702 * between SMM or not, this results in what should be pure userspace
6703 * counters including SMM data.
6704 *
6705 * This is a clear privilege issue, therefore globally disable
6706 * counting SMM by default.
6707 */
6708 .attr_freeze_on_smi = 1,
6709 };
6710
intel_clovertown_quirk(void)6711 static __init void intel_clovertown_quirk(void)
6712 {
6713 /*
6714 * PEBS is unreliable due to:
6715 *
6716 * AJ67 - PEBS may experience CPL leaks
6717 * AJ68 - PEBS PMI may be delayed by one event
6718 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
6719 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
6720 *
6721 * AJ67 could be worked around by restricting the OS/USR flags.
6722 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
6723 *
6724 * AJ106 could possibly be worked around by not allowing LBR
6725 * usage from PEBS, including the fixup.
6726 * AJ68 could possibly be worked around by always programming
6727 * a pebs_event_reset[0] value and coping with the lost events.
6728 *
6729 * But taken together it might just make sense to not enable PEBS on
6730 * these chips.
6731 */
6732 pr_warn("PEBS disabled due to CPU errata\n");
6733 x86_pmu.ds_pebs = 0;
6734 x86_pmu.pebs_constraints = NULL;
6735 }
6736
6737 static const struct x86_cpu_id isolation_ucodes[] = {
6738 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f),
6739 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e),
6740 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015),
6741 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037),
6742 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a),
6743 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023),
6744 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014),
6745 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010),
6746 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009),
6747 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009),
6748 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002),
6749 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014),
6750 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021),
6751 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000),
6752 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000),
6753 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c),
6754 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c),
6755 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e),
6756 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e),
6757 {}
6758 };
6759
intel_check_pebs_isolation(void)6760 static void intel_check_pebs_isolation(void)
6761 {
6762 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes);
6763 }
6764
intel_pebs_isolation_quirk(void)6765 static __init void intel_pebs_isolation_quirk(void)
6766 {
6767 WARN_ON_ONCE(x86_pmu.check_microcode);
6768 x86_pmu.check_microcode = intel_check_pebs_isolation;
6769 intel_check_pebs_isolation();
6770 }
6771
6772 static const struct x86_cpu_id pebs_ucodes[] = {
6773 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028),
6774 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618),
6775 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c),
6776 {}
6777 };
6778
intel_snb_pebs_broken(void)6779 static bool intel_snb_pebs_broken(void)
6780 {
6781 return !x86_match_min_microcode_rev(pebs_ucodes);
6782 }
6783
intel_snb_check_microcode(void)6784 static void intel_snb_check_microcode(void)
6785 {
6786 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
6787 return;
6788
6789 /*
6790 * Serialized by the microcode lock..
6791 */
6792 if (x86_pmu.pebs_broken) {
6793 pr_info("PEBS enabled due to microcode update\n");
6794 x86_pmu.pebs_broken = 0;
6795 } else {
6796 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
6797 x86_pmu.pebs_broken = 1;
6798 }
6799 }
6800
is_lbr_from(unsigned long msr)6801 static bool is_lbr_from(unsigned long msr)
6802 {
6803 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
6804
6805 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
6806 }
6807
6808 /*
6809 * Under certain circumstances, access certain MSR may cause #GP.
6810 * The function tests if the input MSR can be safely accessed.
6811 */
check_msr(unsigned long msr,u64 mask)6812 static bool check_msr(unsigned long msr, u64 mask)
6813 {
6814 u64 val_old, val_new, val_tmp;
6815
6816 /*
6817 * Disable the check for real HW, so we don't
6818 * mess with potentially enabled registers:
6819 */
6820 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
6821 return true;
6822
6823 /*
6824 * Read the current value, change it and read it back to see if it
6825 * matches, this is needed to detect certain hardware emulators
6826 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
6827 */
6828 if (rdmsrq_safe(msr, &val_old))
6829 return false;
6830
6831 /*
6832 * Only change the bits which can be updated by wrmsrq.
6833 */
6834 val_tmp = val_old ^ mask;
6835
6836 if (is_lbr_from(msr))
6837 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
6838
6839 if (wrmsrq_safe(msr, val_tmp) ||
6840 rdmsrq_safe(msr, &val_new))
6841 return false;
6842
6843 /*
6844 * Quirk only affects validation in wrmsr(), so wrmsrq()'s value
6845 * should equal rdmsrq()'s even with the quirk.
6846 */
6847 if (val_new != val_tmp)
6848 return false;
6849
6850 if (is_lbr_from(msr))
6851 val_old = lbr_from_signext_quirk_wr(val_old);
6852
6853 /* Here it's sure that the MSR can be safely accessed.
6854 * Restore the old value and return.
6855 */
6856 wrmsrq(msr, val_old);
6857
6858 return true;
6859 }
6860
intel_sandybridge_quirk(void)6861 static __init void intel_sandybridge_quirk(void)
6862 {
6863 x86_pmu.check_microcode = intel_snb_check_microcode;
6864 cpus_read_lock();
6865 intel_snb_check_microcode();
6866 cpus_read_unlock();
6867 }
6868
6869 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
6870 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
6871 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
6872 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
6873 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
6874 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
6875 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
6876 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
6877 };
6878
intel_arch_events_quirk(void)6879 static __init void intel_arch_events_quirk(void)
6880 {
6881 int bit;
6882
6883 /* disable event that reported as not present by cpuid */
6884 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
6885 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
6886 pr_warn("CPUID marked event: \'%s\' unavailable\n",
6887 intel_arch_events_map[bit].name);
6888 }
6889 }
6890
intel_nehalem_quirk(void)6891 static __init void intel_nehalem_quirk(void)
6892 {
6893 union cpuid10_ebx ebx;
6894
6895 ebx.full = x86_pmu.events_maskl;
6896 if (ebx.split.no_branch_misses_retired) {
6897 /*
6898 * Erratum AAJ80 detected, we work it around by using
6899 * the BR_MISP_EXEC.ANY event. This will over-count
6900 * branch-misses, but it's still much better than the
6901 * architectural event which is often completely bogus:
6902 */
6903 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
6904 ebx.split.no_branch_misses_retired = 0;
6905 x86_pmu.events_maskl = ebx.full;
6906 pr_info("CPU erratum AAJ80 worked around\n");
6907 }
6908 }
6909
6910 /*
6911 * enable software workaround for errata:
6912 * SNB: BJ122
6913 * IVB: BV98
6914 * HSW: HSD29
6915 *
6916 * Only needed when HT is enabled. However detecting
6917 * if HT is enabled is difficult (model specific). So instead,
6918 * we enable the workaround in the early boot, and verify if
6919 * it is needed in a later initcall phase once we have valid
6920 * topology information to check if HT is actually enabled
6921 */
intel_ht_bug(void)6922 static __init void intel_ht_bug(void)
6923 {
6924 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
6925
6926 x86_pmu.start_scheduling = intel_start_scheduling;
6927 x86_pmu.commit_scheduling = intel_commit_scheduling;
6928 x86_pmu.stop_scheduling = intel_stop_scheduling;
6929 }
6930
6931 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
6932 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
6933
6934 /* Haswell special events */
6935 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
6936 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
6937 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
6938 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
6939 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
6940 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
6941 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
6942 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
6943 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
6944 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
6945 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
6946 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
6947
6948 static struct attribute *hsw_events_attrs[] = {
6949 EVENT_PTR(td_slots_issued),
6950 EVENT_PTR(td_slots_retired),
6951 EVENT_PTR(td_fetch_bubbles),
6952 EVENT_PTR(td_total_slots),
6953 EVENT_PTR(td_total_slots_scale),
6954 EVENT_PTR(td_recovery_bubbles),
6955 EVENT_PTR(td_recovery_bubbles_scale),
6956 NULL
6957 };
6958
6959 static struct attribute *hsw_mem_events_attrs[] = {
6960 EVENT_PTR(mem_ld_hsw),
6961 EVENT_PTR(mem_st_hsw),
6962 NULL,
6963 };
6964
6965 static struct attribute *hsw_tsx_events_attrs[] = {
6966 EVENT_PTR(tx_start),
6967 EVENT_PTR(tx_commit),
6968 EVENT_PTR(tx_abort),
6969 EVENT_PTR(tx_capacity),
6970 EVENT_PTR(tx_conflict),
6971 EVENT_PTR(el_start),
6972 EVENT_PTR(el_commit),
6973 EVENT_PTR(el_abort),
6974 EVENT_PTR(el_capacity),
6975 EVENT_PTR(el_conflict),
6976 EVENT_PTR(cycles_t),
6977 EVENT_PTR(cycles_ct),
6978 NULL
6979 };
6980
6981 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
6982 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
6983 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
6984 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
6985
6986 static struct attribute *icl_events_attrs[] = {
6987 EVENT_PTR(mem_ld_hsw),
6988 EVENT_PTR(mem_st_hsw),
6989 NULL,
6990 };
6991
6992 static struct attribute *icl_td_events_attrs[] = {
6993 EVENT_PTR(slots),
6994 EVENT_PTR(td_retiring),
6995 EVENT_PTR(td_bad_spec),
6996 EVENT_PTR(td_fe_bound),
6997 EVENT_PTR(td_be_bound),
6998 NULL,
6999 };
7000
7001 static struct attribute *icl_tsx_events_attrs[] = {
7002 EVENT_PTR(tx_start),
7003 EVENT_PTR(tx_abort),
7004 EVENT_PTR(tx_commit),
7005 EVENT_PTR(tx_capacity_read),
7006 EVENT_PTR(tx_capacity_write),
7007 EVENT_PTR(tx_conflict),
7008 EVENT_PTR(el_start),
7009 EVENT_PTR(el_abort),
7010 EVENT_PTR(el_commit),
7011 EVENT_PTR(el_capacity_read),
7012 EVENT_PTR(el_capacity_write),
7013 EVENT_PTR(el_conflict),
7014 EVENT_PTR(cycles_t),
7015 EVENT_PTR(cycles_ct),
7016 NULL,
7017 };
7018
7019
7020 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
7021 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
7022
7023 static struct attribute *glc_events_attrs[] = {
7024 EVENT_PTR(mem_ld_hsw),
7025 EVENT_PTR(mem_st_spr),
7026 EVENT_PTR(mem_ld_aux),
7027 NULL,
7028 };
7029
7030 static struct attribute *glc_td_events_attrs[] = {
7031 EVENT_PTR(slots),
7032 EVENT_PTR(td_retiring),
7033 EVENT_PTR(td_bad_spec),
7034 EVENT_PTR(td_fe_bound),
7035 EVENT_PTR(td_be_bound),
7036 EVENT_PTR(td_heavy_ops),
7037 EVENT_PTR(td_br_mispredict),
7038 EVENT_PTR(td_fetch_lat),
7039 EVENT_PTR(td_mem_bound),
7040 NULL,
7041 };
7042
7043 static struct attribute *glc_tsx_events_attrs[] = {
7044 EVENT_PTR(tx_start),
7045 EVENT_PTR(tx_abort),
7046 EVENT_PTR(tx_commit),
7047 EVENT_PTR(tx_capacity_read),
7048 EVENT_PTR(tx_capacity_write),
7049 EVENT_PTR(tx_conflict),
7050 EVENT_PTR(cycles_t),
7051 EVENT_PTR(cycles_ct),
7052 NULL,
7053 };
7054
freeze_on_smi_show(struct device * cdev,struct device_attribute * attr,char * buf)7055 static ssize_t freeze_on_smi_show(struct device *cdev,
7056 struct device_attribute *attr,
7057 char *buf)
7058 {
7059 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
7060 }
7061
7062 static DEFINE_MUTEX(freeze_on_smi_mutex);
7063
freeze_on_smi_store(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)7064 static ssize_t freeze_on_smi_store(struct device *cdev,
7065 struct device_attribute *attr,
7066 const char *buf, size_t count)
7067 {
7068 unsigned long val;
7069 ssize_t ret;
7070
7071 ret = kstrtoul(buf, 0, &val);
7072 if (ret)
7073 return ret;
7074
7075 if (val > 1)
7076 return -EINVAL;
7077
7078 mutex_lock(&freeze_on_smi_mutex);
7079
7080 if (x86_pmu.attr_freeze_on_smi == val)
7081 goto done;
7082
7083 x86_pmu.attr_freeze_on_smi = val;
7084
7085 cpus_read_lock();
7086 on_each_cpu(flip_smm_bit, &val, 1);
7087 cpus_read_unlock();
7088 done:
7089 mutex_unlock(&freeze_on_smi_mutex);
7090
7091 return count;
7092 }
7093
update_tfa_sched(void * ignored)7094 static void update_tfa_sched(void *ignored)
7095 {
7096 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
7097
7098 /*
7099 * check if PMC3 is used
7100 * and if so force schedule out for all event types all contexts
7101 */
7102 if (test_bit(3, cpuc->active_mask))
7103 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
7104 }
7105
show_sysctl_tfa(struct device * cdev,struct device_attribute * attr,char * buf)7106 static ssize_t show_sysctl_tfa(struct device *cdev,
7107 struct device_attribute *attr,
7108 char *buf)
7109 {
7110 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
7111 }
7112
set_sysctl_tfa(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)7113 static ssize_t set_sysctl_tfa(struct device *cdev,
7114 struct device_attribute *attr,
7115 const char *buf, size_t count)
7116 {
7117 bool val;
7118 ssize_t ret;
7119
7120 ret = kstrtobool(buf, &val);
7121 if (ret)
7122 return ret;
7123
7124 /* no change */
7125 if (val == allow_tsx_force_abort)
7126 return count;
7127
7128 allow_tsx_force_abort = val;
7129
7130 cpus_read_lock();
7131 on_each_cpu(update_tfa_sched, NULL, 1);
7132 cpus_read_unlock();
7133
7134 return count;
7135 }
7136
7137
7138 static DEVICE_ATTR_RW(freeze_on_smi);
7139
branches_show(struct device * cdev,struct device_attribute * attr,char * buf)7140 static ssize_t branches_show(struct device *cdev,
7141 struct device_attribute *attr,
7142 char *buf)
7143 {
7144 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
7145 }
7146
7147 static DEVICE_ATTR_RO(branches);
7148
branch_counter_nr_show(struct device * cdev,struct device_attribute * attr,char * buf)7149 static ssize_t branch_counter_nr_show(struct device *cdev,
7150 struct device_attribute *attr,
7151 char *buf)
7152 {
7153 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters));
7154 }
7155
7156 static DEVICE_ATTR_RO(branch_counter_nr);
7157
branch_counter_width_show(struct device * cdev,struct device_attribute * attr,char * buf)7158 static ssize_t branch_counter_width_show(struct device *cdev,
7159 struct device_attribute *attr,
7160 char *buf)
7161 {
7162 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS);
7163 }
7164
7165 static DEVICE_ATTR_RO(branch_counter_width);
7166
7167 static struct attribute *lbr_attrs[] = {
7168 &dev_attr_branches.attr,
7169 &dev_attr_branch_counter_nr.attr,
7170 &dev_attr_branch_counter_width.attr,
7171 NULL
7172 };
7173
7174 static umode_t
lbr_is_visible(struct kobject * kobj,struct attribute * attr,int i)7175 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7176 {
7177 /* branches */
7178 if (i == 0)
7179 return x86_pmu.lbr_nr ? attr->mode : 0;
7180
7181 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0;
7182 }
7183
7184 static char pmu_name_str[30];
7185
7186 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str);
7187
7188 static struct attribute *intel_pmu_caps_attrs[] = {
7189 &dev_attr_pmu_name.attr.attr,
7190 NULL
7191 };
7192
7193 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
7194 show_sysctl_tfa,
7195 set_sysctl_tfa);
7196
7197 static struct attribute *intel_pmu_attrs[] = {
7198 &dev_attr_freeze_on_smi.attr,
7199 &dev_attr_allow_tsx_force_abort.attr,
7200 NULL,
7201 };
7202
7203 static umode_t
default_is_visible(struct kobject * kobj,struct attribute * attr,int i)7204 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7205 {
7206 if (attr == &dev_attr_allow_tsx_force_abort.attr)
7207 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
7208
7209 return attr->mode;
7210 }
7211
7212 static umode_t
tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)7213 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7214 {
7215 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
7216 }
7217
7218 static umode_t
pebs_is_visible(struct kobject * kobj,struct attribute * attr,int i)7219 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7220 {
7221 return intel_pmu_has_pebs() ? attr->mode : 0;
7222 }
7223
7224 static umode_t
mem_is_visible(struct kobject * kobj,struct attribute * attr,int i)7225 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7226 {
7227 if (attr == &event_attr_mem_ld_aux.attr.attr)
7228 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;
7229
7230 return pebs_is_visible(kobj, attr, i);
7231 }
7232
7233 static umode_t
exra_is_visible(struct kobject * kobj,struct attribute * attr,int i)7234 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7235 {
7236 return x86_pmu.version >= 2 ? attr->mode : 0;
7237 }
7238
7239 static umode_t
td_is_visible(struct kobject * kobj,struct attribute * attr,int i)7240 td_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7241 {
7242 /*
7243 * Hide the perf metrics topdown events
7244 * if the feature is not enumerated.
7245 */
7246 if (x86_pmu.num_topdown_events)
7247 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0;
7248
7249 return attr->mode;
7250 }
7251
7252 PMU_FORMAT_ATTR(acr_mask, "config2:0-63");
7253
7254 static struct attribute *format_acr_attrs[] = {
7255 &format_attr_acr_mask.attr,
7256 NULL
7257 };
7258
7259 static umode_t
acr_is_visible(struct kobject * kobj,struct attribute * attr,int i)7260 acr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7261 {
7262 struct device *dev = kobj_to_dev(kobj);
7263
7264 return intel_pmu_has_acr(dev_get_drvdata(dev)) ? attr->mode : 0;
7265 }
7266
7267 static struct attribute_group group_events_td = {
7268 .name = "events",
7269 .is_visible = td_is_visible,
7270 };
7271
7272 static struct attribute_group group_events_mem = {
7273 .name = "events",
7274 .is_visible = mem_is_visible,
7275 };
7276
7277 static struct attribute_group group_events_tsx = {
7278 .name = "events",
7279 .is_visible = tsx_is_visible,
7280 };
7281
7282 static struct attribute_group group_caps_gen = {
7283 .name = "caps",
7284 .attrs = intel_pmu_caps_attrs,
7285 };
7286
7287 static struct attribute_group group_caps_lbr = {
7288 .name = "caps",
7289 .attrs = lbr_attrs,
7290 .is_visible = lbr_is_visible,
7291 };
7292
7293 static struct attribute_group group_format_extra = {
7294 .name = "format",
7295 .is_visible = exra_is_visible,
7296 };
7297
7298 static struct attribute_group group_format_extra_skl = {
7299 .name = "format",
7300 .is_visible = exra_is_visible,
7301 };
7302
7303 static struct attribute_group group_format_evtsel_ext = {
7304 .name = "format",
7305 .attrs = format_evtsel_ext_attrs,
7306 .is_visible = evtsel_ext_is_visible,
7307 };
7308
7309 static struct attribute_group group_format_acr = {
7310 .name = "format",
7311 .attrs = format_acr_attrs,
7312 .is_visible = acr_is_visible,
7313 };
7314
7315 static struct attribute_group group_default = {
7316 .attrs = intel_pmu_attrs,
7317 .is_visible = default_is_visible,
7318 };
7319
7320 static const struct attribute_group *attr_update[] = {
7321 &group_events_td,
7322 &group_events_mem,
7323 &group_events_tsx,
7324 &group_caps_gen,
7325 &group_caps_lbr,
7326 &group_format_extra,
7327 &group_format_extra_skl,
7328 &group_format_evtsel_ext,
7329 &group_format_acr,
7330 &group_default,
7331 NULL,
7332 };
7333
7334 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big);
7335 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
7336 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
7337 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
7338 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
7339 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big);
7340 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big);
7341 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big);
7342 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big);
7343
7344 static struct attribute *adl_hybrid_events_attrs[] = {
7345 EVENT_PTR(slots_adl),
7346 EVENT_PTR(td_retiring_adl),
7347 EVENT_PTR(td_bad_spec_adl),
7348 EVENT_PTR(td_fe_bound_adl),
7349 EVENT_PTR(td_be_bound_adl),
7350 EVENT_PTR(td_heavy_ops_adl),
7351 EVENT_PTR(td_br_mis_adl),
7352 EVENT_PTR(td_fetch_lat_adl),
7353 EVENT_PTR(td_mem_bound_adl),
7354 NULL,
7355 };
7356
7357 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small);
7358 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small);
7359 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small);
7360
7361 static struct attribute *lnl_hybrid_events_attrs[] = {
7362 EVENT_PTR(slots_adl),
7363 EVENT_PTR(td_retiring_lnl),
7364 EVENT_PTR(td_bad_spec_adl),
7365 EVENT_PTR(td_fe_bound_lnl),
7366 EVENT_PTR(td_be_bound_lnl),
7367 EVENT_PTR(td_heavy_ops_adl),
7368 EVENT_PTR(td_br_mis_adl),
7369 EVENT_PTR(td_fetch_lat_adl),
7370 EVENT_PTR(td_mem_bound_adl),
7371 NULL
7372 };
7373
7374 /* The event string must be in PMU IDX order. */
7375 EVENT_ATTR_STR_HYBRID(topdown-retiring,
7376 td_retiring_arl_h,
7377 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0",
7378 hybrid_big_small_tiny);
7379 EVENT_ATTR_STR_HYBRID(topdown-bad-spec,
7380 td_bad_spec_arl_h,
7381 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0",
7382 hybrid_big_small_tiny);
7383 EVENT_ATTR_STR_HYBRID(topdown-fe-bound,
7384 td_fe_bound_arl_h,
7385 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0",
7386 hybrid_big_small_tiny);
7387 EVENT_ATTR_STR_HYBRID(topdown-be-bound,
7388 td_be_bound_arl_h,
7389 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0",
7390 hybrid_big_small_tiny);
7391
7392 static struct attribute *arl_h_hybrid_events_attrs[] = {
7393 EVENT_PTR(slots_adl),
7394 EVENT_PTR(td_retiring_arl_h),
7395 EVENT_PTR(td_bad_spec_arl_h),
7396 EVENT_PTR(td_fe_bound_arl_h),
7397 EVENT_PTR(td_be_bound_arl_h),
7398 EVENT_PTR(td_heavy_ops_adl),
7399 EVENT_PTR(td_br_mis_adl),
7400 EVENT_PTR(td_fetch_lat_adl),
7401 EVENT_PTR(td_mem_bound_adl),
7402 NULL,
7403 };
7404
7405 /* Must be in IDX order */
7406 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
7407 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
7408 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big);
7409
7410 static struct attribute *adl_hybrid_mem_attrs[] = {
7411 EVENT_PTR(mem_ld_adl),
7412 EVENT_PTR(mem_st_adl),
7413 EVENT_PTR(mem_ld_aux_adl),
7414 NULL,
7415 };
7416
7417 static struct attribute *mtl_hybrid_mem_attrs[] = {
7418 EVENT_PTR(mem_ld_adl),
7419 EVENT_PTR(mem_st_adl),
7420 NULL
7421 };
7422
7423 EVENT_ATTR_STR_HYBRID(mem-loads,
7424 mem_ld_arl_h,
7425 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3",
7426 hybrid_big_small_tiny);
7427 EVENT_ATTR_STR_HYBRID(mem-stores,
7428 mem_st_arl_h,
7429 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6",
7430 hybrid_big_small_tiny);
7431
7432 static struct attribute *arl_h_hybrid_mem_attrs[] = {
7433 EVENT_PTR(mem_ld_arl_h),
7434 EVENT_PTR(mem_st_arl_h),
7435 NULL,
7436 };
7437
7438 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
7439 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
7440 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
7441 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big);
7442 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big);
7443 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
7444 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big);
7445 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big);
7446
7447 static struct attribute *adl_hybrid_tsx_attrs[] = {
7448 EVENT_PTR(tx_start_adl),
7449 EVENT_PTR(tx_abort_adl),
7450 EVENT_PTR(tx_commit_adl),
7451 EVENT_PTR(tx_capacity_read_adl),
7452 EVENT_PTR(tx_capacity_write_adl),
7453 EVENT_PTR(tx_conflict_adl),
7454 EVENT_PTR(cycles_t_adl),
7455 EVENT_PTR(cycles_ct_adl),
7456 NULL,
7457 };
7458
7459 FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
7460 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
7461 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny);
7462 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny);
7463 FORMAT_ATTR_HYBRID(frontend, hybrid_big);
7464
7465 #define ADL_HYBRID_RTM_FORMAT_ATTR \
7466 FORMAT_HYBRID_PTR(in_tx), \
7467 FORMAT_HYBRID_PTR(in_tx_cp)
7468
7469 #define ADL_HYBRID_FORMAT_ATTR \
7470 FORMAT_HYBRID_PTR(offcore_rsp), \
7471 FORMAT_HYBRID_PTR(ldlat), \
7472 FORMAT_HYBRID_PTR(frontend)
7473
7474 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
7475 ADL_HYBRID_RTM_FORMAT_ATTR,
7476 ADL_HYBRID_FORMAT_ATTR,
7477 NULL
7478 };
7479
7480 static struct attribute *adl_hybrid_extra_attr[] = {
7481 ADL_HYBRID_FORMAT_ATTR,
7482 NULL
7483 };
7484
7485 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny);
7486
7487 static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
7488 ADL_HYBRID_RTM_FORMAT_ATTR,
7489 ADL_HYBRID_FORMAT_ATTR,
7490 FORMAT_HYBRID_PTR(snoop_rsp),
7491 NULL
7492 };
7493
7494 static struct attribute *mtl_hybrid_extra_attr[] = {
7495 ADL_HYBRID_FORMAT_ATTR,
7496 FORMAT_HYBRID_PTR(snoop_rsp),
7497 NULL
7498 };
7499
is_attr_for_this_pmu(struct kobject * kobj,struct attribute * attr)7500 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
7501 {
7502 struct device *dev = kobj_to_dev(kobj);
7503 struct x86_hybrid_pmu *pmu =
7504 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7505 struct perf_pmu_events_hybrid_attr *pmu_attr =
7506 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
7507
7508 return pmu->pmu_type & pmu_attr->pmu_type;
7509 }
7510
hybrid_events_is_visible(struct kobject * kobj,struct attribute * attr,int i)7511 static umode_t hybrid_events_is_visible(struct kobject *kobj,
7512 struct attribute *attr, int i)
7513 {
7514 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
7515 }
7516
hybrid_find_supported_cpu(struct x86_hybrid_pmu * pmu)7517 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
7518 {
7519 int cpu = cpumask_first(&pmu->supported_cpus);
7520
7521 return (cpu >= nr_cpu_ids) ? -1 : cpu;
7522 }
7523
hybrid_tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)7524 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
7525 struct attribute *attr, int i)
7526 {
7527 struct device *dev = kobj_to_dev(kobj);
7528 struct x86_hybrid_pmu *pmu =
7529 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7530 int cpu = hybrid_find_supported_cpu(pmu);
7531
7532 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
7533 }
7534
hybrid_format_is_visible(struct kobject * kobj,struct attribute * attr,int i)7535 static umode_t hybrid_format_is_visible(struct kobject *kobj,
7536 struct attribute *attr, int i)
7537 {
7538 struct device *dev = kobj_to_dev(kobj);
7539 struct x86_hybrid_pmu *pmu =
7540 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7541 struct perf_pmu_format_hybrid_attr *pmu_attr =
7542 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
7543 int cpu = hybrid_find_supported_cpu(pmu);
7544
7545 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0;
7546 }
7547
hybrid_td_is_visible(struct kobject * kobj,struct attribute * attr,int i)7548 static umode_t hybrid_td_is_visible(struct kobject *kobj,
7549 struct attribute *attr, int i)
7550 {
7551 struct device *dev = kobj_to_dev(kobj);
7552 struct x86_hybrid_pmu *pmu =
7553 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7554
7555 if (!is_attr_for_this_pmu(kobj, attr))
7556 return 0;
7557
7558
7559 /* Only the big core supports perf metrics */
7560 if (pmu->pmu_type == hybrid_big)
7561 return pmu->intel_cap.perf_metrics ? attr->mode : 0;
7562
7563 return attr->mode;
7564 }
7565
7566 static struct attribute_group hybrid_group_events_td = {
7567 .name = "events",
7568 .is_visible = hybrid_td_is_visible,
7569 };
7570
7571 static struct attribute_group hybrid_group_events_mem = {
7572 .name = "events",
7573 .is_visible = hybrid_events_is_visible,
7574 };
7575
7576 static struct attribute_group hybrid_group_events_tsx = {
7577 .name = "events",
7578 .is_visible = hybrid_tsx_is_visible,
7579 };
7580
7581 static struct attribute_group hybrid_group_format_extra = {
7582 .name = "format",
7583 .is_visible = hybrid_format_is_visible,
7584 };
7585
intel_hybrid_get_attr_cpus(struct device * dev,struct device_attribute * attr,char * buf)7586 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
7587 struct device_attribute *attr,
7588 char *buf)
7589 {
7590 struct x86_hybrid_pmu *pmu =
7591 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7592
7593 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(&pmu->supported_cpus));
7594 }
7595
7596 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
7597 static struct attribute *intel_hybrid_cpus_attrs[] = {
7598 &dev_attr_cpus.attr,
7599 NULL,
7600 };
7601
7602 static struct attribute_group hybrid_group_cpus = {
7603 .attrs = intel_hybrid_cpus_attrs,
7604 };
7605
7606 static const struct attribute_group *hybrid_attr_update[] = {
7607 &hybrid_group_events_td,
7608 &hybrid_group_events_mem,
7609 &hybrid_group_events_tsx,
7610 &group_caps_gen,
7611 &group_caps_lbr,
7612 &hybrid_group_format_extra,
7613 &group_format_evtsel_ext,
7614 &group_format_acr,
7615 &group_default,
7616 &hybrid_group_cpus,
7617 NULL,
7618 };
7619
7620 static struct attribute *empty_attrs;
7621
intel_pmu_check_event_constraints(struct event_constraint * event_constraints,u64 cntr_mask,u64 fixed_cntr_mask,u64 intel_ctrl)7622 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
7623 u64 cntr_mask,
7624 u64 fixed_cntr_mask,
7625 u64 intel_ctrl)
7626 {
7627 struct event_constraint *c;
7628
7629 if (!event_constraints)
7630 return;
7631
7632 /*
7633 * event on fixed counter2 (REF_CYCLES) only works on this
7634 * counter, so do not extend mask to generic counters
7635 */
7636 for_each_event_constraint(c, event_constraints) {
7637 /*
7638 * Don't extend the topdown slots and metrics
7639 * events to the generic counters.
7640 */
7641 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
7642 /*
7643 * Disable topdown slots and metrics events,
7644 * if slots event is not in CPUID.
7645 */
7646 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
7647 c->idxmsk64 = 0;
7648 c->weight = hweight64(c->idxmsk64);
7649 continue;
7650 }
7651
7652 if (c->cmask == FIXED_EVENT_FLAGS) {
7653 /* Disabled fixed counters which are not in CPUID */
7654 c->idxmsk64 &= intel_ctrl;
7655
7656 /*
7657 * Don't extend the pseudo-encoding to the
7658 * generic counters
7659 */
7660 if (!use_fixed_pseudo_encoding(c->code))
7661 c->idxmsk64 |= cntr_mask;
7662 }
7663 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED);
7664 c->weight = hweight64(c->idxmsk64);
7665 }
7666 }
7667
intel_pmu_check_extra_regs(struct extra_reg * extra_regs)7668 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
7669 {
7670 struct extra_reg *er;
7671
7672 /*
7673 * Access extra MSR may cause #GP under certain circumstances.
7674 * E.g. KVM doesn't support offcore event
7675 * Check all extra_regs here.
7676 */
7677 if (!extra_regs)
7678 return;
7679
7680 for (er = extra_regs; er->msr; er++) {
7681 er->extra_msr_access = check_msr(er->msr, 0x11UL);
7682 /* Disable LBR select mapping */
7683 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
7684 x86_pmu.lbr_sel_map = NULL;
7685 }
7686 }
7687
intel_pmu_v6_addr_offset(int index,bool eventsel)7688 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel)
7689 {
7690 return MSR_IA32_PMC_V6_STEP * index;
7691 }
7692
7693 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = {
7694 { hybrid_small, "cpu_atom" },
7695 { hybrid_big, "cpu_core" },
7696 { hybrid_tiny, "cpu_lowpower" },
7697 };
7698
intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)7699 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
7700 {
7701 unsigned long pmus_mask = pmus;
7702 struct x86_hybrid_pmu *pmu;
7703 int idx = 0, bit;
7704
7705 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask);
7706 x86_pmu.hybrid_pmu = kzalloc_objs(struct x86_hybrid_pmu,
7707 x86_pmu.num_hybrid_pmus);
7708 if (!x86_pmu.hybrid_pmu) {
7709 x86_pmu.num_hybrid_pmus = 0;
7710 return -ENOMEM;
7711 }
7712
7713 static_branch_enable(&perf_is_hybrid);
7714 x86_pmu.filter = intel_pmu_filter;
7715
7716 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) {
7717 pmu = &x86_pmu.hybrid_pmu[idx++];
7718 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id;
7719 pmu->name = intel_hybrid_pmu_type_map[bit].name;
7720
7721 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7722 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7723 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
7724 pmu->config_mask = X86_RAW_EVENT_MASK;
7725 pmu->unconstrained = (struct event_constraint)
7726 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
7727 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
7728
7729 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
7730 if (pmu->pmu_type & hybrid_small_tiny) {
7731 pmu->intel_cap.perf_metrics = 0;
7732 pmu->mid_ack = true;
7733 } else if (pmu->pmu_type & hybrid_big) {
7734 pmu->intel_cap.perf_metrics = 1;
7735 pmu->late_ack = true;
7736 }
7737 }
7738
7739 return 0;
7740 }
7741
intel_pmu_ref_cycles_ext(void)7742 static __always_inline void intel_pmu_ref_cycles_ext(void)
7743 {
7744 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))
7745 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c;
7746 }
7747
intel_pmu_init_glc(struct pmu * pmu)7748 static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
7749 {
7750 x86_pmu.late_ack = true;
7751 x86_pmu.limit_period = glc_limit_period;
7752 x86_pmu.pebs_aliases = NULL;
7753 x86_pmu.pebs_prec_dist = true;
7754 x86_pmu.pebs_block = true;
7755 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7756 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7757 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
7758 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
7759 x86_pmu.lbr_pt_coexist = true;
7760 x86_pmu.num_topdown_events = 8;
7761 static_call_update(intel_pmu_update_topdown_event,
7762 &icl_update_topdown_event);
7763 static_call_update(intel_pmu_set_topdown_event_period,
7764 &icl_set_topdown_event_period);
7765
7766 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7767 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7768 hybrid(pmu, event_constraints) = intel_glc_event_constraints;
7769 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;
7770
7771 intel_pmu_ref_cycles_ext();
7772 }
7773
intel_pmu_init_glc_hybrid(struct pmu * pmu)7774 static __always_inline void intel_pmu_init_glc_hybrid(struct pmu *pmu)
7775 {
7776 intel_pmu_init_glc(pmu);
7777
7778 /* ADL has different extra MSR values from Server for the L3 or node OCR/OMR events. */
7779 memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7780 memcpy(hybrid_var(pmu, hw_cache_extra_regs), adl_glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7781 }
7782
intel_pmu_init_grt(struct pmu * pmu)7783 static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
7784 {
7785 x86_pmu.mid_ack = true;
7786 x86_pmu.limit_period = glc_limit_period;
7787 x86_pmu.pebs_aliases = NULL;
7788 x86_pmu.pebs_prec_dist = true;
7789 x86_pmu.pebs_block = true;
7790 x86_pmu.lbr_pt_coexist = true;
7791 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7792 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
7793
7794 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7795 memcpy(hybrid_var(pmu, hw_cache_extra_regs), grt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7796 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7797 hybrid(pmu, event_constraints) = intel_grt_event_constraints;
7798 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
7799 hybrid(pmu, extra_regs) = intel_grt_extra_regs;
7800
7801 intel_pmu_ref_cycles_ext();
7802 }
7803
intel_pmu_init_cmt(struct pmu * pmu)7804 static __always_inline void intel_pmu_init_cmt(struct pmu *pmu)
7805 {
7806 intel_pmu_init_grt(pmu);
7807 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7808 cmt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7809 hybrid(pmu, pebs_constraints) = intel_cmt_pebs_event_constraints;
7810 hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
7811 }
7812
intel_pmu_init_lnc(struct pmu * pmu)7813 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
7814 {
7815 intel_pmu_init_glc(pmu);
7816 hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
7817 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
7818 hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
7819
7820 memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7821 memcpy(hybrid_var(pmu, hw_cache_extra_regs), lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7822 }
7823
intel_pmu_init_pnc(struct pmu * pmu)7824 static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)
7825 {
7826 intel_pmu_init_glc(pmu);
7827 x86_pmu.flags &= ~PMU_FL_HAS_RSP_1;
7828 x86_pmu.flags |= PMU_FL_HAS_OMR;
7829 memcpy(hybrid_var(pmu, hw_cache_event_ids),
7830 pnc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7831 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7832 pnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7833 hybrid(pmu, event_constraints) = intel_pnc_event_constraints;
7834 hybrid(pmu, pebs_constraints) = intel_pnc_pebs_event_constraints;
7835 hybrid(pmu, extra_regs) = intel_pnc_extra_regs;
7836 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7837 }
7838
intel_pmu_init_cyc(struct pmu * pmu)7839 static __always_inline void intel_pmu_init_cyc(struct pmu *pmu)
7840 {
7841 intel_pmu_init_pnc(pmu);
7842 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7843 cyc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7844 }
7845
intel_pmu_init_skt(struct pmu * pmu)7846 static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
7847 {
7848 intel_pmu_init_cmt(pmu);
7849 hybrid(pmu, event_constraints) = intel_skt_event_constraints;
7850 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7851 skt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7852 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7853 }
7854
7855 /* Hybrid client variant. */
intel_pmu_init_dkt_hybrid(struct pmu * pmu)7856 static __always_inline void intel_pmu_init_dkt_hybrid(struct pmu *pmu)
7857 {
7858 intel_pmu_init_skt(pmu);
7859 hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
7860 }
7861
7862 /*
7863 * Darkmont is used by the CWF and PTL E-cores, but their L3 OCR
7864 * events require different extra MSR values. Keep a separate init
7865 * function for the non-hybrid server variant.
7866 */
intel_pmu_init_dkt(struct pmu * pmu)7867 static __always_inline void intel_pmu_init_dkt(struct pmu *pmu)
7868 {
7869 intel_pmu_init_dkt_hybrid(pmu);
7870 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7871 dkt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7872 }
7873
intel_pmu_init_arw(struct pmu * pmu)7874 static __always_inline void intel_pmu_init_arw(struct pmu *pmu)
7875 {
7876 intel_pmu_init_grt(pmu);
7877 x86_pmu.flags &= ~PMU_FL_HAS_RSP_1;
7878 x86_pmu.flags |= PMU_FL_HAS_OMR;
7879 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7880 arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7881 hybrid(pmu, event_constraints) = intel_arw_event_constraints;
7882 hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
7883 hybrid(pmu, extra_regs) = intel_arw_extra_regs;
7884 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7885 }
7886
intel_pmu_init(void)7887 __init int intel_pmu_init(void)
7888 {
7889 struct attribute **extra_skl_attr = &empty_attrs;
7890 struct attribute **extra_attr = &empty_attrs;
7891 struct attribute **td_attr = &empty_attrs;
7892 struct attribute **mem_attr = &empty_attrs;
7893 struct attribute **tsx_attr = &empty_attrs;
7894 struct x86_hybrid_pmu *pmu;
7895 unsigned int fixed_mask;
7896 union cpuid10_edx edx;
7897 union cpuid10_eax eax;
7898 union cpuid10_ebx ebx;
7899 int version, i, ret;
7900 bool pmem = false;
7901 char *name;
7902
7903 /* Architectural Perfmon was introduced starting with Core "Yonah" */
7904 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
7905 switch (boot_cpu_data.x86) {
7906 case 6:
7907 if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH)
7908 return p6_pmu_init();
7909 break;
7910 case 11:
7911 return knc_pmu_init();
7912 case 15:
7913 return p4_pmu_init();
7914 }
7915
7916 pr_cont("unsupported CPU family %d model %d ",
7917 boot_cpu_data.x86, boot_cpu_data.x86_model);
7918 return -ENODEV;
7919 }
7920
7921 /*
7922 * Check whether the Architectural PerfMon supports
7923 * Branch Misses Retired hw_event or not.
7924 */
7925 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
7926 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
7927 return -ENODEV;
7928
7929 version = eax.split.version_id;
7930 if (version < 2)
7931 x86_pmu = core_pmu;
7932 else
7933 x86_pmu = intel_pmu;
7934
7935 x86_pmu.version = version;
7936 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0);
7937 x86_pmu.cntval_bits = eax.split.bit_width;
7938 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
7939
7940 x86_pmu.events_maskl = ebx.full;
7941 x86_pmu.events_mask_len = eax.split.mask_length;
7942
7943 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64);
7944 x86_pmu.pebs_capable = PEBS_COUNTER_MASK;
7945 x86_pmu.config_mask = X86_RAW_EVENT_MASK;
7946
7947 /*
7948 * Quirk: v2 perfmon does not report fixed-purpose events, so
7949 * assume at least 3 events, when not running in a hypervisor:
7950 */
7951 if (version > 1 && version < 5) {
7952 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
7953
7954 x86_pmu.fixed_cntr_mask64 =
7955 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0);
7956 } else if (version >= 5)
7957 x86_pmu.fixed_cntr_mask64 = fixed_mask;
7958
7959 if (boot_cpu_has(X86_FEATURE_PDCM)) {
7960 u64 capabilities;
7961
7962 rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities);
7963 x86_pmu.intel_cap.capabilities = capabilities;
7964 }
7965
7966 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
7967 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
7968 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
7969 }
7970
7971 intel_pebs_init();
7972
7973 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
7974
7975 /* The perf side of core PMU is ready to support the mediated vPMU. */
7976 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_MEDIATED_VPMU;
7977
7978 /*
7979 * Many features on and after V6 require dynamic constraint,
7980 * e.g., Arch PEBS, ACR.
7981 */
7982 if (version >= 6) {
7983 x86_pmu.flags |= PMU_FL_DYN_CONSTRAINT;
7984 x86_pmu.late_setup = intel_pmu_late_setup;
7985 }
7986
7987 /*
7988 * Install the hw-cache-events table:
7989 */
7990 switch (boot_cpu_data.x86_vfm) {
7991 case INTEL_CORE_YONAH:
7992 pr_cont("Core events, ");
7993 name = "core";
7994 break;
7995
7996 case INTEL_CORE2_MEROM:
7997 x86_add_quirk(intel_clovertown_quirk);
7998 fallthrough;
7999
8000 case INTEL_CORE2_MEROM_L:
8001 case INTEL_CORE2_PENRYN:
8002 case INTEL_CORE2_DUNNINGTON:
8003 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
8004 sizeof(hw_cache_event_ids));
8005
8006 intel_pmu_lbr_init_core();
8007
8008 x86_pmu.event_constraints = intel_core2_event_constraints;
8009 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
8010 pr_cont("Core2 events, ");
8011 name = "core2";
8012 break;
8013
8014 case INTEL_NEHALEM:
8015 case INTEL_NEHALEM_EP:
8016 case INTEL_NEHALEM_EX:
8017 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
8018 sizeof(hw_cache_event_ids));
8019 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
8020 sizeof(hw_cache_extra_regs));
8021
8022 intel_pmu_lbr_init_nhm();
8023
8024 x86_pmu.event_constraints = intel_nehalem_event_constraints;
8025 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
8026 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
8027 x86_pmu.extra_regs = intel_nehalem_extra_regs;
8028 x86_pmu.limit_period = nhm_limit_period;
8029
8030 mem_attr = nhm_mem_events_attrs;
8031
8032 /* UOPS_ISSUED.STALLED_CYCLES */
8033 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8034 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8035 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
8036 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
8037 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
8038
8039 intel_pmu_pebs_data_source_nhm();
8040 x86_add_quirk(intel_nehalem_quirk);
8041 x86_pmu.pebs_no_tlb = 1;
8042 extra_attr = nhm_format_attr;
8043
8044 pr_cont("Nehalem events, ");
8045 name = "nehalem";
8046 break;
8047
8048 case INTEL_ATOM_BONNELL:
8049 case INTEL_ATOM_BONNELL_MID:
8050 case INTEL_ATOM_SALTWELL:
8051 case INTEL_ATOM_SALTWELL_MID:
8052 case INTEL_ATOM_SALTWELL_TABLET:
8053 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
8054 sizeof(hw_cache_event_ids));
8055
8056 intel_pmu_lbr_init_atom();
8057
8058 x86_pmu.event_constraints = intel_gen_event_constraints;
8059 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
8060 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
8061 pr_cont("Atom events, ");
8062 name = "bonnell";
8063 break;
8064
8065 case INTEL_ATOM_SILVERMONT:
8066 case INTEL_ATOM_SILVERMONT_D:
8067 case INTEL_ATOM_SILVERMONT_MID:
8068 case INTEL_ATOM_AIRMONT:
8069 case INTEL_ATOM_AIRMONT_NP:
8070 case INTEL_ATOM_SILVERMONT_MID2:
8071 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
8072 sizeof(hw_cache_event_ids));
8073 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
8074 sizeof(hw_cache_extra_regs));
8075
8076 intel_pmu_lbr_init_slm();
8077
8078 x86_pmu.event_constraints = intel_slm_event_constraints;
8079 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
8080 x86_pmu.extra_regs = intel_slm_extra_regs;
8081 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8082 td_attr = slm_events_attrs;
8083 extra_attr = slm_format_attr;
8084 pr_cont("Silvermont events, ");
8085 name = "silvermont";
8086 break;
8087
8088 case INTEL_ATOM_GOLDMONT:
8089 case INTEL_ATOM_GOLDMONT_D:
8090 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
8091 sizeof(hw_cache_event_ids));
8092 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
8093 sizeof(hw_cache_extra_regs));
8094
8095 intel_pmu_lbr_init_skl();
8096
8097 x86_pmu.event_constraints = intel_slm_event_constraints;
8098 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
8099 x86_pmu.extra_regs = intel_glm_extra_regs;
8100 /*
8101 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
8102 * for precise cycles.
8103 * :pp is identical to :ppp
8104 */
8105 x86_pmu.pebs_aliases = NULL;
8106 x86_pmu.pebs_prec_dist = true;
8107 x86_pmu.lbr_pt_coexist = true;
8108 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8109 td_attr = glm_events_attrs;
8110 extra_attr = slm_format_attr;
8111 pr_cont("Goldmont events, ");
8112 name = "goldmont";
8113 break;
8114
8115 case INTEL_ATOM_GOLDMONT_PLUS:
8116 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
8117 sizeof(hw_cache_event_ids));
8118 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
8119 sizeof(hw_cache_extra_regs));
8120
8121 intel_pmu_lbr_init_skl();
8122
8123 x86_pmu.event_constraints = intel_slm_event_constraints;
8124 x86_pmu.extra_regs = intel_glm_extra_regs;
8125 /*
8126 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
8127 * for precise cycles.
8128 */
8129 x86_pmu.pebs_aliases = NULL;
8130 x86_pmu.pebs_prec_dist = true;
8131 x86_pmu.lbr_pt_coexist = true;
8132 x86_pmu.pebs_capable = ~0ULL;
8133 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8134 x86_pmu.flags |= PMU_FL_PEBS_ALL;
8135 x86_pmu.get_event_constraints = glp_get_event_constraints;
8136 td_attr = glm_events_attrs;
8137 /* Goldmont Plus has 4-wide pipeline */
8138 event_attr_td_total_slots_scale_glm.event_str = "4";
8139 extra_attr = slm_format_attr;
8140 pr_cont("Goldmont plus events, ");
8141 name = "goldmont_plus";
8142 break;
8143
8144 case INTEL_ATOM_TREMONT_D:
8145 case INTEL_ATOM_TREMONT:
8146 case INTEL_ATOM_TREMONT_L:
8147 x86_pmu.late_ack = true;
8148 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
8149 sizeof(hw_cache_event_ids));
8150 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
8151 sizeof(hw_cache_extra_regs));
8152 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
8153
8154 intel_pmu_lbr_init_skl();
8155
8156 x86_pmu.event_constraints = intel_slm_event_constraints;
8157 x86_pmu.extra_regs = intel_tnt_extra_regs;
8158 /*
8159 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
8160 * for precise cycles.
8161 */
8162 x86_pmu.pebs_aliases = NULL;
8163 x86_pmu.pebs_prec_dist = true;
8164 x86_pmu.lbr_pt_coexist = true;
8165 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8166 x86_pmu.get_event_constraints = tnt_get_event_constraints;
8167 td_attr = tnt_events_attrs;
8168 extra_attr = slm_format_attr;
8169 pr_cont("Tremont events, ");
8170 name = "Tremont";
8171 break;
8172
8173 case INTEL_ATOM_GRACEMONT:
8174 intel_pmu_init_grt(NULL);
8175 intel_pmu_pebs_data_source_grt();
8176 x86_pmu.pebs_latency_data = grt_latency_data;
8177 x86_pmu.get_event_constraints = tnt_get_event_constraints;
8178 td_attr = tnt_events_attrs;
8179 mem_attr = grt_mem_attrs;
8180 extra_attr = nhm_format_attr;
8181 pr_cont("Gracemont events, ");
8182 name = "gracemont";
8183 break;
8184
8185 case INTEL_ATOM_CRESTMONT:
8186 case INTEL_ATOM_CRESTMONT_X:
8187 intel_pmu_init_cmt(NULL);
8188 intel_pmu_pebs_data_source_cmt();
8189 x86_pmu.pebs_latency_data = cmt_latency_data;
8190 x86_pmu.get_event_constraints = cmt_get_event_constraints;
8191 td_attr = cmt_events_attrs;
8192 mem_attr = grt_mem_attrs;
8193 extra_attr = cmt_format_attr;
8194 pr_cont("Crestmont events, ");
8195 name = "crestmont";
8196 break;
8197
8198 case INTEL_ATOM_DARKMONT_X:
8199 intel_pmu_init_dkt(NULL);
8200 intel_pmu_pebs_data_source_cmt();
8201 x86_pmu.pebs_latency_data = cmt_latency_data;
8202 x86_pmu.get_event_constraints = cmt_get_event_constraints;
8203 td_attr = skt_events_attrs;
8204 mem_attr = grt_mem_attrs;
8205 extra_attr = cmt_format_attr;
8206 pr_cont("Darkmont events, ");
8207 name = "darkmont";
8208 break;
8209
8210 case INTEL_WESTMERE:
8211 case INTEL_WESTMERE_EP:
8212 case INTEL_WESTMERE_EX:
8213 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
8214 sizeof(hw_cache_event_ids));
8215 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
8216 sizeof(hw_cache_extra_regs));
8217
8218 intel_pmu_lbr_init_nhm();
8219
8220 x86_pmu.event_constraints = intel_westmere_event_constraints;
8221 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
8222 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
8223 x86_pmu.extra_regs = intel_westmere_extra_regs;
8224 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8225
8226 mem_attr = nhm_mem_events_attrs;
8227
8228 /* UOPS_ISSUED.STALLED_CYCLES */
8229 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8230 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8231 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
8232 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
8233 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
8234
8235 intel_pmu_pebs_data_source_nhm();
8236 extra_attr = nhm_format_attr;
8237 pr_cont("Westmere events, ");
8238 name = "westmere";
8239 break;
8240
8241 case INTEL_SANDYBRIDGE:
8242 case INTEL_SANDYBRIDGE_X:
8243 x86_add_quirk(intel_sandybridge_quirk);
8244 x86_add_quirk(intel_ht_bug);
8245 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
8246 sizeof(hw_cache_event_ids));
8247 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
8248 sizeof(hw_cache_extra_regs));
8249
8250 intel_pmu_lbr_init_snb();
8251
8252 x86_pmu.event_constraints = intel_snb_event_constraints;
8253 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
8254 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
8255 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X)
8256 x86_pmu.extra_regs = intel_snbep_extra_regs;
8257 else
8258 x86_pmu.extra_regs = intel_snb_extra_regs;
8259
8260
8261 /* all extra regs are per-cpu when HT is on */
8262 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8263 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8264
8265 td_attr = snb_events_attrs;
8266 mem_attr = snb_mem_events_attrs;
8267
8268 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
8269 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8270 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8271 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
8272 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
8273 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
8274
8275 extra_attr = nhm_format_attr;
8276
8277 pr_cont("SandyBridge events, ");
8278 name = "sandybridge";
8279 break;
8280
8281 case INTEL_IVYBRIDGE:
8282 case INTEL_IVYBRIDGE_X:
8283 x86_add_quirk(intel_ht_bug);
8284 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
8285 sizeof(hw_cache_event_ids));
8286 /* dTLB-load-misses on IVB is different than SNB */
8287 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
8288
8289 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
8290 sizeof(hw_cache_extra_regs));
8291
8292 intel_pmu_lbr_init_snb();
8293
8294 x86_pmu.event_constraints = intel_ivb_event_constraints;
8295 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
8296 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
8297 x86_pmu.pebs_prec_dist = true;
8298 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X)
8299 x86_pmu.extra_regs = intel_snbep_extra_regs;
8300 else
8301 x86_pmu.extra_regs = intel_snb_extra_regs;
8302 /* all extra regs are per-cpu when HT is on */
8303 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8304 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8305
8306 td_attr = snb_events_attrs;
8307 mem_attr = snb_mem_events_attrs;
8308
8309 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
8310 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8311 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8312
8313 extra_attr = nhm_format_attr;
8314
8315 pr_cont("IvyBridge events, ");
8316 name = "ivybridge";
8317 break;
8318
8319
8320 case INTEL_HASWELL:
8321 case INTEL_HASWELL_X:
8322 case INTEL_HASWELL_L:
8323 case INTEL_HASWELL_G:
8324 x86_add_quirk(intel_ht_bug);
8325 x86_add_quirk(intel_pebs_isolation_quirk);
8326 x86_pmu.late_ack = true;
8327 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8328 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8329
8330 intel_pmu_lbr_init_hsw();
8331
8332 x86_pmu.event_constraints = intel_hsw_event_constraints;
8333 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
8334 x86_pmu.extra_regs = intel_snbep_extra_regs;
8335 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
8336 x86_pmu.pebs_prec_dist = true;
8337 /* all extra regs are per-cpu when HT is on */
8338 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8339 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8340
8341 x86_pmu.hw_config = hsw_hw_config;
8342 x86_pmu.get_event_constraints = hsw_get_event_constraints;
8343 x86_pmu.limit_period = hsw_limit_period;
8344 x86_pmu.lbr_double_abort = true;
8345 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8346 hsw_format_attr : nhm_format_attr;
8347 td_attr = hsw_events_attrs;
8348 mem_attr = hsw_mem_events_attrs;
8349 tsx_attr = hsw_tsx_events_attrs;
8350 pr_cont("Haswell events, ");
8351 name = "haswell";
8352 break;
8353
8354 case INTEL_BROADWELL:
8355 case INTEL_BROADWELL_D:
8356 case INTEL_BROADWELL_G:
8357 case INTEL_BROADWELL_X:
8358 x86_add_quirk(intel_pebs_isolation_quirk);
8359 x86_pmu.late_ack = true;
8360 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8361 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8362
8363 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
8364 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
8365 BDW_L3_MISS|HSW_SNOOP_DRAM;
8366 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
8367 HSW_SNOOP_DRAM;
8368 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
8369 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
8370 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
8371 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
8372
8373 intel_pmu_lbr_init_hsw();
8374
8375 x86_pmu.event_constraints = intel_bdw_event_constraints;
8376 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
8377 x86_pmu.extra_regs = intel_snbep_extra_regs;
8378 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
8379 x86_pmu.pebs_prec_dist = true;
8380 /* all extra regs are per-cpu when HT is on */
8381 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8382 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8383
8384 x86_pmu.hw_config = hsw_hw_config;
8385 x86_pmu.get_event_constraints = hsw_get_event_constraints;
8386 x86_pmu.limit_period = bdw_limit_period;
8387 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8388 hsw_format_attr : nhm_format_attr;
8389 td_attr = hsw_events_attrs;
8390 mem_attr = hsw_mem_events_attrs;
8391 tsx_attr = hsw_tsx_events_attrs;
8392 pr_cont("Broadwell events, ");
8393 name = "broadwell";
8394 break;
8395
8396 case INTEL_XEON_PHI_KNL:
8397 case INTEL_XEON_PHI_KNM:
8398 memcpy(hw_cache_event_ids,
8399 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8400 memcpy(hw_cache_extra_regs,
8401 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8402 intel_pmu_lbr_init_knl();
8403
8404 x86_pmu.event_constraints = intel_slm_event_constraints;
8405 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
8406 x86_pmu.extra_regs = intel_knl_extra_regs;
8407
8408 /* all extra regs are per-cpu when HT is on */
8409 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8410 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8411 extra_attr = slm_format_attr;
8412 pr_cont("Knights Landing/Mill events, ");
8413 name = "knights-landing";
8414 break;
8415
8416 case INTEL_SKYLAKE_X:
8417 pmem = true;
8418 fallthrough;
8419 case INTEL_SKYLAKE_L:
8420 case INTEL_SKYLAKE:
8421 case INTEL_KABYLAKE_L:
8422 case INTEL_KABYLAKE:
8423 case INTEL_COMETLAKE_L:
8424 case INTEL_COMETLAKE:
8425 x86_add_quirk(intel_pebs_isolation_quirk);
8426 x86_pmu.late_ack = true;
8427 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8428 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8429 intel_pmu_lbr_init_skl();
8430
8431 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
8432 event_attr_td_recovery_bubbles.event_str_noht =
8433 "event=0xd,umask=0x1,cmask=1";
8434 event_attr_td_recovery_bubbles.event_str_ht =
8435 "event=0xd,umask=0x1,cmask=1,any=1";
8436
8437 x86_pmu.event_constraints = intel_skl_event_constraints;
8438 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
8439 x86_pmu.extra_regs = intel_skl_extra_regs;
8440 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
8441 x86_pmu.pebs_prec_dist = true;
8442 /* all extra regs are per-cpu when HT is on */
8443 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8444 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8445
8446 x86_pmu.hw_config = hsw_hw_config;
8447 x86_pmu.get_event_constraints = hsw_get_event_constraints;
8448 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8449 hsw_format_attr : nhm_format_attr;
8450 extra_skl_attr = skl_format_attr;
8451 td_attr = hsw_events_attrs;
8452 mem_attr = hsw_mem_events_attrs;
8453 tsx_attr = hsw_tsx_events_attrs;
8454 intel_pmu_pebs_data_source_skl(pmem);
8455
8456 /*
8457 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
8458 * TSX force abort hooks are not required on these systems. Only deploy
8459 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
8460 */
8461 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
8462 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
8463 x86_pmu.flags |= PMU_FL_TFA;
8464 x86_pmu.get_event_constraints = tfa_get_event_constraints;
8465 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
8466 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
8467 }
8468
8469 pr_cont("Skylake events, ");
8470 name = "skylake";
8471 break;
8472
8473 case INTEL_ICELAKE_X:
8474 case INTEL_ICELAKE_D:
8475 memcpy(hw_cache_extra_regs, snc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8476 x86_pmu.pebs_ept = 1;
8477 pmem = true;
8478 goto snc_common;
8479 case INTEL_ICELAKE_L:
8480 case INTEL_ICELAKE:
8481 case INTEL_TIGERLAKE_L:
8482 case INTEL_TIGERLAKE:
8483 case INTEL_ROCKETLAKE:
8484 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8485 snc_common:
8486 x86_pmu.late_ack = true;
8487 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8488 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
8489 intel_pmu_lbr_init_skl();
8490
8491 x86_pmu.event_constraints = intel_icl_event_constraints;
8492 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
8493 x86_pmu.extra_regs = intel_icl_extra_regs;
8494 x86_pmu.pebs_aliases = NULL;
8495 x86_pmu.pebs_prec_dist = true;
8496 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8497 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8498
8499 x86_pmu.hw_config = hsw_hw_config;
8500 x86_pmu.get_event_constraints = icl_get_event_constraints;
8501 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8502 hsw_format_attr : nhm_format_attr;
8503 extra_skl_attr = skl_format_attr;
8504 mem_attr = icl_events_attrs;
8505 td_attr = icl_td_events_attrs;
8506 tsx_attr = icl_tsx_events_attrs;
8507 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
8508 x86_pmu.lbr_pt_coexist = true;
8509 intel_pmu_pebs_data_source_skl(pmem);
8510 x86_pmu.num_topdown_events = 4;
8511 static_call_update(intel_pmu_update_topdown_event,
8512 &icl_update_topdown_event);
8513 static_call_update(intel_pmu_set_topdown_event_period,
8514 &icl_set_topdown_event_period);
8515 pr_cont("Icelake events, ");
8516 name = "icelake";
8517 break;
8518
8519 case INTEL_SAPPHIRERAPIDS_X:
8520 case INTEL_EMERALDRAPIDS_X:
8521 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
8522 x86_pmu.extra_regs = intel_glc_extra_regs;
8523 pr_cont("Sapphire Rapids events, ");
8524 name = "sapphire_rapids";
8525 goto glc_common;
8526
8527 case INTEL_GRANITERAPIDS_X:
8528 case INTEL_GRANITERAPIDS_D:
8529 x86_pmu.extra_regs = intel_rwc_extra_regs;
8530 pr_cont("Granite Rapids events, ");
8531 name = "granite_rapids";
8532 goto glc_common;
8533
8534 case INTEL_DIAMONDRAPIDS_X:
8535 intel_pmu_init_pnc(NULL);
8536 x86_pmu.pebs_latency_data = pnc_latency_data;
8537
8538 pr_cont("Panthercove events, ");
8539 name = "panthercove";
8540 goto glc_base;
8541
8542 glc_common:
8543 intel_pmu_init_glc(NULL);
8544 intel_pmu_pebs_data_source_skl(true);
8545
8546 glc_base:
8547 x86_pmu.pebs_ept = 1;
8548 x86_pmu.hw_config = hsw_hw_config;
8549 x86_pmu.get_event_constraints = glc_get_event_constraints;
8550 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8551 hsw_format_attr : nhm_format_attr;
8552 extra_skl_attr = skl_format_attr;
8553 mem_attr = glc_events_attrs;
8554 td_attr = glc_td_events_attrs;
8555 tsx_attr = glc_tsx_events_attrs;
8556 break;
8557
8558 case INTEL_ALDERLAKE:
8559 case INTEL_ALDERLAKE_L:
8560 case INTEL_RAPTORLAKE:
8561 case INTEL_RAPTORLAKE_P:
8562 case INTEL_RAPTORLAKE_S:
8563 /*
8564 * Alder Lake has 2 types of CPU, core and atom.
8565 *
8566 * Initialize the common PerfMon capabilities here.
8567 */
8568 ret = intel_pmu_init_hybrid(hybrid_big_small);
8569 if (ret)
8570 return ret;
8571
8572 x86_pmu.pebs_latency_data = grt_latency_data;
8573 x86_pmu.get_event_constraints = adl_get_event_constraints;
8574 x86_pmu.hw_config = adl_hw_config;
8575 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
8576
8577 td_attr = adl_hybrid_events_attrs;
8578 mem_attr = adl_hybrid_mem_attrs;
8579 tsx_attr = adl_hybrid_tsx_attrs;
8580 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8581 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
8582
8583 /* Initialize big core specific PerfMon capabilities.*/
8584 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8585 intel_pmu_init_glc_hybrid(&pmu->pmu);
8586 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
8587 pmu->cntr_mask64 <<= 2;
8588 pmu->cntr_mask64 |= 0x3;
8589 pmu->fixed_cntr_mask64 <<= 1;
8590 pmu->fixed_cntr_mask64 |= 0x1;
8591 } else {
8592 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
8593 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
8594 }
8595
8596 /*
8597 * Quirk: For some Alder Lake machine, when all E-cores are disabled in
8598 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
8599 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
8600 * mistakenly add extra counters for P-cores. Correct the number of
8601 * counters here.
8602 */
8603 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) {
8604 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
8605 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
8606 }
8607
8608 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
8609 pmu->unconstrained = (struct event_constraint)
8610 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
8611 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
8612
8613 pmu->extra_regs = intel_glc_extra_regs;
8614
8615 /* Initialize Atom core specific PerfMon capabilities.*/
8616 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8617 intel_pmu_init_grt(&pmu->pmu);
8618
8619 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
8620 intel_pmu_pebs_data_source_adl();
8621 pr_cont("Alderlake Hybrid events, ");
8622 name = "alderlake_hybrid";
8623 break;
8624
8625 case INTEL_METEORLAKE:
8626 case INTEL_METEORLAKE_L:
8627 case INTEL_ARROWLAKE_U:
8628 ret = intel_pmu_init_hybrid(hybrid_big_small);
8629 if (ret)
8630 return ret;
8631
8632 x86_pmu.pebs_latency_data = cmt_latency_data;
8633 x86_pmu.get_event_constraints = mtl_get_event_constraints;
8634 x86_pmu.hw_config = adl_hw_config;
8635
8636 td_attr = adl_hybrid_events_attrs;
8637 mem_attr = mtl_hybrid_mem_attrs;
8638 tsx_attr = adl_hybrid_tsx_attrs;
8639 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8640 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8641
8642 /* Initialize big core specific PerfMon capabilities.*/
8643 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8644 intel_pmu_init_glc_hybrid(&pmu->pmu);
8645 pmu->extra_regs = intel_rwc_extra_regs;
8646
8647 /* Initialize Atom core specific PerfMon capabilities.*/
8648 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8649 intel_pmu_init_cmt(&pmu->pmu);
8650
8651 intel_pmu_pebs_data_source_mtl();
8652 pr_cont("Meteorlake Hybrid events, ");
8653 name = "meteorlake_hybrid";
8654 break;
8655
8656 case INTEL_PANTHERLAKE_L:
8657 case INTEL_WILDCATLAKE_L:
8658 pr_cont("Pantherlake Hybrid events, ");
8659 name = "pantherlake_hybrid";
8660
8661 ret = intel_pmu_init_hybrid(hybrid_big_small);
8662 if (ret)
8663 return ret;
8664
8665 /* Initialize big core specific PerfMon capabilities.*/
8666 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8667 intel_pmu_init_lnc(&pmu->pmu);
8668 /* Initialize Atom core specific PerfMon capabilities.*/
8669 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8670 intel_pmu_init_dkt_hybrid(&pmu->pmu);
8671
8672 goto lnl_common;
8673
8674 case INTEL_ARROWLAKE:
8675 pr_cont("Arrowlake Hybrid events, ");
8676 name = "arrowlake_hybrid";
8677
8678 ret = intel_pmu_init_hybrid(hybrid_big_small);
8679 if (ret)
8680 return ret;
8681
8682 /* Initialize big core specific PerfMon capabilities.*/
8683 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8684 intel_pmu_init_lnc(&pmu->pmu);
8685 memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs),
8686 arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8687 /* Initialize Atom core specific PerfMon capabilities.*/
8688 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8689 intel_pmu_init_skt(&pmu->pmu);
8690
8691 goto lnl_common;
8692
8693 case INTEL_LUNARLAKE_M:
8694 pr_cont("Lunarlake Hybrid events, ");
8695 name = "lunarlake_hybrid";
8696
8697 ret = intel_pmu_init_hybrid(hybrid_big_small);
8698 if (ret)
8699 return ret;
8700
8701 /* Initialize big core specific PerfMon capabilities.*/
8702 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8703 intel_pmu_init_lnc(&pmu->pmu);
8704 /* Initialize Atom core specific PerfMon capabilities.*/
8705 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8706 intel_pmu_init_skt(&pmu->pmu);
8707
8708 lnl_common:
8709
8710 x86_pmu.pebs_latency_data = lnl_latency_data;
8711 x86_pmu.get_event_constraints = mtl_get_event_constraints;
8712 x86_pmu.hw_config = adl_hw_config;
8713
8714 td_attr = lnl_hybrid_events_attrs;
8715 mem_attr = mtl_hybrid_mem_attrs;
8716 tsx_attr = adl_hybrid_tsx_attrs;
8717 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8718 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8719
8720 intel_pmu_pebs_data_source_lnl();
8721 break;
8722
8723 case INTEL_ARROWLAKE_H:
8724 ret = intel_pmu_init_hybrid(hybrid_big_small_tiny);
8725 if (ret)
8726 return ret;
8727
8728 x86_pmu.pebs_latency_data = arl_h_latency_data;
8729 x86_pmu.get_event_constraints = arl_h_get_event_constraints;
8730 x86_pmu.hw_config = arl_h_hw_config;
8731
8732 td_attr = arl_h_hybrid_events_attrs;
8733 mem_attr = arl_h_hybrid_mem_attrs;
8734 tsx_attr = adl_hybrid_tsx_attrs;
8735 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8736 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8737
8738 /* Initialize big core specific PerfMon capabilities. */
8739 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8740 intel_pmu_init_lnc(&pmu->pmu);
8741 memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs),
8742 arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8743
8744 /* Initialize Atom core specific PerfMon capabilities. */
8745 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8746 intel_pmu_init_skt(&pmu->pmu);
8747
8748 /* Initialize Lower Power Atom specific PerfMon capabilities. */
8749 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX];
8750 intel_pmu_init_cmt(&pmu->pmu);
8751
8752 intel_pmu_pebs_data_source_arl_h();
8753 pr_cont("ArrowLake-H Hybrid events, ");
8754 name = "arrowlake_h_hybrid";
8755 break;
8756
8757 case INTEL_NOVALAKE:
8758 case INTEL_NOVALAKE_L:
8759 pr_cont("Novalake Hybrid events, ");
8760 name = "novalake_hybrid";
8761 ret = intel_pmu_init_hybrid(hybrid_big_small);
8762 if (ret)
8763 return ret;
8764
8765 x86_pmu.pebs_latency_data = nvl_latency_data;
8766 x86_pmu.get_event_constraints = mtl_get_event_constraints;
8767 x86_pmu.hw_config = adl_hw_config;
8768
8769 td_attr = lnl_hybrid_events_attrs;
8770 mem_attr = mtl_hybrid_mem_attrs;
8771 tsx_attr = adl_hybrid_tsx_attrs;
8772 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8773 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8774
8775 /* Initialize big core specific PerfMon capabilities.*/
8776 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8777 intel_pmu_init_cyc(&pmu->pmu);
8778
8779 /* Initialize Atom core specific PerfMon capabilities.*/
8780 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8781 intel_pmu_init_arw(&pmu->pmu);
8782
8783 intel_pmu_pebs_data_source_lnl();
8784 break;
8785
8786 default:
8787 switch (x86_pmu.version) {
8788 case 1:
8789 x86_pmu.event_constraints = intel_v1_event_constraints;
8790 pr_cont("generic architected perfmon v1, ");
8791 name = "generic_arch_v1";
8792 break;
8793 case 2:
8794 case 3:
8795 case 4:
8796 /*
8797 * default constraints for v2 and up
8798 */
8799 x86_pmu.event_constraints = intel_gen_event_constraints;
8800 pr_cont("generic architected perfmon, ");
8801 name = "generic_arch_v2+";
8802 break;
8803 default:
8804 /*
8805 * The default constraints for v5 and up can support up to
8806 * 16 fixed counters. For the fixed counters 4 and later,
8807 * the pseudo-encoding is applied.
8808 * The constraints may be cut according to the CPUID enumeration
8809 * by inserting the EVENT_CONSTRAINT_END.
8810 */
8811 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED)
8812 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
8813 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1;
8814 x86_pmu.event_constraints = intel_v5_gen_event_constraints;
8815 pr_cont("generic architected perfmon, ");
8816 name = "generic_arch_v5+";
8817 break;
8818 }
8819 }
8820
8821 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
8822
8823 if (!is_hybrid()) {
8824 group_events_td.attrs = td_attr;
8825 group_events_mem.attrs = mem_attr;
8826 group_events_tsx.attrs = tsx_attr;
8827 group_format_extra.attrs = extra_attr;
8828 group_format_extra_skl.attrs = extra_skl_attr;
8829
8830 x86_pmu.attr_update = attr_update;
8831 } else {
8832 hybrid_group_events_td.attrs = td_attr;
8833 hybrid_group_events_mem.attrs = mem_attr;
8834 hybrid_group_events_tsx.attrs = tsx_attr;
8835 hybrid_group_format_extra.attrs = extra_attr;
8836
8837 x86_pmu.attr_update = hybrid_attr_update;
8838 }
8839
8840 /*
8841 * The archPerfmonExt (0x23) includes an enhanced enumeration of
8842 * PMU architectural features with a per-core view. For non-hybrid,
8843 * each core has the same PMU capabilities. It's good enough to
8844 * update the x86_pmu from the booting CPU. For hybrid, the x86_pmu
8845 * is used to keep the common capabilities. Still keep the values
8846 * from the leaf 0xa. The core specific update will be done later
8847 * when a new type is online.
8848 */
8849 if (!is_hybrid())
8850 intel_update_pmu_caps(NULL);
8851
8852 if (x86_pmu.arch_pebs) {
8853 static_call_update(intel_pmu_disable_event_ext,
8854 intel_pmu_disable_event_ext);
8855 static_call_update(intel_pmu_enable_event_ext,
8856 intel_pmu_enable_event_ext);
8857 pr_cont("Architectural PEBS, ");
8858 }
8859
8860 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64,
8861 &x86_pmu.fixed_cntr_mask64,
8862 &x86_pmu.intel_ctrl);
8863
8864 /* AnyThread may be deprecated on arch perfmon v5 or later */
8865 if (version >= 5 && edx.split.anythread_deprecated) {
8866 x86_pmu.format_attrs = intel_arch_formats_attr;
8867 pr_cont("AnyThread deprecated, ");
8868 }
8869
8870 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
8871 intel_pmu_arch_lbr_init();
8872
8873 intel_pmu_check_event_constraints_all(NULL);
8874
8875 /*
8876 * Access LBR MSR may cause #GP under certain circumstances.
8877 * Check all LBR MSR here.
8878 * Disable LBR access if any LBR MSRs can not be accessed.
8879 */
8880 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
8881 x86_pmu.lbr_nr = 0;
8882 for (i = 0; i < x86_pmu.lbr_nr; i++) {
8883 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
8884 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
8885 x86_pmu.lbr_nr = 0;
8886 }
8887
8888 if (x86_pmu.lbr_nr) {
8889 intel_pmu_lbr_init();
8890
8891 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
8892
8893 /* only support branch_stack snapshot for perfmon >= v2 */
8894 if (x86_pmu.disable_all == intel_pmu_disable_all) {
8895 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) {
8896 static_call_update(perf_snapshot_branch_stack,
8897 intel_pmu_snapshot_arch_branch_stack);
8898 } else {
8899 static_call_update(perf_snapshot_branch_stack,
8900 intel_pmu_snapshot_branch_stack);
8901 }
8902 }
8903 }
8904
8905 intel_pmu_check_extra_regs(x86_pmu.extra_regs);
8906
8907 /* Support full width counters using alternative MSR range */
8908 if (x86_pmu.intel_cap.full_width_write) {
8909 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
8910 x86_pmu.perfctr = MSR_IA32_PMC0;
8911 pr_cont("full-width counters, ");
8912 }
8913
8914 /* Support V6+ MSR Aliasing */
8915 if (x86_pmu.version >= 6) {
8916 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR;
8917 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A;
8918 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR;
8919 x86_pmu.addr_offset = intel_pmu_v6_addr_offset;
8920 }
8921
8922 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
8923 x86_pmu.intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS;
8924
8925 if (x86_pmu.intel_cap.pebs_timing_info)
8926 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;
8927
8928 intel_aux_output_init();
8929
8930 return 0;
8931 }
8932
8933 /*
8934 * HT bug: phase 2 init
8935 * Called once we have valid topology information to check
8936 * whether or not HT is enabled
8937 * If HT is off, then we disable the workaround
8938 */
fixup_ht_bug(void)8939 static __init int fixup_ht_bug(void)
8940 {
8941 int c;
8942 /*
8943 * problem not present on this CPU model, nothing to do
8944 */
8945 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
8946 return 0;
8947
8948 if (topology_max_smt_threads() > 1) {
8949 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
8950 return 0;
8951 }
8952
8953 cpus_read_lock();
8954
8955 hardlockup_detector_perf_stop();
8956
8957 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
8958
8959 x86_pmu.start_scheduling = NULL;
8960 x86_pmu.commit_scheduling = NULL;
8961 x86_pmu.stop_scheduling = NULL;
8962
8963 hardlockup_detector_perf_restart();
8964
8965 for_each_online_cpu(c)
8966 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
8967
8968 cpus_read_unlock();
8969 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
8970 return 0;
8971 }
8972 subsys_initcall(fixup_ht_bug)
8973