1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 #include <linux/device.h> 5 #include <linux/dma-mapping.h> 6 #include <linux/io.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/reset.h> 10 #include <linux/sched/signal.h> 11 #include <linux/uaccess.h> 12 13 #include <drm/drm_managed.h> 14 #include <drm/drm_print.h> 15 16 #include "v3d_drv.h" 17 #include "v3d_regs.h" 18 #include "v3d_trace.h" 19 20 static void 21 v3d_init_core(struct v3d_dev *v3d, int core) 22 { 23 /* Set OVRTMUOUT, which means that the texture sampler uniform 24 * configuration's tmu output type field is used, instead of 25 * using the hardware default behavior based on the texture 26 * type. If you want the default behavior, you can still put 27 * "2" in the indirect texture state's output_type field. 28 */ 29 if (v3d->ver < V3D_GEN_41) 30 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT); 31 32 /* Whenever we flush the L2T cache, we always want to flush 33 * the whole thing. 34 */ 35 V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0); 36 V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0); 37 } 38 39 static void 40 v3d_idle_axi(struct v3d_dev *v3d, int core) 41 { 42 V3D_CORE_WRITE(core, V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ); 43 44 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS(v3d->ver)) & 45 (V3D_GMP_STATUS_RD_COUNT_MASK | 46 V3D_GMP_STATUS_WR_COUNT_MASK | 47 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) { 48 drm_err(&v3d->drm, "Failed to wait for safe GMP shutdown\n"); 49 } 50 } 51 52 static void 53 v3d_idle_gca(struct v3d_dev *v3d) 54 { 55 if (v3d->ver >= V3D_GEN_41) 56 return; 57 58 V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN); 59 60 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) & 61 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) == 62 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) { 63 drm_err(&v3d->drm, "Failed to wait for safe GCA shutdown\n"); 64 } 65 } 66 67 static void 68 v3d_reset_by_bridge(struct v3d_dev *v3d) 69 { 70 int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION); 71 72 if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) { 73 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 74 V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT); 75 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0); 76 77 /* GFXH-1383: The SW_INIT may cause a stray write to address 0 78 * of the unit, so reset it to its power-on value here. 79 */ 80 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK); 81 } else { 82 WARN_ON_ONCE(V3D_GET_FIELD(version, 83 V3D_TOP_GR_BRIDGE_MAJOR) != 7); 84 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 85 V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT); 86 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0); 87 } 88 } 89 90 static void 91 v3d_reset_v3d(struct v3d_dev *v3d) 92 { 93 if (v3d->reset) 94 reset_control_reset(v3d->reset); 95 else 96 v3d_reset_by_bridge(v3d); 97 98 v3d_init_hw_state(v3d); 99 } 100 101 void 102 v3d_reset_sms(struct v3d_dev *v3d) 103 { 104 if (v3d->ver < V3D_GEN_71) 105 return; 106 107 V3D_SMS_WRITE(V3D_SMS_REE_CS, V3D_SET_FIELD(0x4, V3D_SMS_STATE)); 108 109 if (wait_for(!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 110 V3D_SMS_STATE) == V3D_SMS_ISOLATING_FOR_RESET) && 111 !(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS), 112 V3D_SMS_STATE) == V3D_SMS_RESETTING), 100)) { 113 drm_err(&v3d->drm, "Failed to wait for SMS reset\n"); 114 } 115 } 116 117 void 118 v3d_reset(struct v3d_dev *v3d) 119 { 120 struct drm_device *dev = &v3d->drm; 121 122 drm_err(dev, "Resetting GPU for hang.\n"); 123 drm_err(dev, "V3D_ERR_STAT: 0x%08x\n", V3D_CORE_READ(0, V3D_ERR_STAT)); 124 125 trace_v3d_reset_begin(dev); 126 127 /* XXX: only needed for safe powerdown, not reset. */ 128 if (false) 129 v3d_idle_axi(v3d, 0); 130 131 v3d_irq_disable(v3d); 132 133 v3d_idle_gca(v3d); 134 v3d_reset_sms(v3d); 135 v3d_reset_v3d(v3d); 136 137 v3d_mmu_set_page_table(v3d); 138 v3d_irq_reset(v3d); 139 140 v3d_perfmon_stop(v3d, v3d->active_perfmon, false); 141 142 trace_v3d_reset_end(dev); 143 } 144 145 static void 146 v3d_flush_l3(struct v3d_dev *v3d) 147 { 148 if (v3d->ver < V3D_GEN_41) { 149 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL); 150 151 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 152 gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH); 153 154 if (v3d->ver < V3D_GEN_33) { 155 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL, 156 gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH); 157 } 158 } 159 } 160 161 /* Invalidates the (read-only) L2C cache. This was the L2 cache for 162 * uniforms and instructions on V3D 3.2. 163 */ 164 static void 165 v3d_invalidate_l2c(struct v3d_dev *v3d, int core) 166 { 167 if (v3d->ver >= V3D_GEN_33) 168 return; 169 170 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL, 171 V3D_L2CACTL_L2CCLR | 172 V3D_L2CACTL_L2CENA); 173 } 174 175 /* Invalidates texture L2 cachelines */ 176 static void 177 v3d_flush_l2t(struct v3d_dev *v3d, int core) 178 { 179 /* While there is a busy bit (V3D_L2TCACTL_L2TFLS), we don't 180 * need to wait for completion before dispatching the job -- 181 * L2T accesses will be stalled until the flush has completed. 182 * However, we do need to make sure we don't try to trigger a 183 * new flush while the L2_CLEAN queue is trying to 184 * synchronously clean after a job. 185 */ 186 mutex_lock(&v3d->cache_clean_lock); 187 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 188 V3D_L2TCACTL_L2TFLS | 189 V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM)); 190 mutex_unlock(&v3d->cache_clean_lock); 191 } 192 193 /* Cleans texture L1 and L2 cachelines (writing back dirty data). 194 * 195 * For cleaning, which happens from the CACHE_CLEAN queue after CSD has 196 * executed, we need to make sure that the clean is done before 197 * signaling job completion. So, we synchronously wait before 198 * returning, and we make sure that L2 invalidates don't happen in the 199 * meantime to confuse our are-we-done checks. 200 */ 201 void 202 v3d_clean_caches(struct v3d_dev *v3d) 203 { 204 struct drm_device *dev = &v3d->drm; 205 int core = 0; 206 207 trace_v3d_cache_clean_begin(dev); 208 209 /* GFXH-1897: Ensure pending flushes complete before writing L2TCACTL */ 210 if (v3d->ver < V3D_GEN_71) { 211 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 212 V3D_L2TCACTL_L2TFLS), 100)) { 213 drm_err(dev, "Timeout waiting for L2T clean\n"); 214 } 215 } 216 217 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); 218 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 219 V3D_L2TCACTL_TMUWCF), 100)) { 220 drm_err(dev, "Timeout waiting for TMU write combiner flush\n"); 221 } 222 223 mutex_lock(&v3d->cache_clean_lock); 224 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, 225 V3D_L2TCACTL_L2TFLS | 226 V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAN, V3D_L2TCACTL_FLM)); 227 228 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & 229 V3D_L2TCACTL_L2TFLS), 100)) { 230 drm_err(dev, "Timeout waiting for L2T clean\n"); 231 } 232 233 mutex_unlock(&v3d->cache_clean_lock); 234 235 trace_v3d_cache_clean_end(dev); 236 } 237 238 /* Invalidates the slice caches. These are read-only caches. */ 239 static void 240 v3d_invalidate_slices(struct v3d_dev *v3d, int core) 241 { 242 V3D_CORE_WRITE(core, V3D_CTL_SLCACTL, 243 V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) | 244 V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) | 245 V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) | 246 V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC)); 247 } 248 249 void 250 v3d_invalidate_caches(struct v3d_dev *v3d) 251 { 252 /* Invalidate the caches from the outside in. That way if 253 * another CL's concurrent use of nearby memory were to pull 254 * an invalidated cacheline back in, we wouldn't leave stale 255 * data in the inner cache. 256 */ 257 v3d_flush_l3(v3d); 258 v3d_invalidate_l2c(v3d, 0); 259 v3d_flush_l2t(v3d, 0); 260 v3d_invalidate_slices(v3d, 0); 261 } 262 263 /* Sets invariant state for the HW. */ 264 void 265 v3d_init_hw_state(struct v3d_dev *v3d) 266 { 267 v3d_init_core(v3d, 0); 268 } 269 270 static void 271 v3d_huge_mnt_init(struct v3d_dev *v3d) 272 { 273 int err = 0; 274 275 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) && super_pages) 276 err = drm_gem_huge_mnt_create(&v3d->drm, "within_size"); 277 278 if (drm_gem_get_huge_mnt(&v3d->drm)) 279 drm_info(&v3d->drm, "Using Transparent Hugepages\n"); 280 else if (err) 281 drm_warn(&v3d->drm, "Can't use Transparent Hugepages (%d)\n", 282 err); 283 else 284 drm_notice(&v3d->drm, 285 "Transparent Hugepage support is recommended for optimal performance on this platform!\n"); 286 } 287 288 int 289 v3d_gem_init(struct drm_device *dev) 290 { 291 struct v3d_dev *v3d = to_v3d_dev(dev); 292 u32 pt_size = 4096 * 1024; 293 int ret, i; 294 295 for (i = 0; i < V3D_MAX_QUEUES; i++) { 296 struct v3d_queue_state *queue = &v3d->queue[i]; 297 298 queue->stats = v3d_stats_alloc(); 299 if (!queue->stats) { 300 ret = -ENOMEM; 301 goto err_stats; 302 } 303 304 queue->fence_context = dma_fence_context_alloc(1); 305 306 spin_lock_init(&queue->queue_lock); 307 } 308 309 spin_lock_init(&v3d->mm_lock); 310 ret = drmm_mutex_init(dev, &v3d->bo_lock); 311 if (ret) 312 goto err_stats; 313 ret = drmm_mutex_init(dev, &v3d->reset_lock); 314 if (ret) 315 goto err_stats; 316 ret = drmm_mutex_init(dev, &v3d->sched_lock); 317 if (ret) 318 goto err_stats; 319 ret = drmm_mutex_init(dev, &v3d->cache_clean_lock); 320 if (ret) 321 goto err_stats; 322 323 /* Note: We don't allocate address 0. Various bits of HW 324 * treat 0 as special, such as the occlusion query counters 325 * where 0 means "disabled". 326 */ 327 drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1); 328 329 v3d->pt = dma_alloc_wc(v3d->drm.dev, pt_size, 330 &v3d->pt_paddr, 331 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 332 if (!v3d->pt) { 333 dev_err(v3d->drm.dev, 334 "Failed to allocate page tables. Please ensure you have DMA enabled.\n"); 335 ret = -ENOMEM; 336 goto err_dma_alloc; 337 } 338 339 v3d_huge_mnt_init(v3d); 340 341 ret = v3d_sched_init(v3d); 342 if (ret) 343 goto err_sched; 344 345 return 0; 346 347 err_sched: 348 dma_free_coherent(v3d->drm.dev, pt_size, (void *)v3d->pt, v3d->pt_paddr); 349 err_dma_alloc: 350 drm_mm_takedown(&v3d->mm); 351 err_stats: 352 for (i--; i >= 0; i--) 353 v3d_stats_put(v3d->queue[i].stats); 354 355 return ret; 356 } 357 358 void 359 v3d_gem_destroy(struct drm_device *dev) 360 { 361 struct v3d_dev *v3d = to_v3d_dev(dev); 362 enum v3d_queue q; 363 364 v3d_sched_fini(v3d); 365 366 /* Waiting for jobs to finish would need to be done before 367 * unregistering V3D. 368 */ 369 for (q = 0; q < V3D_MAX_QUEUES; q++) { 370 WARN_ON(v3d->queue[q].active_job); 371 v3d_stats_put(v3d->queue[q].stats); 372 } 373 374 drm_mm_takedown(&v3d->mm); 375 376 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt, 377 v3d->pt_paddr); 378 } 379