1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * arizona.c - Wolfson Arizona class device shared support 4 * 5 * Copyright 2012 Wolfson Microelectronics plc 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 */ 9 10 #include <linux/cleanup.h> 11 #include <linux/delay.h> 12 #include <linux/gcd.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pm_runtime.h> 16 #include <sound/pcm.h> 17 #include <sound/pcm_params.h> 18 #include <sound/tlv.h> 19 20 #include <linux/mfd/arizona/core.h> 21 #include <linux/mfd/arizona/registers.h> 22 23 #include "arizona.h" 24 25 #define ARIZONA_AIF_BCLK_CTRL 0x00 26 #define ARIZONA_AIF_TX_PIN_CTRL 0x01 27 #define ARIZONA_AIF_RX_PIN_CTRL 0x02 28 #define ARIZONA_AIF_RATE_CTRL 0x03 29 #define ARIZONA_AIF_FORMAT 0x04 30 #define ARIZONA_AIF_TX_BCLK_RATE 0x05 31 #define ARIZONA_AIF_RX_BCLK_RATE 0x06 32 #define ARIZONA_AIF_FRAME_CTRL_1 0x07 33 #define ARIZONA_AIF_FRAME_CTRL_2 0x08 34 #define ARIZONA_AIF_FRAME_CTRL_3 0x09 35 #define ARIZONA_AIF_FRAME_CTRL_4 0x0A 36 #define ARIZONA_AIF_FRAME_CTRL_5 0x0B 37 #define ARIZONA_AIF_FRAME_CTRL_6 0x0C 38 #define ARIZONA_AIF_FRAME_CTRL_7 0x0D 39 #define ARIZONA_AIF_FRAME_CTRL_8 0x0E 40 #define ARIZONA_AIF_FRAME_CTRL_9 0x0F 41 #define ARIZONA_AIF_FRAME_CTRL_10 0x10 42 #define ARIZONA_AIF_FRAME_CTRL_11 0x11 43 #define ARIZONA_AIF_FRAME_CTRL_12 0x12 44 #define ARIZONA_AIF_FRAME_CTRL_13 0x13 45 #define ARIZONA_AIF_FRAME_CTRL_14 0x14 46 #define ARIZONA_AIF_FRAME_CTRL_15 0x15 47 #define ARIZONA_AIF_FRAME_CTRL_16 0x16 48 #define ARIZONA_AIF_FRAME_CTRL_17 0x17 49 #define ARIZONA_AIF_FRAME_CTRL_18 0x18 50 #define ARIZONA_AIF_TX_ENABLES 0x19 51 #define ARIZONA_AIF_RX_ENABLES 0x1A 52 #define ARIZONA_AIF_FORCE_WRITE 0x1B 53 54 #define ARIZONA_FLL_VCO_CORNER 141900000 55 #define ARIZONA_FLL_MAX_FREF 13500000 56 #define ARIZONA_FLL_MIN_FVCO 90000000 57 #define ARIZONA_FLL_MAX_FRATIO 16 58 #define ARIZONA_FLL_MAX_REFDIV 8 59 #define ARIZONA_FLL_MIN_OUTDIV 2 60 #define ARIZONA_FLL_MAX_OUTDIV 7 61 62 #define ARIZONA_FMT_DSP_MODE_A 0 63 #define ARIZONA_FMT_DSP_MODE_B 1 64 #define ARIZONA_FMT_I2S_MODE 2 65 #define ARIZONA_FMT_LEFT_JUSTIFIED_MODE 3 66 67 #define arizona_fll_err(_fll, fmt, ...) \ 68 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) 69 #define arizona_fll_warn(_fll, fmt, ...) \ 70 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) 71 #define arizona_fll_dbg(_fll, fmt, ...) \ 72 dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) 73 74 #define arizona_aif_err(_dai, fmt, ...) \ 75 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__) 76 #define arizona_aif_warn(_dai, fmt, ...) \ 77 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__) 78 #define arizona_aif_dbg(_dai, fmt, ...) \ 79 dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__) 80 81 static int arizona_spk_ev(struct snd_soc_dapm_widget *w, 82 struct snd_kcontrol *kcontrol, 83 int event) 84 { 85 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 86 struct arizona *arizona = dev_get_drvdata(component->dev->parent); 87 int val; 88 89 switch (event) { 90 case SND_SOC_DAPM_POST_PMU: 91 val = snd_soc_component_read(component, 92 ARIZONA_INTERRUPT_RAW_STATUS_3); 93 if (val & ARIZONA_SPK_OVERHEAT_STS) { 94 dev_crit(arizona->dev, 95 "Speaker not enabled due to temperature\n"); 96 return -EBUSY; 97 } 98 99 regmap_update_bits_async(arizona->regmap, 100 ARIZONA_OUTPUT_ENABLES_1, 101 1 << w->shift, 1 << w->shift); 102 break; 103 case SND_SOC_DAPM_PRE_PMD: 104 regmap_update_bits_async(arizona->regmap, 105 ARIZONA_OUTPUT_ENABLES_1, 106 1 << w->shift, 0); 107 break; 108 default: 109 break; 110 } 111 112 return arizona_out_ev(w, kcontrol, event); 113 } 114 115 static irqreturn_t arizona_thermal_warn(int irq, void *data) 116 { 117 struct arizona *arizona = data; 118 unsigned int val; 119 int ret; 120 121 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3, 122 &val); 123 if (ret != 0) { 124 dev_err(arizona->dev, "Failed to read thermal status: %d\n", 125 ret); 126 } else if (val & ARIZONA_SPK_OVERHEAT_WARN_STS) { 127 dev_crit(arizona->dev, "Thermal warning\n"); 128 } 129 130 return IRQ_HANDLED; 131 } 132 133 static irqreturn_t arizona_thermal_shutdown(int irq, void *data) 134 { 135 struct arizona *arizona = data; 136 unsigned int val; 137 int ret; 138 139 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3, 140 &val); 141 if (ret != 0) { 142 dev_err(arizona->dev, "Failed to read thermal status: %d\n", 143 ret); 144 } else if (val & ARIZONA_SPK_OVERHEAT_STS) { 145 dev_crit(arizona->dev, "Thermal shutdown\n"); 146 ret = regmap_update_bits(arizona->regmap, 147 ARIZONA_OUTPUT_ENABLES_1, 148 ARIZONA_OUT4L_ENA | 149 ARIZONA_OUT4R_ENA, 0); 150 if (ret != 0) 151 dev_crit(arizona->dev, 152 "Failed to disable speaker outputs: %d\n", 153 ret); 154 } 155 156 return IRQ_HANDLED; 157 } 158 159 static const struct snd_soc_dapm_widget arizona_spkl = 160 SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM, 161 ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev, 162 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 163 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD); 164 165 static const struct snd_soc_dapm_widget arizona_spkr = 166 SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM, 167 ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev, 168 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 169 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD); 170 171 int arizona_init_spk(struct snd_soc_component *component) 172 { 173 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 174 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 175 struct arizona *arizona = priv->arizona; 176 int ret; 177 178 ret = snd_soc_dapm_new_controls(dapm, &arizona_spkl, 1); 179 if (ret != 0) 180 return ret; 181 182 switch (arizona->type) { 183 case WM8997: 184 case CS47L24: 185 case WM1831: 186 break; 187 default: 188 ret = snd_soc_dapm_new_controls(dapm, &arizona_spkr, 1); 189 if (ret != 0) 190 return ret; 191 break; 192 } 193 194 return 0; 195 } 196 EXPORT_SYMBOL_GPL(arizona_init_spk); 197 198 int arizona_init_spk_irqs(struct arizona *arizona) 199 { 200 int ret; 201 202 ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT_WARN, 203 "Thermal warning", arizona_thermal_warn, 204 arizona); 205 if (ret != 0) 206 dev_err(arizona->dev, 207 "Failed to get thermal warning IRQ: %d\n", 208 ret); 209 210 ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT, 211 "Thermal shutdown", arizona_thermal_shutdown, 212 arizona); 213 if (ret != 0) 214 dev_err(arizona->dev, 215 "Failed to get thermal shutdown IRQ: %d\n", 216 ret); 217 218 return 0; 219 } 220 EXPORT_SYMBOL_GPL(arizona_init_spk_irqs); 221 222 int arizona_free_spk_irqs(struct arizona *arizona) 223 { 224 arizona_free_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT_WARN, arizona); 225 arizona_free_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT, arizona); 226 227 return 0; 228 } 229 EXPORT_SYMBOL_GPL(arizona_free_spk_irqs); 230 231 static const struct snd_soc_dapm_route arizona_mono_routes[] = { 232 { "OUT1R", NULL, "OUT1L" }, 233 { "OUT2R", NULL, "OUT2L" }, 234 { "OUT3R", NULL, "OUT3L" }, 235 { "OUT4R", NULL, "OUT4L" }, 236 { "OUT5R", NULL, "OUT5L" }, 237 { "OUT6R", NULL, "OUT6L" }, 238 }; 239 240 int arizona_init_mono(struct snd_soc_component *component) 241 { 242 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 243 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 244 struct arizona *arizona = priv->arizona; 245 int i; 246 247 for (i = 0; i < ARIZONA_MAX_OUTPUT; ++i) { 248 if (arizona->pdata.out_mono[i]) 249 snd_soc_dapm_add_routes(dapm, 250 &arizona_mono_routes[i], 1); 251 } 252 253 return 0; 254 } 255 EXPORT_SYMBOL_GPL(arizona_init_mono); 256 257 int arizona_init_gpio(struct snd_soc_component *component) 258 { 259 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 260 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 261 struct arizona *arizona = priv->arizona; 262 int i; 263 264 switch (arizona->type) { 265 case WM5110: 266 case WM8280: 267 snd_soc_dapm_disable_pin(dapm, "DRC2 Signal Activity"); 268 break; 269 default: 270 break; 271 } 272 273 snd_soc_dapm_disable_pin(dapm, "DRC1 Signal Activity"); 274 275 for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) { 276 switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) { 277 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT: 278 snd_soc_dapm_enable_pin(dapm, "DRC1 Signal Activity"); 279 break; 280 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT: 281 snd_soc_dapm_enable_pin(dapm, "DRC2 Signal Activity"); 282 break; 283 default: 284 break; 285 } 286 } 287 288 return 0; 289 } 290 EXPORT_SYMBOL_GPL(arizona_init_gpio); 291 292 int arizona_init_common(struct arizona *arizona) 293 { 294 struct arizona_pdata *pdata = &arizona->pdata; 295 unsigned int val, mask; 296 int i; 297 298 BLOCKING_INIT_NOTIFIER_HEAD(&arizona->notifier); 299 300 for (i = 0; i < ARIZONA_MAX_OUTPUT; ++i) { 301 /* Default is 0 so noop with defaults */ 302 if (pdata->out_mono[i]) 303 val = ARIZONA_OUT1_MONO; 304 else 305 val = 0; 306 307 regmap_update_bits(arizona->regmap, 308 ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8), 309 ARIZONA_OUT1_MONO, val); 310 } 311 312 for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) { 313 if (pdata->spk_mute[i]) 314 regmap_update_bits(arizona->regmap, 315 ARIZONA_PDM_SPK1_CTRL_1 + (i * 2), 316 ARIZONA_SPK1_MUTE_ENDIAN_MASK | 317 ARIZONA_SPK1_MUTE_SEQ1_MASK, 318 pdata->spk_mute[i]); 319 320 if (pdata->spk_fmt[i]) 321 regmap_update_bits(arizona->regmap, 322 ARIZONA_PDM_SPK1_CTRL_2 + (i * 2), 323 ARIZONA_SPK1_FMT_MASK, 324 pdata->spk_fmt[i]); 325 } 326 327 for (i = 0; i < ARIZONA_MAX_INPUT; i++) { 328 /* Default for both is 0 so noop with defaults */ 329 val = pdata->dmic_ref[i] << ARIZONA_IN1_DMIC_SUP_SHIFT; 330 if (pdata->inmode[i] & ARIZONA_INMODE_DMIC) 331 val |= 1 << ARIZONA_IN1_MODE_SHIFT; 332 333 switch (arizona->type) { 334 case WM8998: 335 case WM1814: 336 regmap_update_bits(arizona->regmap, 337 ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 8), 338 ARIZONA_IN1L_SRC_SE_MASK, 339 (pdata->inmode[i] & ARIZONA_INMODE_SE) 340 << ARIZONA_IN1L_SRC_SE_SHIFT); 341 342 regmap_update_bits(arizona->regmap, 343 ARIZONA_ADC_DIGITAL_VOLUME_1R + (i * 8), 344 ARIZONA_IN1R_SRC_SE_MASK, 345 (pdata->inmode[i] & ARIZONA_INMODE_SE) 346 << ARIZONA_IN1R_SRC_SE_SHIFT); 347 348 mask = ARIZONA_IN1_DMIC_SUP_MASK | 349 ARIZONA_IN1_MODE_MASK; 350 break; 351 default: 352 if (pdata->inmode[i] & ARIZONA_INMODE_SE) 353 val |= 1 << ARIZONA_IN1_SINGLE_ENDED_SHIFT; 354 355 mask = ARIZONA_IN1_DMIC_SUP_MASK | 356 ARIZONA_IN1_MODE_MASK | 357 ARIZONA_IN1_SINGLE_ENDED_MASK; 358 break; 359 } 360 361 regmap_update_bits(arizona->regmap, 362 ARIZONA_IN1L_CONTROL + (i * 8), 363 mask, val); 364 } 365 366 return 0; 367 } 368 EXPORT_SYMBOL_GPL(arizona_init_common); 369 370 int arizona_init_vol_limit(struct arizona *arizona) 371 { 372 int i; 373 374 for (i = 0; i < ARRAY_SIZE(arizona->pdata.out_vol_limit); ++i) { 375 if (arizona->pdata.out_vol_limit[i]) 376 regmap_update_bits(arizona->regmap, 377 ARIZONA_DAC_VOLUME_LIMIT_1L + i * 4, 378 ARIZONA_OUT1L_VOL_LIM_MASK, 379 arizona->pdata.out_vol_limit[i]); 380 } 381 382 return 0; 383 } 384 EXPORT_SYMBOL_GPL(arizona_init_vol_limit); 385 386 const char * const arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = { 387 "None", 388 "Tone Generator 1", 389 "Tone Generator 2", 390 "Haptics", 391 "AEC", 392 "AEC2", 393 "Mic Mute Mixer", 394 "Noise Generator", 395 "IN1L", 396 "IN1R", 397 "IN2L", 398 "IN2R", 399 "IN3L", 400 "IN3R", 401 "IN4L", 402 "IN4R", 403 "AIF1RX1", 404 "AIF1RX2", 405 "AIF1RX3", 406 "AIF1RX4", 407 "AIF1RX5", 408 "AIF1RX6", 409 "AIF1RX7", 410 "AIF1RX8", 411 "AIF2RX1", 412 "AIF2RX2", 413 "AIF2RX3", 414 "AIF2RX4", 415 "AIF2RX5", 416 "AIF2RX6", 417 "AIF3RX1", 418 "AIF3RX2", 419 "SLIMRX1", 420 "SLIMRX2", 421 "SLIMRX3", 422 "SLIMRX4", 423 "SLIMRX5", 424 "SLIMRX6", 425 "SLIMRX7", 426 "SLIMRX8", 427 "EQ1", 428 "EQ2", 429 "EQ3", 430 "EQ4", 431 "DRC1L", 432 "DRC1R", 433 "DRC2L", 434 "DRC2R", 435 "LHPF1", 436 "LHPF2", 437 "LHPF3", 438 "LHPF4", 439 "DSP1.1", 440 "DSP1.2", 441 "DSP1.3", 442 "DSP1.4", 443 "DSP1.5", 444 "DSP1.6", 445 "DSP2.1", 446 "DSP2.2", 447 "DSP2.3", 448 "DSP2.4", 449 "DSP2.5", 450 "DSP2.6", 451 "DSP3.1", 452 "DSP3.2", 453 "DSP3.3", 454 "DSP3.4", 455 "DSP3.5", 456 "DSP3.6", 457 "DSP4.1", 458 "DSP4.2", 459 "DSP4.3", 460 "DSP4.4", 461 "DSP4.5", 462 "DSP4.6", 463 "ASRC1L", 464 "ASRC1R", 465 "ASRC2L", 466 "ASRC2R", 467 "ISRC1INT1", 468 "ISRC1INT2", 469 "ISRC1INT3", 470 "ISRC1INT4", 471 "ISRC1DEC1", 472 "ISRC1DEC2", 473 "ISRC1DEC3", 474 "ISRC1DEC4", 475 "ISRC2INT1", 476 "ISRC2INT2", 477 "ISRC2INT3", 478 "ISRC2INT4", 479 "ISRC2DEC1", 480 "ISRC2DEC2", 481 "ISRC2DEC3", 482 "ISRC2DEC4", 483 "ISRC3INT1", 484 "ISRC3INT2", 485 "ISRC3INT3", 486 "ISRC3INT4", 487 "ISRC3DEC1", 488 "ISRC3DEC2", 489 "ISRC3DEC3", 490 "ISRC3DEC4", 491 }; 492 EXPORT_SYMBOL_GPL(arizona_mixer_texts); 493 494 unsigned int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = { 495 0x00, /* None */ 496 0x04, /* Tone */ 497 0x05, 498 0x06, /* Haptics */ 499 0x08, /* AEC */ 500 0x09, /* AEC2 */ 501 0x0c, /* Noise mixer */ 502 0x0d, /* Comfort noise */ 503 0x10, /* IN1L */ 504 0x11, 505 0x12, 506 0x13, 507 0x14, 508 0x15, 509 0x16, 510 0x17, 511 0x20, /* AIF1RX1 */ 512 0x21, 513 0x22, 514 0x23, 515 0x24, 516 0x25, 517 0x26, 518 0x27, 519 0x28, /* AIF2RX1 */ 520 0x29, 521 0x2a, 522 0x2b, 523 0x2c, 524 0x2d, 525 0x30, /* AIF3RX1 */ 526 0x31, 527 0x38, /* SLIMRX1 */ 528 0x39, 529 0x3a, 530 0x3b, 531 0x3c, 532 0x3d, 533 0x3e, 534 0x3f, 535 0x50, /* EQ1 */ 536 0x51, 537 0x52, 538 0x53, 539 0x58, /* DRC1L */ 540 0x59, 541 0x5a, 542 0x5b, 543 0x60, /* LHPF1 */ 544 0x61, 545 0x62, 546 0x63, 547 0x68, /* DSP1.1 */ 548 0x69, 549 0x6a, 550 0x6b, 551 0x6c, 552 0x6d, 553 0x70, /* DSP2.1 */ 554 0x71, 555 0x72, 556 0x73, 557 0x74, 558 0x75, 559 0x78, /* DSP3.1 */ 560 0x79, 561 0x7a, 562 0x7b, 563 0x7c, 564 0x7d, 565 0x80, /* DSP4.1 */ 566 0x81, 567 0x82, 568 0x83, 569 0x84, 570 0x85, 571 0x90, /* ASRC1L */ 572 0x91, 573 0x92, 574 0x93, 575 0xa0, /* ISRC1INT1 */ 576 0xa1, 577 0xa2, 578 0xa3, 579 0xa4, /* ISRC1DEC1 */ 580 0xa5, 581 0xa6, 582 0xa7, 583 0xa8, /* ISRC2DEC1 */ 584 0xa9, 585 0xaa, 586 0xab, 587 0xac, /* ISRC2INT1 */ 588 0xad, 589 0xae, 590 0xaf, 591 0xb0, /* ISRC3DEC1 */ 592 0xb1, 593 0xb2, 594 0xb3, 595 0xb4, /* ISRC3INT1 */ 596 0xb5, 597 0xb6, 598 0xb7, 599 }; 600 EXPORT_SYMBOL_GPL(arizona_mixer_values); 601 602 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0); 603 EXPORT_SYMBOL_GPL(arizona_mixer_tlv); 604 605 const char * const arizona_sample_rate_text[ARIZONA_SAMPLE_RATE_ENUM_SIZE] = { 606 "12kHz", "24kHz", "48kHz", "96kHz", "192kHz", 607 "11.025kHz", "22.05kHz", "44.1kHz", "88.2kHz", "176.4kHz", 608 "4kHz", "8kHz", "16kHz", "32kHz", 609 }; 610 EXPORT_SYMBOL_GPL(arizona_sample_rate_text); 611 612 const unsigned int arizona_sample_rate_val[ARIZONA_SAMPLE_RATE_ENUM_SIZE] = { 613 0x01, 0x02, 0x03, 0x04, 0x05, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 614 0x10, 0x11, 0x12, 0x13, 615 }; 616 EXPORT_SYMBOL_GPL(arizona_sample_rate_val); 617 618 const char *arizona_sample_rate_val_to_name(unsigned int rate_val) 619 { 620 int i; 621 622 for (i = 0; i < ARRAY_SIZE(arizona_sample_rate_val); ++i) { 623 if (arizona_sample_rate_val[i] == rate_val) 624 return arizona_sample_rate_text[i]; 625 } 626 627 return "Illegal"; 628 } 629 EXPORT_SYMBOL_GPL(arizona_sample_rate_val_to_name); 630 631 const char * const arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = { 632 "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate", 633 }; 634 EXPORT_SYMBOL_GPL(arizona_rate_text); 635 636 const unsigned int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = { 637 0, 1, 2, 8, 638 }; 639 EXPORT_SYMBOL_GPL(arizona_rate_val); 640 641 const struct soc_enum arizona_isrc_fsh[] = { 642 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1, 643 ARIZONA_ISRC1_FSH_SHIFT, 0xf, 644 ARIZONA_RATE_ENUM_SIZE, 645 arizona_rate_text, arizona_rate_val), 646 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1, 647 ARIZONA_ISRC2_FSH_SHIFT, 0xf, 648 ARIZONA_RATE_ENUM_SIZE, 649 arizona_rate_text, arizona_rate_val), 650 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1, 651 ARIZONA_ISRC3_FSH_SHIFT, 0xf, 652 ARIZONA_RATE_ENUM_SIZE, 653 arizona_rate_text, arizona_rate_val), 654 }; 655 EXPORT_SYMBOL_GPL(arizona_isrc_fsh); 656 657 const struct soc_enum arizona_isrc_fsl[] = { 658 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2, 659 ARIZONA_ISRC1_FSL_SHIFT, 0xf, 660 ARIZONA_RATE_ENUM_SIZE, 661 arizona_rate_text, arizona_rate_val), 662 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2, 663 ARIZONA_ISRC2_FSL_SHIFT, 0xf, 664 ARIZONA_RATE_ENUM_SIZE, 665 arizona_rate_text, arizona_rate_val), 666 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2, 667 ARIZONA_ISRC3_FSL_SHIFT, 0xf, 668 ARIZONA_RATE_ENUM_SIZE, 669 arizona_rate_text, arizona_rate_val), 670 }; 671 EXPORT_SYMBOL_GPL(arizona_isrc_fsl); 672 673 const struct soc_enum arizona_asrc_rate1 = 674 SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1, 675 ARIZONA_ASRC_RATE1_SHIFT, 0xf, 676 ARIZONA_RATE_ENUM_SIZE - 1, 677 arizona_rate_text, arizona_rate_val); 678 EXPORT_SYMBOL_GPL(arizona_asrc_rate1); 679 680 static const char * const arizona_vol_ramp_text[] = { 681 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB", 682 "15ms/6dB", "30ms/6dB", 683 }; 684 685 SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp, 686 ARIZONA_INPUT_VOLUME_RAMP, 687 ARIZONA_IN_VD_RAMP_SHIFT, 688 arizona_vol_ramp_text); 689 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp); 690 691 SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp, 692 ARIZONA_INPUT_VOLUME_RAMP, 693 ARIZONA_IN_VI_RAMP_SHIFT, 694 arizona_vol_ramp_text); 695 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp); 696 697 SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp, 698 ARIZONA_OUTPUT_VOLUME_RAMP, 699 ARIZONA_OUT_VD_RAMP_SHIFT, 700 arizona_vol_ramp_text); 701 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp); 702 703 SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp, 704 ARIZONA_OUTPUT_VOLUME_RAMP, 705 ARIZONA_OUT_VI_RAMP_SHIFT, 706 arizona_vol_ramp_text); 707 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp); 708 709 static const char * const arizona_lhpf_mode_text[] = { 710 "Low-pass", "High-pass" 711 }; 712 713 SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode, 714 ARIZONA_HPLPF1_1, 715 ARIZONA_LHPF1_MODE_SHIFT, 716 arizona_lhpf_mode_text); 717 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode); 718 719 SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode, 720 ARIZONA_HPLPF2_1, 721 ARIZONA_LHPF2_MODE_SHIFT, 722 arizona_lhpf_mode_text); 723 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode); 724 725 SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode, 726 ARIZONA_HPLPF3_1, 727 ARIZONA_LHPF3_MODE_SHIFT, 728 arizona_lhpf_mode_text); 729 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode); 730 731 SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode, 732 ARIZONA_HPLPF4_1, 733 ARIZONA_LHPF4_MODE_SHIFT, 734 arizona_lhpf_mode_text); 735 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode); 736 737 static const char * const arizona_ng_hold_text[] = { 738 "30ms", "120ms", "250ms", "500ms", 739 }; 740 741 SOC_ENUM_SINGLE_DECL(arizona_ng_hold, 742 ARIZONA_NOISE_GATE_CONTROL, 743 ARIZONA_NGATE_HOLD_SHIFT, 744 arizona_ng_hold_text); 745 EXPORT_SYMBOL_GPL(arizona_ng_hold); 746 747 static const char * const arizona_in_hpf_cut_text[] = { 748 "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz" 749 }; 750 751 SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum, 752 ARIZONA_HPF_CONTROL, 753 ARIZONA_IN_HPF_CUT_SHIFT, 754 arizona_in_hpf_cut_text); 755 EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum); 756 757 static const char * const arizona_in_dmic_osr_text[] = { 758 "1.536MHz", "3.072MHz", "6.144MHz", "768kHz", 759 }; 760 761 const struct soc_enum arizona_in_dmic_osr[] = { 762 SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT, 763 ARRAY_SIZE(arizona_in_dmic_osr_text), 764 arizona_in_dmic_osr_text), 765 SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT, 766 ARRAY_SIZE(arizona_in_dmic_osr_text), 767 arizona_in_dmic_osr_text), 768 SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT, 769 ARRAY_SIZE(arizona_in_dmic_osr_text), 770 arizona_in_dmic_osr_text), 771 SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT, 772 ARRAY_SIZE(arizona_in_dmic_osr_text), 773 arizona_in_dmic_osr_text), 774 }; 775 EXPORT_SYMBOL_GPL(arizona_in_dmic_osr); 776 777 static const char * const arizona_anc_input_src_text[] = { 778 "None", "IN1", "IN2", "IN3", "IN4", 779 }; 780 781 static const char * const arizona_anc_channel_src_text[] = { 782 "None", "Left", "Right", "Combine", 783 }; 784 785 const struct soc_enum arizona_anc_input_src[] = { 786 SOC_ENUM_SINGLE(ARIZONA_ANC_SRC, 787 ARIZONA_IN_RXANCL_SEL_SHIFT, 788 ARRAY_SIZE(arizona_anc_input_src_text), 789 arizona_anc_input_src_text), 790 SOC_ENUM_SINGLE(ARIZONA_FCL_ADC_REFORMATTER_CONTROL, 791 ARIZONA_FCL_MIC_MODE_SEL_SHIFT, 792 ARRAY_SIZE(arizona_anc_channel_src_text), 793 arizona_anc_channel_src_text), 794 SOC_ENUM_SINGLE(ARIZONA_ANC_SRC, 795 ARIZONA_IN_RXANCR_SEL_SHIFT, 796 ARRAY_SIZE(arizona_anc_input_src_text), 797 arizona_anc_input_src_text), 798 SOC_ENUM_SINGLE(ARIZONA_FCR_ADC_REFORMATTER_CONTROL, 799 ARIZONA_FCR_MIC_MODE_SEL_SHIFT, 800 ARRAY_SIZE(arizona_anc_channel_src_text), 801 arizona_anc_channel_src_text), 802 }; 803 EXPORT_SYMBOL_GPL(arizona_anc_input_src); 804 805 static const char * const arizona_anc_ng_texts[] = { 806 "None", 807 "Internal", 808 "External", 809 }; 810 811 SOC_ENUM_SINGLE_DECL(arizona_anc_ng_enum, SND_SOC_NOPM, 0, 812 arizona_anc_ng_texts); 813 EXPORT_SYMBOL_GPL(arizona_anc_ng_enum); 814 815 static const char * const arizona_output_anc_src_text[] = { 816 "None", "RXANCL", "RXANCR", 817 }; 818 819 const struct soc_enum arizona_output_anc_src[] = { 820 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_1L, 821 ARIZONA_OUT1L_ANC_SRC_SHIFT, 822 ARRAY_SIZE(arizona_output_anc_src_text), 823 arizona_output_anc_src_text), 824 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_1R, 825 ARIZONA_OUT1R_ANC_SRC_SHIFT, 826 ARRAY_SIZE(arizona_output_anc_src_text), 827 arizona_output_anc_src_text), 828 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_2L, 829 ARIZONA_OUT2L_ANC_SRC_SHIFT, 830 ARRAY_SIZE(arizona_output_anc_src_text), 831 arizona_output_anc_src_text), 832 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_2R, 833 ARIZONA_OUT2R_ANC_SRC_SHIFT, 834 ARRAY_SIZE(arizona_output_anc_src_text), 835 arizona_output_anc_src_text), 836 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_3L, 837 ARIZONA_OUT3L_ANC_SRC_SHIFT, 838 ARRAY_SIZE(arizona_output_anc_src_text), 839 arizona_output_anc_src_text), 840 SOC_ENUM_SINGLE(ARIZONA_DAC_VOLUME_LIMIT_3R, 841 ARIZONA_OUT3R_ANC_SRC_SHIFT, 842 ARRAY_SIZE(arizona_output_anc_src_text), 843 arizona_output_anc_src_text), 844 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_4L, 845 ARIZONA_OUT4L_ANC_SRC_SHIFT, 846 ARRAY_SIZE(arizona_output_anc_src_text), 847 arizona_output_anc_src_text), 848 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_4R, 849 ARIZONA_OUT4R_ANC_SRC_SHIFT, 850 ARRAY_SIZE(arizona_output_anc_src_text), 851 arizona_output_anc_src_text), 852 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_5L, 853 ARIZONA_OUT5L_ANC_SRC_SHIFT, 854 ARRAY_SIZE(arizona_output_anc_src_text), 855 arizona_output_anc_src_text), 856 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_5R, 857 ARIZONA_OUT5R_ANC_SRC_SHIFT, 858 ARRAY_SIZE(arizona_output_anc_src_text), 859 arizona_output_anc_src_text), 860 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_6L, 861 ARIZONA_OUT6L_ANC_SRC_SHIFT, 862 ARRAY_SIZE(arizona_output_anc_src_text), 863 arizona_output_anc_src_text), 864 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_6R, 865 ARIZONA_OUT6R_ANC_SRC_SHIFT, 866 ARRAY_SIZE(arizona_output_anc_src_text), 867 arizona_output_anc_src_text), 868 }; 869 EXPORT_SYMBOL_GPL(arizona_output_anc_src); 870 871 const struct snd_kcontrol_new arizona_voice_trigger_switch[] = { 872 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), 873 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 1, 1, 0), 874 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 2, 1, 0), 875 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 3, 1, 0), 876 }; 877 EXPORT_SYMBOL_GPL(arizona_voice_trigger_switch); 878 879 static void arizona_in_set_vu(struct snd_soc_component *component, int ena) 880 { 881 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 882 unsigned int val; 883 int i; 884 885 if (ena) 886 val = ARIZONA_IN_VU; 887 else 888 val = 0; 889 890 for (i = 0; i < priv->num_inputs; i++) 891 snd_soc_component_update_bits(component, 892 ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 4), 893 ARIZONA_IN_VU, val); 894 } 895 896 bool arizona_input_analog(struct snd_soc_component *component, int shift) 897 { 898 unsigned int reg = ARIZONA_IN1L_CONTROL + ((shift / 2) * 8); 899 unsigned int val = snd_soc_component_read(component, reg); 900 901 return !(val & ARIZONA_IN1_MODE_MASK); 902 } 903 EXPORT_SYMBOL_GPL(arizona_input_analog); 904 905 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, 906 int event) 907 { 908 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 909 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 910 unsigned int reg; 911 912 if (w->shift % 2) 913 reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8); 914 else 915 reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8); 916 917 switch (event) { 918 case SND_SOC_DAPM_PRE_PMU: 919 priv->in_pending++; 920 break; 921 case SND_SOC_DAPM_POST_PMU: 922 snd_soc_component_update_bits(component, reg, 923 ARIZONA_IN1L_MUTE, 0); 924 925 /* If this is the last input pending then allow VU */ 926 priv->in_pending--; 927 if (priv->in_pending == 0) { 928 msleep(1); 929 arizona_in_set_vu(component, 1); 930 } 931 break; 932 case SND_SOC_DAPM_PRE_PMD: 933 snd_soc_component_update_bits(component, reg, 934 ARIZONA_IN1L_MUTE | ARIZONA_IN_VU, 935 ARIZONA_IN1L_MUTE | ARIZONA_IN_VU); 936 break; 937 case SND_SOC_DAPM_POST_PMD: 938 /* Disable volume updates if no inputs are enabled */ 939 reg = snd_soc_component_read(component, ARIZONA_INPUT_ENABLES); 940 if (reg == 0) 941 arizona_in_set_vu(component, 0); 942 break; 943 default: 944 break; 945 } 946 947 return 0; 948 } 949 EXPORT_SYMBOL_GPL(arizona_in_ev); 950 951 int arizona_out_ev(struct snd_soc_dapm_widget *w, 952 struct snd_kcontrol *kcontrol, 953 int event) 954 { 955 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 956 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 957 struct arizona *arizona = priv->arizona; 958 959 switch (event) { 960 case SND_SOC_DAPM_PRE_PMU: 961 switch (w->shift) { 962 case ARIZONA_OUT1L_ENA_SHIFT: 963 case ARIZONA_OUT1R_ENA_SHIFT: 964 case ARIZONA_OUT2L_ENA_SHIFT: 965 case ARIZONA_OUT2R_ENA_SHIFT: 966 case ARIZONA_OUT3L_ENA_SHIFT: 967 case ARIZONA_OUT3R_ENA_SHIFT: 968 priv->out_up_pending++; 969 priv->out_up_delay += 17000; 970 break; 971 case ARIZONA_OUT4L_ENA_SHIFT: 972 case ARIZONA_OUT4R_ENA_SHIFT: 973 priv->out_up_pending++; 974 switch (arizona->type) { 975 case WM5102: 976 case WM8997: 977 break; 978 default: 979 priv->out_up_delay += 10000; 980 break; 981 } 982 break; 983 default: 984 break; 985 } 986 break; 987 case SND_SOC_DAPM_POST_PMU: 988 switch (w->shift) { 989 case ARIZONA_OUT1L_ENA_SHIFT: 990 case ARIZONA_OUT1R_ENA_SHIFT: 991 case ARIZONA_OUT2L_ENA_SHIFT: 992 case ARIZONA_OUT2R_ENA_SHIFT: 993 case ARIZONA_OUT3L_ENA_SHIFT: 994 case ARIZONA_OUT3R_ENA_SHIFT: 995 case ARIZONA_OUT4L_ENA_SHIFT: 996 case ARIZONA_OUT4R_ENA_SHIFT: 997 priv->out_up_pending--; 998 if (!priv->out_up_pending && priv->out_up_delay) { 999 dev_dbg(component->dev, "Power up delay: %d\n", 1000 priv->out_up_delay); 1001 fsleep(priv->out_up_delay); 1002 priv->out_up_delay = 0; 1003 } 1004 break; 1005 1006 default: 1007 break; 1008 } 1009 break; 1010 case SND_SOC_DAPM_PRE_PMD: 1011 switch (w->shift) { 1012 case ARIZONA_OUT1L_ENA_SHIFT: 1013 case ARIZONA_OUT1R_ENA_SHIFT: 1014 case ARIZONA_OUT2L_ENA_SHIFT: 1015 case ARIZONA_OUT2R_ENA_SHIFT: 1016 case ARIZONA_OUT3L_ENA_SHIFT: 1017 case ARIZONA_OUT3R_ENA_SHIFT: 1018 priv->out_down_pending++; 1019 priv->out_down_delay += 1000; 1020 break; 1021 case ARIZONA_OUT4L_ENA_SHIFT: 1022 case ARIZONA_OUT4R_ENA_SHIFT: 1023 priv->out_down_pending++; 1024 switch (arizona->type) { 1025 case WM5102: 1026 case WM8997: 1027 break; 1028 case WM8998: 1029 case WM1814: 1030 priv->out_down_delay += 5000; 1031 break; 1032 default: 1033 priv->out_down_delay += 1000; 1034 break; 1035 } 1036 break; 1037 default: 1038 break; 1039 } 1040 break; 1041 case SND_SOC_DAPM_POST_PMD: 1042 switch (w->shift) { 1043 case ARIZONA_OUT1L_ENA_SHIFT: 1044 case ARIZONA_OUT1R_ENA_SHIFT: 1045 case ARIZONA_OUT2L_ENA_SHIFT: 1046 case ARIZONA_OUT2R_ENA_SHIFT: 1047 case ARIZONA_OUT3L_ENA_SHIFT: 1048 case ARIZONA_OUT3R_ENA_SHIFT: 1049 case ARIZONA_OUT4L_ENA_SHIFT: 1050 case ARIZONA_OUT4R_ENA_SHIFT: 1051 priv->out_down_pending--; 1052 if (!priv->out_down_pending && priv->out_down_delay) { 1053 dev_dbg(component->dev, "Power down delay: %d\n", 1054 priv->out_down_delay); 1055 fsleep(priv->out_down_delay); 1056 priv->out_down_delay = 0; 1057 } 1058 break; 1059 default: 1060 break; 1061 } 1062 break; 1063 default: 1064 break; 1065 } 1066 1067 return 0; 1068 } 1069 EXPORT_SYMBOL_GPL(arizona_out_ev); 1070 1071 int arizona_hp_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, 1072 int event) 1073 { 1074 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1075 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1076 struct arizona *arizona = priv->arizona; 1077 unsigned int mask = 1 << w->shift; 1078 unsigned int val; 1079 1080 switch (event) { 1081 case SND_SOC_DAPM_POST_PMU: 1082 val = mask; 1083 break; 1084 case SND_SOC_DAPM_PRE_PMD: 1085 val = 0; 1086 break; 1087 case SND_SOC_DAPM_PRE_PMU: 1088 case SND_SOC_DAPM_POST_PMD: 1089 return arizona_out_ev(w, kcontrol, event); 1090 default: 1091 return -EINVAL; 1092 } 1093 1094 /* Store the desired state for the HP outputs */ 1095 priv->arizona->hp_ena &= ~mask; 1096 priv->arizona->hp_ena |= val; 1097 1098 /* Force off if HPDET clamp is active */ 1099 if (priv->arizona->hpdet_clamp) 1100 val = 0; 1101 1102 regmap_update_bits_async(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1, 1103 mask, val); 1104 1105 return arizona_out_ev(w, kcontrol, event); 1106 } 1107 EXPORT_SYMBOL_GPL(arizona_hp_ev); 1108 1109 static int arizona_dvfs_enable(struct snd_soc_component *component) 1110 { 1111 const struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1112 struct arizona *arizona = priv->arizona; 1113 int ret; 1114 1115 ret = regulator_set_voltage(arizona->dcvdd, 1800000, 1800000); 1116 if (ret) { 1117 dev_err(component->dev, "Failed to boost DCVDD: %d\n", ret); 1118 return ret; 1119 } 1120 1121 ret = regmap_update_bits(arizona->regmap, 1122 ARIZONA_DYNAMIC_FREQUENCY_SCALING_1, 1123 ARIZONA_SUBSYS_MAX_FREQ, 1124 ARIZONA_SUBSYS_MAX_FREQ); 1125 if (ret) { 1126 dev_err(component->dev, "Failed to enable subsys max: %d\n", ret); 1127 regulator_set_voltage(arizona->dcvdd, 1200000, 1800000); 1128 return ret; 1129 } 1130 1131 return 0; 1132 } 1133 1134 static int arizona_dvfs_disable(struct snd_soc_component *component) 1135 { 1136 const struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1137 struct arizona *arizona = priv->arizona; 1138 int ret; 1139 1140 ret = regmap_update_bits(arizona->regmap, 1141 ARIZONA_DYNAMIC_FREQUENCY_SCALING_1, 1142 ARIZONA_SUBSYS_MAX_FREQ, 0); 1143 if (ret) { 1144 dev_err(component->dev, "Failed to disable subsys max: %d\n", ret); 1145 return ret; 1146 } 1147 1148 ret = regulator_set_voltage(arizona->dcvdd, 1200000, 1800000); 1149 if (ret) { 1150 dev_err(component->dev, "Failed to unboost DCVDD: %d\n", ret); 1151 return ret; 1152 } 1153 1154 return 0; 1155 } 1156 1157 int arizona_dvfs_up(struct snd_soc_component *component, unsigned int flags) 1158 { 1159 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1160 int ret = 0; 1161 1162 guard(mutex)(&priv->dvfs_lock); 1163 1164 if (!priv->dvfs_cached && !priv->dvfs_reqs) { 1165 ret = arizona_dvfs_enable(component); 1166 if (ret) 1167 return ret; 1168 } 1169 1170 priv->dvfs_reqs |= flags; 1171 1172 return ret; 1173 } 1174 EXPORT_SYMBOL_GPL(arizona_dvfs_up); 1175 1176 int arizona_dvfs_down(struct snd_soc_component *component, unsigned int flags) 1177 { 1178 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1179 unsigned int old_reqs; 1180 int ret = 0; 1181 1182 guard(mutex)(&priv->dvfs_lock); 1183 1184 old_reqs = priv->dvfs_reqs; 1185 priv->dvfs_reqs &= ~flags; 1186 1187 if (!priv->dvfs_cached && old_reqs && !priv->dvfs_reqs) 1188 ret = arizona_dvfs_disable(component); 1189 1190 return ret; 1191 } 1192 EXPORT_SYMBOL_GPL(arizona_dvfs_down); 1193 1194 int arizona_dvfs_sysclk_ev(struct snd_soc_dapm_widget *w, 1195 struct snd_kcontrol *kcontrol, int event) 1196 { 1197 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1198 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1199 int ret = 0; 1200 1201 guard(mutex)(&priv->dvfs_lock); 1202 1203 switch (event) { 1204 case SND_SOC_DAPM_POST_PMU: 1205 if (priv->dvfs_reqs) 1206 ret = arizona_dvfs_enable(component); 1207 1208 priv->dvfs_cached = false; 1209 break; 1210 case SND_SOC_DAPM_PRE_PMD: 1211 /* We must ensure DVFS is disabled before the codec goes into 1212 * suspend so that we are never in an illegal state of DVFS 1213 * enabled without enough DCVDD 1214 */ 1215 priv->dvfs_cached = true; 1216 1217 if (priv->dvfs_reqs) 1218 ret = arizona_dvfs_disable(component); 1219 break; 1220 default: 1221 break; 1222 } 1223 1224 return ret; 1225 } 1226 EXPORT_SYMBOL_GPL(arizona_dvfs_sysclk_ev); 1227 1228 void arizona_init_dvfs(struct arizona_priv *priv) 1229 { 1230 mutex_init(&priv->dvfs_lock); 1231 } 1232 EXPORT_SYMBOL_GPL(arizona_init_dvfs); 1233 1234 int arizona_anc_ev(struct snd_soc_dapm_widget *w, 1235 struct snd_kcontrol *kcontrol, 1236 int event) 1237 { 1238 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1239 unsigned int val; 1240 1241 switch (event) { 1242 case SND_SOC_DAPM_POST_PMU: 1243 val = 1 << w->shift; 1244 break; 1245 case SND_SOC_DAPM_PRE_PMD: 1246 val = 1 << (w->shift + 1); 1247 break; 1248 default: 1249 return 0; 1250 } 1251 1252 snd_soc_component_write(component, ARIZONA_CLOCK_CONTROL, val); 1253 1254 return 0; 1255 } 1256 EXPORT_SYMBOL_GPL(arizona_anc_ev); 1257 1258 static unsigned int arizona_opclk_ref_48k_rates[] = { 1259 6144000, 1260 12288000, 1261 24576000, 1262 49152000, 1263 }; 1264 1265 static unsigned int arizona_opclk_ref_44k1_rates[] = { 1266 5644800, 1267 11289600, 1268 22579200, 1269 45158400, 1270 }; 1271 1272 static int arizona_set_opclk(struct snd_soc_component *component, 1273 unsigned int clk, unsigned int freq) 1274 { 1275 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1276 unsigned int reg; 1277 unsigned int *rates; 1278 int ref, div, refclk; 1279 1280 switch (clk) { 1281 case ARIZONA_CLK_OPCLK: 1282 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK; 1283 refclk = priv->sysclk; 1284 break; 1285 case ARIZONA_CLK_ASYNC_OPCLK: 1286 reg = ARIZONA_OUTPUT_ASYNC_CLOCK; 1287 refclk = priv->asyncclk; 1288 break; 1289 default: 1290 return -EINVAL; 1291 } 1292 1293 if (refclk % 8000) 1294 rates = arizona_opclk_ref_44k1_rates; 1295 else 1296 rates = arizona_opclk_ref_48k_rates; 1297 1298 for (ref = 0; ref < ARRAY_SIZE(arizona_opclk_ref_48k_rates) && 1299 rates[ref] <= refclk; ref++) { 1300 div = 1; 1301 while (rates[ref] / div >= freq && div < 32) { 1302 if (rates[ref] / div == freq) { 1303 dev_dbg(component->dev, "Configured %dHz OPCLK\n", 1304 freq); 1305 snd_soc_component_update_bits(component, reg, 1306 ARIZONA_OPCLK_DIV_MASK | 1307 ARIZONA_OPCLK_SEL_MASK, 1308 (div << 1309 ARIZONA_OPCLK_DIV_SHIFT) | 1310 ref); 1311 return 0; 1312 } 1313 div++; 1314 } 1315 } 1316 1317 dev_err(component->dev, "Unable to generate %dHz OPCLK\n", freq); 1318 return -EINVAL; 1319 } 1320 1321 int arizona_clk_ev(struct snd_soc_dapm_widget *w, 1322 struct snd_kcontrol *kcontrol, int event) 1323 { 1324 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1325 struct arizona *arizona = dev_get_drvdata(component->dev->parent); 1326 unsigned int val; 1327 int clk_idx; 1328 int ret; 1329 1330 ret = regmap_read(arizona->regmap, w->reg, &val); 1331 if (ret) { 1332 dev_err(component->dev, "Failed to check clock source: %d\n", ret); 1333 return ret; 1334 } 1335 1336 val = (val & ARIZONA_SYSCLK_SRC_MASK) >> ARIZONA_SYSCLK_SRC_SHIFT; 1337 1338 switch (val) { 1339 case ARIZONA_CLK_SRC_MCLK1: 1340 clk_idx = ARIZONA_MCLK1; 1341 break; 1342 case ARIZONA_CLK_SRC_MCLK2: 1343 clk_idx = ARIZONA_MCLK2; 1344 break; 1345 default: 1346 return 0; 1347 } 1348 1349 switch (event) { 1350 case SND_SOC_DAPM_PRE_PMU: 1351 return clk_prepare_enable(arizona->mclk[clk_idx]); 1352 case SND_SOC_DAPM_POST_PMD: 1353 clk_disable_unprepare(arizona->mclk[clk_idx]); 1354 return 0; 1355 default: 1356 return 0; 1357 } 1358 } 1359 EXPORT_SYMBOL_GPL(arizona_clk_ev); 1360 1361 int arizona_set_sysclk(struct snd_soc_component *component, int clk_id, 1362 int source, unsigned int freq, int dir) 1363 { 1364 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1365 struct arizona *arizona = priv->arizona; 1366 char *name; 1367 unsigned int reg; 1368 unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK; 1369 unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT; 1370 int *clk; 1371 1372 switch (clk_id) { 1373 case ARIZONA_CLK_SYSCLK: 1374 name = "SYSCLK"; 1375 reg = ARIZONA_SYSTEM_CLOCK_1; 1376 clk = &priv->sysclk; 1377 mask |= ARIZONA_SYSCLK_FRAC; 1378 break; 1379 case ARIZONA_CLK_ASYNCCLK: 1380 name = "ASYNCCLK"; 1381 reg = ARIZONA_ASYNC_CLOCK_1; 1382 clk = &priv->asyncclk; 1383 break; 1384 case ARIZONA_CLK_OPCLK: 1385 case ARIZONA_CLK_ASYNC_OPCLK: 1386 return arizona_set_opclk(component, clk_id, freq); 1387 default: 1388 return -EINVAL; 1389 } 1390 1391 switch (freq) { 1392 case 5644800: 1393 case 6144000: 1394 break; 1395 case 11289600: 1396 case 12288000: 1397 val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; 1398 break; 1399 case 22579200: 1400 case 24576000: 1401 val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; 1402 break; 1403 case 45158400: 1404 case 49152000: 1405 val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; 1406 break; 1407 case 67737600: 1408 case 73728000: 1409 val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; 1410 break; 1411 case 90316800: 1412 case 98304000: 1413 val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; 1414 break; 1415 case 135475200: 1416 case 147456000: 1417 val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; 1418 break; 1419 case 0: 1420 dev_dbg(arizona->dev, "%s cleared\n", name); 1421 *clk = freq; 1422 return 0; 1423 default: 1424 return -EINVAL; 1425 } 1426 1427 *clk = freq; 1428 1429 if (freq % 6144000) 1430 val |= ARIZONA_SYSCLK_FRAC; 1431 1432 dev_dbg(arizona->dev, "%s set to %uHz", name, freq); 1433 1434 return regmap_update_bits(arizona->regmap, reg, mask, val); 1435 } 1436 EXPORT_SYMBOL_GPL(arizona_set_sysclk); 1437 1438 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1439 { 1440 struct snd_soc_component *component = dai->component; 1441 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1442 struct arizona *arizona = priv->arizona; 1443 int lrclk, bclk, mode, base; 1444 1445 base = dai->driver->base; 1446 1447 lrclk = 0; 1448 bclk = 0; 1449 1450 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1451 case SND_SOC_DAIFMT_DSP_A: 1452 mode = ARIZONA_FMT_DSP_MODE_A; 1453 break; 1454 case SND_SOC_DAIFMT_DSP_B: 1455 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) 1456 != SND_SOC_DAIFMT_CBP_CFP) { 1457 arizona_aif_err(dai, "DSP_B not valid in slave mode\n"); 1458 return -EINVAL; 1459 } 1460 mode = ARIZONA_FMT_DSP_MODE_B; 1461 break; 1462 case SND_SOC_DAIFMT_I2S: 1463 mode = ARIZONA_FMT_I2S_MODE; 1464 break; 1465 case SND_SOC_DAIFMT_LEFT_J: 1466 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) 1467 != SND_SOC_DAIFMT_CBP_CFP) { 1468 arizona_aif_err(dai, "LEFT_J not valid in slave mode\n"); 1469 return -EINVAL; 1470 } 1471 mode = ARIZONA_FMT_LEFT_JUSTIFIED_MODE; 1472 break; 1473 default: 1474 arizona_aif_err(dai, "Unsupported DAI format %d\n", 1475 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1476 return -EINVAL; 1477 } 1478 1479 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1480 case SND_SOC_DAIFMT_CBC_CFC: 1481 break; 1482 case SND_SOC_DAIFMT_CBC_CFP: 1483 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR; 1484 break; 1485 case SND_SOC_DAIFMT_CBP_CFC: 1486 bclk |= ARIZONA_AIF1_BCLK_MSTR; 1487 break; 1488 case SND_SOC_DAIFMT_CBP_CFP: 1489 bclk |= ARIZONA_AIF1_BCLK_MSTR; 1490 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR; 1491 break; 1492 default: 1493 arizona_aif_err(dai, "Unsupported master mode %d\n", 1494 fmt & SND_SOC_DAIFMT_MASTER_MASK); 1495 return -EINVAL; 1496 } 1497 1498 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1499 case SND_SOC_DAIFMT_NB_NF: 1500 break; 1501 case SND_SOC_DAIFMT_IB_IF: 1502 bclk |= ARIZONA_AIF1_BCLK_INV; 1503 lrclk |= ARIZONA_AIF1TX_LRCLK_INV; 1504 break; 1505 case SND_SOC_DAIFMT_IB_NF: 1506 bclk |= ARIZONA_AIF1_BCLK_INV; 1507 break; 1508 case SND_SOC_DAIFMT_NB_IF: 1509 lrclk |= ARIZONA_AIF1TX_LRCLK_INV; 1510 break; 1511 default: 1512 return -EINVAL; 1513 } 1514 1515 regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL, 1516 ARIZONA_AIF1_BCLK_INV | 1517 ARIZONA_AIF1_BCLK_MSTR, 1518 bclk); 1519 regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL, 1520 ARIZONA_AIF1TX_LRCLK_INV | 1521 ARIZONA_AIF1TX_LRCLK_MSTR, lrclk); 1522 regmap_update_bits_async(arizona->regmap, 1523 base + ARIZONA_AIF_RX_PIN_CTRL, 1524 ARIZONA_AIF1RX_LRCLK_INV | 1525 ARIZONA_AIF1RX_LRCLK_MSTR, lrclk); 1526 regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FORMAT, 1527 ARIZONA_AIF1_FMT_MASK, mode); 1528 1529 return 0; 1530 } 1531 1532 static const int arizona_48k_bclk_rates[] = { 1533 -1, 1534 48000, 1535 64000, 1536 96000, 1537 128000, 1538 192000, 1539 256000, 1540 384000, 1541 512000, 1542 768000, 1543 1024000, 1544 1536000, 1545 2048000, 1546 3072000, 1547 4096000, 1548 6144000, 1549 8192000, 1550 12288000, 1551 24576000, 1552 }; 1553 1554 static const int arizona_44k1_bclk_rates[] = { 1555 -1, 1556 44100, 1557 58800, 1558 88200, 1559 117600, 1560 177640, 1561 235200, 1562 352800, 1563 470400, 1564 705600, 1565 940800, 1566 1411200, 1567 1881600, 1568 2822400, 1569 3763200, 1570 5644800, 1571 7526400, 1572 11289600, 1573 22579200, 1574 }; 1575 1576 static const unsigned int arizona_sr_vals[] = { 1577 0, 1578 12000, 1579 24000, 1580 48000, 1581 96000, 1582 192000, 1583 384000, 1584 768000, 1585 0, 1586 11025, 1587 22050, 1588 44100, 1589 88200, 1590 176400, 1591 352800, 1592 705600, 1593 4000, 1594 8000, 1595 16000, 1596 32000, 1597 64000, 1598 128000, 1599 256000, 1600 512000, 1601 }; 1602 1603 #define ARIZONA_48K_RATE_MASK 0x0F003E 1604 #define ARIZONA_44K1_RATE_MASK 0x003E00 1605 #define ARIZONA_RATE_MASK (ARIZONA_48K_RATE_MASK | ARIZONA_44K1_RATE_MASK) 1606 1607 static const struct snd_pcm_hw_constraint_list arizona_constraint = { 1608 .count = ARRAY_SIZE(arizona_sr_vals), 1609 .list = arizona_sr_vals, 1610 }; 1611 1612 static int arizona_startup(struct snd_pcm_substream *substream, 1613 struct snd_soc_dai *dai) 1614 { 1615 struct snd_soc_component *component = dai->component; 1616 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1617 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1]; 1618 unsigned int base_rate; 1619 1620 if (!substream->runtime) 1621 return 0; 1622 1623 switch (dai_priv->clk) { 1624 case ARIZONA_CLK_SYSCLK: 1625 base_rate = priv->sysclk; 1626 break; 1627 case ARIZONA_CLK_ASYNCCLK: 1628 base_rate = priv->asyncclk; 1629 break; 1630 default: 1631 return 0; 1632 } 1633 1634 if (base_rate == 0) 1635 dai_priv->constraint.mask = ARIZONA_RATE_MASK; 1636 else if (base_rate % 8000) 1637 dai_priv->constraint.mask = ARIZONA_44K1_RATE_MASK; 1638 else 1639 dai_priv->constraint.mask = ARIZONA_48K_RATE_MASK; 1640 1641 return snd_pcm_hw_constraint_list(substream->runtime, 0, 1642 SNDRV_PCM_HW_PARAM_RATE, 1643 &dai_priv->constraint); 1644 } 1645 1646 static void arizona_wm5102_set_dac_comp(struct snd_soc_component *component, 1647 unsigned int rate) 1648 { 1649 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1650 struct arizona *arizona = priv->arizona; 1651 struct reg_sequence dac_comp[] = { 1652 { 0x80, 0x3 }, 1653 { ARIZONA_DAC_COMP_1, 0 }, 1654 { ARIZONA_DAC_COMP_2, 0 }, 1655 { 0x80, 0x0 }, 1656 }; 1657 1658 scoped_guard(mutex, &arizona->dac_comp_lock) { 1659 dac_comp[1].def = arizona->dac_comp_coeff; 1660 if (rate >= 176400) 1661 dac_comp[2].def = arizona->dac_comp_enabled; 1662 } 1663 1664 regmap_multi_reg_write(arizona->regmap, 1665 dac_comp, 1666 ARRAY_SIZE(dac_comp)); 1667 } 1668 1669 static int arizona_hw_params_rate(struct snd_pcm_substream *substream, 1670 struct snd_pcm_hw_params *params, 1671 struct snd_soc_dai *dai) 1672 { 1673 struct snd_soc_component *component = dai->component; 1674 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1675 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1]; 1676 int base = dai->driver->base; 1677 int i, sr_val, ret; 1678 1679 /* 1680 * We will need to be more flexible than this in future, 1681 * currently we use a single sample rate for SYSCLK. 1682 */ 1683 for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++) 1684 if (arizona_sr_vals[i] == params_rate(params)) 1685 break; 1686 if (i == ARRAY_SIZE(arizona_sr_vals)) { 1687 arizona_aif_err(dai, "Unsupported sample rate %dHz\n", 1688 params_rate(params)); 1689 return -EINVAL; 1690 } 1691 sr_val = i; 1692 1693 switch (priv->arizona->type) { 1694 case WM5102: 1695 case WM8997: 1696 if (arizona_sr_vals[sr_val] >= 88200) 1697 ret = arizona_dvfs_up(component, ARIZONA_DVFS_SR1_RQ); 1698 else 1699 ret = arizona_dvfs_down(component, ARIZONA_DVFS_SR1_RQ); 1700 1701 if (ret) { 1702 arizona_aif_err(dai, "Failed to change DVFS %d\n", ret); 1703 return ret; 1704 } 1705 break; 1706 default: 1707 break; 1708 } 1709 1710 switch (dai_priv->clk) { 1711 case ARIZONA_CLK_SYSCLK: 1712 switch (priv->arizona->type) { 1713 case WM5102: 1714 arizona_wm5102_set_dac_comp(component, 1715 params_rate(params)); 1716 break; 1717 default: 1718 break; 1719 } 1720 1721 snd_soc_component_update_bits(component, ARIZONA_SAMPLE_RATE_1, 1722 ARIZONA_SAMPLE_RATE_1_MASK, 1723 sr_val); 1724 if (base) 1725 snd_soc_component_update_bits(component, 1726 base + ARIZONA_AIF_RATE_CTRL, 1727 ARIZONA_AIF1_RATE_MASK, 0); 1728 break; 1729 case ARIZONA_CLK_ASYNCCLK: 1730 snd_soc_component_update_bits(component, 1731 ARIZONA_ASYNC_SAMPLE_RATE_1, 1732 ARIZONA_ASYNC_SAMPLE_RATE_1_MASK, 1733 sr_val); 1734 if (base) 1735 snd_soc_component_update_bits(component, 1736 base + ARIZONA_AIF_RATE_CTRL, 1737 ARIZONA_AIF1_RATE_MASK, 1738 8 << ARIZONA_AIF1_RATE_SHIFT); 1739 break; 1740 default: 1741 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk); 1742 return -EINVAL; 1743 } 1744 1745 return 0; 1746 } 1747 1748 static bool arizona_aif_cfg_changed(struct snd_soc_component *component, 1749 int base, int bclk, int lrclk, int frame) 1750 { 1751 int val; 1752 1753 val = snd_soc_component_read(component, base + ARIZONA_AIF_BCLK_CTRL); 1754 if (bclk != (val & ARIZONA_AIF1_BCLK_FREQ_MASK)) 1755 return true; 1756 1757 val = snd_soc_component_read(component, base + ARIZONA_AIF_RX_BCLK_RATE); 1758 if (lrclk != (val & ARIZONA_AIF1RX_BCPF_MASK)) 1759 return true; 1760 1761 val = snd_soc_component_read(component, base + ARIZONA_AIF_FRAME_CTRL_1); 1762 if (frame != (val & (ARIZONA_AIF1TX_WL_MASK | 1763 ARIZONA_AIF1TX_SLOT_LEN_MASK))) 1764 return true; 1765 1766 return false; 1767 } 1768 1769 static int arizona_hw_params(struct snd_pcm_substream *substream, 1770 struct snd_pcm_hw_params *params, 1771 struct snd_soc_dai *dai) 1772 { 1773 struct snd_soc_component *component = dai->component; 1774 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1775 struct arizona *arizona = priv->arizona; 1776 int base = dai->driver->base; 1777 const int *rates; 1778 int i, ret, val; 1779 int channels = params_channels(params); 1780 int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1]; 1781 int tdm_width = arizona->tdm_width[dai->id - 1]; 1782 int tdm_slots = arizona->tdm_slots[dai->id - 1]; 1783 int bclk, lrclk, wl, frame, bclk_target; 1784 bool reconfig; 1785 unsigned int aif_tx_state, aif_rx_state; 1786 1787 if (params_rate(params) % 4000) 1788 rates = &arizona_44k1_bclk_rates[0]; 1789 else 1790 rates = &arizona_48k_bclk_rates[0]; 1791 1792 wl = params_width(params); 1793 1794 if (tdm_slots) { 1795 arizona_aif_dbg(dai, "Configuring for %d %d bit TDM slots\n", 1796 tdm_slots, tdm_width); 1797 bclk_target = tdm_slots * tdm_width * params_rate(params); 1798 channels = tdm_slots; 1799 } else { 1800 bclk_target = snd_soc_params_to_bclk(params); 1801 tdm_width = wl; 1802 } 1803 1804 if (chan_limit && chan_limit < channels) { 1805 arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit); 1806 bclk_target /= channels; 1807 bclk_target *= chan_limit; 1808 } 1809 1810 /* Force multiple of 2 channels for I2S mode */ 1811 val = snd_soc_component_read(component, base + ARIZONA_AIF_FORMAT); 1812 val &= ARIZONA_AIF1_FMT_MASK; 1813 if ((channels & 1) && (val == ARIZONA_FMT_I2S_MODE)) { 1814 arizona_aif_dbg(dai, "Forcing stereo mode\n"); 1815 bclk_target /= channels; 1816 bclk_target *= channels + 1; 1817 } 1818 1819 for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) { 1820 if (rates[i] >= bclk_target && 1821 rates[i] % params_rate(params) == 0) { 1822 bclk = i; 1823 break; 1824 } 1825 } 1826 if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) { 1827 arizona_aif_err(dai, "Unsupported sample rate %dHz\n", 1828 params_rate(params)); 1829 return -EINVAL; 1830 } 1831 1832 lrclk = rates[bclk] / params_rate(params); 1833 1834 arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n", 1835 rates[bclk], rates[bclk] / lrclk); 1836 1837 frame = wl << ARIZONA_AIF1TX_WL_SHIFT | tdm_width; 1838 1839 reconfig = arizona_aif_cfg_changed(component, base, bclk, lrclk, frame); 1840 1841 if (reconfig) { 1842 /* Save AIF TX/RX state */ 1843 aif_tx_state = snd_soc_component_read(component, 1844 base + ARIZONA_AIF_TX_ENABLES); 1845 aif_rx_state = snd_soc_component_read(component, 1846 base + ARIZONA_AIF_RX_ENABLES); 1847 /* Disable AIF TX/RX before reconfiguring it */ 1848 regmap_update_bits_async(arizona->regmap, 1849 base + ARIZONA_AIF_TX_ENABLES, 1850 0xff, 0x0); 1851 regmap_update_bits(arizona->regmap, 1852 base + ARIZONA_AIF_RX_ENABLES, 0xff, 0x0); 1853 } 1854 1855 ret = arizona_hw_params_rate(substream, params, dai); 1856 if (ret != 0) 1857 goto restore_aif; 1858 1859 if (reconfig) { 1860 regmap_update_bits_async(arizona->regmap, 1861 base + ARIZONA_AIF_BCLK_CTRL, 1862 ARIZONA_AIF1_BCLK_FREQ_MASK, bclk); 1863 regmap_update_bits_async(arizona->regmap, 1864 base + ARIZONA_AIF_TX_BCLK_RATE, 1865 ARIZONA_AIF1TX_BCPF_MASK, lrclk); 1866 regmap_update_bits_async(arizona->regmap, 1867 base + ARIZONA_AIF_RX_BCLK_RATE, 1868 ARIZONA_AIF1RX_BCPF_MASK, lrclk); 1869 regmap_update_bits_async(arizona->regmap, 1870 base + ARIZONA_AIF_FRAME_CTRL_1, 1871 ARIZONA_AIF1TX_WL_MASK | 1872 ARIZONA_AIF1TX_SLOT_LEN_MASK, frame); 1873 regmap_update_bits(arizona->regmap, 1874 base + ARIZONA_AIF_FRAME_CTRL_2, 1875 ARIZONA_AIF1RX_WL_MASK | 1876 ARIZONA_AIF1RX_SLOT_LEN_MASK, frame); 1877 } 1878 1879 restore_aif: 1880 if (reconfig) { 1881 /* Restore AIF TX/RX state */ 1882 regmap_update_bits_async(arizona->regmap, 1883 base + ARIZONA_AIF_TX_ENABLES, 1884 0xff, aif_tx_state); 1885 regmap_update_bits(arizona->regmap, 1886 base + ARIZONA_AIF_RX_ENABLES, 1887 0xff, aif_rx_state); 1888 } 1889 return ret; 1890 } 1891 1892 static const char *arizona_dai_clk_str(int clk_id) 1893 { 1894 switch (clk_id) { 1895 case ARIZONA_CLK_SYSCLK: 1896 return "SYSCLK"; 1897 case ARIZONA_CLK_ASYNCCLK: 1898 return "ASYNCCLK"; 1899 default: 1900 return "Unknown clock"; 1901 } 1902 } 1903 1904 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai, 1905 int clk_id, unsigned int freq, int dir) 1906 { 1907 struct snd_soc_component *component = dai->component; 1908 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1909 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1910 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1]; 1911 struct snd_soc_dapm_route routes[2]; 1912 1913 switch (clk_id) { 1914 case ARIZONA_CLK_SYSCLK: 1915 case ARIZONA_CLK_ASYNCCLK: 1916 break; 1917 default: 1918 return -EINVAL; 1919 } 1920 1921 if (clk_id == dai_priv->clk) 1922 return 0; 1923 1924 if (snd_soc_dai_active(dai)) { 1925 dev_err(component->dev, "Can't change clock on active DAI %d\n", 1926 dai->id); 1927 return -EBUSY; 1928 } 1929 1930 dev_dbg(component->dev, "Setting AIF%d to %s\n", dai->id + 1, 1931 arizona_dai_clk_str(clk_id)); 1932 1933 memset(&routes, 0, sizeof(routes)); 1934 routes[0].sink = dai->driver->capture.stream_name; 1935 routes[1].sink = dai->driver->playback.stream_name; 1936 1937 routes[0].source = arizona_dai_clk_str(dai_priv->clk); 1938 routes[1].source = arizona_dai_clk_str(dai_priv->clk); 1939 snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes)); 1940 1941 routes[0].source = arizona_dai_clk_str(clk_id); 1942 routes[1].source = arizona_dai_clk_str(clk_id); 1943 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes)); 1944 1945 dai_priv->clk = clk_id; 1946 1947 return snd_soc_dapm_sync(dapm); 1948 } 1949 1950 static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate) 1951 { 1952 struct snd_soc_component *component = dai->component; 1953 int base = dai->driver->base; 1954 unsigned int reg; 1955 1956 if (tristate) 1957 reg = ARIZONA_AIF1_TRI; 1958 else 1959 reg = 0; 1960 1961 return snd_soc_component_update_bits(component, 1962 base + ARIZONA_AIF_RATE_CTRL, 1963 ARIZONA_AIF1_TRI, reg); 1964 } 1965 1966 static void arizona_set_channels_to_mask(struct snd_soc_dai *dai, 1967 unsigned int base, 1968 int channels, unsigned int mask) 1969 { 1970 struct snd_soc_component *component = dai->component; 1971 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1972 struct arizona *arizona = priv->arizona; 1973 int slot, i; 1974 1975 for (i = 0; i < channels; ++i) { 1976 slot = ffs(mask) - 1; 1977 if (slot < 0) 1978 return; 1979 1980 regmap_write(arizona->regmap, base + i, slot); 1981 1982 mask &= ~(1 << slot); 1983 } 1984 1985 if (mask) 1986 arizona_aif_warn(dai, "Too many channels in TDM mask\n"); 1987 } 1988 1989 static int arizona_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1990 unsigned int rx_mask, int slots, int slot_width) 1991 { 1992 struct snd_soc_component *component = dai->component; 1993 struct arizona_priv *priv = snd_soc_component_get_drvdata(component); 1994 struct arizona *arizona = priv->arizona; 1995 int base = dai->driver->base; 1996 int rx_max_chan = dai->driver->playback.channels_max; 1997 int tx_max_chan = dai->driver->capture.channels_max; 1998 1999 /* Only support TDM for the physical AIFs */ 2000 if (dai->id > ARIZONA_MAX_AIF) 2001 return -ENOTSUPP; 2002 2003 if (slots == 0) { 2004 tx_mask = (1 << tx_max_chan) - 1; 2005 rx_mask = (1 << rx_max_chan) - 1; 2006 } 2007 2008 arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_3, 2009 tx_max_chan, tx_mask); 2010 arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_11, 2011 rx_max_chan, rx_mask); 2012 2013 arizona->tdm_width[dai->id - 1] = slot_width; 2014 arizona->tdm_slots[dai->id - 1] = slots; 2015 2016 return 0; 2017 } 2018 2019 const struct snd_soc_dai_ops arizona_dai_ops = { 2020 .startup = arizona_startup, 2021 .set_fmt = arizona_set_fmt, 2022 .set_tdm_slot = arizona_set_tdm_slot, 2023 .hw_params = arizona_hw_params, 2024 .set_sysclk = arizona_dai_set_sysclk, 2025 .set_tristate = arizona_set_tristate, 2026 }; 2027 EXPORT_SYMBOL_GPL(arizona_dai_ops); 2028 2029 const struct snd_soc_dai_ops arizona_simple_dai_ops = { 2030 .startup = arizona_startup, 2031 .hw_params = arizona_hw_params_rate, 2032 .set_sysclk = arizona_dai_set_sysclk, 2033 }; 2034 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops); 2035 2036 int arizona_init_dai(struct arizona_priv *priv, int id) 2037 { 2038 struct arizona_dai_priv *dai_priv = &priv->dai[id]; 2039 2040 dai_priv->clk = ARIZONA_CLK_SYSCLK; 2041 dai_priv->constraint = arizona_constraint; 2042 2043 return 0; 2044 } 2045 EXPORT_SYMBOL_GPL(arizona_init_dai); 2046 2047 static struct { 2048 unsigned int min; 2049 unsigned int max; 2050 u16 fratio; 2051 int ratio; 2052 } fll_fratios[] = { 2053 { 0, 64000, 4, 16 }, 2054 { 64000, 128000, 3, 8 }, 2055 { 128000, 256000, 2, 4 }, 2056 { 256000, 1000000, 1, 2 }, 2057 { 1000000, 13500000, 0, 1 }, 2058 }; 2059 2060 static const unsigned int pseudo_fref_max[ARIZONA_FLL_MAX_FRATIO] = { 2061 13500000, 2062 6144000, 2063 6144000, 2064 3072000, 2065 3072000, 2066 2822400, 2067 2822400, 2068 1536000, 2069 1536000, 2070 1536000, 2071 1536000, 2072 1536000, 2073 1536000, 2074 1536000, 2075 1536000, 2076 768000, 2077 }; 2078 2079 static struct { 2080 unsigned int min; 2081 unsigned int max; 2082 u16 gain; 2083 } fll_gains[] = { 2084 { 0, 256000, 0 }, 2085 { 256000, 1000000, 2 }, 2086 { 1000000, 13500000, 4 }, 2087 }; 2088 2089 struct arizona_fll_cfg { 2090 int n; 2091 unsigned int theta; 2092 unsigned int lambda; 2093 int refdiv; 2094 int outdiv; 2095 int fratio; 2096 int gain; 2097 }; 2098 2099 static int arizona_validate_fll(struct arizona_fll *fll, 2100 unsigned int Fref, 2101 unsigned int Fout) 2102 { 2103 unsigned int Fvco_min; 2104 2105 if (fll->fout && Fout != fll->fout) { 2106 arizona_fll_err(fll, 2107 "Can't change output on active FLL\n"); 2108 return -EINVAL; 2109 } 2110 2111 if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) { 2112 arizona_fll_err(fll, 2113 "Can't scale %dMHz in to <=13.5MHz\n", 2114 Fref); 2115 return -EINVAL; 2116 } 2117 2118 Fvco_min = ARIZONA_FLL_MIN_FVCO * fll->vco_mult; 2119 if (Fout * ARIZONA_FLL_MAX_OUTDIV < Fvco_min) { 2120 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n", 2121 Fout); 2122 return -EINVAL; 2123 } 2124 2125 return 0; 2126 } 2127 2128 static int arizona_find_fratio(unsigned int Fref, int *fratio) 2129 { 2130 int i; 2131 2132 /* Find an appropriate FLL_FRATIO */ 2133 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 2134 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 2135 if (fratio) 2136 *fratio = fll_fratios[i].fratio; 2137 return fll_fratios[i].ratio; 2138 } 2139 } 2140 2141 return -EINVAL; 2142 } 2143 2144 static int arizona_calc_fratio(struct arizona_fll *fll, 2145 struct arizona_fll_cfg *cfg, 2146 unsigned int target, 2147 unsigned int Fref, bool sync) 2148 { 2149 int init_ratio, ratio; 2150 int refdiv, div; 2151 2152 /* Fref must be <=13.5MHz, find initial refdiv */ 2153 div = 1; 2154 cfg->refdiv = 0; 2155 while (Fref > ARIZONA_FLL_MAX_FREF) { 2156 div *= 2; 2157 Fref /= 2; 2158 cfg->refdiv++; 2159 2160 if (div > ARIZONA_FLL_MAX_REFDIV) 2161 return -EINVAL; 2162 } 2163 2164 /* Find an appropriate FLL_FRATIO */ 2165 init_ratio = arizona_find_fratio(Fref, &cfg->fratio); 2166 if (init_ratio < 0) { 2167 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n", 2168 Fref); 2169 return init_ratio; 2170 } 2171 2172 switch (fll->arizona->type) { 2173 case WM5102: 2174 case WM8997: 2175 return init_ratio; 2176 case WM5110: 2177 case WM8280: 2178 if (fll->arizona->rev < 3 || sync) 2179 return init_ratio; 2180 break; 2181 default: 2182 if (sync) 2183 return init_ratio; 2184 break; 2185 } 2186 2187 cfg->fratio = init_ratio - 1; 2188 2189 /* Adjust FRATIO/refdiv to avoid integer mode if possible */ 2190 refdiv = cfg->refdiv; 2191 2192 arizona_fll_dbg(fll, "pseudo: initial ratio=%u fref=%u refdiv=%u\n", 2193 init_ratio, Fref, refdiv); 2194 2195 while (div <= ARIZONA_FLL_MAX_REFDIV) { 2196 /* start from init_ratio because this may already give a 2197 * fractional N.K 2198 */ 2199 for (ratio = init_ratio; ratio > 0; ratio--) { 2200 if (target % (ratio * Fref)) { 2201 cfg->refdiv = refdiv; 2202 cfg->fratio = ratio - 1; 2203 arizona_fll_dbg(fll, 2204 "pseudo: found fref=%u refdiv=%d(%d) ratio=%d\n", 2205 Fref, refdiv, div, ratio); 2206 return ratio; 2207 } 2208 } 2209 2210 for (ratio = init_ratio + 1; ratio <= ARIZONA_FLL_MAX_FRATIO; 2211 ratio++) { 2212 if ((ARIZONA_FLL_VCO_CORNER / 2) / 2213 (fll->vco_mult * ratio) < Fref) { 2214 arizona_fll_dbg(fll, "pseudo: hit VCO corner\n"); 2215 break; 2216 } 2217 2218 if (Fref > pseudo_fref_max[ratio - 1]) { 2219 arizona_fll_dbg(fll, 2220 "pseudo: exceeded max fref(%u) for ratio=%u\n", 2221 pseudo_fref_max[ratio - 1], 2222 ratio); 2223 break; 2224 } 2225 2226 if (target % (ratio * Fref)) { 2227 cfg->refdiv = refdiv; 2228 cfg->fratio = ratio - 1; 2229 arizona_fll_dbg(fll, 2230 "pseudo: found fref=%u refdiv=%d(%d) ratio=%d\n", 2231 Fref, refdiv, div, ratio); 2232 return ratio; 2233 } 2234 } 2235 2236 div *= 2; 2237 Fref /= 2; 2238 refdiv++; 2239 init_ratio = arizona_find_fratio(Fref, NULL); 2240 arizona_fll_dbg(fll, 2241 "pseudo: change fref=%u refdiv=%d(%d) ratio=%u\n", 2242 Fref, refdiv, div, init_ratio); 2243 } 2244 2245 arizona_fll_warn(fll, "Falling back to integer mode operation\n"); 2246 return cfg->fratio + 1; 2247 } 2248 2249 static int arizona_calc_fll(struct arizona_fll *fll, 2250 struct arizona_fll_cfg *cfg, 2251 unsigned int Fref, bool sync) 2252 { 2253 unsigned int target, div, gcd_fll; 2254 int i, ratio; 2255 2256 arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, fll->fout); 2257 2258 /* Fvco should be over the targt; don't check the upper bound */ 2259 div = ARIZONA_FLL_MIN_OUTDIV; 2260 while (fll->fout * div < ARIZONA_FLL_MIN_FVCO * fll->vco_mult) { 2261 div++; 2262 if (div > ARIZONA_FLL_MAX_OUTDIV) 2263 return -EINVAL; 2264 } 2265 target = fll->fout * div / fll->vco_mult; 2266 cfg->outdiv = div; 2267 2268 arizona_fll_dbg(fll, "Fvco=%dHz\n", target); 2269 2270 /* Find an appropriate FLL_FRATIO and refdiv */ 2271 ratio = arizona_calc_fratio(fll, cfg, target, Fref, sync); 2272 if (ratio < 0) 2273 return ratio; 2274 2275 /* Apply the division for our remaining calculations */ 2276 Fref = Fref / (1 << cfg->refdiv); 2277 2278 cfg->n = target / (ratio * Fref); 2279 2280 if (target % (ratio * Fref)) { 2281 gcd_fll = gcd(target, ratio * Fref); 2282 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll); 2283 2284 cfg->theta = (target - (cfg->n * ratio * Fref)) 2285 / gcd_fll; 2286 cfg->lambda = (ratio * Fref) / gcd_fll; 2287 } else { 2288 cfg->theta = 0; 2289 cfg->lambda = 0; 2290 } 2291 2292 /* Round down to 16bit range with cost of accuracy lost. 2293 * Denominator must be bigger than numerator so we only 2294 * take care of it. 2295 */ 2296 while (cfg->lambda >= (1 << 16)) { 2297 cfg->theta >>= 1; 2298 cfg->lambda >>= 1; 2299 } 2300 2301 for (i = 0; i < ARRAY_SIZE(fll_gains); i++) { 2302 if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) { 2303 cfg->gain = fll_gains[i].gain; 2304 break; 2305 } 2306 } 2307 if (i == ARRAY_SIZE(fll_gains)) { 2308 arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n", 2309 Fref); 2310 return -EINVAL; 2311 } 2312 2313 arizona_fll_dbg(fll, "N=%d THETA=%d LAMBDA=%d\n", 2314 cfg->n, cfg->theta, cfg->lambda); 2315 arizona_fll_dbg(fll, "FRATIO=0x%x(%d) OUTDIV=%d REFCLK_DIV=0x%x(%d)\n", 2316 cfg->fratio, ratio, cfg->outdiv, 2317 cfg->refdiv, 1 << cfg->refdiv); 2318 arizona_fll_dbg(fll, "GAIN=0x%x(%d)\n", cfg->gain, 1 << cfg->gain); 2319 2320 return 0; 2321 } 2322 2323 static void arizona_apply_fll(struct arizona *arizona, unsigned int base, 2324 struct arizona_fll_cfg *cfg, int source, 2325 bool sync) 2326 { 2327 regmap_update_bits_async(arizona->regmap, base + 3, 2328 ARIZONA_FLL1_THETA_MASK, cfg->theta); 2329 regmap_update_bits_async(arizona->regmap, base + 4, 2330 ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda); 2331 regmap_update_bits_async(arizona->regmap, base + 5, 2332 ARIZONA_FLL1_FRATIO_MASK, 2333 cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT); 2334 regmap_update_bits_async(arizona->regmap, base + 6, 2335 ARIZONA_FLL1_CLK_REF_DIV_MASK | 2336 ARIZONA_FLL1_CLK_REF_SRC_MASK, 2337 cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT | 2338 source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT); 2339 2340 if (sync) { 2341 regmap_update_bits(arizona->regmap, base + 0x7, 2342 ARIZONA_FLL1_GAIN_MASK, 2343 cfg->gain << ARIZONA_FLL1_GAIN_SHIFT); 2344 } else { 2345 regmap_update_bits(arizona->regmap, base + 0x5, 2346 ARIZONA_FLL1_OUTDIV_MASK, 2347 cfg->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT); 2348 regmap_update_bits(arizona->regmap, base + 0x9, 2349 ARIZONA_FLL1_GAIN_MASK, 2350 cfg->gain << ARIZONA_FLL1_GAIN_SHIFT); 2351 } 2352 2353 regmap_update_bits_async(arizona->regmap, base + 2, 2354 ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK, 2355 ARIZONA_FLL1_CTRL_UPD | cfg->n); 2356 } 2357 2358 static int arizona_is_enabled_fll(struct arizona_fll *fll, int base) 2359 { 2360 struct arizona *arizona = fll->arizona; 2361 unsigned int reg; 2362 int ret; 2363 2364 ret = regmap_read(arizona->regmap, base + 1, ®); 2365 if (ret != 0) { 2366 arizona_fll_err(fll, "Failed to read current state: %d\n", 2367 ret); 2368 return ret; 2369 } 2370 2371 return reg & ARIZONA_FLL1_ENA; 2372 } 2373 2374 static int arizona_set_fll_clks(struct arizona_fll *fll, int base, bool ena) 2375 { 2376 struct arizona *arizona = fll->arizona; 2377 unsigned int val; 2378 struct clk *clk; 2379 int ret; 2380 2381 ret = regmap_read(arizona->regmap, base + 6, &val); 2382 if (ret != 0) { 2383 arizona_fll_err(fll, "Failed to read current source: %d\n", 2384 ret); 2385 return ret; 2386 } 2387 2388 val &= ARIZONA_FLL1_CLK_REF_SRC_MASK; 2389 val >>= ARIZONA_FLL1_CLK_REF_SRC_SHIFT; 2390 2391 switch (val) { 2392 case ARIZONA_FLL_SRC_MCLK1: 2393 clk = arizona->mclk[ARIZONA_MCLK1]; 2394 break; 2395 case ARIZONA_FLL_SRC_MCLK2: 2396 clk = arizona->mclk[ARIZONA_MCLK2]; 2397 break; 2398 default: 2399 return 0; 2400 } 2401 2402 if (ena) { 2403 return clk_prepare_enable(clk); 2404 } else { 2405 clk_disable_unprepare(clk); 2406 return 0; 2407 } 2408 } 2409 2410 static int arizona_enable_fll(struct arizona_fll *fll) 2411 { 2412 struct arizona *arizona = fll->arizona; 2413 bool use_sync = false; 2414 int already_enabled = arizona_is_enabled_fll(fll, fll->base); 2415 int sync_enabled = arizona_is_enabled_fll(fll, fll->base + 0x10); 2416 struct arizona_fll_cfg cfg; 2417 int i; 2418 unsigned int val; 2419 2420 if (already_enabled < 0) 2421 return already_enabled; 2422 if (sync_enabled < 0) 2423 return sync_enabled; 2424 2425 if (already_enabled) { 2426 /* Facilitate smooth refclk across the transition */ 2427 regmap_update_bits(fll->arizona->regmap, fll->base + 1, 2428 ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN); 2429 udelay(32); 2430 regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x9, 2431 ARIZONA_FLL1_GAIN_MASK, 0); 2432 2433 if (arizona_is_enabled_fll(fll, fll->base + 0x10) > 0) 2434 arizona_set_fll_clks(fll, fll->base + 0x10, false); 2435 arizona_set_fll_clks(fll, fll->base, false); 2436 } 2437 2438 /* 2439 * If we have both REFCLK and SYNCCLK then enable both, 2440 * otherwise apply the SYNCCLK settings to REFCLK. 2441 */ 2442 if (fll->ref_src >= 0 && fll->ref_freq && 2443 fll->ref_src != fll->sync_src) { 2444 arizona_calc_fll(fll, &cfg, fll->ref_freq, false); 2445 2446 /* Ref path hardcodes lambda to 65536 when sync is on */ 2447 if (fll->sync_src >= 0 && cfg.lambda) 2448 cfg.theta = (cfg.theta * (1 << 16)) / cfg.lambda; 2449 2450 arizona_apply_fll(arizona, fll->base, &cfg, fll->ref_src, 2451 false); 2452 if (fll->sync_src >= 0) { 2453 arizona_calc_fll(fll, &cfg, fll->sync_freq, true); 2454 2455 arizona_apply_fll(arizona, fll->base + 0x10, &cfg, 2456 fll->sync_src, true); 2457 use_sync = true; 2458 } 2459 } else if (fll->sync_src >= 0) { 2460 arizona_calc_fll(fll, &cfg, fll->sync_freq, false); 2461 2462 arizona_apply_fll(arizona, fll->base, &cfg, 2463 fll->sync_src, false); 2464 2465 regmap_update_bits_async(arizona->regmap, fll->base + 0x11, 2466 ARIZONA_FLL1_SYNC_ENA, 0); 2467 } else { 2468 arizona_fll_err(fll, "No clocks provided\n"); 2469 return -EINVAL; 2470 } 2471 2472 if (already_enabled && !!sync_enabled != use_sync) 2473 arizona_fll_warn(fll, "Synchroniser changed on active FLL\n"); 2474 2475 /* 2476 * Increase the bandwidth if we're not using a low frequency 2477 * sync source. 2478 */ 2479 if (use_sync && fll->sync_freq > 100000) 2480 regmap_update_bits_async(arizona->regmap, fll->base + 0x17, 2481 ARIZONA_FLL1_SYNC_BW, 0); 2482 else 2483 regmap_update_bits_async(arizona->regmap, fll->base + 0x17, 2484 ARIZONA_FLL1_SYNC_BW, 2485 ARIZONA_FLL1_SYNC_BW); 2486 2487 if (!already_enabled) 2488 pm_runtime_get_sync(arizona->dev); 2489 2490 if (use_sync) { 2491 arizona_set_fll_clks(fll, fll->base + 0x10, true); 2492 regmap_update_bits_async(arizona->regmap, fll->base + 0x11, 2493 ARIZONA_FLL1_SYNC_ENA, 2494 ARIZONA_FLL1_SYNC_ENA); 2495 } 2496 arizona_set_fll_clks(fll, fll->base, true); 2497 regmap_update_bits_async(arizona->regmap, fll->base + 1, 2498 ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA); 2499 2500 if (already_enabled) 2501 regmap_update_bits_async(arizona->regmap, fll->base + 1, 2502 ARIZONA_FLL1_FREERUN, 0); 2503 2504 arizona_fll_dbg(fll, "Waiting for FLL lock...\n"); 2505 val = 0; 2506 for (i = 0; i < 15; i++) { 2507 if (i < 5) 2508 usleep_range(200, 400); 2509 else 2510 msleep(20); 2511 2512 regmap_read(arizona->regmap, 2513 ARIZONA_INTERRUPT_RAW_STATUS_5, 2514 &val); 2515 if (val & (ARIZONA_FLL1_CLOCK_OK_STS << (fll->id - 1))) 2516 break; 2517 } 2518 if (i == 15) 2519 arizona_fll_warn(fll, "Timed out waiting for lock\n"); 2520 else 2521 arizona_fll_dbg(fll, "FLL locked (%d polls)\n", i); 2522 2523 return 0; 2524 } 2525 2526 static void arizona_disable_fll(struct arizona_fll *fll) 2527 { 2528 struct arizona *arizona = fll->arizona; 2529 bool ref_change, sync_change; 2530 2531 regmap_update_bits_async(arizona->regmap, fll->base + 1, 2532 ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN); 2533 regmap_update_bits_check(arizona->regmap, fll->base + 1, 2534 ARIZONA_FLL1_ENA, 0, &ref_change); 2535 regmap_update_bits_check(arizona->regmap, fll->base + 0x11, 2536 ARIZONA_FLL1_SYNC_ENA, 0, &sync_change); 2537 regmap_update_bits_async(arizona->regmap, fll->base + 1, 2538 ARIZONA_FLL1_FREERUN, 0); 2539 2540 if (sync_change) 2541 arizona_set_fll_clks(fll, fll->base + 0x10, false); 2542 2543 if (ref_change) { 2544 arizona_set_fll_clks(fll, fll->base, false); 2545 pm_runtime_put_autosuspend(arizona->dev); 2546 } 2547 } 2548 2549 int arizona_set_fll_refclk(struct arizona_fll *fll, int source, 2550 unsigned int Fref, unsigned int Fout) 2551 { 2552 int ret = 0; 2553 2554 if (fll->ref_src == source && fll->ref_freq == Fref) 2555 return 0; 2556 2557 if (fll->fout && Fref > 0) { 2558 ret = arizona_validate_fll(fll, Fref, fll->fout); 2559 if (ret != 0) 2560 return ret; 2561 } 2562 2563 fll->ref_src = source; 2564 fll->ref_freq = Fref; 2565 2566 if (fll->fout && Fref > 0) 2567 ret = arizona_enable_fll(fll); 2568 2569 return ret; 2570 } 2571 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk); 2572 2573 int arizona_set_fll(struct arizona_fll *fll, int source, 2574 unsigned int Fref, unsigned int Fout) 2575 { 2576 int ret = 0; 2577 2578 if (fll->sync_src == source && 2579 fll->sync_freq == Fref && fll->fout == Fout) 2580 return 0; 2581 2582 if (Fout) { 2583 if (fll->ref_src >= 0) { 2584 ret = arizona_validate_fll(fll, fll->ref_freq, Fout); 2585 if (ret != 0) 2586 return ret; 2587 } 2588 2589 ret = arizona_validate_fll(fll, Fref, Fout); 2590 if (ret != 0) 2591 return ret; 2592 } 2593 2594 fll->sync_src = source; 2595 fll->sync_freq = Fref; 2596 fll->fout = Fout; 2597 2598 if (Fout) 2599 ret = arizona_enable_fll(fll); 2600 else 2601 arizona_disable_fll(fll); 2602 2603 return ret; 2604 } 2605 EXPORT_SYMBOL_GPL(arizona_set_fll); 2606 2607 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq, 2608 int ok_irq, struct arizona_fll *fll) 2609 { 2610 unsigned int val; 2611 2612 fll->id = id; 2613 fll->base = base; 2614 fll->arizona = arizona; 2615 fll->sync_src = ARIZONA_FLL_SRC_NONE; 2616 2617 /* Configure default refclk to 32kHz if we have one */ 2618 regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val); 2619 switch (val & ARIZONA_CLK_32K_SRC_MASK) { 2620 case ARIZONA_CLK_SRC_MCLK1: 2621 case ARIZONA_CLK_SRC_MCLK2: 2622 fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK; 2623 break; 2624 default: 2625 fll->ref_src = ARIZONA_FLL_SRC_NONE; 2626 } 2627 fll->ref_freq = 32768; 2628 2629 snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id); 2630 snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name), 2631 "FLL%d clock OK", id); 2632 2633 regmap_update_bits(arizona->regmap, fll->base + 1, 2634 ARIZONA_FLL1_FREERUN, 0); 2635 2636 return 0; 2637 } 2638 EXPORT_SYMBOL_GPL(arizona_init_fll); 2639 2640 /** 2641 * arizona_set_output_mode - Set the mode of the specified output 2642 * 2643 * @component: Device to configure 2644 * @output: Output number 2645 * @diff: True to set the output to differential mode 2646 * 2647 * Some systems use external analogue switches to connect more 2648 * analogue devices to the CODEC than are supported by the device. In 2649 * some systems this requires changing the switched output from single 2650 * ended to differential mode dynamically at runtime, an operation 2651 * supported using this function. 2652 * 2653 * Most systems have a single static configuration and should use 2654 * platform data instead. 2655 */ 2656 int arizona_set_output_mode(struct snd_soc_component *component, int output, 2657 bool diff) 2658 { 2659 unsigned int reg, val; 2660 2661 if (output < 1 || output > 6) 2662 return -EINVAL; 2663 2664 reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8; 2665 2666 if (diff) 2667 val = ARIZONA_OUT1_MONO; 2668 else 2669 val = 0; 2670 2671 return snd_soc_component_update_bits(component, reg, 2672 ARIZONA_OUT1_MONO, val); 2673 } 2674 EXPORT_SYMBOL_GPL(arizona_set_output_mode); 2675 2676 static const struct soc_enum arizona_adsp2_rate_enum[] = { 2677 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1, 2678 ARIZONA_DSP1_RATE_SHIFT, 0xf, 2679 ARIZONA_RATE_ENUM_SIZE, 2680 arizona_rate_text, arizona_rate_val), 2681 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1, 2682 ARIZONA_DSP1_RATE_SHIFT, 0xf, 2683 ARIZONA_RATE_ENUM_SIZE, 2684 arizona_rate_text, arizona_rate_val), 2685 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1, 2686 ARIZONA_DSP1_RATE_SHIFT, 0xf, 2687 ARIZONA_RATE_ENUM_SIZE, 2688 arizona_rate_text, arizona_rate_val), 2689 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1, 2690 ARIZONA_DSP1_RATE_SHIFT, 0xf, 2691 ARIZONA_RATE_ENUM_SIZE, 2692 arizona_rate_text, arizona_rate_val), 2693 }; 2694 2695 const struct snd_kcontrol_new arizona_adsp2_rate_controls[] = { 2696 SOC_ENUM("DSP1 Rate", arizona_adsp2_rate_enum[0]), 2697 SOC_ENUM("DSP2 Rate", arizona_adsp2_rate_enum[1]), 2698 SOC_ENUM("DSP3 Rate", arizona_adsp2_rate_enum[2]), 2699 SOC_ENUM("DSP4 Rate", arizona_adsp2_rate_enum[3]), 2700 }; 2701 EXPORT_SYMBOL_GPL(arizona_adsp2_rate_controls); 2702 2703 static bool arizona_eq_filter_unstable(bool mode, __be16 _a, __be16 _b) 2704 { 2705 s16 a = be16_to_cpu(_a); 2706 s16 b = be16_to_cpu(_b); 2707 2708 if (!mode) { 2709 return abs(a) >= 4096; 2710 } else { 2711 if (abs(b) >= 4096) 2712 return true; 2713 2714 return (abs((a << 16) / (4096 - b)) >= 4096 << 4); 2715 } 2716 } 2717 2718 int arizona_eq_coeff_put(struct snd_kcontrol *kcontrol, 2719 struct snd_ctl_elem_value *ucontrol) 2720 { 2721 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2722 struct arizona *arizona = dev_get_drvdata(component->dev->parent); 2723 struct soc_bytes *params = (void *)kcontrol->private_value; 2724 unsigned int val; 2725 __be16 *data; 2726 int len; 2727 int ret; 2728 2729 len = params->num_regs * regmap_get_val_bytes(arizona->regmap); 2730 2731 data = kmemdup(ucontrol->value.bytes.data, len, GFP_KERNEL | GFP_DMA); 2732 if (!data) 2733 return -ENOMEM; 2734 2735 data[0] &= cpu_to_be16(ARIZONA_EQ1_B1_MODE); 2736 2737 if (arizona_eq_filter_unstable(!!data[0], data[1], data[2]) || 2738 arizona_eq_filter_unstable(true, data[4], data[5]) || 2739 arizona_eq_filter_unstable(true, data[8], data[9]) || 2740 arizona_eq_filter_unstable(true, data[12], data[13]) || 2741 arizona_eq_filter_unstable(false, data[16], data[17])) { 2742 dev_err(arizona->dev, "Rejecting unstable EQ coefficients\n"); 2743 ret = -EINVAL; 2744 goto out; 2745 } 2746 2747 ret = regmap_read(arizona->regmap, params->base, &val); 2748 if (ret != 0) 2749 goto out; 2750 2751 val &= ~ARIZONA_EQ1_B1_MODE; 2752 data[0] |= cpu_to_be16(val); 2753 2754 ret = regmap_raw_write(arizona->regmap, params->base, data, len); 2755 2756 out: 2757 kfree(data); 2758 return ret; 2759 } 2760 EXPORT_SYMBOL_GPL(arizona_eq_coeff_put); 2761 2762 int arizona_lhpf_coeff_put(struct snd_kcontrol *kcontrol, 2763 struct snd_ctl_elem_value *ucontrol) 2764 { 2765 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2766 struct arizona *arizona = dev_get_drvdata(component->dev->parent); 2767 __be16 *data = (__be16 *)ucontrol->value.bytes.data; 2768 s16 val = be16_to_cpu(*data); 2769 2770 if (abs(val) >= 4096) { 2771 dev_err(arizona->dev, "Rejecting unstable LHPF coefficients\n"); 2772 return -EINVAL; 2773 } 2774 2775 return snd_soc_bytes_put(kcontrol, ucontrol); 2776 } 2777 EXPORT_SYMBOL_GPL(arizona_lhpf_coeff_put); 2778 2779 int arizona_of_get_audio_pdata(struct arizona *arizona) 2780 { 2781 struct arizona_pdata *pdata = &arizona->pdata; 2782 struct device_node *np = arizona->dev->of_node; 2783 u32 val; 2784 u32 pdm_val[ARIZONA_MAX_PDM_SPK]; 2785 int ret; 2786 int count = 0; 2787 2788 count = 0; 2789 of_property_for_each_u32(np, "wlf,inmode", val) { 2790 if (count == ARRAY_SIZE(pdata->inmode)) 2791 break; 2792 2793 pdata->inmode[count] = val; 2794 count++; 2795 } 2796 2797 count = 0; 2798 of_property_for_each_u32(np, "wlf,dmic-ref", val) { 2799 if (count == ARRAY_SIZE(pdata->dmic_ref)) 2800 break; 2801 2802 pdata->dmic_ref[count] = val; 2803 count++; 2804 } 2805 2806 count = 0; 2807 of_property_for_each_u32(np, "wlf,out-mono", val) { 2808 if (count == ARRAY_SIZE(pdata->out_mono)) 2809 break; 2810 2811 pdata->out_mono[count] = !!val; 2812 count++; 2813 } 2814 2815 count = 0; 2816 of_property_for_each_u32(np, "wlf,max-channels-clocked", val) { 2817 if (count == ARRAY_SIZE(pdata->max_channels_clocked)) 2818 break; 2819 2820 pdata->max_channels_clocked[count] = val; 2821 count++; 2822 } 2823 2824 count = 0; 2825 of_property_for_each_u32(np, "wlf,out-volume-limit", val) { 2826 if (count == ARRAY_SIZE(pdata->out_vol_limit)) 2827 break; 2828 2829 pdata->out_vol_limit[count] = val; 2830 count++; 2831 } 2832 2833 ret = of_property_read_u32_array(np, "wlf,spk-fmt", 2834 pdm_val, ARRAY_SIZE(pdm_val)); 2835 2836 if (ret >= 0) 2837 for (count = 0; count < ARRAY_SIZE(pdata->spk_fmt); ++count) 2838 pdata->spk_fmt[count] = pdm_val[count]; 2839 2840 ret = of_property_read_u32_array(np, "wlf,spk-mute", 2841 pdm_val, ARRAY_SIZE(pdm_val)); 2842 2843 if (ret >= 0) 2844 for (count = 0; count < ARRAY_SIZE(pdata->spk_mute); ++count) 2845 pdata->spk_mute[count] = pdm_val[count]; 2846 2847 return 0; 2848 } 2849 EXPORT_SYMBOL_GPL(arizona_of_get_audio_pdata); 2850 2851 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support"); 2852 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 2853 MODULE_LICENSE("GPL"); 2854