1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for the ADC present in the Atmel AT91 evaluation boards. 4 * 5 * Copyright 2011 Free Electrons 6 */ 7 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/input.h> 15 #include <linux/interrupt.h> 16 #include <linux/jiffies.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/sched.h> 22 #include <linux/slab.h> 23 #include <linux/wait.h> 24 25 #include <linux/iio/iio.h> 26 #include <linux/iio/buffer.h> 27 #include <linux/iio/trigger.h> 28 #include <linux/iio/trigger_consumer.h> 29 #include <linux/iio/triggered_buffer.h> 30 #include <linux/pinctrl/consumer.h> 31 32 /* Registers */ 33 #define AT91_ADC_CR 0x00 /* Control Register */ 34 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */ 35 #define AT91_ADC_START (1 << 1) /* Start Conversion */ 36 37 #define AT91_ADC_MR 0x04 /* Mode Register */ 38 #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */ 39 #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */ 40 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */ 41 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ 42 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ 43 #define AT91_ADC_TRGSEL_TC0 (0 << 1) 44 #define AT91_ADC_TRGSEL_TC1 (1 << 1) 45 #define AT91_ADC_TRGSEL_TC2 (2 << 1) 46 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) 47 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ 48 #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ 49 #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */ 50 #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */ 51 #define AT91_ADC_PRESCAL_9G45 (0xff << 8) 52 #define AT91_ADC_PRESCAL_(x) ((x) << 8) 53 #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */ 54 #define AT91_ADC_STARTUP_9G45 (0x7f << 16) 55 #define AT91_ADC_STARTUP_9X5 (0xf << 16) 56 #define AT91_ADC_STARTUP_(x) ((x) << 16) 57 #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ 58 #define AT91_ADC_SHTIM_(x) ((x) << 24) 59 #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */ 60 #define AT91_ADC_PENDBC_(x) ((x) << 28) 61 62 #define AT91_ADC_TSR 0x0C 63 #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */ 64 #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24) 65 66 #define AT91_ADC_CHER 0x10 /* Channel Enable Register */ 67 #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ 68 #define AT91_ADC_CHSR 0x18 /* Channel Status Register */ 69 #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ 70 71 #define AT91_ADC_SR 0x1C /* Status Register */ 72 #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ 73 #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ 74 #define AT91_ADC_DRDY (1 << 16) /* Data Ready */ 75 #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ 76 #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ 77 #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ 78 79 #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */ 80 #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */ 81 82 #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ 83 #define AT91_ADC_LDATA (0x3ff) 84 85 #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ 86 #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ 87 #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ 88 #define AT91RL_ADC_IER_PEN (1 << 20) 89 #define AT91RL_ADC_IER_NOPEN (1 << 21) 90 #define AT91_ADC_IER_PEN (1 << 29) 91 #define AT91_ADC_IER_NOPEN (1 << 30) 92 #define AT91_ADC_IER_XRDY (1 << 20) 93 #define AT91_ADC_IER_YRDY (1 << 21) 94 #define AT91_ADC_IER_PRDY (1 << 22) 95 #define AT91_ADC_ISR_PENS (1 << 31) 96 97 #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ 98 #define AT91_ADC_DATA (0x3ff) 99 100 #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ 101 102 #define AT91_ADC_ACR 0x94 /* Analog Control Register */ 103 #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */ 104 105 #define AT91_ADC_TSMR 0xB0 106 #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */ 107 #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0) 108 #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0) 109 #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0) 110 #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0) 111 #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */ 112 #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4) 113 #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */ 114 #define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16) 115 #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */ 116 #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28) 117 #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */ 118 #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */ 119 #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */ 120 121 #define AT91_ADC_TSXPOSR 0xB4 122 #define AT91_ADC_TSYPOSR 0xB8 123 #define AT91_ADC_TSPRESSR 0xBC 124 125 #define AT91_ADC_TRGR_9260 AT91_ADC_MR 126 #define AT91_ADC_TRGR_9G45 0x08 127 #define AT91_ADC_TRGR_9X5 0xC0 128 129 /* Trigger Register bit field */ 130 #define AT91_ADC_TRGR_TRGPER (0xffff << 16) 131 #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16) 132 #define AT91_ADC_TRGR_TRGMOD (0x7 << 0) 133 #define AT91_ADC_TRGR_NONE (0 << 0) 134 #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0) 135 136 #define AT91_ADC_CHAN(st, ch) \ 137 (st->registers->channel_base + (ch * 4)) 138 #define at91_adc_readl(st, reg) \ 139 (readl_relaxed(st->reg_base + reg)) 140 #define at91_adc_writel(st, reg, val) \ 141 (writel_relaxed(val, st->reg_base + reg)) 142 143 #define DRIVER_NAME "at91_adc" 144 #define MAX_POS_BITS 12 145 146 #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ 147 #define TOUCH_PEN_DETECT_DEBOUNCE_US 200 148 149 #define MAX_RLPOS_BITS 10 150 #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */ 151 #define TOUCH_SHTIM 0xa 152 #define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */ 153 154 enum atmel_adc_ts_type { 155 ATMEL_ADC_TOUCHSCREEN_NONE = 0, 156 ATMEL_ADC_TOUCHSCREEN_4WIRE = 4, 157 ATMEL_ADC_TOUCHSCREEN_5WIRE = 5, 158 }; 159 160 /** 161 * struct at91_adc_trigger - description of triggers 162 * @name: name of the trigger advertised to the user 163 * @value: value to set in the ADC's trigger setup register 164 * to enable the trigger 165 * @is_external: Does the trigger rely on an external pin? 166 */ 167 struct at91_adc_trigger { 168 const char *name; 169 u8 value; 170 bool is_external; 171 }; 172 173 /** 174 * struct at91_adc_reg_desc - Various information relative to registers 175 * @channel_base: Base offset for the channel data registers 176 * @drdy_mask: Mask of the DRDY field in the relevant registers 177 * (Interruptions registers mostly) 178 * @status_register: Offset of the Interrupt Status Register 179 * @trigger_register: Offset of the Trigger setup register 180 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register 181 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register 182 */ 183 struct at91_adc_reg_desc { 184 u8 channel_base; 185 u32 drdy_mask; 186 u8 status_register; 187 u8 trigger_register; 188 u32 mr_prescal_mask; 189 u32 mr_startup_mask; 190 }; 191 192 struct at91_adc_caps { 193 bool has_ts; /* Support touch screen */ 194 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */ 195 /* 196 * Numbers of sampling data will be averaged. Can be 0~3. 197 * Hardware can average (2 ^ ts_filter_average) sample data. 198 */ 199 u8 ts_filter_average; 200 /* Pen Detection input pull-up resistor, can be 0~3 */ 201 u8 ts_pen_detect_sensitivity; 202 203 /* startup time calculate function */ 204 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz); 205 206 u8 num_channels; 207 208 u8 low_res_bits; 209 u8 high_res_bits; 210 u32 trigger_number; 211 const struct at91_adc_trigger *triggers; 212 struct at91_adc_reg_desc registers; 213 }; 214 215 struct at91_adc_state { 216 struct clk *adc_clk; 217 u16 *buffer; 218 unsigned long channels_mask; 219 struct clk *clk; 220 bool done; 221 int irq; 222 u16 last_value; 223 int chnb; 224 struct mutex lock; 225 u8 num_channels; 226 void __iomem *reg_base; 227 const struct at91_adc_reg_desc *registers; 228 u32 startup_time; 229 u8 sample_hold_time; 230 bool sleep_mode; 231 struct iio_trigger **trig; 232 bool use_external; 233 u32 vref_mv; 234 u32 res; /* resolution used for conversions */ 235 wait_queue_head_t wq_data_avail; 236 const struct at91_adc_caps *caps; 237 238 /* 239 * Following ADC channels are shared by touchscreen: 240 * 241 * CH0 -- Touch screen XP/UL 242 * CH1 -- Touch screen XM/UR 243 * CH2 -- Touch screen YP/LL 244 * CH3 -- Touch screen YM/Sense 245 * CH4 -- Touch screen LR(5-wire only) 246 * 247 * The bitfields below represents the reserved channel in the 248 * touchscreen mode. 249 */ 250 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0) 251 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0) 252 enum atmel_adc_ts_type touchscreen_type; 253 struct input_dev *ts_input; 254 255 u16 ts_sample_period_val; 256 u32 ts_pressure_threshold; 257 u16 ts_pendbc; 258 259 bool ts_bufferedmeasure; 260 u32 ts_prev_absx; 261 u32 ts_prev_absy; 262 }; 263 264 static irqreturn_t at91_adc_trigger_handler(int irq, void *p) 265 { 266 struct iio_poll_func *pf = p; 267 struct iio_dev *idev = pf->indio_dev; 268 struct at91_adc_state *st = iio_priv(idev); 269 struct iio_chan_spec const *chan; 270 int i, j = 0; 271 272 iio_for_each_active_channel(idev, i) { 273 chan = idev->channels + i; 274 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel)); 275 j++; 276 } 277 278 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp); 279 280 iio_trigger_notify_done(idev->trig); 281 282 /* Needed to ACK the DRDY interruption */ 283 at91_adc_readl(st, AT91_ADC_LCDR); 284 285 enable_irq(st->irq); 286 287 return IRQ_HANDLED; 288 } 289 290 /* Handler for classic adc channel eoc trigger */ 291 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev) 292 { 293 struct at91_adc_state *st = iio_priv(idev); 294 295 if (iio_buffer_enabled(idev)) { 296 disable_irq_nosync(irq); 297 iio_trigger_poll(idev->trig); 298 } else { 299 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb)); 300 /* Needed to ACK the DRDY interruption */ 301 at91_adc_readl(st, AT91_ADC_LCDR); 302 st->done = true; 303 wake_up_interruptible(&st->wq_data_avail); 304 } 305 } 306 307 static void at91_ts_sample(struct iio_dev *idev) 308 { 309 struct at91_adc_state *st = iio_priv(idev); 310 unsigned int xscale, yscale, reg, z1, z2; 311 unsigned int x, y, pres, xpos, ypos; 312 unsigned int rxp = 1; 313 unsigned int factor = 1000; 314 315 unsigned int xyz_mask_bits = st->res; 316 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1; 317 318 /* calculate position */ 319 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */ 320 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR); 321 xpos = reg & xyz_mask; 322 x = (xpos << MAX_POS_BITS) - xpos; 323 xscale = (reg >> 16) & xyz_mask; 324 if (xscale == 0) { 325 dev_err(&idev->dev, "Error: xscale == 0!\n"); 326 return; 327 } 328 x /= xscale; 329 330 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */ 331 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR); 332 ypos = reg & xyz_mask; 333 y = (ypos << MAX_POS_BITS) - ypos; 334 yscale = (reg >> 16) & xyz_mask; 335 if (yscale == 0) { 336 dev_err(&idev->dev, "Error: yscale == 0!\n"); 337 return; 338 } 339 y /= yscale; 340 341 /* calculate the pressure */ 342 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR); 343 z1 = reg & xyz_mask; 344 z2 = (reg >> 16) & xyz_mask; 345 346 if (z1 != 0) 347 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor) 348 / factor; 349 else 350 pres = st->ts_pressure_threshold; /* no pen contacted */ 351 352 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n", 353 xpos, xscale, ypos, yscale, z1, z2, pres); 354 355 if (pres < st->ts_pressure_threshold) { 356 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n", 357 x, y, pres / factor); 358 input_report_abs(st->ts_input, ABS_X, x); 359 input_report_abs(st->ts_input, ABS_Y, y); 360 input_report_abs(st->ts_input, ABS_PRESSURE, pres); 361 input_report_key(st->ts_input, BTN_TOUCH, 1); 362 input_sync(st->ts_input); 363 } else { 364 dev_dbg(&idev->dev, "pressure too low: not reporting\n"); 365 } 366 } 367 368 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private) 369 { 370 struct iio_dev *idev = private; 371 struct at91_adc_state *st = iio_priv(idev); 372 u32 status = at91_adc_readl(st, st->registers->status_register); 373 unsigned int reg; 374 375 status &= at91_adc_readl(st, AT91_ADC_IMR); 376 if (status & GENMASK(st->num_channels - 1, 0)) 377 handle_adc_eoc_trigger(irq, idev); 378 379 if (status & AT91RL_ADC_IER_PEN) { 380 /* Disabling pen debounce is required to get a NOPEN irq */ 381 reg = at91_adc_readl(st, AT91_ADC_MR); 382 reg &= ~AT91_ADC_PENDBC; 383 at91_adc_writel(st, AT91_ADC_MR, reg); 384 385 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); 386 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN 387 | AT91_ADC_EOC(3)); 388 /* Set up period trigger for sampling */ 389 at91_adc_writel(st, st->registers->trigger_register, 390 AT91_ADC_TRGR_MOD_PERIOD_TRIG | 391 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); 392 } else if (status & AT91RL_ADC_IER_NOPEN) { 393 reg = at91_adc_readl(st, AT91_ADC_MR); 394 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; 395 at91_adc_writel(st, AT91_ADC_MR, reg); 396 at91_adc_writel(st, st->registers->trigger_register, 397 AT91_ADC_TRGR_NONE); 398 399 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN 400 | AT91_ADC_EOC(3)); 401 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); 402 st->ts_bufferedmeasure = false; 403 input_report_key(st->ts_input, BTN_TOUCH, 0); 404 input_sync(st->ts_input); 405 } else if (status & AT91_ADC_EOC(3) && st->ts_input) { 406 /* Conversion finished and we've a touchscreen */ 407 if (st->ts_bufferedmeasure) { 408 /* 409 * Last measurement is always discarded, since it can 410 * be erroneous. 411 * Always report previous measurement 412 */ 413 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx); 414 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy); 415 input_report_key(st->ts_input, BTN_TOUCH, 1); 416 input_sync(st->ts_input); 417 } else 418 st->ts_bufferedmeasure = true; 419 420 /* Now make new measurement */ 421 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3)) 422 << MAX_RLPOS_BITS; 423 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2)); 424 425 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1)) 426 << MAX_RLPOS_BITS; 427 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0)); 428 } 429 430 return IRQ_HANDLED; 431 } 432 433 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private) 434 { 435 struct iio_dev *idev = private; 436 struct at91_adc_state *st = iio_priv(idev); 437 u32 status = at91_adc_readl(st, st->registers->status_register); 438 const uint32_t ts_data_irq_mask = 439 AT91_ADC_IER_XRDY | 440 AT91_ADC_IER_YRDY | 441 AT91_ADC_IER_PRDY; 442 443 if (status & GENMASK(st->num_channels - 1, 0)) 444 handle_adc_eoc_trigger(irq, idev); 445 446 if (status & AT91_ADC_IER_PEN) { 447 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); 448 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN | 449 ts_data_irq_mask); 450 /* Set up period trigger for sampling */ 451 at91_adc_writel(st, st->registers->trigger_register, 452 AT91_ADC_TRGR_MOD_PERIOD_TRIG | 453 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); 454 } else if (status & AT91_ADC_IER_NOPEN) { 455 at91_adc_writel(st, st->registers->trigger_register, 0); 456 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN | 457 ts_data_irq_mask); 458 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); 459 460 input_report_key(st->ts_input, BTN_TOUCH, 0); 461 input_sync(st->ts_input); 462 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) { 463 /* Now all touchscreen data is ready */ 464 465 if (status & AT91_ADC_ISR_PENS) { 466 /* validate data by pen contact */ 467 at91_ts_sample(idev); 468 } else { 469 /* triggered by event that is no pen contact, just read 470 * them to clean the interrupt and discard all. 471 */ 472 at91_adc_readl(st, AT91_ADC_TSXPOSR); 473 at91_adc_readl(st, AT91_ADC_TSYPOSR); 474 at91_adc_readl(st, AT91_ADC_TSPRESSR); 475 } 476 } 477 478 return IRQ_HANDLED; 479 } 480 481 static int at91_adc_channel_init(struct iio_dev *idev) 482 { 483 struct at91_adc_state *st = iio_priv(idev); 484 struct iio_chan_spec *chan_array; 485 int bit, idx = 0; 486 unsigned long rsvd_mask = 0; 487 488 /* If touchscreen is enable, then reserve the adc channels */ 489 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) 490 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE; 491 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE) 492 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE; 493 494 /* set up the channel mask to reserve touchscreen channels */ 495 st->channels_mask &= ~rsvd_mask; 496 497 idev->num_channels = bitmap_weight(&st->channels_mask, 498 st->num_channels) + 1; 499 500 chan_array = devm_kzalloc(&idev->dev, 501 ((idev->num_channels + 1) * 502 sizeof(struct iio_chan_spec)), 503 GFP_KERNEL); 504 505 if (!chan_array) 506 return -ENOMEM; 507 508 for_each_set_bit(bit, &st->channels_mask, st->num_channels) { 509 struct iio_chan_spec *chan = chan_array + idx; 510 511 chan->type = IIO_VOLTAGE; 512 chan->indexed = 1; 513 chan->channel = bit; 514 chan->scan_index = idx; 515 chan->scan_type.sign = 'u'; 516 chan->scan_type.realbits = st->res; 517 chan->scan_type.storagebits = 16; 518 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 519 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 520 idx++; 521 } 522 523 chan_array[idx] = IIO_CHAN_SOFT_TIMESTAMP(idx); 524 525 idev->channels = chan_array; 526 return idev->num_channels; 527 } 528 529 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev, 530 const struct at91_adc_trigger *triggers, 531 const char *trigger_name) 532 { 533 struct at91_adc_state *st = iio_priv(idev); 534 int i; 535 536 for (i = 0; i < st->caps->trigger_number; i++) { 537 char *name __free(kfree) = kasprintf(GFP_KERNEL, "%s-dev%d-%s", 538 idev->name, 539 iio_device_id(idev), 540 triggers[i].name); 541 if (!name) 542 return -ENOMEM; 543 544 if (strcmp(trigger_name, name) == 0) { 545 if (triggers[i].value == 0) 546 return -EINVAL; 547 return triggers[i].value; 548 } 549 } 550 551 return -EINVAL; 552 } 553 554 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) 555 { 556 struct iio_dev *idev = iio_trigger_get_drvdata(trig); 557 struct at91_adc_state *st = iio_priv(idev); 558 const struct at91_adc_reg_desc *reg = st->registers; 559 u32 status = at91_adc_readl(st, reg->trigger_register); 560 int value; 561 u8 bit; 562 563 value = at91_adc_get_trigger_value_by_name(idev, 564 st->caps->triggers, 565 idev->trig->name); 566 if (value < 0) 567 return value; 568 569 if (state) { 570 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); 571 if (st->buffer == NULL) 572 return -ENOMEM; 573 574 at91_adc_writel(st, reg->trigger_register, 575 status | value); 576 577 for_each_set_bit(bit, idev->active_scan_mask, 578 st->num_channels) { 579 struct iio_chan_spec const *chan = idev->channels + bit; 580 at91_adc_writel(st, AT91_ADC_CHER, 581 AT91_ADC_CH(chan->channel)); 582 } 583 584 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); 585 586 } else { 587 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); 588 589 at91_adc_writel(st, reg->trigger_register, 590 status & ~value); 591 592 for_each_set_bit(bit, idev->active_scan_mask, 593 st->num_channels) { 594 struct iio_chan_spec const *chan = idev->channels + bit; 595 at91_adc_writel(st, AT91_ADC_CHDR, 596 AT91_ADC_CH(chan->channel)); 597 } 598 kfree(st->buffer); 599 } 600 601 return 0; 602 } 603 604 static const struct iio_trigger_ops at91_adc_trigger_ops = { 605 .set_trigger_state = &at91_adc_configure_trigger, 606 }; 607 608 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, 609 const struct at91_adc_trigger *trigger) 610 { 611 struct iio_trigger *trig; 612 int ret; 613 614 trig = iio_trigger_alloc(idev->dev.parent, "%s-dev%d-%s", idev->name, 615 iio_device_id(idev), trigger->name); 616 if (trig == NULL) 617 return NULL; 618 619 iio_trigger_set_drvdata(trig, idev); 620 trig->ops = &at91_adc_trigger_ops; 621 622 ret = iio_trigger_register(trig); 623 if (ret) { 624 iio_trigger_free(trig); 625 return NULL; 626 } 627 628 return trig; 629 } 630 631 static int at91_adc_trigger_init(struct iio_dev *idev) 632 { 633 struct at91_adc_state *st = iio_priv(idev); 634 int i, ret; 635 636 st->trig = devm_kcalloc(&idev->dev, 637 st->caps->trigger_number, sizeof(*st->trig), 638 GFP_KERNEL); 639 640 if (st->trig == NULL) { 641 ret = -ENOMEM; 642 goto error_ret; 643 } 644 645 for (i = 0; i < st->caps->trigger_number; i++) { 646 if (st->caps->triggers[i].is_external && !(st->use_external)) 647 continue; 648 649 st->trig[i] = at91_adc_allocate_trigger(idev, 650 st->caps->triggers + i); 651 if (st->trig[i] == NULL) { 652 dev_err(&idev->dev, 653 "Could not allocate trigger %d\n", i); 654 ret = -ENOMEM; 655 goto error_trigger; 656 } 657 } 658 659 return 0; 660 661 error_trigger: 662 for (i--; i >= 0; i--) { 663 iio_trigger_unregister(st->trig[i]); 664 iio_trigger_free(st->trig[i]); 665 } 666 error_ret: 667 return ret; 668 } 669 670 static void at91_adc_trigger_remove(struct iio_dev *idev) 671 { 672 struct at91_adc_state *st = iio_priv(idev); 673 int i; 674 675 for (i = 0; i < st->caps->trigger_number; i++) { 676 iio_trigger_unregister(st->trig[i]); 677 iio_trigger_free(st->trig[i]); 678 } 679 } 680 681 static int at91_adc_buffer_init(struct iio_dev *idev) 682 { 683 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, 684 &at91_adc_trigger_handler, NULL); 685 } 686 687 static void at91_adc_buffer_remove(struct iio_dev *idev) 688 { 689 iio_triggered_buffer_cleanup(idev); 690 } 691 692 static int at91_adc_read_raw(struct iio_dev *idev, 693 struct iio_chan_spec const *chan, 694 int *val, int *val2, long mask) 695 { 696 struct at91_adc_state *st = iio_priv(idev); 697 int ret; 698 699 switch (mask) { 700 case IIO_CHAN_INFO_RAW: 701 mutex_lock(&st->lock); 702 703 st->chnb = chan->channel; 704 at91_adc_writel(st, AT91_ADC_CHER, 705 AT91_ADC_CH(chan->channel)); 706 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel)); 707 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); 708 709 ret = wait_event_interruptible_timeout(st->wq_data_avail, 710 st->done, 711 msecs_to_jiffies(1000)); 712 713 /* Disable interrupts, regardless if adc conversion was 714 * successful or not 715 */ 716 at91_adc_writel(st, AT91_ADC_CHDR, 717 AT91_ADC_CH(chan->channel)); 718 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel)); 719 720 if (ret > 0) { 721 /* a valid conversion took place */ 722 *val = st->last_value; 723 st->last_value = 0; 724 st->done = false; 725 ret = IIO_VAL_INT; 726 } else if (ret == 0) { 727 /* conversion timeout */ 728 dev_err(&idev->dev, "ADC Channel %d timeout.\n", 729 chan->channel); 730 ret = -ETIMEDOUT; 731 } 732 733 mutex_unlock(&st->lock); 734 return ret; 735 736 case IIO_CHAN_INFO_SCALE: 737 *val = st->vref_mv; 738 *val2 = chan->scan_type.realbits; 739 return IIO_VAL_FRACTIONAL_LOG2; 740 default: 741 break; 742 } 743 return -EINVAL; 744 } 745 746 747 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz) 748 { 749 /* 750 * Number of ticks needed to cover the startup time of the ADC 751 * as defined in the electrical characteristics of the board, 752 * divided by 8. The formula thus is : 753 * Startup Time = (ticks + 1) * 8 / ADC Clock 754 */ 755 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8; 756 } 757 758 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz) 759 { 760 /* 761 * For sama5d3x and at91sam9x5, the formula changes to: 762 * Startup Time = <lookup_table_value> / ADC Clock 763 */ 764 static const int startup_lookup[] = { 765 0, 8, 16, 24, 766 64, 80, 96, 112, 767 512, 576, 640, 704, 768 768, 832, 896, 960 769 }; 770 int i, size = ARRAY_SIZE(startup_lookup); 771 unsigned int ticks; 772 773 ticks = startup_time * adc_clk_khz / 1000; 774 for (i = 0; i < size; i++) 775 if (ticks < startup_lookup[i]) 776 break; 777 778 ticks = i; 779 if (ticks == size) 780 /* Reach the end of lookup table */ 781 ticks = size - 1; 782 783 return ticks; 784 } 785 786 static int at91_adc_probe_dt_ts(struct device_node *node, 787 struct at91_adc_state *st, struct device *dev) 788 { 789 int ret; 790 u32 prop; 791 792 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop); 793 if (ret) { 794 dev_info(dev, "ADC Touch screen is disabled.\n"); 795 return 0; 796 } 797 798 switch (prop) { 799 case 4: 800 case 5: 801 st->touchscreen_type = prop; 802 break; 803 default: 804 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop); 805 return -EINVAL; 806 } 807 808 if (!st->caps->has_tsmr) 809 return 0; 810 prop = 0; 811 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop); 812 st->ts_pressure_threshold = prop; 813 if (st->ts_pressure_threshold) { 814 return 0; 815 } else { 816 dev_err(dev, "Invalid pressure threshold for the touchscreen\n"); 817 return -EINVAL; 818 } 819 } 820 821 static const struct iio_info at91_adc_info = { 822 .read_raw = &at91_adc_read_raw, 823 }; 824 825 /* Touchscreen related functions */ 826 static int atmel_ts_open(struct input_dev *dev) 827 { 828 struct at91_adc_state *st = input_get_drvdata(dev); 829 830 if (st->caps->has_tsmr) 831 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); 832 else 833 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); 834 return 0; 835 } 836 837 static void atmel_ts_close(struct input_dev *dev) 838 { 839 struct at91_adc_state *st = input_get_drvdata(dev); 840 841 if (st->caps->has_tsmr) 842 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); 843 else 844 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); 845 } 846 847 static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz) 848 { 849 struct at91_adc_state *st = iio_priv(idev); 850 u32 reg = 0; 851 u32 tssctim = 0; 852 int i = 0; 853 854 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid 855 * pen detect noise. 856 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock 857 */ 858 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz / 859 1000, 1); 860 861 while (st->ts_pendbc >> ++i) 862 ; /* Empty! Find the shift offset */ 863 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1)))) 864 st->ts_pendbc = i; 865 else 866 st->ts_pendbc = i - 1; 867 868 if (!st->caps->has_tsmr) { 869 reg = at91_adc_readl(st, AT91_ADC_MR); 870 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET; 871 872 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; 873 at91_adc_writel(st, AT91_ADC_MR, reg); 874 875 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM; 876 at91_adc_writel(st, AT91_ADC_TSR, reg); 877 878 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL * 879 adc_clk_khz / 1000) - 1, 1); 880 881 return 0; 882 } 883 884 /* Touchscreen Switches Closure time needed for allowing the value to 885 * stabilize. 886 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods 887 */ 888 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4); 889 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n", 890 adc_clk_khz, tssctim); 891 892 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) 893 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS; 894 else 895 reg = AT91_ADC_TSMR_TSMODE_5WIRE; 896 897 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM; 898 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average) 899 & AT91_ADC_TSMR_TSAV; 900 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC; 901 reg |= AT91_ADC_TSMR_NOTSDMA; 902 reg |= AT91_ADC_TSMR_PENDET_ENA; 903 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */ 904 905 at91_adc_writel(st, AT91_ADC_TSMR, reg); 906 907 /* Change adc internal resistor value for better pen detection, 908 * default value is 100 kOhm. 909 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm 910 * option only available on ES2 and higher 911 */ 912 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity 913 & AT91_ADC_ACR_PENDETSENS); 914 915 /* Sample Period Time = (TRGPER + 1) / ADCClock */ 916 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US * 917 adc_clk_khz / 1000) - 1, 1); 918 919 return 0; 920 } 921 922 static int at91_ts_register(struct iio_dev *idev, 923 struct platform_device *pdev) 924 { 925 struct at91_adc_state *st = iio_priv(idev); 926 struct input_dev *input; 927 int ret; 928 929 input = input_allocate_device(); 930 if (!input) { 931 dev_err(&idev->dev, "Failed to allocate TS device!\n"); 932 return -ENOMEM; 933 } 934 935 input->name = DRIVER_NAME; 936 input->id.bustype = BUS_HOST; 937 input->dev.parent = &pdev->dev; 938 input->open = atmel_ts_open; 939 input->close = atmel_ts_close; 940 941 __set_bit(EV_ABS, input->evbit); 942 __set_bit(EV_KEY, input->evbit); 943 __set_bit(BTN_TOUCH, input->keybit); 944 if (st->caps->has_tsmr) { 945 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1, 946 0, 0); 947 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1, 948 0, 0); 949 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0); 950 } else { 951 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) { 952 dev_err(&pdev->dev, 953 "This touchscreen controller only support 4 wires\n"); 954 ret = -EINVAL; 955 goto err; 956 } 957 958 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1, 959 0, 0); 960 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1, 961 0, 0); 962 } 963 964 st->ts_input = input; 965 input_set_drvdata(input, st); 966 967 ret = input_register_device(input); 968 if (ret) 969 goto err; 970 971 return ret; 972 973 err: 974 input_free_device(input); 975 return ret; 976 } 977 978 static void at91_ts_unregister(struct at91_adc_state *st) 979 { 980 input_unregister_device(st->ts_input); 981 } 982 983 static int at91_adc_probe(struct platform_device *pdev) 984 { 985 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim; 986 struct device_node *node = pdev->dev.of_node; 987 int ret; 988 struct iio_dev *idev; 989 struct at91_adc_state *st; 990 u32 reg, prop; 991 char *s; 992 993 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state)); 994 if (!idev) 995 return -ENOMEM; 996 997 st = iio_priv(idev); 998 999 st->caps = of_device_get_match_data(&pdev->dev); 1000 1001 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); 1002 1003 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) 1004 return dev_err_probe(&idev->dev, -EINVAL, 1005 "Missing adc-channels-used property in the DT.\n"); 1006 st->channels_mask = prop; 1007 1008 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode"); 1009 1010 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) 1011 return dev_err_probe(&idev->dev, -EINVAL, 1012 "Missing adc-startup-time property in the DT.\n"); 1013 st->startup_time = prop; 1014 1015 prop = 0; 1016 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop); 1017 st->sample_hold_time = prop; 1018 1019 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) 1020 return dev_err_probe(&idev->dev, -EINVAL, 1021 "Missing adc-vref property in the DT.\n"); 1022 st->vref_mv = prop; 1023 1024 st->res = st->caps->high_res_bits; 1025 if (st->caps->low_res_bits && 1026 !of_property_read_string(node, "atmel,adc-use-res", (const char **)&s) 1027 && !strcmp(s, "lowres")) 1028 st->res = st->caps->low_res_bits; 1029 1030 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res); 1031 1032 st->registers = &st->caps->registers; 1033 st->num_channels = st->caps->num_channels; 1034 1035 /* Check if touchscreen is supported. */ 1036 if (st->caps->has_ts) { 1037 ret = at91_adc_probe_dt_ts(node, st, &idev->dev); 1038 if (ret) 1039 return ret; 1040 } 1041 1042 platform_set_drvdata(pdev, idev); 1043 1044 idev->name = dev_name(&pdev->dev); 1045 idev->modes = INDIO_DIRECT_MODE; 1046 idev->info = &at91_adc_info; 1047 1048 st->irq = platform_get_irq(pdev, 0); 1049 if (st->irq < 0) 1050 return -ENODEV; 1051 1052 st->reg_base = devm_platform_ioremap_resource(pdev, 0); 1053 if (IS_ERR(st->reg_base)) 1054 return PTR_ERR(st->reg_base); 1055 1056 /* 1057 * Disable all IRQs before setting up the handler 1058 */ 1059 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); 1060 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); 1061 1062 if (st->caps->has_tsmr) 1063 ret = devm_request_irq(&pdev->dev, st->irq, 1064 at91_adc_9x5_interrupt, 0, 1065 pdev->dev.driver->name, idev); 1066 else 1067 ret = devm_request_irq(&pdev->dev, st->irq, 1068 at91_adc_rl_interrupt, 0, 1069 pdev->dev.driver->name, idev); 1070 if (ret) 1071 return dev_err_probe(&pdev->dev, ret, 1072 "Failed to allocate IRQ.\n"); 1073 1074 st->clk = devm_clk_get_enabled(&pdev->dev, "adc_clk"); 1075 if (IS_ERR(st->clk)) 1076 return dev_err_probe(&pdev->dev, PTR_ERR(st->clk), 1077 "Could not prepare or enable the clock.\n"); 1078 1079 st->adc_clk = devm_clk_get_enabled(&pdev->dev, "adc_op_clk"); 1080 if (IS_ERR(st->adc_clk)) 1081 return dev_err_probe(&pdev->dev, PTR_ERR(st->adc_clk), 1082 "Could not prepare or enable the ADC clock.\n"); 1083 1084 /* 1085 * Prescaler rate computation using the formula from the Atmel's 1086 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being 1087 * specified by the electrical characteristics of the board. 1088 */ 1089 mstrclk = clk_get_rate(st->clk); 1090 adc_clk = clk_get_rate(st->adc_clk); 1091 adc_clk_khz = adc_clk / 1000; 1092 1093 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n", 1094 mstrclk, adc_clk); 1095 1096 prsc = (mstrclk / (2 * adc_clk)) - 1; 1097 1098 if (!st->startup_time) 1099 return dev_err_probe(&pdev->dev, -EINVAL, 1100 "No startup time available.\n"); 1101 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz); 1102 1103 /* 1104 * a minimal Sample and Hold Time is necessary for the ADC to guarantee 1105 * the best converted final value between two channels selection 1106 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock 1107 */ 1108 if (st->sample_hold_time > 0) 1109 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000) 1110 - 1, 1); 1111 else 1112 shtim = 0; 1113 1114 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; 1115 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; 1116 if (st->res == st->caps->low_res_bits) 1117 reg |= AT91_ADC_LOWRES; 1118 if (st->sleep_mode) 1119 reg |= AT91_ADC_SLEEP; 1120 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM; 1121 at91_adc_writel(st, AT91_ADC_MR, reg); 1122 1123 /* Setup the ADC channels available on the board */ 1124 ret = at91_adc_channel_init(idev); 1125 if (ret < 0) 1126 return dev_err_probe(&pdev->dev, ret, 1127 "Couldn't initialize the channels.\n"); 1128 1129 init_waitqueue_head(&st->wq_data_avail); 1130 mutex_init(&st->lock); 1131 1132 /* 1133 * Since touch screen will set trigger register as period trigger. So 1134 * when touch screen is enabled, then we have to disable hardware 1135 * trigger for classic adc. 1136 */ 1137 if (!st->touchscreen_type) { 1138 ret = at91_adc_buffer_init(idev); 1139 if (ret < 0) 1140 return dev_err_probe(&pdev->dev, ret, 1141 "Couldn't initialize the buffer.\n"); 1142 1143 ret = at91_adc_trigger_init(idev); 1144 if (ret < 0) { 1145 dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); 1146 at91_adc_buffer_remove(idev); 1147 return ret; 1148 } 1149 } else { 1150 ret = at91_ts_register(idev, pdev); 1151 if (ret) 1152 return ret; 1153 1154 at91_ts_hw_init(idev, adc_clk_khz); 1155 } 1156 1157 ret = iio_device_register(idev); 1158 if (ret < 0) { 1159 dev_err(&pdev->dev, "Couldn't register the device.\n"); 1160 goto error_iio_device_register; 1161 } 1162 1163 return 0; 1164 1165 error_iio_device_register: 1166 if (!st->touchscreen_type) { 1167 at91_adc_trigger_remove(idev); 1168 at91_adc_buffer_remove(idev); 1169 } else { 1170 at91_ts_unregister(st); 1171 } 1172 return ret; 1173 } 1174 1175 static void at91_adc_remove(struct platform_device *pdev) 1176 { 1177 struct iio_dev *idev = platform_get_drvdata(pdev); 1178 struct at91_adc_state *st = iio_priv(idev); 1179 1180 iio_device_unregister(idev); 1181 if (!st->touchscreen_type) { 1182 at91_adc_trigger_remove(idev); 1183 at91_adc_buffer_remove(idev); 1184 } else { 1185 at91_ts_unregister(st); 1186 } 1187 } 1188 1189 static int at91_adc_suspend(struct device *dev) 1190 { 1191 struct iio_dev *idev = dev_get_drvdata(dev); 1192 struct at91_adc_state *st = iio_priv(idev); 1193 1194 pinctrl_pm_select_sleep_state(dev); 1195 clk_disable_unprepare(st->clk); 1196 1197 return 0; 1198 } 1199 1200 static int at91_adc_resume(struct device *dev) 1201 { 1202 struct iio_dev *idev = dev_get_drvdata(dev); 1203 struct at91_adc_state *st = iio_priv(idev); 1204 1205 clk_prepare_enable(st->clk); 1206 pinctrl_pm_select_default_state(dev); 1207 1208 return 0; 1209 } 1210 1211 static DEFINE_SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, 1212 at91_adc_resume); 1213 1214 static const struct at91_adc_trigger at91sam9260_triggers[] = { 1215 { .name = "timer-counter-0", .value = 0x1 }, 1216 { .name = "timer-counter-1", .value = 0x3 }, 1217 { .name = "timer-counter-2", .value = 0x5 }, 1218 { .name = "external", .value = 0xd, .is_external = true }, 1219 }; 1220 1221 static const struct at91_adc_caps at91sam9260_caps = { 1222 .calc_startup_ticks = calc_startup_ticks_9260, 1223 .num_channels = 4, 1224 .low_res_bits = 8, 1225 .high_res_bits = 10, 1226 .registers = { 1227 .channel_base = AT91_ADC_CHR(0), 1228 .drdy_mask = AT91_ADC_DRDY, 1229 .status_register = AT91_ADC_SR, 1230 .trigger_register = AT91_ADC_TRGR_9260, 1231 .mr_prescal_mask = AT91_ADC_PRESCAL_9260, 1232 .mr_startup_mask = AT91_ADC_STARTUP_9260, 1233 }, 1234 .triggers = at91sam9260_triggers, 1235 .trigger_number = ARRAY_SIZE(at91sam9260_triggers), 1236 }; 1237 1238 static const struct at91_adc_trigger at91sam9x5_triggers[] = { 1239 { .name = "external-rising", .value = 0x1, .is_external = true }, 1240 { .name = "external-falling", .value = 0x2, .is_external = true }, 1241 { .name = "external-any", .value = 0x3, .is_external = true }, 1242 { .name = "continuous", .value = 0x6 }, 1243 }; 1244 1245 static const struct at91_adc_caps at91sam9rl_caps = { 1246 .has_ts = true, 1247 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 1248 .num_channels = 6, 1249 .low_res_bits = 8, 1250 .high_res_bits = 10, 1251 .registers = { 1252 .channel_base = AT91_ADC_CHR(0), 1253 .drdy_mask = AT91_ADC_DRDY, 1254 .status_register = AT91_ADC_SR, 1255 .trigger_register = AT91_ADC_TRGR_9G45, 1256 .mr_prescal_mask = AT91_ADC_PRESCAL_9260, 1257 .mr_startup_mask = AT91_ADC_STARTUP_9G45, 1258 }, 1259 .triggers = at91sam9x5_triggers, 1260 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), 1261 }; 1262 1263 static const struct at91_adc_caps at91sam9g45_caps = { 1264 .has_ts = true, 1265 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 1266 .num_channels = 8, 1267 .low_res_bits = 8, 1268 .high_res_bits = 10, 1269 .registers = { 1270 .channel_base = AT91_ADC_CHR(0), 1271 .drdy_mask = AT91_ADC_DRDY, 1272 .status_register = AT91_ADC_SR, 1273 .trigger_register = AT91_ADC_TRGR_9G45, 1274 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 1275 .mr_startup_mask = AT91_ADC_STARTUP_9G45, 1276 }, 1277 .triggers = at91sam9x5_triggers, 1278 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), 1279 }; 1280 1281 static const struct at91_adc_caps at91sam9x5_caps = { 1282 .has_ts = true, 1283 .has_tsmr = true, 1284 .ts_filter_average = 3, 1285 .ts_pen_detect_sensitivity = 2, 1286 .calc_startup_ticks = calc_startup_ticks_9x5, 1287 .num_channels = 12, 1288 .low_res_bits = 8, 1289 .high_res_bits = 10, 1290 .registers = { 1291 .channel_base = AT91_ADC_CDR0_9X5, 1292 .drdy_mask = AT91_ADC_SR_DRDY_9X5, 1293 .status_register = AT91_ADC_SR_9X5, 1294 .trigger_register = AT91_ADC_TRGR_9X5, 1295 /* prescal mask is same as 9G45 */ 1296 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 1297 .mr_startup_mask = AT91_ADC_STARTUP_9X5, 1298 }, 1299 .triggers = at91sam9x5_triggers, 1300 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), 1301 }; 1302 1303 static const struct at91_adc_caps sama5d3_caps = { 1304 .has_ts = true, 1305 .has_tsmr = true, 1306 .ts_filter_average = 3, 1307 .ts_pen_detect_sensitivity = 2, 1308 .calc_startup_ticks = calc_startup_ticks_9x5, 1309 .num_channels = 12, 1310 .low_res_bits = 0, 1311 .high_res_bits = 12, 1312 .registers = { 1313 .channel_base = AT91_ADC_CDR0_9X5, 1314 .drdy_mask = AT91_ADC_SR_DRDY_9X5, 1315 .status_register = AT91_ADC_SR_9X5, 1316 .trigger_register = AT91_ADC_TRGR_9X5, 1317 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 1318 .mr_startup_mask = AT91_ADC_STARTUP_9X5, 1319 }, 1320 .triggers = at91sam9x5_triggers, 1321 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), 1322 }; 1323 1324 static const struct of_device_id at91_adc_dt_ids[] = { 1325 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps }, 1326 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps }, 1327 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps }, 1328 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps }, 1329 { .compatible = "atmel,sama5d3-adc", .data = &sama5d3_caps }, 1330 { } 1331 }; 1332 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); 1333 1334 static struct platform_driver at91_adc_driver = { 1335 .probe = at91_adc_probe, 1336 .remove = at91_adc_remove, 1337 .driver = { 1338 .name = DRIVER_NAME, 1339 .of_match_table = at91_adc_dt_ids, 1340 .pm = pm_sleep_ptr(&at91_adc_pm_ops), 1341 }, 1342 }; 1343 1344 module_platform_driver(at91_adc_driver); 1345 1346 MODULE_LICENSE("GPL"); 1347 MODULE_DESCRIPTION("Atmel AT91 ADC Driver"); 1348 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1349