1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2022 Jonathan Neuschäfer
3
4 #include <linux/clk.h>
5 #include <linux/mfd/syscon.h>
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
8 #include <linux/regmap.h>
9 #include <linux/spi/spi-mem.h>
10
11 #define FIU_CFG 0x00
12 #define FIU_BURST_BFG 0x01
13 #define FIU_RESP_CFG 0x02
14 #define FIU_CFBB_PROT 0x03
15 #define FIU_FWIN1_LOW 0x04
16 #define FIU_FWIN1_HIGH 0x06
17 #define FIU_FWIN2_LOW 0x08
18 #define FIU_FWIN2_HIGH 0x0a
19 #define FIU_FWIN3_LOW 0x0c
20 #define FIU_FWIN3_HIGH 0x0e
21 #define FIU_PROT_LOCK 0x10
22 #define FIU_PROT_CLEAR 0x11
23 #define FIU_SPI_FL_CFG 0x14
24 #define FIU_UMA_CODE 0x16
25 #define FIU_UMA_AB0 0x17
26 #define FIU_UMA_AB1 0x18
27 #define FIU_UMA_AB2 0x19
28 #define FIU_UMA_DB0 0x1a
29 #define FIU_UMA_DB1 0x1b
30 #define FIU_UMA_DB2 0x1c
31 #define FIU_UMA_DB3 0x1d
32 #define FIU_UMA_CTS 0x1e
33 #define FIU_UMA_ECTS 0x1f
34
35 #define FIU_BURST_CFG_R16 3
36
37 #define FIU_UMA_CTS_D_SIZE(x) (x)
38 #define FIU_UMA_CTS_A_SIZE BIT(3)
39 #define FIU_UMA_CTS_WR BIT(4)
40 #define FIU_UMA_CTS_CS(x) ((x) << 5)
41 #define FIU_UMA_CTS_EXEC_DONE BIT(7)
42
43 #define SHM_FLASH_SIZE 0x02
44 #define SHM_FLASH_SIZE_STALL_HOST BIT(6)
45
46 /*
47 * I observed a typical wait time of 16 iterations for a UMA transfer to
48 * finish, so this should be a safe limit.
49 */
50 #define UMA_WAIT_ITERATIONS 100
51
52 /* The memory-mapped view of flash is 16 MiB long */
53 #define MAX_MEMORY_SIZE_PER_CS (16 << 20)
54 #define MAX_MEMORY_SIZE_TOTAL (4 * MAX_MEMORY_SIZE_PER_CS)
55
56 struct wpcm_fiu_spi {
57 struct device *dev;
58 struct clk *clk;
59 void __iomem *regs;
60 void __iomem *memory;
61 size_t memory_size;
62 struct regmap *shm_regmap;
63 };
64
wpcm_fiu_set_opcode(struct wpcm_fiu_spi * fiu,u8 opcode)65 static void wpcm_fiu_set_opcode(struct wpcm_fiu_spi *fiu, u8 opcode)
66 {
67 writeb(opcode, fiu->regs + FIU_UMA_CODE);
68 }
69
wpcm_fiu_set_addr(struct wpcm_fiu_spi * fiu,u32 addr)70 static void wpcm_fiu_set_addr(struct wpcm_fiu_spi *fiu, u32 addr)
71 {
72 writeb((addr >> 0) & 0xff, fiu->regs + FIU_UMA_AB0);
73 writeb((addr >> 8) & 0xff, fiu->regs + FIU_UMA_AB1);
74 writeb((addr >> 16) & 0xff, fiu->regs + FIU_UMA_AB2);
75 }
76
wpcm_fiu_set_data(struct wpcm_fiu_spi * fiu,const u8 * data,unsigned int nbytes)77 static void wpcm_fiu_set_data(struct wpcm_fiu_spi *fiu, const u8 *data, unsigned int nbytes)
78 {
79 int i;
80
81 for (i = 0; i < nbytes; i++)
82 writeb(data[i], fiu->regs + FIU_UMA_DB0 + i);
83 }
84
wpcm_fiu_get_data(struct wpcm_fiu_spi * fiu,u8 * data,unsigned int nbytes)85 static void wpcm_fiu_get_data(struct wpcm_fiu_spi *fiu, u8 *data, unsigned int nbytes)
86 {
87 int i;
88
89 for (i = 0; i < nbytes; i++)
90 data[i] = readb(fiu->regs + FIU_UMA_DB0 + i);
91 }
92
93 /*
94 * Perform a UMA (User Mode Access) operation, i.e. a software-controlled SPI transfer.
95 */
wpcm_fiu_do_uma(struct wpcm_fiu_spi * fiu,unsigned int cs,bool use_addr,bool write,int data_bytes)96 static int wpcm_fiu_do_uma(struct wpcm_fiu_spi *fiu, unsigned int cs,
97 bool use_addr, bool write, int data_bytes)
98 {
99 int i = 0;
100 u8 cts = FIU_UMA_CTS_EXEC_DONE | FIU_UMA_CTS_CS(cs);
101
102 if (use_addr)
103 cts |= FIU_UMA_CTS_A_SIZE;
104 if (write)
105 cts |= FIU_UMA_CTS_WR;
106 cts |= FIU_UMA_CTS_D_SIZE(data_bytes);
107
108 writeb(cts, fiu->regs + FIU_UMA_CTS);
109
110 for (i = 0; i < UMA_WAIT_ITERATIONS; i++)
111 if (!(readb(fiu->regs + FIU_UMA_CTS) & FIU_UMA_CTS_EXEC_DONE))
112 return 0;
113
114 dev_info(fiu->dev, "UMA transfer has not finished in %d iterations\n", UMA_WAIT_ITERATIONS);
115 return -EIO;
116 }
117
wpcm_fiu_ects_assert(struct wpcm_fiu_spi * fiu,unsigned int cs)118 static void wpcm_fiu_ects_assert(struct wpcm_fiu_spi *fiu, unsigned int cs)
119 {
120 u8 ects = readb(fiu->regs + FIU_UMA_ECTS);
121
122 ects &= ~BIT(cs);
123 writeb(ects, fiu->regs + FIU_UMA_ECTS);
124 }
125
wpcm_fiu_ects_deassert(struct wpcm_fiu_spi * fiu,unsigned int cs)126 static void wpcm_fiu_ects_deassert(struct wpcm_fiu_spi *fiu, unsigned int cs)
127 {
128 u8 ects = readb(fiu->regs + FIU_UMA_ECTS);
129
130 ects |= BIT(cs);
131 writeb(ects, fiu->regs + FIU_UMA_ECTS);
132 }
133
134 struct wpcm_fiu_op_shape {
135 bool (*match)(const struct spi_mem_op *op);
136 int (*exec)(struct spi_mem *mem, const struct spi_mem_op *op);
137 };
138
wpcm_fiu_normal_match(const struct spi_mem_op * op)139 static bool wpcm_fiu_normal_match(const struct spi_mem_op *op)
140 {
141 // Opcode 0x0b (FAST READ) is treated differently in hardware
142 if (op->cmd.opcode == 0x0b)
143 return false;
144
145 return (op->addr.nbytes == 0 || op->addr.nbytes == 3) &&
146 op->dummy.nbytes == 0 && op->data.nbytes <= 4;
147 }
148
wpcm_fiu_normal_exec(struct spi_mem * mem,const struct spi_mem_op * op)149 static int wpcm_fiu_normal_exec(struct spi_mem *mem, const struct spi_mem_op *op)
150 {
151 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
152 int ret;
153
154 wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
155 wpcm_fiu_set_addr(fiu, op->addr.val);
156 if (op->data.dir == SPI_MEM_DATA_OUT)
157 wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes);
158
159 ret = wpcm_fiu_do_uma(fiu, spi_get_chipselect(mem->spi, 0), op->addr.nbytes == 3,
160 op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes);
161
162 if (op->data.dir == SPI_MEM_DATA_IN)
163 wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes);
164
165 return ret;
166 }
167
wpcm_fiu_fast_read_match(const struct spi_mem_op * op)168 static bool wpcm_fiu_fast_read_match(const struct spi_mem_op *op)
169 {
170 return op->cmd.opcode == 0x0b && op->addr.nbytes == 3 &&
171 op->dummy.nbytes == 1 &&
172 op->data.nbytes >= 1 && op->data.nbytes <= 4 &&
173 op->data.dir == SPI_MEM_DATA_IN;
174 }
175
wpcm_fiu_fast_read_exec(struct spi_mem * mem,const struct spi_mem_op * op)176 static int wpcm_fiu_fast_read_exec(struct spi_mem *mem, const struct spi_mem_op *op)
177 {
178 return -EINVAL;
179 }
180
181 /*
182 * 4-byte addressing.
183 *
184 * Flash view: [ C A A A A D D D D]
185 * bytes: 13 aa bb cc dd -> 5a a5 f0 0f
186 * FIU's view: [ C A A A][ C D D D D]
187 * FIU mode: [ read/write][ read ]
188 */
wpcm_fiu_4ba_match(const struct spi_mem_op * op)189 static bool wpcm_fiu_4ba_match(const struct spi_mem_op *op)
190 {
191 return op->addr.nbytes == 4 && op->dummy.nbytes == 0 && op->data.nbytes <= 4;
192 }
193
wpcm_fiu_4ba_exec(struct spi_mem * mem,const struct spi_mem_op * op)194 static int wpcm_fiu_4ba_exec(struct spi_mem *mem, const struct spi_mem_op *op)
195 {
196 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
197 int cs = spi_get_chipselect(mem->spi, 0);
198
199 wpcm_fiu_ects_assert(fiu, cs);
200
201 wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
202 wpcm_fiu_set_addr(fiu, op->addr.val >> 8);
203 wpcm_fiu_do_uma(fiu, cs, true, false, 0);
204
205 wpcm_fiu_set_opcode(fiu, op->addr.val & 0xff);
206 wpcm_fiu_set_addr(fiu, 0);
207 if (op->data.dir == SPI_MEM_DATA_OUT)
208 wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes);
209 wpcm_fiu_do_uma(fiu, cs, false, op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes);
210
211 wpcm_fiu_ects_deassert(fiu, cs);
212
213 if (op->data.dir == SPI_MEM_DATA_IN)
214 wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes);
215
216 return 0;
217 }
218
219 /*
220 * RDID (Read Identification) needs special handling because Linux expects to
221 * be able to read 6 ID bytes and FIU can only read up to 4 at once.
222 *
223 * We're lucky in this case, because executing the RDID instruction twice will
224 * result in the same result.
225 *
226 * What we do is as follows (C: write command/opcode byte, D: read data byte,
227 * A: write address byte):
228 *
229 * 1. C D D D
230 * 2. C A A A D D D
231 */
wpcm_fiu_rdid_match(const struct spi_mem_op * op)232 static bool wpcm_fiu_rdid_match(const struct spi_mem_op *op)
233 {
234 return op->cmd.opcode == 0x9f && op->addr.nbytes == 0 &&
235 op->dummy.nbytes == 0 && op->data.nbytes == 6 &&
236 op->data.dir == SPI_MEM_DATA_IN;
237 }
238
wpcm_fiu_rdid_exec(struct spi_mem * mem,const struct spi_mem_op * op)239 static int wpcm_fiu_rdid_exec(struct spi_mem *mem, const struct spi_mem_op *op)
240 {
241 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
242 int cs = spi_get_chipselect(mem->spi, 0);
243
244 /* First transfer */
245 wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
246 wpcm_fiu_set_addr(fiu, 0);
247 wpcm_fiu_do_uma(fiu, cs, false, false, 3);
248 wpcm_fiu_get_data(fiu, op->data.buf.in, 3);
249
250 /* Second transfer */
251 wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
252 wpcm_fiu_set_addr(fiu, 0);
253 wpcm_fiu_do_uma(fiu, cs, true, false, 3);
254 wpcm_fiu_get_data(fiu, op->data.buf.in + 3, 3);
255
256 return 0;
257 }
258
259 /*
260 * With some dummy bytes.
261 *
262 * C A A A X* X D D D D
263 * [C A A A D*][C D D D D]
264 */
wpcm_fiu_dummy_match(const struct spi_mem_op * op)265 static bool wpcm_fiu_dummy_match(const struct spi_mem_op *op)
266 {
267 // Opcode 0x0b (FAST READ) is treated differently in hardware
268 if (op->cmd.opcode == 0x0b)
269 return false;
270
271 return (op->addr.nbytes == 0 || op->addr.nbytes == 3) &&
272 op->dummy.nbytes >= 1 && op->dummy.nbytes <= 5 &&
273 op->data.nbytes <= 4;
274 }
275
wpcm_fiu_dummy_exec(struct spi_mem * mem,const struct spi_mem_op * op)276 static int wpcm_fiu_dummy_exec(struct spi_mem *mem, const struct spi_mem_op *op)
277 {
278 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
279 int cs = spi_get_chipselect(mem->spi, 0);
280
281 wpcm_fiu_ects_assert(fiu, cs);
282
283 /* First transfer */
284 wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
285 wpcm_fiu_set_addr(fiu, op->addr.val);
286 wpcm_fiu_do_uma(fiu, cs, op->addr.nbytes != 0, true, op->dummy.nbytes - 1);
287
288 /* Second transfer */
289 wpcm_fiu_set_opcode(fiu, 0);
290 wpcm_fiu_set_addr(fiu, 0);
291 wpcm_fiu_do_uma(fiu, cs, false, false, op->data.nbytes);
292 wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes);
293
294 wpcm_fiu_ects_deassert(fiu, cs);
295
296 return 0;
297 }
298
299 static const struct wpcm_fiu_op_shape wpcm_fiu_op_shapes[] = {
300 { .match = wpcm_fiu_normal_match, .exec = wpcm_fiu_normal_exec },
301 { .match = wpcm_fiu_fast_read_match, .exec = wpcm_fiu_fast_read_exec },
302 { .match = wpcm_fiu_4ba_match, .exec = wpcm_fiu_4ba_exec },
303 { .match = wpcm_fiu_rdid_match, .exec = wpcm_fiu_rdid_exec },
304 { .match = wpcm_fiu_dummy_match, .exec = wpcm_fiu_dummy_exec },
305 };
306
wpcm_fiu_find_op_shape(const struct spi_mem_op * op)307 static const struct wpcm_fiu_op_shape *wpcm_fiu_find_op_shape(const struct spi_mem_op *op)
308 {
309 size_t i;
310
311 for (i = 0; i < ARRAY_SIZE(wpcm_fiu_op_shapes); i++) {
312 const struct wpcm_fiu_op_shape *shape = &wpcm_fiu_op_shapes[i];
313
314 if (shape->match(op))
315 return shape;
316 }
317
318 return NULL;
319 }
320
wpcm_fiu_supports_op(struct spi_mem * mem,const struct spi_mem_op * op)321 static bool wpcm_fiu_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
322 {
323 if (!spi_mem_default_supports_op(mem, op))
324 return false;
325
326 if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
327 return false;
328
329 if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
330 op->dummy.buswidth > 1 || op->data.buswidth > 1)
331 return false;
332
333 return wpcm_fiu_find_op_shape(op) != NULL;
334 }
335
336 /*
337 * In order to ensure the integrity of SPI transfers performed via UMA,
338 * temporarily disable (stall) memory accesses coming from the host CPU.
339 */
wpcm_fiu_stall_host(struct wpcm_fiu_spi * fiu,bool stall)340 static void wpcm_fiu_stall_host(struct wpcm_fiu_spi *fiu, bool stall)
341 {
342 if (fiu->shm_regmap) {
343 int res = regmap_update_bits(fiu->shm_regmap, SHM_FLASH_SIZE,
344 SHM_FLASH_SIZE_STALL_HOST,
345 stall ? SHM_FLASH_SIZE_STALL_HOST : 0);
346 if (res)
347 dev_warn(fiu->dev, "Failed to (un)stall host memory accesses: %d\n", res);
348 }
349 }
350
wpcm_fiu_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)351 static int wpcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
352 {
353 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
354 const struct wpcm_fiu_op_shape *shape = wpcm_fiu_find_op_shape(op);
355
356 wpcm_fiu_stall_host(fiu, true);
357
358 if (shape)
359 return shape->exec(mem, op);
360
361 wpcm_fiu_stall_host(fiu, false);
362
363 return -EOPNOTSUPP;
364 }
365
wpcm_fiu_adjust_op_size(struct spi_mem * mem,struct spi_mem_op * op)366 static int wpcm_fiu_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
367 {
368 if (op->data.nbytes > 4)
369 op->data.nbytes = 4;
370
371 return 0;
372 }
373
wpcm_fiu_dirmap_create(struct spi_mem_dirmap_desc * desc)374 static int wpcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
375 {
376 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
377 int cs = spi_get_chipselect(desc->mem->spi, 0);
378
379 if (desc->info.op_tmpl->data.dir != SPI_MEM_DATA_IN)
380 return -EOPNOTSUPP;
381
382 /*
383 * Unfortunately, FIU only supports a 16 MiB direct mapping window (per
384 * attached flash chip), but the SPI MEM core doesn't support partial
385 * direct mappings. This means that we can't support direct mapping on
386 * flashes that are bigger than 16 MiB.
387 */
388 if (desc->info.offset + desc->info.length > MAX_MEMORY_SIZE_PER_CS)
389 return -EINVAL;
390
391 /* Don't read past the memory window */
392 if (cs * MAX_MEMORY_SIZE_PER_CS + desc->info.offset + desc->info.length > fiu->memory_size)
393 return -EINVAL;
394
395 return 0;
396 }
397
wpcm_fiu_direct_read(struct spi_mem_dirmap_desc * desc,u64 offs,size_t len,void * buf)398 static ssize_t wpcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf)
399 {
400 struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
401 int cs = spi_get_chipselect(desc->mem->spi, 0);
402
403 if (offs >= MAX_MEMORY_SIZE_PER_CS)
404 return -ENOTSUPP;
405
406 offs += cs * MAX_MEMORY_SIZE_PER_CS;
407
408 if (!fiu->memory || offs >= fiu->memory_size)
409 return -ENOTSUPP;
410
411 len = min_t(size_t, len, fiu->memory_size - offs);
412 memcpy_fromio(buf, fiu->memory + offs, len);
413
414 return len;
415 }
416
417 static const struct spi_controller_mem_ops wpcm_fiu_mem_ops = {
418 .adjust_op_size = wpcm_fiu_adjust_op_size,
419 .supports_op = wpcm_fiu_supports_op,
420 .exec_op = wpcm_fiu_exec_op,
421 .dirmap_create = wpcm_fiu_dirmap_create,
422 .dirmap_read = wpcm_fiu_direct_read,
423 };
424
wpcm_fiu_hw_init(struct wpcm_fiu_spi * fiu)425 static void wpcm_fiu_hw_init(struct wpcm_fiu_spi *fiu)
426 {
427 /* Configure memory-mapped flash access */
428 writeb(FIU_BURST_CFG_R16, fiu->regs + FIU_BURST_BFG);
429 writeb(MAX_MEMORY_SIZE_TOTAL / (512 << 10), fiu->regs + FIU_CFG);
430 writeb(MAX_MEMORY_SIZE_PER_CS / (512 << 10) | BIT(6), fiu->regs + FIU_SPI_FL_CFG);
431
432 /* Deassert all manually asserted chip selects */
433 writeb(0x0f, fiu->regs + FIU_UMA_ECTS);
434 }
435
wpcm_fiu_probe(struct platform_device * pdev)436 static int wpcm_fiu_probe(struct platform_device *pdev)
437 {
438 struct device *dev = &pdev->dev;
439 struct spi_controller *ctrl;
440 struct wpcm_fiu_spi *fiu;
441 struct resource *res;
442
443 ctrl = devm_spi_alloc_host(dev, sizeof(*fiu));
444 if (!ctrl)
445 return -ENOMEM;
446
447 fiu = spi_controller_get_devdata(ctrl);
448 fiu->dev = dev;
449
450 fiu->regs = devm_platform_ioremap_resource_byname(pdev, "control");
451 if (IS_ERR(fiu->regs))
452 return dev_err_probe(dev, PTR_ERR(fiu->regs),
453 "Failed to map registers\n");
454
455 fiu->clk = devm_clk_get_enabled(dev, NULL);
456 if (IS_ERR(fiu->clk))
457 return PTR_ERR(fiu->clk);
458
459 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory");
460 fiu->memory = devm_ioremap_resource(dev, res);
461 if (IS_ERR(fiu->memory))
462 return dev_err_probe(dev, PTR_ERR(fiu->memory),
463 "Failed to map flash memory window\n");
464
465 fiu->memory_size = min_t(size_t, resource_size(res), MAX_MEMORY_SIZE_TOTAL);
466 fiu->shm_regmap = syscon_regmap_lookup_by_phandle_optional(dev->of_node, "nuvoton,shm");
467
468 wpcm_fiu_hw_init(fiu);
469
470 ctrl->bus_num = -1;
471 ctrl->mem_ops = &wpcm_fiu_mem_ops;
472 ctrl->num_chipselect = 4;
473
474 /*
475 * The FIU doesn't include a clock divider, the clock is entirely
476 * determined by the AHB3 bus clock.
477 */
478 ctrl->min_speed_hz = clk_get_rate(fiu->clk);
479 ctrl->max_speed_hz = clk_get_rate(fiu->clk);
480
481 return devm_spi_register_controller(dev, ctrl);
482 }
483
484 static const struct of_device_id wpcm_fiu_dt_ids[] = {
485 { .compatible = "nuvoton,wpcm450-fiu", },
486 { }
487 };
488 MODULE_DEVICE_TABLE(of, wpcm_fiu_dt_ids);
489
490 static struct platform_driver wpcm_fiu_driver = {
491 .driver = {
492 .name = "wpcm450-fiu",
493 .bus = &platform_bus_type,
494 .of_match_table = wpcm_fiu_dt_ids,
495 },
496 .probe = wpcm_fiu_probe,
497 };
498 module_platform_driver(wpcm_fiu_driver);
499
500 MODULE_DESCRIPTION("Nuvoton WPCM450 FIU SPI controller driver");
501 MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
502 MODULE_LICENSE("GPL");
503