1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3576-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rk3576-power.h> 12#include <dt-bindings/reset/rockchip,rk3576-cru.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3576"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 i2c8 = &i2c8; 33 i2c9 = &i2c9; 34 serial0 = &uart0; 35 serial1 = &uart1; 36 serial2 = &uart2; 37 serial3 = &uart3; 38 serial4 = &uart4; 39 serial5 = &uart5; 40 serial6 = &uart6; 41 serial7 = &uart7; 42 serial8 = &uart8; 43 serial9 = &uart9; 44 serial10 = &uart10; 45 serial11 = &uart11; 46 spi0 = &spi0; 47 spi1 = &spi1; 48 spi2 = &spi2; 49 spi3 = &spi3; 50 spi4 = &spi4; 51 }; 52 53 xin32k: clock-xin32k { 54 compatible = "fixed-clock"; 55 clock-frequency = <32768>; 56 clock-output-names = "xin32k"; 57 #clock-cells = <0>; 58 }; 59 60 xin24m: clock-xin24m { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <24000000>; 64 clock-output-names = "xin24m"; 65 }; 66 67 spll: clock-spll { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <702000000>; 71 clock-output-names = "spll"; 72 }; 73 74 cpus { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 cpu-map { 79 cluster0 { 80 core0 { 81 cpu = <&cpu_l0>; 82 }; 83 core1 { 84 cpu = <&cpu_l1>; 85 }; 86 core2 { 87 cpu = <&cpu_l2>; 88 }; 89 core3 { 90 cpu = <&cpu_l3>; 91 }; 92 }; 93 cluster1 { 94 core0 { 95 cpu = <&cpu_b0>; 96 }; 97 core1 { 98 cpu = <&cpu_b1>; 99 }; 100 core2 { 101 cpu = <&cpu_b2>; 102 }; 103 core3 { 104 cpu = <&cpu_b3>; 105 }; 106 }; 107 }; 108 109 cpu_l0: cpu@0 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a53"; 112 reg = <0x0>; 113 enable-method = "psci"; 114 capacity-dmips-mhz = <485>; 115 clocks = <&scmi_clk SCMI_ARMCLK_L>; 116 operating-points-v2 = <&cluster0_opp_table>; 117 dynamic-power-coefficient = <120>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 #cooling-cells = <2>; 120 }; 121 122 cpu_l1: cpu@1 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53"; 125 reg = <0x1>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <485>; 128 clocks = <&scmi_clk SCMI_ARMCLK_L>; 129 operating-points-v2 = <&cluster0_opp_table>; 130 cpu-idle-states = <&CPU_SLEEP>; 131 #cooling-cells = <2>; 132 }; 133 134 cpu_l2: cpu@2 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a53"; 137 reg = <0x2>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <485>; 140 clocks = <&scmi_clk SCMI_ARMCLK_L>; 141 operating-points-v2 = <&cluster0_opp_table>; 142 cpu-idle-states = <&CPU_SLEEP>; 143 #cooling-cells = <2>; 144 }; 145 146 cpu_l3: cpu@3 { 147 device_type = "cpu"; 148 compatible = "arm,cortex-a53"; 149 reg = <0x3>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <485>; 152 clocks = <&scmi_clk SCMI_ARMCLK_L>; 153 operating-points-v2 = <&cluster0_opp_table>; 154 cpu-idle-states = <&CPU_SLEEP>; 155 #cooling-cells = <2>; 156 }; 157 158 cpu_b0: cpu@100 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a72"; 161 reg = <0x100>; 162 enable-method = "psci"; 163 capacity-dmips-mhz = <1024>; 164 clocks = <&scmi_clk SCMI_ARMCLK_B>; 165 operating-points-v2 = <&cluster1_opp_table>; 166 dynamic-power-coefficient = <320>; 167 cpu-idle-states = <&CPU_SLEEP>; 168 #cooling-cells = <2>; 169 }; 170 171 cpu_b1: cpu@101 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a72"; 174 reg = <0x101>; 175 enable-method = "psci"; 176 capacity-dmips-mhz = <1024>; 177 clocks = <&scmi_clk SCMI_ARMCLK_B>; 178 operating-points-v2 = <&cluster1_opp_table>; 179 cpu-idle-states = <&CPU_SLEEP>; 180 #cooling-cells = <2>; 181 }; 182 183 cpu_b2: cpu@102 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-a72"; 186 reg = <0x102>; 187 enable-method = "psci"; 188 capacity-dmips-mhz = <1024>; 189 clocks = <&scmi_clk SCMI_ARMCLK_B>; 190 operating-points-v2 = <&cluster1_opp_table>; 191 cpu-idle-states = <&CPU_SLEEP>; 192 #cooling-cells = <2>; 193 }; 194 195 cpu_b3: cpu@103 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-a72"; 198 reg = <0x103>; 199 enable-method = "psci"; 200 capacity-dmips-mhz = <1024>; 201 clocks = <&scmi_clk SCMI_ARMCLK_B>; 202 operating-points-v2 = <&cluster1_opp_table>; 203 cpu-idle-states = <&CPU_SLEEP>; 204 #cooling-cells = <2>; 205 }; 206 207 idle-states { 208 entry-method = "psci"; 209 210 CPU_SLEEP: cpu-sleep { 211 compatible = "arm,idle-state"; 212 arm,psci-suspend-param = <0x0010000>; 213 entry-latency-us = <120>; 214 exit-latency-us = <250>; 215 min-residency-us = <900>; 216 local-timer-stop; 217 }; 218 }; 219 }; 220 221 cluster0_opp_table: opp-table-cluster0 { 222 compatible = "operating-points-v2"; 223 opp-shared; 224 225 opp-408000000 { 226 opp-hz = /bits/ 64 <408000000>; 227 opp-microvolt = <700000 700000 950000>; 228 clock-latency-ns = <40000>; 229 }; 230 231 opp-600000000 { 232 opp-hz = /bits/ 64 <600000000>; 233 opp-microvolt = <700000 700000 950000>; 234 clock-latency-ns = <40000>; 235 }; 236 237 opp-816000000 { 238 opp-hz = /bits/ 64 <816000000>; 239 opp-microvolt = <700000 700000 950000>; 240 clock-latency-ns = <40000>; 241 }; 242 243 opp-1008000000 { 244 opp-hz = /bits/ 64 <1008000000>; 245 opp-microvolt = <700000 700000 950000>; 246 clock-latency-ns = <40000>; 247 }; 248 249 opp-1200000000 { 250 opp-hz = /bits/ 64 <1200000000>; 251 opp-microvolt = <700000 700000 950000>; 252 clock-latency-ns = <40000>; 253 }; 254 255 opp-1416000000 { 256 opp-hz = /bits/ 64 <1416000000>; 257 opp-microvolt = <725000 725000 950000>; 258 clock-latency-ns = <40000>; 259 }; 260 261 opp-1608000000 { 262 opp-hz = /bits/ 64 <1608000000>; 263 opp-microvolt = <750000 750000 950000>; 264 clock-latency-ns = <40000>; 265 }; 266 267 opp-1800000000 { 268 opp-hz = /bits/ 64 <1800000000>; 269 opp-microvolt = <825000 825000 950000>; 270 clock-latency-ns = <40000>; 271 opp-suspend; 272 }; 273 274 opp-2016000000 { 275 opp-hz = /bits/ 64 <2016000000>; 276 opp-microvolt = <900000 900000 950000>; 277 clock-latency-ns = <40000>; 278 }; 279 }; 280 281 cluster1_opp_table: opp-table-cluster1 { 282 compatible = "operating-points-v2"; 283 opp-shared; 284 285 opp-408000000 { 286 opp-hz = /bits/ 64 <408000000>; 287 opp-microvolt = <700000 700000 950000>; 288 clock-latency-ns = <40000>; 289 opp-suspend; 290 }; 291 292 opp-600000000 { 293 opp-hz = /bits/ 64 <600000000>; 294 opp-microvolt = <700000 700000 950000>; 295 clock-latency-ns = <40000>; 296 }; 297 298 opp-816000000 { 299 opp-hz = /bits/ 64 <816000000>; 300 opp-microvolt = <700000 700000 950000>; 301 clock-latency-ns = <40000>; 302 }; 303 304 opp-1008000000 { 305 opp-hz = /bits/ 64 <1008000000>; 306 opp-microvolt = <700000 700000 950000>; 307 clock-latency-ns = <40000>; 308 }; 309 310 opp-1200000000 { 311 opp-hz = /bits/ 64 <1200000000>; 312 opp-microvolt = <700000 700000 950000>; 313 clock-latency-ns = <40000>; 314 }; 315 316 opp-1416000000 { 317 opp-hz = /bits/ 64 <1416000000>; 318 opp-microvolt = <712500 712500 950000>; 319 clock-latency-ns = <40000>; 320 }; 321 322 opp-1608000000 { 323 opp-hz = /bits/ 64 <1608000000>; 324 opp-microvolt = <737500 737500 950000>; 325 clock-latency-ns = <40000>; 326 }; 327 328 opp-1800000000 { 329 opp-hz = /bits/ 64 <1800000000>; 330 opp-microvolt = <800000 800000 950000>; 331 clock-latency-ns = <40000>; 332 }; 333 334 opp-2016000000 { 335 opp-hz = /bits/ 64 <2016000000>; 336 opp-microvolt = <862500 862500 950000>; 337 clock-latency-ns = <40000>; 338 }; 339 340 opp-2208000000 { 341 opp-hz = /bits/ 64 <2208000000>; 342 opp-microvolt = <925000 925000 950000>; 343 clock-latency-ns = <40000>; 344 }; 345 }; 346 347 gpu_opp_table: opp-table-gpu { 348 compatible = "operating-points-v2"; 349 350 opp-300000000 { 351 opp-hz = /bits/ 64 <300000000>; 352 opp-microvolt = <700000 700000 850000>; 353 }; 354 355 opp-400000000 { 356 opp-hz = /bits/ 64 <400000000>; 357 opp-microvolt = <700000 700000 850000>; 358 }; 359 360 opp-500000000 { 361 opp-hz = /bits/ 64 <500000000>; 362 opp-microvolt = <700000 700000 850000>; 363 }; 364 365 opp-600000000 { 366 opp-hz = /bits/ 64 <600000000>; 367 opp-microvolt = <700000 700000 850000>; 368 }; 369 370 opp-700000000 { 371 opp-hz = /bits/ 64 <700000000>; 372 opp-microvolt = <725000 725000 850000>; 373 }; 374 375 opp-800000000 { 376 opp-hz = /bits/ 64 <800000000>; 377 opp-microvolt = <775000 775000 850000>; 378 }; 379 380 opp-900000000 { 381 opp-hz = /bits/ 64 <900000000>; 382 opp-microvolt = <825000 825000 850000>; 383 }; 384 385 opp-950000000 { 386 opp-hz = /bits/ 64 <950000000>; 387 opp-microvolt = <850000 850000 850000>; 388 }; 389 }; 390 391 display_subsystem: display-subsystem { 392 compatible = "rockchip,display-subsystem"; 393 ports = <&vop_out>; 394 }; 395 396 firmware { 397 scmi: scmi { 398 compatible = "arm,scmi-smc"; 399 arm,smc-id = <0x82000010>; 400 shmem = <&scmi_shmem>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 404 scmi_clk: protocol@14 { 405 reg = <0x14>; 406 #clock-cells = <1>; 407 }; 408 }; 409 }; 410 411 hdmi_sound: hdmi-sound { 412 compatible = "simple-audio-card"; 413 simple-audio-card,name = "HDMI"; 414 simple-audio-card,format = "i2s"; 415 simple-audio-card,mclk-fs = <256>; 416 status = "disabled"; 417 418 simple-audio-card,codec { 419 sound-dai = <&hdmi>; 420 }; 421 422 simple-audio-card,cpu { 423 sound-dai = <&sai6>; 424 }; 425 }; 426 427 pinctrl: pinctrl { 428 compatible = "rockchip,rk3576-pinctrl"; 429 rockchip,grf = <&ioc_grf>; 430 #address-cells = <2>; 431 #size-cells = <2>; 432 ranges; 433 434 gpio0: gpio@27320000 { 435 compatible = "rockchip,gpio-bank"; 436 reg = <0x0 0x27320000 0x0 0x200>; 437 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 438 gpio-controller; 439 gpio-ranges = <&pinctrl 0 0 32>; 440 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 441 interrupt-controller; 442 #gpio-cells = <2>; 443 #interrupt-cells = <2>; 444 }; 445 446 gpio1: gpio@2ae10000 { 447 compatible = "rockchip,gpio-bank"; 448 reg = <0x0 0x2ae10000 0x0 0x200>; 449 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 450 gpio-controller; 451 gpio-ranges = <&pinctrl 0 32 32>; 452 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 453 interrupt-controller; 454 #gpio-cells = <2>; 455 #interrupt-cells = <2>; 456 }; 457 458 gpio2: gpio@2ae20000 { 459 compatible = "rockchip,gpio-bank"; 460 reg = <0x0 0x2ae20000 0x0 0x200>; 461 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 462 gpio-controller; 463 gpio-ranges = <&pinctrl 0 64 32>; 464 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-controller; 466 #gpio-cells = <2>; 467 #interrupt-cells = <2>; 468 }; 469 470 gpio3: gpio@2ae30000 { 471 compatible = "rockchip,gpio-bank"; 472 reg = <0x0 0x2ae30000 0x0 0x200>; 473 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 474 gpio-controller; 475 gpio-ranges = <&pinctrl 0 96 32>; 476 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 477 interrupt-controller; 478 #gpio-cells = <2>; 479 #interrupt-cells = <2>; 480 }; 481 482 gpio4: gpio@2ae40000 { 483 compatible = "rockchip,gpio-bank"; 484 reg = <0x0 0x2ae40000 0x0 0x200>; 485 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 486 gpio-controller; 487 gpio-ranges = <&pinctrl 0 128 32>; 488 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 489 interrupt-controller; 490 #gpio-cells = <2>; 491 #interrupt-cells = <2>; 492 }; 493 }; 494 495 pmu_a53: pmu-a53 { 496 compatible = "arm,cortex-a53-pmu"; 497 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 501 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>; 502 }; 503 504 pmu_a72: pmu-a72 { 505 compatible = "arm,cortex-a72-pmu"; 506 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 510 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 511 }; 512 513 psci { 514 compatible = "arm,psci-1.0"; 515 method = "smc"; 516 }; 517 518 thermal_zones: thermal-zones { 519 /* sensor near the center of the SoC */ 520 package_thermal: package-thermal { 521 polling-delay-passive = <0>; 522 polling-delay = <0>; 523 thermal-sensors = <&tsadc 0>; 524 525 trips { 526 package_crit: package-crit { 527 temperature = <115000>; 528 hysteresis = <0>; 529 type = "critical"; 530 }; 531 }; 532 }; 533 534 /* sensor for cluster1 (big Cortex-A72 cores) */ 535 bigcore_thermal: bigcore-thermal { 536 polling-delay-passive = <100>; 537 polling-delay = <0>; 538 thermal-sensors = <&tsadc 1>; 539 540 trips { 541 bigcore_alert: bigcore-alert { 542 temperature = <85000>; 543 hysteresis = <2000>; 544 type = "passive"; 545 }; 546 547 bigcore_crit: bigcore-crit { 548 temperature = <115000>; 549 hysteresis = <0>; 550 type = "critical"; 551 }; 552 }; 553 554 cooling-maps { 555 map0 { 556 trip = <&bigcore_alert>; 557 cooling-device = 558 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 559 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 560 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 561 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 562 }; 563 }; 564 }; 565 566 /* sensor for cluster0 (little Cortex-A53 cores) */ 567 littlecore_thermal: littlecore-thermal { 568 polling-delay-passive = <100>; 569 polling-delay = <0>; 570 thermal-sensors = <&tsadc 2>; 571 572 trips { 573 littlecore_alert: littlecore-alert { 574 temperature = <85000>; 575 hysteresis = <2000>; 576 type = "passive"; 577 }; 578 579 littlecore_crit: littlecore-crit { 580 temperature = <115000>; 581 hysteresis = <0>; 582 type = "critical"; 583 }; 584 }; 585 586 cooling-maps { 587 map0 { 588 trip = <&littlecore_alert>; 589 cooling-device = 590 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 591 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 592 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 593 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 594 }; 595 }; 596 }; 597 598 gpu_thermal: gpu-thermal { 599 polling-delay-passive = <100>; 600 polling-delay = <0>; 601 thermal-sensors = <&tsadc 3>; 602 603 trips { 604 gpu_alert: gpu-alert { 605 temperature = <85000>; 606 hysteresis = <2000>; 607 type = "passive"; 608 }; 609 610 gpu_crit: gpu-crit { 611 temperature = <115000>; 612 hysteresis = <0>; 613 type = "critical"; 614 }; 615 }; 616 617 cooling-maps { 618 map0 { 619 trip = <&gpu_alert>; 620 cooling-device = 621 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 622 }; 623 }; 624 }; 625 626 npu_thermal: npu-thermal { 627 polling-delay-passive = <0>; 628 polling-delay = <0>; 629 thermal-sensors = <&tsadc 4>; 630 631 trips { 632 npu_crit: npu-crit { 633 temperature = <115000>; 634 hysteresis = <0>; 635 type = "critical"; 636 }; 637 }; 638 }; 639 640 ddr_thermal: ddr-thermal { 641 polling-delay-passive = <0>; 642 polling-delay = <0>; 643 thermal-sensors = <&tsadc 5>; 644 645 trips { 646 ddr_crit: ddr-crit { 647 temperature = <115000>; 648 hysteresis = <0>; 649 type = "critical"; 650 }; 651 }; 652 }; 653 }; 654 655 timer { 656 compatible = "arm,armv8-timer"; 657 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 658 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 659 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 660 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 661 }; 662 663 soc { 664 compatible = "simple-bus"; 665 #address-cells = <2>; 666 #size-cells = <2>; 667 ranges; 668 669 pcie0: pcie@22000000 { 670 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; 671 reg = <0x0 0x22000000 0x0 0x00400000>, 672 <0x0 0x2a200000 0x0 0x00010000>, 673 <0x0 0x20000000 0x0 0x00100000>; 674 reg-names = "dbi", "apb", "config"; 675 bus-range = <0x0 0xf>; 676 clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, 677 <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, 678 <&cru CLK_PCIE0_AUX>; 679 clock-names = "aclk_mst", "aclk_slv", 680 "aclk_dbi", "pclk", 681 "aux"; 682 device_type = "pci"; 683 dma-coherent; 684 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>; 690 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; 691 #interrupt-cells = <1>; 692 interrupt-map-mask = <0 0 0 7>; 693 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 694 <0 0 0 2 &pcie0_intc 1>, 695 <0 0 0 3 &pcie0_intc 2>, 696 <0 0 0 4 &pcie0_intc 3>; 697 linux,pci-domain = <0>; 698 max-link-speed = <2>; 699 num-ib-windows = <8>; 700 num-viewport = <8>; 701 num-ob-windows = <2>; 702 num-lanes = <1>; 703 phys = <&combphy0_ps PHY_TYPE_PCIE>; 704 phy-names = "pcie-phy"; 705 power-domains = <&power RK3576_PD_PHP>; 706 ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 707 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 708 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; 709 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 710 reset-names = "pwr", "pipe"; 711 #address-cells = <3>; 712 #size-cells = <2>; 713 status = "disabled"; 714 715 pcie0_intc: legacy-interrupt-controller { 716 interrupt-controller; 717 #address-cells = <0>; 718 #interrupt-cells = <1>; 719 interrupt-parent = <&gic>; 720 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; 721 }; 722 }; 723 724 pcie1: pcie@22400000 { 725 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; 726 reg = <0x0 0x22400000 0x0 0x00400000>, 727 <0x0 0x2a210000 0x0 0x00010000>, 728 <0x0 0x21000000 0x0 0x00100000>; 729 reg-names = "dbi", "apb", "config"; 730 bus-range = <0x20 0x2f>; 731 clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, 732 <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, 733 <&cru CLK_PCIE1_AUX>; 734 clock-names = "aclk_mst", "aclk_slv", 735 "aclk_dbi", "pclk", 736 "aux"; 737 device_type = "pci"; 738 dma-coherent; 739 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 745 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; 746 #interrupt-cells = <1>; 747 interrupt-map-mask = <0 0 0 7>; 748 interrupt-map = <0 0 0 1 &pcie1_intc 0>, 749 <0 0 0 2 &pcie1_intc 1>, 750 <0 0 0 3 &pcie1_intc 2>, 751 <0 0 0 4 &pcie1_intc 3>; 752 linux,pci-domain = <1>; 753 max-link-speed = <2>; 754 num-ib-windows = <8>; 755 num-viewport = <8>; 756 num-ob-windows = <2>; 757 num-lanes = <1>; 758 phys = <&combphy1_psu PHY_TYPE_PCIE>; 759 phy-names = "pcie-phy"; 760 power-domains = <&power RK3576_PD_SUBPHP>; 761 ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 762 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 763 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; 764 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 765 reset-names = "pwr", "pipe"; 766 #address-cells = <3>; 767 #size-cells = <2>; 768 status = "disabled"; 769 770 pcie1_intc: legacy-interrupt-controller { 771 interrupt-controller; 772 #address-cells = <0>; 773 #interrupt-cells = <1>; 774 interrupt-parent = <&gic>; 775 interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>; 776 }; 777 }; 778 779 usb_drd0_dwc3: usb@23000000 { 780 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 781 reg = <0x0 0x23000000 0x0 0x400000>; 782 clocks = <&cru CLK_REF_USB3OTG0>, 783 <&cru CLK_SUSPEND_USB3OTG0>, 784 <&cru ACLK_USB3OTG0>; 785 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 786 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 787 power-domains = <&power RK3576_PD_USB>; 788 resets = <&cru SRST_A_USB3OTG0>; 789 dr_mode = "otg"; 790 phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>; 791 phy-names = "usb2-phy", "usb3-phy"; 792 phy_type = "utmi_wide"; 793 snps,dis_enblslpm_quirk; 794 snps,dis-u1-entry-quirk; 795 snps,dis-u2-entry-quirk; 796 snps,dis-u2-freeclk-exists-quirk; 797 snps,dis-del-phy-power-chg-quirk; 798 snps,dis-tx-ipgap-linecheck-quirk; 799 snps,parkmode-disable-hs-quirk; 800 snps,parkmode-disable-ss-quirk; 801 status = "disabled"; 802 }; 803 804 usb_drd1_dwc3: usb@23400000 { 805 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 806 reg = <0x0 0x23400000 0x0 0x400000>; 807 clocks = <&cru CLK_REF_USB3OTG1>, 808 <&cru CLK_SUSPEND_USB3OTG1>, 809 <&cru ACLK_USB3OTG1>; 810 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 811 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 812 power-domains = <&power RK3576_PD_PHP>; 813 resets = <&cru SRST_A_USB3OTG1>; 814 dr_mode = "otg"; 815 phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>; 816 phy-names = "usb2-phy", "usb3-phy"; 817 phy_type = "utmi_wide"; 818 snps,dis_enblslpm_quirk; 819 snps,dis-u1-entry-quirk; 820 snps,dis-u2-entry-quirk; 821 snps,dis-u2-freeclk-exists-quirk; 822 snps,dis-del-phy-power-chg-quirk; 823 snps,dis-tx-ipgap-linecheck-quirk; 824 snps,dis_rxdet_inp3_quirk; 825 snps,parkmode-disable-hs-quirk; 826 snps,parkmode-disable-ss-quirk; 827 dma-coherent; 828 status = "disabled"; 829 }; 830 831 sys_grf: syscon@2600a000 { 832 compatible = "rockchip,rk3576-sys-grf", "syscon"; 833 reg = <0x0 0x2600a000 0x0 0x2000>; 834 }; 835 836 bigcore_grf: syscon@2600c000 { 837 compatible = "rockchip,rk3576-bigcore-grf", "syscon"; 838 reg = <0x0 0x2600c000 0x0 0x2000>; 839 }; 840 841 litcore_grf: syscon@2600e000 { 842 compatible = "rockchip,rk3576-litcore-grf", "syscon"; 843 reg = <0x0 0x2600e000 0x0 0x2000>; 844 }; 845 846 cci_grf: syscon@26010000 { 847 compatible = "rockchip,rk3576-cci-grf", "syscon"; 848 reg = <0x0 0x26010000 0x0 0x2000>; 849 }; 850 851 gpu_grf: syscon@26016000 { 852 compatible = "rockchip,rk3576-gpu-grf", "syscon"; 853 reg = <0x0 0x26016000 0x0 0x2000>; 854 }; 855 856 npu_grf: syscon@26018000 { 857 compatible = "rockchip,rk3576-npu-grf", "syscon"; 858 reg = <0x0 0x26018000 0x0 0x2000>; 859 }; 860 861 vo0_grf: syscon@2601a000 { 862 compatible = "rockchip,rk3576-vo0-grf", "syscon"; 863 reg = <0x0 0x2601a000 0x0 0x2000>; 864 }; 865 866 usb_grf: syscon@2601e000 { 867 compatible = "rockchip,rk3576-usb-grf", "syscon"; 868 reg = <0x0 0x2601e000 0x0 0x1000>; 869 }; 870 871 php_grf: syscon@26020000 { 872 compatible = "rockchip,rk3576-php-grf", "syscon"; 873 reg = <0x0 0x26020000 0x0 0x2000>; 874 }; 875 876 pmu0_grf: syscon@26024000 { 877 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd"; 878 reg = <0x0 0x26024000 0x0 0x1000>; 879 }; 880 881 pmu1_grf: syscon@26026000 { 882 compatible = "rockchip,rk3576-pmu1-grf", "syscon"; 883 reg = <0x0 0x26026000 0x0 0x1000>; 884 }; 885 886 pipe_phy0_grf: syscon@26028000 { 887 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 888 reg = <0x0 0x26028000 0x0 0x2000>; 889 }; 890 891 pipe_phy1_grf: syscon@2602a000 { 892 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 893 reg = <0x0 0x2602a000 0x0 0x2000>; 894 }; 895 896 usbdpphy_grf: syscon@2602c000 { 897 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon"; 898 reg = <0x0 0x2602c000 0x0 0x2000>; 899 }; 900 901 usb2phy_grf: syscon@2602e000 { 902 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd"; 903 reg = <0x0 0x2602e000 0x0 0x4000>; 904 #address-cells = <1>; 905 #size-cells = <1>; 906 907 u2phy0: usb2-phy@0 { 908 compatible = "rockchip,rk3576-usb2phy"; 909 reg = <0x0 0x10>; 910 resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>; 911 reset-names = "phy", "apb"; 912 clocks = <&cru CLK_PHY_REF_SRC>, 913 <&cru ACLK_MMU2>, 914 <&cru ACLK_SLV_MMU2>; 915 clock-names = "phyclk", "aclk", "aclk_slv"; 916 clock-output-names = "usb480m_phy0"; 917 #clock-cells = <0>; 918 status = "disabled"; 919 920 u2phy0_otg: otg-port { 921 #phy-cells = <0>; 922 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 925 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 926 status = "disabled"; 927 }; 928 }; 929 930 u2phy1: usb2-phy@2000 { 931 compatible = "rockchip,rk3576-usb2phy"; 932 reg = <0x2000 0x10>; 933 resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>; 934 reset-names = "phy", "apb"; 935 clocks = <&cru CLK_PHY_REF_SRC>, 936 <&cru ACLK_MMU1>, 937 <&cru ACLK_SLV_MMU1>; 938 clock-names = "phyclk", "aclk", "aclk_slv"; 939 clock-output-names = "usb480m_phy1"; 940 #clock-cells = <0>; 941 status = "disabled"; 942 943 u2phy1_otg: otg-port { 944 #phy-cells = <0>; 945 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 949 status = "disabled"; 950 }; 951 }; 952 }; 953 954 hdptxphy_grf: syscon@26032000 { 955 compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; 956 reg = <0x0 0x26032000 0x0 0x100>; 957 }; 958 959 mipidcphy_grf: syscon@26034000 { 960 compatible = "rockchip,rk3576-dcphy-grf", "syscon"; 961 reg = <0x0 0x26034000 0x0 0x2000>; 962 clocks = <&cru PCLK_PMUPHY_ROOT>; 963 }; 964 965 vo1_grf: syscon@26036000 { 966 compatible = "rockchip,rk3576-vo1-grf", "syscon"; 967 reg = <0x0 0x26036000 0x0 0x100>; 968 clocks = <&cru PCLK_VO1_ROOT>; 969 }; 970 971 sdgmac_grf: syscon@26038000 { 972 compatible = "rockchip,rk3576-sdgmac-grf", "syscon"; 973 reg = <0x0 0x26038000 0x0 0x1000>; 974 }; 975 976 ioc_grf: syscon@26040000 { 977 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd"; 978 reg = <0x0 0x26040000 0x0 0xc000>; 979 }; 980 981 cru: clock-controller@27200000 { 982 compatible = "rockchip,rk3576-cru"; 983 reg = <0x0 0x27200000 0x0 0x50000>; 984 #clock-cells = <1>; 985 #reset-cells = <1>; 986 987 assigned-clocks = 988 <&cru CLK_AUDIO_FRAC_1_SRC>, 989 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 990 <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>, 991 <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>, 992 <&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>, 993 <&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>, 994 <&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>, 995 <&cru ACLK_PHP_ROOT>; 996 assigned-clock-parents = <&cru PLL_AUPLL>; 997 assigned-clock-rates = 998 <0>, 999 <1188000000>, <1000000000>, 1000 <786432000>, <18432000>, 1001 <96000000>, <128000000>, 1002 <45158400>, <49152000>, 1003 <500000000>, <250000000>, 1004 <100000000>, <500000000>, 1005 <250000000>; 1006 }; 1007 1008 i2c0: i2c@27300000 { 1009 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1010 reg = <0x0 0x27300000 0x0 0x1000>; 1011 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 1012 clock-names = "i2c", "pclk"; 1013 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1014 pinctrl-names = "default"; 1015 pinctrl-0 = <&i2c0m0_xfer>; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 status = "disabled"; 1019 }; 1020 1021 uart1: serial@27310000 { 1022 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1023 reg = <0x0 0x27310000 0x0 0x100>; 1024 reg-shift = <2>; 1025 reg-io-width = <4>; 1026 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1027 clock-names = "baudclk", "apb_pclk"; 1028 dmas = <&dmac0 8>, <&dmac0 9>; 1029 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&uart1m0_xfer>; 1032 status = "disabled"; 1033 }; 1034 1035 pmu: power-management@27380000 { 1036 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd"; 1037 reg = <0x0 0x27380000 0x0 0x800>; 1038 1039 power: power-controller { 1040 compatible = "rockchip,rk3576-power-controller"; 1041 #power-domain-cells = <1>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 1045 power-domain@RK3576_PD_NPU { 1046 reg = <RK3576_PD_NPU>; 1047 #power-domain-cells = <1>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 1051 power-domain@RK3576_PD_NPUTOP { 1052 reg = <RK3576_PD_NPUTOP>; 1053 clocks = <&cru ACLK_RKNN0>, 1054 <&cru ACLK_RKNN1>, 1055 <&cru ACLK_RKNN_CBUF>, 1056 <&cru CLK_RKNN_DSU0>, 1057 <&cru HCLK_RKNN_CBUF>, 1058 <&cru HCLK_RKNN_ROOT>, 1059 <&cru HCLK_NPU_CM0_ROOT>, 1060 <&cru PCLK_NPUTOP_ROOT>; 1061 pm_qos = <&qos_npu_mcu>, 1062 <&qos_npu_nsp0>, 1063 <&qos_npu_nsp1>, 1064 <&qos_npu_m0ro>, 1065 <&qos_npu_m1ro>; 1066 #power-domain-cells = <1>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 1070 power-domain@RK3576_PD_NPU0 { 1071 reg = <RK3576_PD_NPU0>; 1072 clocks = <&cru HCLK_RKNN_ROOT>, 1073 <&cru ACLK_RKNN0>; 1074 pm_qos = <&qos_npu_m0>; 1075 #power-domain-cells = <0>; 1076 }; 1077 power-domain@RK3576_PD_NPU1 { 1078 reg = <RK3576_PD_NPU1>; 1079 clocks = <&cru HCLK_RKNN_ROOT>, 1080 <&cru ACLK_RKNN1>; 1081 pm_qos = <&qos_npu_m1>; 1082 #power-domain-cells = <0>; 1083 }; 1084 }; 1085 }; 1086 1087 power-domain@RK3576_PD_GPU { 1088 reg = <RK3576_PD_GPU>; 1089 clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>; 1090 pm_qos = <&qos_gpu>; 1091 #power-domain-cells = <0>; 1092 }; 1093 1094 power-domain@RK3576_PD_NVM { 1095 reg = <RK3576_PD_NVM>; 1096 clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>; 1097 pm_qos = <&qos_emmc>, 1098 <&qos_fspi0>; 1099 #power-domain-cells = <1>; 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 1103 power-domain@RK3576_PD_SDGMAC { 1104 reg = <RK3576_PD_SDGMAC>; 1105 clocks = <&cru ACLK_HSGPIO>, 1106 <&cru ACLK_GMAC0>, 1107 <&cru ACLK_GMAC1>, 1108 <&cru CCLK_SRC_SDIO>, 1109 <&cru CCLK_SRC_SDMMC0>, 1110 <&cru HCLK_HSGPIO>, 1111 <&cru HCLK_SDIO>, 1112 <&cru HCLK_SDMMC0>, 1113 <&cru PCLK_SDGMAC_ROOT>; 1114 pm_qos = <&qos_fspi1>, 1115 <&qos_gmac0>, 1116 <&qos_gmac1>, 1117 <&qos_sdio>, 1118 <&qos_sdmmc>, 1119 <&qos_flexbus>; 1120 #power-domain-cells = <0>; 1121 }; 1122 }; 1123 1124 power-domain@RK3576_PD_PHP { 1125 reg = <RK3576_PD_PHP>; 1126 clocks = <&cru ACLK_PHP_ROOT>, 1127 <&cru PCLK_PHP_ROOT>, 1128 <&cru ACLK_MMU0>, 1129 <&cru ACLK_MMU1>; 1130 pm_qos = <&qos_mmu0>, 1131 <&qos_mmu1>; 1132 #power-domain-cells = <1>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 1136 power-domain@RK3576_PD_SUBPHP { 1137 reg = <RK3576_PD_SUBPHP>; 1138 #power-domain-cells = <0>; 1139 }; 1140 }; 1141 1142 power-domain@RK3576_PD_AUDIO { 1143 reg = <RK3576_PD_AUDIO>; 1144 #power-domain-cells = <0>; 1145 }; 1146 1147 power-domain@RK3576_PD_VEPU1 { 1148 reg = <RK3576_PD_VEPU1>; 1149 clocks = <&cru ACLK_VEPU1>, 1150 <&cru HCLK_VEPU1>; 1151 pm_qos = <&qos_vepu1>; 1152 #power-domain-cells = <0>; 1153 }; 1154 1155 power-domain@RK3576_PD_VPU { 1156 reg = <RK3576_PD_VPU>; 1157 clocks = <&cru ACLK_EBC>, 1158 <&cru HCLK_EBC>, 1159 <&cru ACLK_JPEG>, 1160 <&cru HCLK_JPEG>, 1161 <&cru ACLK_RGA2E_0>, 1162 <&cru HCLK_RGA2E_0>, 1163 <&cru ACLK_RGA2E_1>, 1164 <&cru HCLK_RGA2E_1>, 1165 <&cru ACLK_VDPP>, 1166 <&cru HCLK_VDPP>; 1167 pm_qos = <&qos_ebc>, 1168 <&qos_jpeg>, 1169 <&qos_rga0>, 1170 <&qos_rga1>, 1171 <&qos_vdpp>; 1172 #power-domain-cells = <0>; 1173 }; 1174 1175 power-domain@RK3576_PD_VDEC { 1176 reg = <RK3576_PD_VDEC>; 1177 clocks = <&cru ACLK_RKVDEC_ROOT>, 1178 <&cru HCLK_RKVDEC>; 1179 pm_qos = <&qos_rkvdec>; 1180 #power-domain-cells = <0>; 1181 }; 1182 1183 power-domain@RK3576_PD_VI { 1184 reg = <RK3576_PD_VI>; 1185 clocks = <&cru ACLK_VICAP>, 1186 <&cru HCLK_VICAP>, 1187 <&cru DCLK_VICAP>, 1188 <&cru ACLK_VI_ROOT>, 1189 <&cru HCLK_VI_ROOT>, 1190 <&cru PCLK_VI_ROOT>, 1191 <&cru CLK_ISP_CORE>, 1192 <&cru ACLK_ISP>, 1193 <&cru HCLK_ISP>, 1194 <&cru CLK_CORE_VPSS>, 1195 <&cru ACLK_VPSS>, 1196 <&cru HCLK_VPSS>; 1197 pm_qos = <&qos_isp_mro>, 1198 <&qos_isp_mwo>, 1199 <&qos_vicap_m0>, 1200 <&qos_vpss_mro>, 1201 <&qos_vpss_mwo>; 1202 #power-domain-cells = <1>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 1206 power-domain@RK3576_PD_VEPU0 { 1207 reg = <RK3576_PD_VEPU0>; 1208 clocks = <&cru ACLK_VEPU0>, 1209 <&cru HCLK_VEPU0>; 1210 pm_qos = <&qos_vepu0>; 1211 #power-domain-cells = <0>; 1212 }; 1213 }; 1214 1215 power-domain@RK3576_PD_VOP { 1216 reg = <RK3576_PD_VOP>; 1217 clocks = <&cru ACLK_VOP>, 1218 <&cru HCLK_VOP>, 1219 <&cru HCLK_VOP_ROOT>, 1220 <&cru PCLK_VOP_ROOT>; 1221 pm_qos = <&qos_vop_m0>, 1222 <&qos_vop_m1ro>; 1223 #power-domain-cells = <1>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 1227 power-domain@RK3576_PD_USB { 1228 reg = <RK3576_PD_USB>; 1229 clocks = <&cru PCLK_PHP_ROOT>, 1230 <&cru ACLK_USB_ROOT>, 1231 <&cru ACLK_MMU2>, 1232 <&cru ACLK_SLV_MMU2>, 1233 <&cru ACLK_UFS_SYS>; 1234 pm_qos = <&qos_mmu2>, 1235 <&qos_ufshc>; 1236 #power-domain-cells = <0>; 1237 }; 1238 1239 power-domain@RK3576_PD_VO0 { 1240 reg = <RK3576_PD_VO0>; 1241 clocks = <&cru ACLK_HDCP0>, 1242 <&cru HCLK_HDCP0>, 1243 <&cru ACLK_VO0_ROOT>, 1244 <&cru PCLK_VO0_ROOT>, 1245 <&cru HCLK_VOP_ROOT>; 1246 pm_qos = <&qos_hdcp0>; 1247 #power-domain-cells = <0>; 1248 }; 1249 1250 power-domain@RK3576_PD_VO1 { 1251 reg = <RK3576_PD_VO1>; 1252 clocks = <&cru ACLK_HDCP1>, 1253 <&cru HCLK_HDCP1>, 1254 <&cru ACLK_VO1_ROOT>, 1255 <&cru PCLK_VO1_ROOT>, 1256 <&cru HCLK_VOP_ROOT>; 1257 pm_qos = <&qos_hdcp1>; 1258 #power-domain-cells = <0>; 1259 }; 1260 }; 1261 }; 1262 }; 1263 1264 gpu: gpu@27800000 { 1265 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; 1266 reg = <0x0 0x27800000 0x0 0x20000>; 1267 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 1268 assigned-clock-rates = <198000000>; 1269 clocks = <&cru CLK_GPU>; 1270 clock-names = "core"; 1271 dynamic-power-coefficient = <1625>; 1272 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 1275 interrupt-names = "job", "mmu", "gpu"; 1276 operating-points-v2 = <&gpu_opp_table>; 1277 power-domains = <&power RK3576_PD_GPU>; 1278 #cooling-cells = <2>; 1279 status = "disabled"; 1280 }; 1281 1282 vdec: video-codec@27b00000 { 1283 compatible = "rockchip,rk3576-vdec"; 1284 reg = <0x0 0x27b00100 0x0 0x500>, 1285 <0x0 0x27b00000 0x0 0x100>, 1286 <0x0 0x27b00600 0x0 0x100>; 1287 reg-names = "function", "link", "cache"; 1288 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, 1290 <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, 1291 <&cru CLK_RKVDEC_HEVC_CA>; 1292 clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; 1293 assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>, 1294 <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>; 1295 assigned-clock-rates = <600000000>, <600000000>, 1296 <500000000>, <1000000000>; 1297 iommus = <&vdec_mmu>; 1298 power-domains = <&power RK3576_PD_VDEC>; 1299 resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>, 1300 <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>, 1301 <&cru SRST_RKVDEC_HEVC_CA>; 1302 reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; 1303 sram = <&rkvdec_sram>; 1304 }; 1305 1306 vdec_mmu: iommu@27b00800 { 1307 compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; 1308 reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; 1309 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1310 clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>; 1311 clock-names = "aclk", "iface"; 1312 power-domains = <&power RK3576_PD_VDEC>; 1313 rockchip,disable-mmu-reset; 1314 #iommu-cells = <0>; 1315 }; 1316 1317 vop: vop@27d00000 { 1318 compatible = "rockchip,rk3576-vop"; 1319 reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; 1320 reg-names = "vop", "gamma-lut"; 1321 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1325 interrupt-names = "sys", 1326 "vp0", 1327 "vp1", 1328 "vp2"; 1329 clocks = <&cru ACLK_VOP>, 1330 <&cru HCLK_VOP>, 1331 <&cru DCLK_VP0>, 1332 <&cru DCLK_VP1>, 1333 <&cru DCLK_VP2>, 1334 <&hdptxphy>; 1335 clock-names = "aclk", 1336 "hclk", 1337 "dclk_vp0", 1338 "dclk_vp1", 1339 "dclk_vp2", 1340 "pll_hdmiphy0"; 1341 iommus = <&vop_mmu>; 1342 power-domains = <&power RK3576_PD_VOP>; 1343 rockchip,grf = <&sys_grf>; 1344 rockchip,pmu = <&pmu>; 1345 status = "disabled"; 1346 1347 vop_out: ports { 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 1351 vp0: port@0 { 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 reg = <0>; 1355 }; 1356 1357 vp1: port@1 { 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 reg = <1>; 1361 }; 1362 1363 vp2: port@2 { 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 reg = <2>; 1367 }; 1368 }; 1369 }; 1370 1371 vop_mmu: iommu@27d07e00 { 1372 compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; 1373 reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; 1374 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1375 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1376 clock-names = "aclk", "iface"; 1377 #iommu-cells = <0>; 1378 power-domains = <&power RK3576_PD_VOP>; 1379 status = "disabled"; 1380 }; 1381 1382 sai5: sai@27d40000 { 1383 compatible = "rockchip,rk3576-sai"; 1384 reg = <0x0 0x27d40000 0x0 0x1000>; 1385 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1386 clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>; 1387 clock-names = "mclk", "hclk"; 1388 dmas = <&dmac2 3>; 1389 dma-names = "rx"; 1390 power-domains = <&power RK3576_PD_VO0>; 1391 resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>; 1392 reset-names = "m", "h"; 1393 rockchip,sai-rx-route = <0 1 2 3>; 1394 #sound-dai-cells = <0>; 1395 sound-name-prefix = "SAI5"; 1396 status = "disabled"; 1397 }; 1398 1399 sai6: sai@27d50000 { 1400 compatible = "rockchip,rk3576-sai"; 1401 reg = <0x0 0x27d50000 0x0 0x1000>; 1402 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1403 clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>; 1404 clock-names = "mclk", "hclk"; 1405 dmas = <&dmac2 4>, <&dmac2 5>; 1406 dma-names = "tx", "rx"; 1407 power-domains = <&power RK3576_PD_VO0>; 1408 resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>; 1409 reset-names = "m", "h"; 1410 rockchip,sai-rx-route = <0 1 2 3>; 1411 rockchip,sai-tx-route = <0 1 2 3>; 1412 #sound-dai-cells = <0>; 1413 sound-name-prefix = "SAI6"; 1414 status = "disabled"; 1415 }; 1416 1417 dsi: dsi@27d80000 { 1418 compatible = "rockchip,rk3576-mipi-dsi2"; 1419 reg = <0x0 0x27d80000 0x0 0x10000>; 1420 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1421 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; 1422 clock-names = "pclk", "sys"; 1423 power-domains = <&power RK3576_PD_VO0>; 1424 resets = <&cru SRST_P_DSIHOST0>; 1425 reset-names = "apb"; 1426 phys = <&mipidcphy PHY_TYPE_DPHY>; 1427 phy-names = "dcphy"; 1428 rockchip,grf = <&vo0_grf>; 1429 status = "disabled"; 1430 1431 ports { 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 1435 dsi_in: port@0 { 1436 reg = <0>; 1437 }; 1438 1439 dsi_out: port@1 { 1440 reg = <1>; 1441 }; 1442 }; 1443 }; 1444 1445 hdmi: hdmi@27da0000 { 1446 compatible = "rockchip,rk3576-dw-hdmi-qp"; 1447 reg = <0x0 0x27da0000 0x0 0x20000>; 1448 clocks = <&cru PCLK_HDMITX0>, 1449 <&cru CLK_HDMITX0_EARC>, 1450 <&cru CLK_HDMITX0_REF>, 1451 <&cru MCLK_SAI6_8CH>, 1452 <&cru CLK_HDMITXHDP>, 1453 <&cru HCLK_VO0_ROOT>; 1454 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 1455 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 1460 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 1461 phys = <&hdptxphy>; 1462 pinctrl-names = "default"; 1463 pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; 1464 power-domains = <&power RK3576_PD_VO0>; 1465 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; 1466 reset-names = "ref", "hdp"; 1467 rockchip,grf = <&ioc_grf>; 1468 rockchip,vo-grf = <&vo0_grf>; 1469 #sound-dai-cells = <0>; 1470 status = "disabled"; 1471 1472 ports { 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 1476 hdmi_in: port@0 { 1477 reg = <0>; 1478 }; 1479 1480 hdmi_out: port@1 { 1481 reg = <1>; 1482 }; 1483 }; 1484 }; 1485 1486 sai7: sai@27ed0000 { 1487 compatible = "rockchip,rk3576-sai"; 1488 reg = <0x0 0x27ed0000 0x0 0x1000>; 1489 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1490 clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>; 1491 clock-names = "mclk", "hclk"; 1492 dmas = <&dmac2 19>; 1493 dma-names = "tx"; 1494 power-domains = <&power RK3576_PD_VO1>; 1495 resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>; 1496 reset-names = "m", "h"; 1497 rockchip,sai-tx-route = <0 1 2 3>; 1498 #sound-dai-cells = <0>; 1499 sound-name-prefix = "SAI7"; 1500 status = "disabled"; 1501 }; 1502 1503 sai8: sai@27ee0000 { 1504 compatible = "rockchip,rk3576-sai"; 1505 reg = <0x0 0x27ee0000 0x0 0x1000>; 1506 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1507 clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>; 1508 clock-names = "mclk", "hclk"; 1509 dmas = <&dmac1 7>; 1510 dma-names = "tx"; 1511 power-domains = <&power RK3576_PD_VO1>; 1512 resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>; 1513 reset-names = "m", "h"; 1514 rockchip,sai-tx-route = <0 1 2 3>; 1515 #sound-dai-cells = <0>; 1516 sound-name-prefix = "SAI8"; 1517 status = "disabled"; 1518 }; 1519 1520 sai9: sai@27ef0000 { 1521 compatible = "rockchip,rk3576-sai"; 1522 reg = <0x0 0x27ef0000 0x0 0x1000>; 1523 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1524 clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>; 1525 clock-names = "mclk", "hclk"; 1526 dmas = <&dmac0 26>; 1527 dma-names = "tx"; 1528 power-domains = <&power RK3576_PD_VO1>; 1529 resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>; 1530 reset-names = "m", "h"; 1531 rockchip,sai-tx-route = <0 1 2 3>; 1532 #sound-dai-cells = <0>; 1533 sound-name-prefix = "SAI9"; 1534 status = "disabled"; 1535 }; 1536 1537 qos_hdcp1: qos@27f02000 { 1538 compatible = "rockchip,rk3576-qos", "syscon"; 1539 reg = <0x0 0x27f02000 0x0 0x20>; 1540 }; 1541 1542 qos_fspi1: qos@27f04000 { 1543 compatible = "rockchip,rk3576-qos", "syscon"; 1544 reg = <0x0 0x27f04000 0x0 0x20>; 1545 }; 1546 1547 qos_gmac0: qos@27f04080 { 1548 compatible = "rockchip,rk3576-qos", "syscon"; 1549 reg = <0x0 0x27f04080 0x0 0x20>; 1550 }; 1551 1552 qos_gmac1: qos@27f04100 { 1553 compatible = "rockchip,rk3576-qos", "syscon"; 1554 reg = <0x0 0x27f04100 0x0 0x20>; 1555 }; 1556 1557 qos_sdio: qos@27f04180 { 1558 compatible = "rockchip,rk3576-qos", "syscon"; 1559 reg = <0x0 0x27f04180 0x0 0x20>; 1560 }; 1561 1562 qos_sdmmc: qos@27f04200 { 1563 compatible = "rockchip,rk3576-qos", "syscon"; 1564 reg = <0x0 0x27f04200 0x0 0x20>; 1565 }; 1566 1567 qos_flexbus: qos@27f04280 { 1568 compatible = "rockchip,rk3576-qos", "syscon"; 1569 reg = <0x0 0x27f04280 0x0 0x20>; 1570 }; 1571 1572 qos_gpu: qos@27f05000 { 1573 compatible = "rockchip,rk3576-qos", "syscon"; 1574 reg = <0x0 0x27f05000 0x0 0x20>; 1575 }; 1576 1577 qos_vepu1: qos@27f06000 { 1578 compatible = "rockchip,rk3576-qos", "syscon"; 1579 reg = <0x0 0x27f06000 0x0 0x20>; 1580 }; 1581 1582 qos_npu_mcu: qos@27f08000 { 1583 compatible = "rockchip,rk3576-qos", "syscon"; 1584 reg = <0x0 0x27f08000 0x0 0x20>; 1585 }; 1586 1587 qos_npu_nsp0: qos@27f08080 { 1588 compatible = "rockchip,rk3576-qos", "syscon"; 1589 reg = <0x0 0x27f08080 0x0 0x20>; 1590 }; 1591 1592 qos_npu_nsp1: qos@27f08100 { 1593 compatible = "rockchip,rk3576-qos", "syscon"; 1594 reg = <0x0 0x27f08100 0x0 0x20>; 1595 }; 1596 1597 qos_emmc: qos@27f09000 { 1598 compatible = "rockchip,rk3576-qos", "syscon"; 1599 reg = <0x0 0x27f09000 0x0 0x20>; 1600 }; 1601 1602 qos_fspi0: qos@27f09080 { 1603 compatible = "rockchip,rk3576-qos", "syscon"; 1604 reg = <0x0 0x27f09080 0x0 0x20>; 1605 }; 1606 1607 qos_mmu0: qos@27f0a000 { 1608 compatible = "rockchip,rk3576-qos", "syscon"; 1609 reg = <0x0 0x27f0a000 0x0 0x20>; 1610 }; 1611 1612 qos_mmu1: qos@27f0a080 { 1613 compatible = "rockchip,rk3576-qos", "syscon"; 1614 reg = <0x0 0x27f0a080 0x0 0x20>; 1615 }; 1616 1617 qos_rkvdec: qos@27f0c000 { 1618 compatible = "rockchip,rk3576-qos", "syscon"; 1619 reg = <0x0 0x27f0c000 0x0 0x20>; 1620 }; 1621 1622 qos_crypto: qos@27f0d000 { 1623 compatible = "rockchip,rk3576-qos", "syscon"; 1624 reg = <0x0 0x27f0d000 0x0 0x20>; 1625 }; 1626 1627 qos_mmu2: qos@27f0e000 { 1628 compatible = "rockchip,rk3576-qos", "syscon"; 1629 reg = <0x0 0x27f0e000 0x0 0x20>; 1630 }; 1631 1632 qos_ufshc: qos@27f0e080 { 1633 compatible = "rockchip,rk3576-qos", "syscon"; 1634 reg = <0x0 0x27f0e080 0x0 0x20>; 1635 }; 1636 1637 qos_vepu0: qos@27f0f000 { 1638 compatible = "rockchip,rk3576-qos", "syscon"; 1639 reg = <0x0 0x27f0f000 0x0 0x20>; 1640 }; 1641 1642 qos_isp_mro: qos@27f10000 { 1643 compatible = "rockchip,rk3576-qos", "syscon"; 1644 reg = <0x0 0x27f10000 0x0 0x20>; 1645 }; 1646 1647 qos_isp_mwo: qos@27f10080 { 1648 compatible = "rockchip,rk3576-qos", "syscon"; 1649 reg = <0x0 0x27f10080 0x0 0x20>; 1650 }; 1651 1652 qos_vicap_m0: qos@27f10100 { 1653 compatible = "rockchip,rk3576-qos", "syscon"; 1654 reg = <0x0 0x27f10100 0x0 0x20>; 1655 }; 1656 1657 qos_vpss_mro: qos@27f10180 { 1658 compatible = "rockchip,rk3576-qos", "syscon"; 1659 reg = <0x0 0x27f10180 0x0 0x20>; 1660 }; 1661 1662 qos_vpss_mwo: qos@27f10200 { 1663 compatible = "rockchip,rk3576-qos", "syscon"; 1664 reg = <0x0 0x27f10200 0x0 0x20>; 1665 }; 1666 1667 qos_hdcp0: qos@27f11000 { 1668 compatible = "rockchip,rk3576-qos", "syscon"; 1669 reg = <0x0 0x27f11000 0x0 0x20>; 1670 }; 1671 1672 qos_vop_m0: qos@27f12800 { 1673 compatible = "rockchip,rk3576-qos", "syscon"; 1674 reg = <0x0 0x27f12800 0x0 0x20>; 1675 }; 1676 1677 qos_vop_m1ro: qos@27f12880 { 1678 compatible = "rockchip,rk3576-qos", "syscon"; 1679 reg = <0x0 0x27f12880 0x0 0x20>; 1680 }; 1681 1682 qos_ebc: qos@27f13000 { 1683 compatible = "rockchip,rk3576-qos", "syscon"; 1684 reg = <0x0 0x27f13000 0x0 0x20>; 1685 }; 1686 1687 qos_rga0: qos@27f13080 { 1688 compatible = "rockchip,rk3576-qos", "syscon"; 1689 reg = <0x0 0x27f13080 0x0 0x20>; 1690 }; 1691 1692 qos_rga1: qos@27f13100 { 1693 compatible = "rockchip,rk3576-qos", "syscon"; 1694 reg = <0x0 0x27f13100 0x0 0x20>; 1695 }; 1696 1697 qos_jpeg: qos@27f13180 { 1698 compatible = "rockchip,rk3576-qos", "syscon"; 1699 reg = <0x0 0x27f13180 0x0 0x20>; 1700 }; 1701 1702 qos_vdpp: qos@27f13200 { 1703 compatible = "rockchip,rk3576-qos", "syscon"; 1704 reg = <0x0 0x27f13200 0x0 0x20>; 1705 }; 1706 1707 qos_npu_m0: qos@27f20000 { 1708 compatible = "rockchip,rk3576-qos", "syscon"; 1709 reg = <0x0 0x27f20000 0x0 0x20>; 1710 }; 1711 1712 qos_npu_m1: qos@27f21000 { 1713 compatible = "rockchip,rk3576-qos", "syscon"; 1714 reg = <0x0 0x27f21000 0x0 0x20>; 1715 }; 1716 1717 qos_npu_m0ro: qos@27f22080 { 1718 compatible = "rockchip,rk3576-qos", "syscon"; 1719 reg = <0x0 0x27f22080 0x0 0x20>; 1720 }; 1721 1722 qos_npu_m1ro: qos@27f22100 { 1723 compatible = "rockchip,rk3576-qos", "syscon"; 1724 reg = <0x0 0x27f22100 0x0 0x20>; 1725 }; 1726 1727 gmac0: ethernet@2a220000 { 1728 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1729 reg = <0x0 0x2a220000 0x0 0x10000>; 1730 clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>, 1731 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 1732 <&cru CLK_GMAC0_PTP_REF>; 1733 clock-names = "stmmaceth", "clk_mac_ref", 1734 "pclk_mac", "aclk_mac", 1735 "ptp_ref"; 1736 dma-coherent; 1737 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1739 interrupt-names = "macirq", "eth_wake_irq"; 1740 power-domains = <&power RK3576_PD_SDGMAC>; 1741 resets = <&cru SRST_A_GMAC0>; 1742 reset-names = "stmmaceth"; 1743 rockchip,grf = <&sdgmac_grf>; 1744 rockchip,php-grf = <&ioc_grf>; 1745 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1746 snps,mixed-burst; 1747 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1748 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1749 snps,tso; 1750 status = "disabled"; 1751 1752 mdio0: mdio { 1753 compatible = "snps,dwmac-mdio"; 1754 #address-cells = <0x1>; 1755 #size-cells = <0x0>; 1756 }; 1757 1758 gmac0_stmmac_axi_setup: stmmac-axi-config { 1759 snps,blen = <0 0 0 0 16 8 4>; 1760 snps,rd_osr_lmt = <8>; 1761 snps,wr_osr_lmt = <4>; 1762 }; 1763 1764 gmac0_mtl_rx_setup: rx-queues-config { 1765 snps,rx-queues-to-use = <1>; 1766 queue0 {}; 1767 }; 1768 1769 gmac0_mtl_tx_setup: tx-queues-config { 1770 snps,tx-queues-to-use = <1>; 1771 queue0 {}; 1772 }; 1773 }; 1774 1775 gmac1: ethernet@2a230000 { 1776 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1777 reg = <0x0 0x2a230000 0x0 0x10000>; 1778 clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>, 1779 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1780 <&cru CLK_GMAC1_PTP_REF>; 1781 clock-names = "stmmaceth", "clk_mac_ref", 1782 "pclk_mac", "aclk_mac", 1783 "ptp_ref"; 1784 dma-coherent; 1785 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1787 interrupt-names = "macirq", "eth_wake_irq"; 1788 power-domains = <&power RK3576_PD_SDGMAC>; 1789 resets = <&cru SRST_A_GMAC1>; 1790 reset-names = "stmmaceth"; 1791 rockchip,grf = <&sdgmac_grf>; 1792 rockchip,php-grf = <&ioc_grf>; 1793 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1794 snps,mixed-burst; 1795 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1796 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1797 snps,tso; 1798 status = "disabled"; 1799 1800 mdio1: mdio { 1801 compatible = "snps,dwmac-mdio"; 1802 #address-cells = <0x1>; 1803 #size-cells = <0x0>; 1804 }; 1805 1806 gmac1_stmmac_axi_setup: stmmac-axi-config { 1807 snps,blen = <0 0 0 0 16 8 4>; 1808 snps,rd_osr_lmt = <8>; 1809 snps,wr_osr_lmt = <4>; 1810 }; 1811 1812 gmac1_mtl_rx_setup: rx-queues-config { 1813 snps,rx-queues-to-use = <1>; 1814 queue0 {}; 1815 }; 1816 1817 gmac1_mtl_tx_setup: tx-queues-config { 1818 snps,tx-queues-to-use = <1>; 1819 queue0 {}; 1820 }; 1821 }; 1822 1823 sata0: sata@2a240000 { 1824 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; 1825 reg = <0x0 0x2a240000 0x0 0x1000>; 1826 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1827 <&cru CLK_RXOOB0>; 1828 clock-names = "sata", "pmalive", "rxoob"; 1829 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1830 power-domains = <&power RK3576_PD_SUBPHP>; 1831 phys = <&combphy0_ps PHY_TYPE_SATA>; 1832 phy-names = "sata-phy"; 1833 ports-implemented = <0x1>; 1834 dma-coherent; 1835 status = "disabled"; 1836 }; 1837 1838 sata1: sata@2a250000 { 1839 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; 1840 reg = <0x0 0x2a250000 0x0 0x1000>; 1841 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 1842 <&cru CLK_RXOOB1>; 1843 clock-names = "sata", "pmalive", "rxoob"; 1844 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1845 power-domains = <&power RK3576_PD_SUBPHP>; 1846 phys = <&combphy1_psu PHY_TYPE_SATA>; 1847 phy-names = "sata-phy"; 1848 ports-implemented = <0x1>; 1849 dma-coherent; 1850 status = "disabled"; 1851 }; 1852 1853 ufshc: ufshc@2a2d0000 { 1854 compatible = "rockchip,rk3576-ufshc"; 1855 reg = <0x0 0x2a2d0000 0x0 0x10000>, 1856 <0x0 0x2b040000 0x0 0x10000>, 1857 <0x0 0x2601f000 0x0 0x1000>, 1858 <0x0 0x2603c000 0x0 0x1000>, 1859 <0x0 0x2a2e0000 0x0 0x10000>; 1860 reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; 1861 clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, 1862 <&cru CLK_REF_UFS_CLKOUT>; 1863 clock-names = "core", "pclk", "pclk_mphy", "ref_out"; 1864 assigned-clocks = <&cru CLK_REF_OSC_MPHY>; 1865 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; 1866 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1867 power-domains = <&power RK3576_PD_USB>; 1868 pinctrl-0 = <&ufs_refclk &ufs_rstgpio>; 1869 pinctrl-names = "default"; 1870 resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, 1871 <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; 1872 reset-names = "biu", "sys", "ufs", "grf"; 1873 reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; 1874 status = "disabled"; 1875 }; 1876 1877 sfc1: spi@2a300000 { 1878 compatible = "rockchip,sfc"; 1879 reg = <0x0 0x2a300000 0x0 0x4000>; 1880 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1881 clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; 1882 clock-names = "clk_sfc", "hclk_sfc"; 1883 power-domains = <&power RK3576_PD_SDGMAC>; 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 status = "disabled"; 1887 }; 1888 1889 sdmmc: mmc@2a310000 { 1890 compatible = "rockchip,rk3576-dw-mshc"; 1891 reg = <0x0 0x2a310000 0x0 0x4000>; 1892 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; 1893 clock-names = "biu", "ciu"; 1894 fifo-depth = <0x100>; 1895 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 1896 max-frequency = <200000000>; 1897 pinctrl-names = "default"; 1898 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>; 1899 power-domains = <&power RK3576_PD_SDGMAC>; 1900 resets = <&cru SRST_H_SDMMC0>; 1901 reset-names = "reset"; 1902 status = "disabled"; 1903 }; 1904 1905 sdio: mmc@2a320000 { 1906 compatible = "rockchip,rk3576-dw-mshc"; 1907 reg = <0x0 0x2a320000 0x0 0x4000>; 1908 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>; 1909 clock-names = "biu", "ciu"; 1910 fifo-depth = <0x100>; 1911 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 1912 max-frequency = <200000000>; 1913 pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>; 1914 pinctrl-names = "default"; 1915 power-domains = <&power RK3576_PD_SDGMAC>; 1916 resets = <&cru SRST_H_SDIO>; 1917 reset-names = "reset"; 1918 status = "disabled"; 1919 }; 1920 1921 sdhci: mmc@2a330000 { 1922 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; 1923 reg = <0x0 0x2a330000 0x0 0x10000>; 1924 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 1925 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1926 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 1927 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1928 <&cru TCLK_EMMC>; 1929 clock-names = "core", "bus", "axi", "block", "timer"; 1930 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1931 max-frequency = <200000000>; 1932 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1933 <&emmc_cmd>, <&emmc_strb>; 1934 pinctrl-names = "default"; 1935 power-domains = <&power RK3576_PD_NVM>; 1936 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1937 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1938 <&cru SRST_T_EMMC>; 1939 reset-names = "core", "bus", "axi", "block", "timer"; 1940 supports-cqe; 1941 status = "disabled"; 1942 }; 1943 1944 sfc0: spi@2a340000 { 1945 compatible = "rockchip,sfc"; 1946 reg = <0x0 0x2a340000 0x0 0x4000>; 1947 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1948 clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; 1949 clock-names = "clk_sfc", "hclk_sfc"; 1950 power-domains = <&power RK3576_PD_NVM>; 1951 #address-cells = <1>; 1952 #size-cells = <0>; 1953 status = "disabled"; 1954 }; 1955 1956 rng: rng@2a410000 { 1957 compatible = "rockchip,rk3576-rng"; 1958 reg = <0x0 0x2a410000 0x0 0x200>; 1959 clocks = <&cru HCLK_TRNG_NS>; 1960 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1961 resets = <&cru SRST_H_TRNG_NS>; 1962 }; 1963 1964 otp: otp@2a580000 { 1965 compatible = "rockchip,rk3576-otp"; 1966 reg = <0x0 0x2a580000 0x0 0x400>; 1967 #address-cells = <1>; 1968 #size-cells = <1>; 1969 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 1970 <&cru CLK_OTP_PHY_G>; 1971 clock-names = "otp", "apb_pclk", "phy"; 1972 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; 1973 reset-names = "otp", "apb"; 1974 1975 /* Data cells */ 1976 cpu_code: cpu-code@2 { 1977 reg = <0x02 0x2>; 1978 }; 1979 otp_cpu_version: cpu-version@5 { 1980 reg = <0x05 0x1>; 1981 bits = <3 3>; 1982 }; 1983 otp_id: id@a { 1984 reg = <0x0a 0x10>; 1985 }; 1986 cpub_leakage: cpub-leakage@1e { 1987 reg = <0x1e 0x1>; 1988 }; 1989 cpul_leakage: cpul-leakage@1f { 1990 reg = <0x1f 0x1>; 1991 }; 1992 npu_leakage: npu-leakage@20 { 1993 reg = <0x20 0x1>; 1994 }; 1995 gpu_leakage: gpu-leakage@21 { 1996 reg = <0x21 0x1>; 1997 }; 1998 log_leakage: log-leakage@22 { 1999 reg = <0x22 0x1>; 2000 }; 2001 bigcore_tsadc_trim: bigcore-tsadc-trim@24 { 2002 reg = <0x24 0x2>; 2003 bits = <0 10>; 2004 }; 2005 litcore_tsadc_trim: litcore-tsadc-trim@26 { 2006 reg = <0x26 0x2>; 2007 bits = <0 10>; 2008 }; 2009 ddr_tsadc_trim: ddr-tsadc-trim@28 { 2010 reg = <0x28 0x2>; 2011 bits = <0 10>; 2012 }; 2013 npu_tsadc_trim: npu-tsadc-trim@2a { 2014 reg = <0x2a 0x2>; 2015 bits = <0 10>; 2016 }; 2017 gpu_tsadc_trim: gpu-tsadc-trim@2c { 2018 reg = <0x2c 0x2>; 2019 bits = <0 10>; 2020 }; 2021 soc_tsadc_trim: soc-tsadc-trim@64 { 2022 reg = <0x64 0x2>; 2023 bits = <0 10>; 2024 }; 2025 }; 2026 2027 sai0: sai@2a600000 { 2028 compatible = "rockchip,rk3576-sai"; 2029 reg = <0x0 0x2a600000 0x0 0x1000>; 2030 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2031 clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>; 2032 clock-names = "mclk", "hclk"; 2033 dmas = <&dmac0 0>, <&dmac0 1>; 2034 dma-names = "tx", "rx"; 2035 power-domains = <&power RK3576_PD_AUDIO>; 2036 resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; 2037 reset-names = "m", "h"; 2038 pinctrl-names = "default"; 2039 pinctrl-0 = <&sai0m0_lrck 2040 &sai0m0_sclk 2041 &sai0m0_sdi0 2042 &sai0m0_sdi1 2043 &sai0m0_sdi2 2044 &sai0m0_sdi3 2045 &sai0m0_sdo0 2046 &sai0m0_sdo1 2047 &sai0m0_sdo2 2048 &sai0m0_sdo3>; 2049 #sound-dai-cells = <0>; 2050 sound-name-prefix = "SAI0"; 2051 status = "disabled"; 2052 }; 2053 2054 sai1: sai@2a610000 { 2055 compatible = "rockchip,rk3576-sai"; 2056 reg = <0x0 0x2a610000 0x0 0x1000>; 2057 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2058 clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>; 2059 clock-names = "mclk", "hclk"; 2060 dmas = <&dmac0 2>, <&dmac0 3>; 2061 dma-names = "tx", "rx"; 2062 power-domains = <&power RK3576_PD_AUDIO>; 2063 resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; 2064 reset-names = "m", "h"; 2065 pinctrl-names = "default"; 2066 pinctrl-0 = <&sai1m0_lrck 2067 &sai1m0_sclk 2068 &sai1m0_sdi0 2069 &sai1m0_sdo0 2070 &sai1m0_sdo1 2071 &sai1m0_sdo2 2072 &sai1m0_sdo3>; 2073 #sound-dai-cells = <0>; 2074 sound-name-prefix = "SAI1"; 2075 status = "disabled"; 2076 }; 2077 2078 sai2: sai@2a620000 { 2079 compatible = "rockchip,rk3576-sai"; 2080 reg = <0x0 0x2a620000 0x0 0x1000>; 2081 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2082 clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>; 2083 clock-names = "mclk", "hclk"; 2084 dmas = <&dmac1 0>, <&dmac1 1>; 2085 dma-names = "tx", "rx"; 2086 power-domains = <&power RK3576_PD_AUDIO>; 2087 resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; 2088 reset-names = "m", "h"; 2089 pinctrl-names = "default"; 2090 pinctrl-0 = <&sai2m0_lrck 2091 &sai2m0_sclk 2092 &sai2m0_sdi 2093 &sai2m0_sdo>; 2094 #sound-dai-cells = <0>; 2095 sound-name-prefix = "SAI2"; 2096 status = "disabled"; 2097 }; 2098 2099 sai3: sai@2a630000 { 2100 compatible = "rockchip,rk3576-sai"; 2101 reg = <0x0 0x2a630000 0x0 0x1000>; 2102 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2103 clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>; 2104 clock-names = "mclk", "hclk"; 2105 dmas = <&dmac1 2>, <&dmac1 3>; 2106 dma-names = "tx", "rx"; 2107 power-domains = <&power RK3576_PD_AUDIO>; 2108 resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>; 2109 reset-names = "m", "h"; 2110 pinctrl-names = "default"; 2111 pinctrl-0 = <&sai3m0_lrck 2112 &sai3m0_sclk 2113 &sai3m0_sdi 2114 &sai3m0_sdo>; 2115 #sound-dai-cells = <0>; 2116 sound-name-prefix = "SAI3"; 2117 status = "disabled"; 2118 }; 2119 2120 sai4: sai@2a640000 { 2121 compatible = "rockchip,rk3576-sai"; 2122 reg = <0x0 0x2a640000 0x0 0x1000>; 2123 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2124 clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>; 2125 clock-names = "mclk", "hclk"; 2126 dmas = <&dmac2 0>, <&dmac2 1>; 2127 dma-names = "tx", "rx"; 2128 power-domains = <&power RK3576_PD_AUDIO>; 2129 resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>; 2130 reset-names = "m", "h"; 2131 pinctrl-names = "default"; 2132 pinctrl-0 = <&sai4m0_lrck 2133 &sai4m0_sclk 2134 &sai4m0_sdi 2135 &sai4m0_sdo>; 2136 #sound-dai-cells = <0>; 2137 sound-name-prefix = "SAI4"; 2138 status = "disabled"; 2139 }; 2140 2141 gic: interrupt-controller@2a701000 { 2142 compatible = "arm,gic-400"; 2143 reg = <0x0 0x2a701000 0 0x10000>, 2144 <0x0 0x2a702000 0 0x10000>, 2145 <0x0 0x2a704000 0 0x10000>, 2146 <0x0 0x2a706000 0 0x10000>; 2147 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2148 interrupt-controller; 2149 #interrupt-cells = <3>; 2150 #address-cells = <2>; 2151 #size-cells = <2>; 2152 }; 2153 2154 dmac0: dma-controller@2ab90000 { 2155 compatible = "arm,pl330", "arm,primecell"; 2156 reg = <0x0 0x2ab90000 0x0 0x4000>; 2157 arm,pl330-periph-burst; 2158 clocks = <&cru ACLK_DMAC0>; 2159 clock-names = "apb_pclk"; 2160 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2162 #dma-cells = <1>; 2163 }; 2164 2165 dmac1: dma-controller@2abb0000 { 2166 compatible = "arm,pl330", "arm,primecell"; 2167 reg = <0x0 0x2abb0000 0x0 0x4000>; 2168 arm,pl330-periph-burst; 2169 clocks = <&cru ACLK_DMAC1>; 2170 clock-names = "apb_pclk"; 2171 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2173 #dma-cells = <1>; 2174 }; 2175 2176 dmac2: dma-controller@2abd0000 { 2177 compatible = "arm,pl330", "arm,primecell"; 2178 reg = <0x0 0x2abd0000 0x0 0x4000>; 2179 arm,pl330-periph-burst; 2180 clocks = <&cru ACLK_DMAC2>; 2181 clock-names = "apb_pclk"; 2182 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2184 #dma-cells = <1>; 2185 }; 2186 2187 i2c1: i2c@2ac40000 { 2188 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2189 reg = <0x0 0x2ac40000 0x0 0x1000>; 2190 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2191 clock-names = "i2c", "pclk"; 2192 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 2193 pinctrl-names = "default"; 2194 pinctrl-0 = <&i2c1m0_xfer>; 2195 #address-cells = <1>; 2196 #size-cells = <0>; 2197 status = "disabled"; 2198 }; 2199 2200 i2c2: i2c@2ac50000 { 2201 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2202 reg = <0x0 0x2ac50000 0x0 0x1000>; 2203 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2204 clock-names = "i2c", "pclk"; 2205 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2206 pinctrl-names = "default"; 2207 pinctrl-0 = <&i2c2m0_xfer>; 2208 #address-cells = <1>; 2209 #size-cells = <0>; 2210 status = "disabled"; 2211 }; 2212 2213 i2c3: i2c@2ac60000 { 2214 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2215 reg = <0x0 0x2ac60000 0x0 0x1000>; 2216 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2217 clock-names = "i2c", "pclk"; 2218 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2219 pinctrl-names = "default"; 2220 pinctrl-0 = <&i2c3m0_xfer>; 2221 #address-cells = <1>; 2222 #size-cells = <0>; 2223 status = "disabled"; 2224 }; 2225 2226 i2c4: i2c@2ac70000 { 2227 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2228 reg = <0x0 0x2ac70000 0x0 0x1000>; 2229 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2230 clock-names = "i2c", "pclk"; 2231 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 2232 pinctrl-names = "default"; 2233 pinctrl-0 = <&i2c4m0_xfer>; 2234 #address-cells = <1>; 2235 #size-cells = <0>; 2236 status = "disabled"; 2237 }; 2238 2239 i2c5: i2c@2ac80000 { 2240 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2241 reg = <0x0 0x2ac80000 0x0 0x1000>; 2242 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2243 clock-names = "i2c", "pclk"; 2244 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 2245 pinctrl-names = "default"; 2246 pinctrl-0 = <&i2c5m0_xfer>; 2247 #address-cells = <1>; 2248 #size-cells = <0>; 2249 status = "disabled"; 2250 }; 2251 2252 i2c6: i2c@2ac90000 { 2253 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2254 reg = <0x0 0x2ac90000 0x0 0x1000>; 2255 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2256 clock-names = "i2c", "pclk"; 2257 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 2258 pinctrl-names = "default"; 2259 pinctrl-0 = <&i2c6m0_xfer>; 2260 #address-cells = <1>; 2261 #size-cells = <0>; 2262 status = "disabled"; 2263 }; 2264 2265 i2c7: i2c@2aca0000 { 2266 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2267 reg = <0x0 0x2aca0000 0x0 0x1000>; 2268 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2269 clock-names = "i2c", "pclk"; 2270 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2271 pinctrl-names = "default"; 2272 pinctrl-0 = <&i2c7m0_xfer>; 2273 #address-cells = <1>; 2274 #size-cells = <0>; 2275 status = "disabled"; 2276 }; 2277 2278 i2c8: i2c@2acb0000 { 2279 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2280 reg = <0x0 0x2acb0000 0x0 0x1000>; 2281 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2282 clock-names = "i2c", "pclk"; 2283 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2284 pinctrl-names = "default"; 2285 pinctrl-0 = <&i2c8m0_xfer>; 2286 #address-cells = <1>; 2287 #size-cells = <0>; 2288 status = "disabled"; 2289 }; 2290 2291 timer0: timer@2acc0000 { 2292 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer"; 2293 reg = <0x0 0x2acc0000 0x0 0x20>; 2294 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>; 2295 clock-names = "pclk", "timer"; 2296 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2297 }; 2298 2299 wdt: watchdog@2ace0000 { 2300 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt"; 2301 reg = <0x0 0x2ace0000 0x0 0x100>; 2302 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2303 clock-names = "tclk", "pclk"; 2304 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2305 }; 2306 2307 spi0: spi@2acf0000 { 2308 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2309 reg = <0x0 0x2acf0000 0x0 0x1000>; 2310 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2311 clock-names = "spiclk", "apb_pclk"; 2312 dmas = <&dmac0 14>, <&dmac0 15>; 2313 dma-names = "tx", "rx"; 2314 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2315 num-cs = <2>; 2316 pinctrl-names = "default"; 2317 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 2318 #address-cells = <1>; 2319 #size-cells = <0>; 2320 status = "disabled"; 2321 }; 2322 2323 spi1: spi@2ad00000 { 2324 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2325 reg = <0x0 0x2ad00000 0x0 0x1000>; 2326 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2327 clock-names = "spiclk", "apb_pclk"; 2328 dmas = <&dmac0 16>, <&dmac0 17>; 2329 dma-names = "tx", "rx"; 2330 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2331 num-cs = <2>; 2332 pinctrl-names = "default"; 2333 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 2334 #address-cells = <1>; 2335 #size-cells = <0>; 2336 status = "disabled"; 2337 }; 2338 2339 spi2: spi@2ad10000 { 2340 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2341 reg = <0x0 0x2ad10000 0x0 0x1000>; 2342 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2343 clock-names = "spiclk", "apb_pclk"; 2344 dmas = <&dmac1 15>, <&dmac1 16>; 2345 dma-names = "tx", "rx"; 2346 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2347 num-cs = <2>; 2348 pinctrl-names = "default"; 2349 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 2350 #address-cells = <1>; 2351 #size-cells = <0>; 2352 status = "disabled"; 2353 }; 2354 2355 spi3: spi@2ad20000 { 2356 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2357 reg = <0x0 0x2ad20000 0x0 0x1000>; 2358 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2359 clock-names = "spiclk", "apb_pclk"; 2360 dmas = <&dmac1 17>, <&dmac1 18>; 2361 dma-names = "tx", "rx"; 2362 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2363 num-cs = <2>; 2364 pinctrl-names = "default"; 2365 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>; 2366 #address-cells = <1>; 2367 #size-cells = <0>; 2368 status = "disabled"; 2369 }; 2370 2371 spi4: spi@2ad30000 { 2372 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2373 reg = <0x0 0x2ad30000 0x0 0x1000>; 2374 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2375 clock-names = "spiclk", "apb_pclk"; 2376 dmas = <&dmac2 12>, <&dmac2 13>; 2377 dma-names = "tx", "rx"; 2378 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 2379 num-cs = <2>; 2380 pinctrl-names = "default"; 2381 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>; 2382 #address-cells = <1>; 2383 #size-cells = <0>; 2384 status = "disabled"; 2385 }; 2386 2387 uart0: serial@2ad40000 { 2388 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2389 reg = <0x0 0x2ad40000 0x0 0x100>; 2390 reg-shift = <2>; 2391 reg-io-width = <4>; 2392 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 2393 clock-names = "baudclk", "apb_pclk"; 2394 dmas = <&dmac0 6>, <&dmac0 7>; 2395 dma-names = "tx", "rx"; 2396 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 2397 pinctrl-0 = <&uart0m0_xfer>; 2398 pinctrl-names = "default"; 2399 status = "disabled"; 2400 }; 2401 2402 uart2: serial@2ad50000 { 2403 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2404 reg = <0x0 0x2ad50000 0x0 0x100>; 2405 reg-shift = <2>; 2406 reg-io-width = <4>; 2407 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2408 clock-names = "baudclk", "apb_pclk"; 2409 dmas = <&dmac0 10>, <&dmac0 11>; 2410 dma-names = "tx", "rx"; 2411 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 2412 pinctrl-names = "default"; 2413 pinctrl-0 = <&uart2m0_xfer>; 2414 status = "disabled"; 2415 }; 2416 2417 uart3: serial@2ad60000 { 2418 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2419 reg = <0x0 0x2ad60000 0x0 0x100>; 2420 reg-shift = <2>; 2421 reg-io-width = <4>; 2422 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2423 clock-names = "baudclk", "apb_pclk"; 2424 dmas = <&dmac0 12>, <&dmac0 13>; 2425 dma-names = "tx", "rx"; 2426 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 2427 pinctrl-0 = <&uart3m0_xfer>; 2428 pinctrl-names = "default"; 2429 status = "disabled"; 2430 }; 2431 2432 uart4: serial@2ad70000 { 2433 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2434 reg = <0x0 0x2ad70000 0x0 0x100>; 2435 reg-shift = <2>; 2436 reg-io-width = <4>; 2437 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2438 clock-names = "baudclk", "apb_pclk"; 2439 dmas = <&dmac1 9>, <&dmac1 10>; 2440 dma-names = "tx", "rx"; 2441 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2442 pinctrl-0 = <&uart4m0_xfer>; 2443 pinctrl-names = "default"; 2444 status = "disabled"; 2445 }; 2446 2447 uart5: serial@2ad80000 { 2448 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2449 reg = <0x0 0x2ad80000 0x0 0x100>; 2450 reg-shift = <2>; 2451 reg-io-width = <4>; 2452 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2453 clock-names = "baudclk", "apb_pclk"; 2454 dmas = <&dmac1 11>, <&dmac1 12>; 2455 dma-names = "tx", "rx"; 2456 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2457 pinctrl-0 = <&uart5m0_xfer>; 2458 pinctrl-names = "default"; 2459 status = "disabled"; 2460 }; 2461 2462 uart6: serial@2ad90000 { 2463 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2464 reg = <0x0 0x2ad90000 0x0 0x100>; 2465 reg-shift = <2>; 2466 reg-io-width = <4>; 2467 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2468 clock-names = "baudclk", "apb_pclk"; 2469 dmas = <&dmac1 13>, <&dmac1 14>; 2470 dma-names = "tx", "rx"; 2471 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2472 pinctrl-0 = <&uart6m0_xfer>; 2473 pinctrl-names = "default"; 2474 status = "disabled"; 2475 }; 2476 2477 uart7: serial@2ada0000 { 2478 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2479 reg = <0x0 0x2ada0000 0x0 0x100>; 2480 reg-shift = <2>; 2481 reg-io-width = <4>; 2482 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2483 clock-names = "baudclk", "apb_pclk"; 2484 dmas = <&dmac2 6>, <&dmac2 7>; 2485 dma-names = "tx", "rx"; 2486 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2487 pinctrl-0 = <&uart7m0_xfer>; 2488 pinctrl-names = "default"; 2489 status = "disabled"; 2490 }; 2491 2492 uart8: serial@2adb0000 { 2493 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2494 reg = <0x0 0x2adb0000 0x0 0x100>; 2495 reg-shift = <2>; 2496 reg-io-width = <4>; 2497 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2498 clock-names = "baudclk", "apb_pclk"; 2499 dmas = <&dmac2 8>, <&dmac2 9>; 2500 dma-names = "tx", "rx"; 2501 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 2502 pinctrl-0 = <&uart8m0_xfer>; 2503 pinctrl-names = "default"; 2504 status = "disabled"; 2505 }; 2506 2507 uart9: serial@2adc0000 { 2508 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2509 reg = <0x0 0x2adc0000 0x0 0x100>; 2510 reg-shift = <2>; 2511 reg-io-width = <4>; 2512 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2513 clock-names = "baudclk", "apb_pclk"; 2514 dmas = <&dmac2 10>, <&dmac2 11>; 2515 dma-names = "tx", "rx"; 2516 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 2517 pinctrl-0 = <&uart9m0_xfer>; 2518 pinctrl-names = "default"; 2519 status = "disabled"; 2520 }; 2521 2522 saradc: adc@2ae00000 { 2523 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc"; 2524 reg = <0x0 0x2ae00000 0x0 0x10000>; 2525 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2526 clock-names = "saradc", "apb_pclk"; 2527 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 2528 resets = <&cru SRST_P_SARADC>; 2529 reset-names = "saradc-apb"; 2530 #io-channel-cells = <1>; 2531 status = "disabled"; 2532 }; 2533 2534 tsadc: tsadc@2ae70000 { 2535 compatible = "rockchip,rk3576-tsadc"; 2536 reg = <0x0 0x2ae70000 0x0 0x400>; 2537 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2538 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2539 clock-names = "tsadc", "apb_pclk"; 2540 assigned-clocks = <&cru CLK_TSADC>; 2541 assigned-clock-rates = <2000000>; 2542 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2543 reset-names = "tsadc-apb", "tsadc"; 2544 #thermal-sensor-cells = <1>; 2545 rockchip,hw-tshut-temp = <120000>; 2546 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2547 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2548 #address-cells = <1>; 2549 #size-cells = <0>; 2550 2551 sensor@0 { 2552 reg = <0>; 2553 nvmem-cells = <&soc_tsadc_trim>; 2554 nvmem-cell-names = "trim"; 2555 }; 2556 sensor@1 { 2557 reg = <1>; 2558 nvmem-cells = <&bigcore_tsadc_trim>; 2559 nvmem-cell-names = "trim"; 2560 }; 2561 sensor@2 { 2562 reg = <2>; 2563 nvmem-cells = <&litcore_tsadc_trim>; 2564 nvmem-cell-names = "trim"; 2565 }; 2566 sensor@3 { 2567 reg = <3>; 2568 nvmem-cells = <&ddr_tsadc_trim>; 2569 nvmem-cell-names = "trim"; 2570 }; 2571 sensor@4 { 2572 reg = <4>; 2573 nvmem-cells = <&npu_tsadc_trim>; 2574 nvmem-cell-names = "trim"; 2575 }; 2576 sensor@5 { 2577 reg = <5>; 2578 nvmem-cells = <&gpu_tsadc_trim>; 2579 nvmem-cell-names = "trim"; 2580 }; 2581 }; 2582 2583 i2c9: i2c@2ae80000 { 2584 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2585 reg = <0x0 0x2ae80000 0x0 0x1000>; 2586 clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>; 2587 clock-names = "i2c", "pclk"; 2588 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2589 pinctrl-names = "default"; 2590 pinctrl-0 = <&i2c9m0_xfer>; 2591 #address-cells = <1>; 2592 #size-cells = <0>; 2593 status = "disabled"; 2594 }; 2595 2596 uart10: serial@2afc0000 { 2597 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2598 reg = <0x0 0x2afc0000 0x0 0x100>; 2599 reg-shift = <2>; 2600 reg-io-width = <4>; 2601 clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>; 2602 clock-names = "baudclk", "apb_pclk"; 2603 dmas = <&dmac2 21>, <&dmac2 22>; 2604 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2605 pinctrl-names = "default"; 2606 pinctrl-0 = <&uart10m0_xfer>; 2607 status = "disabled"; 2608 }; 2609 2610 uart11: serial@2afd0000 { 2611 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2612 reg = <0x0 0x2afd0000 0x0 0x100>; 2613 reg-shift = <2>; 2614 reg-io-width = <4>; 2615 clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>; 2616 clock-names = "baudclk", "apb_pclk"; 2617 dmas = <&dmac2 23>, <&dmac2 24>; 2618 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 2619 pinctrl-names = "default"; 2620 pinctrl-0 = <&uart11m0_xfer>; 2621 status = "disabled"; 2622 }; 2623 2624 mipidcphy: phy@2b020000 { 2625 compatible = "rockchip,rk3576-mipi-dcphy"; 2626 reg = <0x0 0x2b020000 0x0 0x10000>; 2627 clocks = <&cru PCLK_MIPI_DCPHY>, 2628 <&cru CLK_PHY_REF_SRC>; 2629 clock-names = "pclk", "ref"; 2630 resets = <&cru SRST_M_MIPI_DCPHY>, 2631 <&cru SRST_P_MIPI_DCPHY>, 2632 <&cru SRST_P_DCPHY_GRF>, 2633 <&cru SRST_S_MIPI_DCPHY>; 2634 reset-names = "m_phy", "apb", "grf", "s_phy"; 2635 rockchip,grf = <&mipidcphy_grf>; 2636 #phy-cells = <1>; 2637 status = "disabled"; 2638 }; 2639 2640 combphy0_ps: phy@2b050000 { 2641 compatible = "rockchip,rk3576-naneng-combphy"; 2642 reg = <0x0 0x2b050000 0x0 0x100>; 2643 #phy-cells = <1>; 2644 clocks = <&cru CLK_REF_PCIE0_PHY>, 2645 <&cru PCLK_PCIE2_COMBOPHY0>, 2646 <&cru PCLK_PCIE0>; 2647 clock-names = "ref", "apb", "pipe"; 2648 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>; 2649 assigned-clock-rates = <100000000>; 2650 resets = <&cru SRST_PCIE0_PIPE_PHY>, 2651 <&cru SRST_P_PCIE2_COMBOPHY0>; 2652 reset-names = "phy", "apb"; 2653 rockchip,pipe-grf = <&php_grf>; 2654 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2655 status = "disabled"; 2656 }; 2657 2658 combphy1_psu: phy@2b060000 { 2659 compatible = "rockchip,rk3576-naneng-combphy"; 2660 reg = <0x0 0x2b060000 0x0 0x100>; 2661 #phy-cells = <1>; 2662 clocks = <&cru CLK_REF_PCIE1_PHY>, 2663 <&cru PCLK_PCIE2_COMBOPHY1>, 2664 <&cru PCLK_PCIE1>; 2665 clock-names = "ref", "apb", "pipe"; 2666 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>; 2667 assigned-clock-rates = <100000000>; 2668 resets = <&cru SRST_PCIE1_PIPE_PHY>, 2669 <&cru SRST_P_PCIE2_COMBOPHY1>; 2670 reset-names = "phy", "apb"; 2671 rockchip,pipe-grf = <&php_grf>; 2672 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 2673 status = "disabled"; 2674 }; 2675 2676 usbdp_phy: phy@2b010000 { 2677 compatible = "rockchip,rk3576-usbdp-phy"; 2678 reg = <0x0 0x2b010000 0x0 0x10000>; 2679 #phy-cells = <1>; 2680 clocks = <&cru CLK_PHY_REF_SRC >, 2681 <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>, 2682 <&cru PCLK_USBDPPHY>, 2683 <&u2phy0>; 2684 clock-names = "refclk", "immortal", "pclk", "utmi"; 2685 resets = <&cru SRST_USBDP_COMBO_PHY_INIT>, 2686 <&cru SRST_USBDP_COMBO_PHY_CMN>, 2687 <&cru SRST_USBDP_COMBO_PHY_LANE>, 2688 <&cru SRST_USBDP_COMBO_PHY_PCS>, 2689 <&cru SRST_P_USBDPPHY>; 2690 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2691 rockchip,u2phy-grf = <&usb2phy_grf>; 2692 rockchip,usb-grf = <&usb_grf>; 2693 rockchip,usbdpphy-grf = <&usbdpphy_grf>; 2694 rockchip,vo-grf = <&vo1_grf>; 2695 status = "disabled"; 2696 }; 2697 2698 hdptxphy: hdmiphy@2b000000 { 2699 compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; 2700 reg = <0x0 0x2b000000 0x0 0x2000>; 2701 clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; 2702 clock-names = "ref", "apb"; 2703 #clock-cells = <0>; 2704 resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, 2705 <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; 2706 reset-names = "apb", "init", "cmn", "lane"; 2707 rockchip,grf = <&hdptxphy_grf>; 2708 #phy-cells = <0>; 2709 status = "disabled"; 2710 }; 2711 2712 sram: sram@3ff88000 { 2713 compatible = "mmio-sram"; 2714 reg = <0x0 0x3ff88000 0x0 0x78000>; 2715 ranges = <0x0 0x0 0x3ff88000 0x78000>; 2716 #address-cells = <1>; 2717 #size-cells = <1>; 2718 2719 /* start address and size should be 4k align */ 2720 rkvdec_sram: rkvdec-sram@0 { 2721 reg = <0x0 0x78000>; 2722 pool; 2723 }; 2724 }; 2725 2726 scmi_shmem: scmi-shmem@4010f000 { 2727 compatible = "arm,scmi-shmem"; 2728 reg = <0x0 0x4010f000 0x0 0x100>; 2729 }; 2730 }; 2731}; 2732 2733#include "rk3576-pinctrl.dtsi" 2734