1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8#include <dt-bindings/clock/qcom,sm8450-videocc.h> 9#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 10#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 11#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 12#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 chosen { }; 33 34 clocks { 35 xo_board: xo-board { 36 compatible = "fixed-clock"; 37 clock-frequency = <76800000>; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 clock-frequency = <32764>; 44 #clock-cells = <0>; 45 }; 46 47 bi_tcxo_div2: bi-tcxo-div2-clk { 48 compatible = "fixed-factor-clock"; 49 #clock-cells = <0>; 50 51 clocks = <&rpmhcc RPMH_CXO_CLK>; 52 clock-mult = <1>; 53 clock-div = <2>; 54 }; 55 56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 57 compatible = "fixed-factor-clock"; 58 #clock-cells = <0>; 59 60 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 61 clock-mult = <1>; 62 clock-div = <2>; 63 }; 64 }; 65 66 cpus { 67 #address-cells = <2>; 68 #size-cells = <0>; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "qcom,oryon"; 73 reg = <0x0 0x0>; 74 enable-method = "psci"; 75 next-level-cache = <&l2_0>; 76 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; 77 power-domain-names = "psci", "perf"; 78 #cooling-cells = <2>; 79 80 l2_0: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 }; 85 }; 86 87 cpu1: cpu@100 { 88 device_type = "cpu"; 89 compatible = "qcom,oryon"; 90 reg = <0x0 0x100>; 91 enable-method = "psci"; 92 next-level-cache = <&l2_0>; 93 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; 94 power-domain-names = "psci", "perf"; 95 #cooling-cells = <2>; 96 }; 97 98 cpu2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "qcom,oryon"; 101 reg = <0x0 0x200>; 102 enable-method = "psci"; 103 next-level-cache = <&l2_0>; 104 power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; 105 power-domain-names = "psci", "perf"; 106 #cooling-cells = <2>; 107 }; 108 109 cpu3: cpu@300 { 110 device_type = "cpu"; 111 compatible = "qcom,oryon"; 112 reg = <0x0 0x300>; 113 enable-method = "psci"; 114 next-level-cache = <&l2_0>; 115 power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; 116 power-domain-names = "psci", "perf"; 117 #cooling-cells = <2>; 118 }; 119 120 cpu4: cpu@10000 { 121 device_type = "cpu"; 122 compatible = "qcom,oryon"; 123 reg = <0x0 0x10000>; 124 enable-method = "psci"; 125 next-level-cache = <&l2_1>; 126 power-domains = <&cpu_pd4>, <&scmi_dvfs 1>; 127 power-domain-names = "psci", "perf"; 128 #cooling-cells = <2>; 129 130 l2_1: l2-cache { 131 compatible = "cache"; 132 cache-level = <2>; 133 cache-unified; 134 }; 135 }; 136 137 cpu5: cpu@10100 { 138 device_type = "cpu"; 139 compatible = "qcom,oryon"; 140 reg = <0x0 0x10100>; 141 enable-method = "psci"; 142 next-level-cache = <&l2_1>; 143 power-domains = <&cpu_pd5>, <&scmi_dvfs 1>; 144 power-domain-names = "psci", "perf"; 145 #cooling-cells = <2>; 146 }; 147 148 cpu6: cpu@10200 { 149 device_type = "cpu"; 150 compatible = "qcom,oryon"; 151 reg = <0x0 0x10200>; 152 enable-method = "psci"; 153 next-level-cache = <&l2_1>; 154 power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; 155 power-domain-names = "psci", "perf"; 156 #cooling-cells = <2>; 157 }; 158 159 cpu7: cpu@10300 { 160 device_type = "cpu"; 161 compatible = "qcom,oryon"; 162 reg = <0x0 0x10300>; 163 enable-method = "psci"; 164 next-level-cache = <&l2_1>; 165 power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; 166 power-domain-names = "psci", "perf"; 167 #cooling-cells = <2>; 168 }; 169 170 cpu8: cpu@20000 { 171 device_type = "cpu"; 172 compatible = "qcom,oryon"; 173 reg = <0x0 0x20000>; 174 enable-method = "psci"; 175 next-level-cache = <&l2_2>; 176 power-domains = <&cpu_pd8>, <&scmi_dvfs 2>; 177 power-domain-names = "psci", "perf"; 178 #cooling-cells = <2>; 179 180 l2_2: l2-cache { 181 compatible = "cache"; 182 cache-level = <2>; 183 cache-unified; 184 }; 185 }; 186 187 cpu9: cpu@20100 { 188 device_type = "cpu"; 189 compatible = "qcom,oryon"; 190 reg = <0x0 0x20100>; 191 enable-method = "psci"; 192 next-level-cache = <&l2_2>; 193 power-domains = <&cpu_pd9>, <&scmi_dvfs 2>; 194 power-domain-names = "psci", "perf"; 195 #cooling-cells = <2>; 196 }; 197 198 cpu10: cpu@20200 { 199 device_type = "cpu"; 200 compatible = "qcom,oryon"; 201 reg = <0x0 0x20200>; 202 enable-method = "psci"; 203 next-level-cache = <&l2_2>; 204 power-domains = <&cpu_pd10>, <&scmi_dvfs 2>; 205 power-domain-names = "psci", "perf"; 206 #cooling-cells = <2>; 207 }; 208 209 cpu11: cpu@20300 { 210 device_type = "cpu"; 211 compatible = "qcom,oryon"; 212 reg = <0x0 0x20300>; 213 enable-method = "psci"; 214 next-level-cache = <&l2_2>; 215 power-domains = <&cpu_pd11>, <&scmi_dvfs 2>; 216 power-domain-names = "psci", "perf"; 217 #cooling-cells = <2>; 218 }; 219 220 cpu-map { 221 cluster0 { 222 core0 { 223 cpu = <&cpu0>; 224 }; 225 226 core1 { 227 cpu = <&cpu1>; 228 }; 229 230 core2 { 231 cpu = <&cpu2>; 232 }; 233 234 core3 { 235 cpu = <&cpu3>; 236 }; 237 }; 238 239 cluster1 { 240 core0 { 241 cpu = <&cpu4>; 242 }; 243 244 core1 { 245 cpu = <&cpu5>; 246 }; 247 248 core2 { 249 cpu = <&cpu6>; 250 }; 251 252 core3 { 253 cpu = <&cpu7>; 254 }; 255 }; 256 257 cpu_map_cluster2: cluster2 { 258 core0 { 259 cpu = <&cpu8>; 260 }; 261 262 core1 { 263 cpu = <&cpu9>; 264 }; 265 266 core2 { 267 cpu = <&cpu10>; 268 }; 269 270 core3 { 271 cpu = <&cpu11>; 272 }; 273 }; 274 }; 275 276 idle-states { 277 entry-method = "psci"; 278 279 cluster_c4: cpu-sleep-0 { 280 compatible = "arm,idle-state"; 281 idle-state-name = "ret"; 282 arm,psci-suspend-param = <0x00000004>; 283 entry-latency-us = <180>; 284 exit-latency-us = <320>; 285 min-residency-us = <600>; 286 }; 287 }; 288 289 domain-idle-states { 290 cluster_cl4: cluster-sleep-0 { 291 compatible = "domain-idle-state"; 292 arm,psci-suspend-param = <0x01000044>; 293 entry-latency-us = <350>; 294 exit-latency-us = <500>; 295 min-residency-us = <2500>; 296 }; 297 298 cluster_cl5: cluster-sleep-1 { 299 compatible = "domain-idle-state"; 300 arm,psci-suspend-param = <0x01000054>; 301 entry-latency-us = <2200>; 302 exit-latency-us = <4000>; 303 min-residency-us = <7000>; 304 }; 305 }; 306 }; 307 308 dummy-sink { 309 compatible = "arm,coresight-dummy-sink"; 310 311 in-ports { 312 port { 313 eud_in: endpoint { 314 remote-endpoint = <&swao_rep_out1>; 315 }; 316 }; 317 }; 318 }; 319 320 firmware { 321 scm: scm { 322 compatible = "qcom,scm-x1e80100", "qcom,scm"; 323 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 324 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 325 qcom,dload-mode = <&tcsr 0x19000>; 326 }; 327 328 scmi { 329 compatible = "arm,scmi"; 330 mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; 331 mbox-names = "tx", "rx"; 332 shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; 333 334 #address-cells = <1>; 335 #size-cells = <0>; 336 337 scmi_dvfs: protocol@13 { 338 reg = <0x13>; 339 #power-domain-cells = <1>; 340 }; 341 }; 342 }; 343 344 clk_virt: interconnect-0 { 345 compatible = "qcom,x1e80100-clk-virt"; 346 #interconnect-cells = <2>; 347 qcom,bcm-voters = <&apps_bcm_voter>; 348 }; 349 350 mc_virt: interconnect-1 { 351 compatible = "qcom,x1e80100-mc-virt"; 352 #interconnect-cells = <2>; 353 qcom,bcm-voters = <&apps_bcm_voter>; 354 }; 355 356 memory@80000000 { 357 device_type = "memory"; 358 /* We expect the bootloader to fill in the size */ 359 reg = <0 0x80000000 0 0>; 360 }; 361 362 pmu { 363 compatible = "arm,armv8-pmuv3"; 364 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 365 }; 366 367 psci { 368 compatible = "arm,psci-1.0"; 369 method = "smc"; 370 371 cpu_pd0: power-domain-cpu0 { 372 #power-domain-cells = <0>; 373 power-domains = <&cluster_pd0>; 374 domain-idle-states = <&cluster_c4>; 375 }; 376 377 cpu_pd1: power-domain-cpu1 { 378 #power-domain-cells = <0>; 379 power-domains = <&cluster_pd0>; 380 domain-idle-states = <&cluster_c4>; 381 }; 382 383 cpu_pd2: power-domain-cpu2 { 384 #power-domain-cells = <0>; 385 power-domains = <&cluster_pd0>; 386 domain-idle-states = <&cluster_c4>; 387 }; 388 389 cpu_pd3: power-domain-cpu3 { 390 #power-domain-cells = <0>; 391 power-domains = <&cluster_pd0>; 392 domain-idle-states = <&cluster_c4>; 393 }; 394 395 cpu_pd4: power-domain-cpu4 { 396 #power-domain-cells = <0>; 397 power-domains = <&cluster_pd1>; 398 domain-idle-states = <&cluster_c4>; 399 }; 400 401 cpu_pd5: power-domain-cpu5 { 402 #power-domain-cells = <0>; 403 power-domains = <&cluster_pd1>; 404 domain-idle-states = <&cluster_c4>; 405 }; 406 407 cpu_pd6: power-domain-cpu6 { 408 #power-domain-cells = <0>; 409 power-domains = <&cluster_pd1>; 410 domain-idle-states = <&cluster_c4>; 411 }; 412 413 cpu_pd7: power-domain-cpu7 { 414 #power-domain-cells = <0>; 415 power-domains = <&cluster_pd1>; 416 domain-idle-states = <&cluster_c4>; 417 }; 418 419 cpu_pd8: power-domain-cpu8 { 420 #power-domain-cells = <0>; 421 power-domains = <&cluster_pd2>; 422 domain-idle-states = <&cluster_c4>; 423 }; 424 425 cpu_pd9: power-domain-cpu9 { 426 #power-domain-cells = <0>; 427 power-domains = <&cluster_pd2>; 428 domain-idle-states = <&cluster_c4>; 429 }; 430 431 cpu_pd10: power-domain-cpu10 { 432 #power-domain-cells = <0>; 433 power-domains = <&cluster_pd2>; 434 domain-idle-states = <&cluster_c4>; 435 }; 436 437 cpu_pd11: power-domain-cpu11 { 438 #power-domain-cells = <0>; 439 power-domains = <&cluster_pd2>; 440 domain-idle-states = <&cluster_c4>; 441 }; 442 443 cluster_pd0: power-domain-cpu-cluster0 { 444 #power-domain-cells = <0>; 445 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 446 power-domains = <&system_pd>; 447 }; 448 449 cluster_pd1: power-domain-cpu-cluster1 { 450 #power-domain-cells = <0>; 451 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 452 power-domains = <&system_pd>; 453 }; 454 455 cluster_pd2: power-domain-cpu-cluster2 { 456 #power-domain-cells = <0>; 457 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 458 power-domains = <&system_pd>; 459 }; 460 461 system_pd: power-domain-system { 462 #power-domain-cells = <0>; 463 /* TODO: system-wide idle states */ 464 }; 465 }; 466 467 reserved-memory { 468 #address-cells = <2>; 469 #size-cells = <2>; 470 ranges; 471 472 gunyah_hyp_mem: gunyah-hyp@80000000 { 473 reg = <0x0 0x80000000 0x0 0x800000>; 474 no-map; 475 }; 476 477 hyp_elf_package_mem: hyp-elf-package@80800000 { 478 reg = <0x0 0x80800000 0x0 0x200000>; 479 no-map; 480 }; 481 482 ncc_mem: ncc@80a00000 { 483 reg = <0x0 0x80a00000 0x0 0x400000>; 484 no-map; 485 }; 486 487 cpucp_log_mem: cpucp-log@80e00000 { 488 reg = <0x0 0x80e00000 0x0 0x40000>; 489 no-map; 490 }; 491 492 cpucp_mem: cpucp@80e40000 { 493 reg = <0x0 0x80e40000 0x0 0x540000>; 494 no-map; 495 }; 496 497 reserved-region@81380000 { 498 reg = <0x0 0x81380000 0x0 0x80000>; 499 no-map; 500 }; 501 502 tags_mem: tags-region@81400000 { 503 reg = <0x0 0x81400000 0x0 0x1a0000>; 504 no-map; 505 }; 506 507 xbl_dtlog_mem: xbl-dtlog@81a00000 { 508 reg = <0x0 0x81a00000 0x0 0x40000>; 509 no-map; 510 }; 511 512 xbl_ramdump_mem: xbl-ramdump@81a40000 { 513 reg = <0x0 0x81a40000 0x0 0x1c0000>; 514 no-map; 515 }; 516 517 aop_image_mem: aop-image@81c00000 { 518 reg = <0x0 0x81c00000 0x0 0x60000>; 519 no-map; 520 }; 521 522 aop_cmd_db_mem: aop-cmd-db@81c60000 { 523 compatible = "qcom,cmd-db"; 524 reg = <0x0 0x81c60000 0x0 0x20000>; 525 no-map; 526 }; 527 528 aop_config_mem: aop-config@81c80000 { 529 reg = <0x0 0x81c80000 0x0 0x20000>; 530 no-map; 531 }; 532 533 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 534 reg = <0x0 0x81ca0000 0x0 0x40000>; 535 no-map; 536 }; 537 538 tme_log_mem: tme-log@81ce0000 { 539 reg = <0x0 0x81ce0000 0x0 0x4000>; 540 no-map; 541 }; 542 543 uefi_log_mem: uefi-log@81ce4000 { 544 reg = <0x0 0x81ce4000 0x0 0x10000>; 545 no-map; 546 }; 547 548 secdata_apss_mem: secdata-apss@81cff000 { 549 reg = <0x0 0x81cff000 0x0 0x1000>; 550 no-map; 551 }; 552 553 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 554 reg = <0x0 0x81e00000 0x0 0x100000>; 555 no-map; 556 }; 557 558 gpu_prr_mem: gpu-prr@81f00000 { 559 reg = <0x0 0x81f00000 0x0 0x10000>; 560 no-map; 561 }; 562 563 tpm_control_mem: tpm-control@81f10000 { 564 reg = <0x0 0x81f10000 0x0 0x10000>; 565 no-map; 566 }; 567 568 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 569 reg = <0x0 0x81f20000 0x0 0x10000>; 570 no-map; 571 }; 572 573 pld_pep_mem: pld-pep@81f30000 { 574 reg = <0x0 0x81f30000 0x0 0x6000>; 575 no-map; 576 }; 577 578 pld_gmu_mem: pld-gmu@81f36000 { 579 reg = <0x0 0x81f36000 0x0 0x1000>; 580 no-map; 581 }; 582 583 pld_pdp_mem: pld-pdp@81f37000 { 584 reg = <0x0 0x81f37000 0x0 0x1000>; 585 no-map; 586 }; 587 588 tz_stat_mem: tz-stat@82700000 { 589 reg = <0x0 0x82700000 0x0 0x100000>; 590 no-map; 591 }; 592 593 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 594 reg = <0x0 0x82800000 0x0 0xc00000>; 595 no-map; 596 }; 597 598 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 599 reg = <0x0 0x84b00000 0x0 0x800000>; 600 no-map; 601 }; 602 603 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 604 reg = <0x0 0x85300000 0x0 0x80000>; 605 no-map; 606 }; 607 608 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 609 reg = <0x0 0x866c0000 0x0 0x40000>; 610 no-map; 611 }; 612 613 spss_region_mem: spss-region@86700000 { 614 reg = <0x0 0x86700000 0x0 0x400000>; 615 no-map; 616 }; 617 618 adsp_boot_mem: adsp-boot@86b00000 { 619 reg = <0x0 0x86b00000 0x0 0xc00000>; 620 no-map; 621 }; 622 623 video_mem: video@87700000 { 624 reg = <0x0 0x87700000 0x0 0x700000>; 625 no-map; 626 }; 627 628 adspslpi_mem: adspslpi@87e00000 { 629 reg = <0x0 0x87e00000 0x0 0x3a00000>; 630 no-map; 631 }; 632 633 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 634 reg = <0x0 0x8b800000 0x0 0x80000>; 635 no-map; 636 }; 637 638 cdsp_mem: cdsp@8b900000 { 639 reg = <0x0 0x8b900000 0x0 0x2000000>; 640 no-map; 641 }; 642 643 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 644 reg = <0x0 0x8d900000 0x0 0x80000>; 645 no-map; 646 }; 647 648 gpu_microcode_mem: gpu-microcode@8d9fe000 { 649 reg = <0x0 0x8d9fe000 0x0 0x2000>; 650 no-map; 651 }; 652 653 cvp_mem: cvp@8da00000 { 654 reg = <0x0 0x8da00000 0x0 0x700000>; 655 no-map; 656 }; 657 658 camera_mem: camera@8e100000 { 659 reg = <0x0 0x8e100000 0x0 0x800000>; 660 no-map; 661 }; 662 663 av1_encoder_mem: av1-encoder@8e900000 { 664 reg = <0x0 0x8e900000 0x0 0x700000>; 665 no-map; 666 }; 667 668 reserved-region@8f000000 { 669 reg = <0x0 0x8f000000 0x0 0xa00000>; 670 no-map; 671 }; 672 673 wpss_mem: wpss@8fa00000 { 674 reg = <0x0 0x8fa00000 0x0 0x1900000>; 675 no-map; 676 }; 677 678 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 679 reg = <0x0 0x91300000 0x0 0x80000>; 680 no-map; 681 }; 682 683 xbl_sc_mem: xbl-sc@d8000000 { 684 reg = <0x0 0xd8000000 0x0 0x40000>; 685 no-map; 686 }; 687 688 reserved-region@d8040000 { 689 reg = <0x0 0xd8040000 0x0 0xa0000>; 690 no-map; 691 }; 692 693 qtee_mem: qtee@d80e0000 { 694 reg = <0x0 0xd80e0000 0x0 0x520000>; 695 no-map; 696 }; 697 698 ta_mem: ta@d8600000 { 699 reg = <0x0 0xd8600000 0x0 0x8a00000>; 700 no-map; 701 }; 702 703 tags_mem1: tags@e1000000 { 704 reg = <0x0 0xe1000000 0x0 0x26a0000>; 705 no-map; 706 }; 707 708 llcc_lpi_mem: llcc-lpi@ff800000 { 709 reg = <0x0 0xff800000 0x0 0x600000>; 710 no-map; 711 }; 712 713 smem_mem: smem@ffe00000 { 714 compatible = "qcom,smem"; 715 reg = <0x0 0xffe00000 0x0 0x200000>; 716 hwlocks = <&tcsr_mutex 3>; 717 no-map; 718 }; 719 }; 720 721 qup_opp_table_100mhz: opp-table-qup100mhz { 722 compatible = "operating-points-v2"; 723 724 opp-75000000 { 725 opp-hz = /bits/ 64 <75000000>; 726 required-opps = <&rpmhpd_opp_low_svs>; 727 }; 728 729 opp-100000000 { 730 opp-hz = /bits/ 64 <100000000>; 731 required-opps = <&rpmhpd_opp_svs>; 732 }; 733 }; 734 735 qup_opp_table_120mhz: opp-table-qup120mhz { 736 compatible = "operating-points-v2"; 737 738 opp-75000000 { 739 opp-hz = /bits/ 64 <75000000>; 740 required-opps = <&rpmhpd_opp_low_svs>; 741 }; 742 743 opp-120000000 { 744 opp-hz = /bits/ 64 <120000000>; 745 required-opps = <&rpmhpd_opp_svs>; 746 }; 747 }; 748 749 smp2p-adsp { 750 compatible = "qcom,smp2p"; 751 752 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 753 IPCC_MPROC_SIGNAL_SMP2P 754 IRQ_TYPE_EDGE_RISING>; 755 756 mboxes = <&ipcc IPCC_CLIENT_LPASS 757 IPCC_MPROC_SIGNAL_SMP2P>; 758 759 qcom,smem = <443>, <429>; 760 qcom,local-pid = <0>; 761 qcom,remote-pid = <2>; 762 763 smp2p_adsp_out: master-kernel { 764 qcom,entry-name = "master-kernel"; 765 #qcom,smem-state-cells = <1>; 766 }; 767 768 smp2p_adsp_in: slave-kernel { 769 qcom,entry-name = "slave-kernel"; 770 interrupt-controller; 771 #interrupt-cells = <2>; 772 }; 773 }; 774 775 smp2p-cdsp { 776 compatible = "qcom,smp2p"; 777 778 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 779 IPCC_MPROC_SIGNAL_SMP2P 780 IRQ_TYPE_EDGE_RISING>; 781 782 mboxes = <&ipcc IPCC_CLIENT_CDSP 783 IPCC_MPROC_SIGNAL_SMP2P>; 784 785 qcom,smem = <94>, <432>; 786 qcom,local-pid = <0>; 787 qcom,remote-pid = <5>; 788 789 smp2p_cdsp_out: master-kernel { 790 qcom,entry-name = "master-kernel"; 791 #qcom,smem-state-cells = <1>; 792 }; 793 794 smp2p_cdsp_in: slave-kernel { 795 qcom,entry-name = "slave-kernel"; 796 interrupt-controller; 797 #interrupt-cells = <2>; 798 }; 799 }; 800 801 soc: soc@0 { 802 compatible = "simple-bus"; 803 804 #address-cells = <2>; 805 #size-cells = <2>; 806 dma-ranges = <0 0 0 0 0x100 0>; 807 ranges = <0 0 0 0 0x100 0>; 808 809 gcc: clock-controller@100000 { 810 compatible = "qcom,x1e80100-gcc"; 811 reg = <0 0x00100000 0 0x200000>; 812 813 clocks = <&bi_tcxo_div2>, 814 <&sleep_clk>, 815 <&pcie3_phy>, 816 <&pcie4_phy>, 817 <&pcie5_phy>, 818 <&pcie6a_phy>, 819 <0>, 820 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 821 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 822 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 823 <0>, 824 <0>, 825 <0>, 826 <0>, 827 <0>, 828 <0>, 829 <0>, 830 <0>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <0>, 836 <0>, 837 <0>, 838 <0>, 839 <0>, 840 <0>, 841 <0>, 842 <0>, 843 <0>, 844 <0>, 845 <0>, 846 <0>, 847 <0>, 848 <0>, 849 <0>, 850 <&ufs_mem_phy 0>, 851 <&ufs_mem_phy 1>, 852 <&ufs_mem_phy 2>; 853 854 power-domains = <&rpmhpd RPMHPD_CX>; 855 #clock-cells = <1>; 856 #reset-cells = <1>; 857 #power-domain-cells = <1>; 858 }; 859 860 ipcc: mailbox@408000 { 861 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 862 reg = <0 0x00408000 0 0x1000>; 863 864 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 865 interrupt-controller; 866 #interrupt-cells = <3>; 867 868 #mbox-cells = <2>; 869 }; 870 871 gpi_dma2: dma-controller@800000 { 872 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 873 reg = <0 0x00800000 0 0x60000>; 874 875 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 887 888 dma-channels = <12>; 889 dma-channel-mask = <0x3e>; 890 #dma-cells = <3>; 891 892 iommus = <&apps_smmu 0x436 0x0>; 893 894 status = "disabled"; 895 }; 896 897 qupv3_2: geniqup@8c0000 { 898 compatible = "qcom,geni-se-qup"; 899 reg = <0 0x008c0000 0 0x2000>; 900 901 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 902 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 903 clock-names = "m-ahb", 904 "s-ahb"; 905 906 iommus = <&apps_smmu 0x423 0x0>; 907 908 #address-cells = <2>; 909 #size-cells = <2>; 910 ranges; 911 912 status = "disabled"; 913 914 i2c16: i2c@880000 { 915 compatible = "qcom,geni-i2c"; 916 reg = <0 0x00880000 0 0x4000>; 917 918 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 919 920 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 921 clock-names = "se"; 922 923 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 924 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 925 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 926 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 927 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 928 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 929 interconnect-names = "qup-core", 930 "qup-config", 931 "qup-memory"; 932 933 power-domains = <&rpmhpd RPMHPD_CX>; 934 required-opps = <&rpmhpd_opp_low_svs>; 935 936 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 937 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 938 dma-names = "tx", 939 "rx"; 940 941 pinctrl-0 = <&qup_i2c16_data_clk>; 942 pinctrl-names = "default"; 943 944 #address-cells = <1>; 945 #size-cells = <0>; 946 947 status = "disabled"; 948 }; 949 950 spi16: spi@880000 { 951 compatible = "qcom,geni-spi"; 952 reg = <0 0x00880000 0 0x4000>; 953 954 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 955 956 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 957 clock-names = "se"; 958 959 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 960 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 961 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 962 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 963 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 964 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 965 interconnect-names = "qup-core", 966 "qup-config", 967 "qup-memory"; 968 969 power-domains = <&rpmhpd RPMHPD_CX>; 970 operating-points-v2 = <&qup_opp_table_120mhz>; 971 972 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 973 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 974 dma-names = "tx", 975 "rx"; 976 977 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 978 pinctrl-names = "default"; 979 980 #address-cells = <1>; 981 #size-cells = <0>; 982 983 status = "disabled"; 984 }; 985 986 i2c17: i2c@884000 { 987 compatible = "qcom,geni-i2c"; 988 reg = <0 0x00884000 0 0x4000>; 989 990 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 991 992 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 993 clock-names = "se"; 994 995 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 996 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 997 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 998 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 999 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1000 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1001 interconnect-names = "qup-core", 1002 "qup-config", 1003 "qup-memory"; 1004 1005 power-domains = <&rpmhpd RPMHPD_CX>; 1006 required-opps = <&rpmhpd_opp_low_svs>; 1007 1008 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1009 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1010 dma-names = "tx", 1011 "rx"; 1012 1013 pinctrl-0 = <&qup_i2c17_data_clk>; 1014 pinctrl-names = "default"; 1015 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 1019 status = "disabled"; 1020 }; 1021 1022 spi17: spi@884000 { 1023 compatible = "qcom,geni-spi"; 1024 reg = <0 0x00884000 0 0x4000>; 1025 1026 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 1027 1028 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1029 clock-names = "se"; 1030 1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1032 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1033 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1034 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1035 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1036 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1037 interconnect-names = "qup-core", 1038 "qup-config", 1039 "qup-memory"; 1040 1041 power-domains = <&rpmhpd RPMHPD_CX>; 1042 operating-points-v2 = <&qup_opp_table_120mhz>; 1043 1044 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1045 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1046 dma-names = "tx", 1047 "rx"; 1048 1049 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 1050 pinctrl-names = "default"; 1051 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 1055 status = "disabled"; 1056 }; 1057 1058 i2c18: i2c@888000 { 1059 compatible = "qcom,geni-i2c"; 1060 reg = <0 0x00888000 0 0x4000>; 1061 1062 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1063 1064 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1065 clock-names = "se"; 1066 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1068 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1069 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1070 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1071 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1072 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1073 interconnect-names = "qup-core", 1074 "qup-config", 1075 "qup-memory"; 1076 1077 power-domains = <&rpmhpd RPMHPD_CX>; 1078 required-opps = <&rpmhpd_opp_low_svs>; 1079 1080 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1081 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1082 dma-names = "tx", 1083 "rx"; 1084 1085 pinctrl-0 = <&qup_i2c18_data_clk>; 1086 pinctrl-names = "default"; 1087 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 1091 status = "disabled"; 1092 }; 1093 1094 spi18: spi@888000 { 1095 compatible = "qcom,geni-spi"; 1096 reg = <0 0x00888000 0 0x4000>; 1097 1098 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1099 1100 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1101 clock-names = "se"; 1102 1103 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1104 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1105 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1106 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1107 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1108 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1109 interconnect-names = "qup-core", 1110 "qup-config", 1111 "qup-memory"; 1112 1113 power-domains = <&rpmhpd RPMHPD_CX>; 1114 operating-points-v2 = <&qup_opp_table_100mhz>; 1115 1116 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1117 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1118 dma-names = "tx", 1119 "rx"; 1120 1121 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1122 pinctrl-names = "default"; 1123 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 1127 status = "disabled"; 1128 }; 1129 1130 i2c19: i2c@88c000 { 1131 compatible = "qcom,geni-i2c"; 1132 reg = <0 0x0088c000 0 0x4000>; 1133 1134 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1135 1136 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1137 clock-names = "se"; 1138 1139 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1140 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1141 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1142 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1143 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1144 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1145 interconnect-names = "qup-core", 1146 "qup-config", 1147 "qup-memory"; 1148 1149 power-domains = <&rpmhpd RPMHPD_CX>; 1150 required-opps = <&rpmhpd_opp_low_svs>; 1151 1152 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1153 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1154 dma-names = "tx", 1155 "rx"; 1156 1157 pinctrl-0 = <&qup_i2c19_data_clk>; 1158 pinctrl-names = "default"; 1159 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 1163 status = "disabled"; 1164 }; 1165 1166 spi19: spi@88c000 { 1167 compatible = "qcom,geni-spi"; 1168 reg = <0 0x0088c000 0 0x4000>; 1169 1170 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1171 1172 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1173 clock-names = "se"; 1174 1175 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1176 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1177 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1178 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1179 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1180 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1181 interconnect-names = "qup-core", 1182 "qup-config", 1183 "qup-memory"; 1184 1185 power-domains = <&rpmhpd RPMHPD_CX>; 1186 operating-points-v2 = <&qup_opp_table_100mhz>; 1187 1188 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1189 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1190 dma-names = "tx", 1191 "rx"; 1192 1193 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1194 pinctrl-names = "default"; 1195 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 1199 status = "disabled"; 1200 }; 1201 1202 i2c20: i2c@890000 { 1203 compatible = "qcom,geni-i2c"; 1204 reg = <0 0x00890000 0 0x4000>; 1205 1206 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1207 1208 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1209 clock-names = "se"; 1210 1211 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1212 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1213 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1214 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1215 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1216 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1217 interconnect-names = "qup-core", 1218 "qup-config", 1219 "qup-memory"; 1220 1221 power-domains = <&rpmhpd RPMHPD_CX>; 1222 required-opps = <&rpmhpd_opp_low_svs>; 1223 1224 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1225 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1226 dma-names = "tx", 1227 "rx"; 1228 1229 pinctrl-0 = <&qup_i2c20_data_clk>; 1230 pinctrl-names = "default"; 1231 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 1235 status = "disabled"; 1236 }; 1237 1238 spi20: spi@890000 { 1239 compatible = "qcom,geni-spi"; 1240 reg = <0 0x00890000 0 0x4000>; 1241 1242 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1243 1244 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1245 clock-names = "se"; 1246 1247 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1248 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1249 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1250 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1251 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1252 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1253 interconnect-names = "qup-core", 1254 "qup-config", 1255 "qup-memory"; 1256 1257 power-domains = <&rpmhpd RPMHPD_CX>; 1258 operating-points-v2 = <&qup_opp_table_100mhz>; 1259 1260 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1261 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1262 dma-names = "tx", 1263 "rx"; 1264 1265 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1266 pinctrl-names = "default"; 1267 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 1271 status = "disabled"; 1272 }; 1273 1274 i2c21: i2c@894000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0 0x00894000 0 0x4000>; 1277 1278 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1279 1280 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1281 clock-names = "se"; 1282 1283 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1284 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1285 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1286 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1287 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1288 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1289 interconnect-names = "qup-core", 1290 "qup-config", 1291 "qup-memory"; 1292 1293 power-domains = <&rpmhpd RPMHPD_CX>; 1294 required-opps = <&rpmhpd_opp_low_svs>; 1295 1296 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1297 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1298 dma-names = "tx", 1299 "rx"; 1300 1301 pinctrl-0 = <&qup_i2c21_data_clk>; 1302 pinctrl-names = "default"; 1303 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 1307 status = "disabled"; 1308 }; 1309 1310 spi21: spi@894000 { 1311 compatible = "qcom,geni-spi"; 1312 reg = <0 0x00894000 0 0x4000>; 1313 1314 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1315 1316 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1317 clock-names = "se"; 1318 1319 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1320 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1321 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1322 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1323 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1324 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1325 interconnect-names = "qup-core", 1326 "qup-config", 1327 "qup-memory"; 1328 1329 power-domains = <&rpmhpd RPMHPD_CX>; 1330 operating-points-v2 = <&qup_opp_table_100mhz>; 1331 1332 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1333 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1334 dma-names = "tx", 1335 "rx"; 1336 1337 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1338 pinctrl-names = "default"; 1339 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 1343 status = "disabled"; 1344 }; 1345 1346 uart21: serial@894000 { 1347 compatible = "qcom,geni-uart"; 1348 reg = <0 0x00894000 0 0x4000>; 1349 1350 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1351 1352 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1353 clock-names = "se"; 1354 1355 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1356 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1357 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1358 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1359 interconnect-names = "qup-core", 1360 "qup-config"; 1361 1362 power-domains = <&rpmhpd RPMHPD_CX>; 1363 operating-points-v2 = <&qup_opp_table_100mhz>; 1364 1365 pinctrl-0 = <&qup_uart21_default>; 1366 pinctrl-names = "default"; 1367 1368 status = "disabled"; 1369 }; 1370 1371 i2c22: i2c@898000 { 1372 compatible = "qcom,geni-i2c"; 1373 reg = <0 0x00898000 0 0x4000>; 1374 1375 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1376 1377 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1378 clock-names = "se"; 1379 1380 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1381 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1382 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1383 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1384 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1385 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1386 interconnect-names = "qup-core", 1387 "qup-config", 1388 "qup-memory"; 1389 1390 power-domains = <&rpmhpd RPMHPD_CX>; 1391 required-opps = <&rpmhpd_opp_low_svs>; 1392 1393 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1394 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1395 dma-names = "tx", 1396 "rx"; 1397 1398 pinctrl-0 = <&qup_i2c22_data_clk>; 1399 pinctrl-names = "default"; 1400 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 1404 status = "disabled"; 1405 }; 1406 1407 spi22: spi@898000 { 1408 compatible = "qcom,geni-spi"; 1409 reg = <0 0x00898000 0 0x4000>; 1410 1411 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1412 1413 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1414 clock-names = "se"; 1415 1416 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1417 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1418 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1419 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1420 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1421 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1422 interconnect-names = "qup-core", 1423 "qup-config", 1424 "qup-memory"; 1425 1426 power-domains = <&rpmhpd RPMHPD_CX>; 1427 operating-points-v2 = <&qup_opp_table_100mhz>; 1428 1429 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1430 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1431 dma-names = "tx", 1432 "rx"; 1433 1434 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1435 pinctrl-names = "default"; 1436 1437 #address-cells = <1>; 1438 #size-cells = <0>; 1439 1440 status = "disabled"; 1441 }; 1442 1443 i2c23: i2c@89c000 { 1444 compatible = "qcom,geni-i2c"; 1445 reg = <0 0x0089c000 0 0x4000>; 1446 1447 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1448 1449 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1450 clock-names = "se"; 1451 1452 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1453 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1454 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1455 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1456 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1457 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1458 interconnect-names = "qup-core", 1459 "qup-config", 1460 "qup-memory"; 1461 1462 power-domains = <&rpmhpd RPMHPD_CX>; 1463 required-opps = <&rpmhpd_opp_low_svs>; 1464 1465 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1466 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1467 dma-names = "tx", 1468 "rx"; 1469 1470 pinctrl-0 = <&qup_i2c23_data_clk>; 1471 pinctrl-names = "default"; 1472 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 1476 status = "disabled"; 1477 }; 1478 1479 spi23: spi@89c000 { 1480 compatible = "qcom,geni-spi"; 1481 reg = <0 0x0089c000 0 0x4000>; 1482 1483 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1484 1485 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1486 clock-names = "se"; 1487 1488 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1489 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1490 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1491 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1492 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1493 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1494 interconnect-names = "qup-core", 1495 "qup-config", 1496 "qup-memory"; 1497 1498 power-domains = <&rpmhpd RPMHPD_CX>; 1499 operating-points-v2 = <&qup_opp_table_100mhz>; 1500 1501 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1502 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1503 dma-names = "tx", 1504 "rx"; 1505 1506 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1507 pinctrl-names = "default"; 1508 1509 #address-cells = <1>; 1510 #size-cells = <0>; 1511 1512 status = "disabled"; 1513 }; 1514 }; 1515 1516 gpi_dma1: dma-controller@a00000 { 1517 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1518 reg = <0 0x00a00000 0 0x60000>; 1519 1520 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1532 1533 dma-channels = <12>; 1534 dma-channel-mask = <0x3e>; 1535 #dma-cells = <3>; 1536 1537 iommus = <&apps_smmu 0x136 0x0>; 1538 1539 status = "disabled"; 1540 }; 1541 1542 qupv3_1: geniqup@ac0000 { 1543 compatible = "qcom,geni-se-qup"; 1544 reg = <0 0x00ac0000 0 0x2000>; 1545 1546 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1547 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1548 clock-names = "m-ahb", 1549 "s-ahb"; 1550 1551 iommus = <&apps_smmu 0x123 0x0>; 1552 1553 #address-cells = <2>; 1554 #size-cells = <2>; 1555 ranges; 1556 1557 status = "disabled"; 1558 1559 i2c8: i2c@a80000 { 1560 compatible = "qcom,geni-i2c"; 1561 reg = <0 0x00a80000 0 0x4000>; 1562 1563 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1564 1565 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1566 clock-names = "se"; 1567 1568 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1569 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1570 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1571 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1572 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1573 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1574 interconnect-names = "qup-core", 1575 "qup-config", 1576 "qup-memory"; 1577 1578 power-domains = <&rpmhpd RPMHPD_CX>; 1579 required-opps = <&rpmhpd_opp_low_svs>; 1580 1581 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1582 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1583 dma-names = "tx", 1584 "rx"; 1585 1586 pinctrl-0 = <&qup_i2c8_data_clk>; 1587 pinctrl-names = "default"; 1588 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 1592 status = "disabled"; 1593 }; 1594 1595 spi8: spi@a80000 { 1596 compatible = "qcom,geni-spi"; 1597 reg = <0 0x00a80000 0 0x4000>; 1598 1599 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1600 1601 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1602 clock-names = "se"; 1603 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1605 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1606 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1607 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1608 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1609 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1610 interconnect-names = "qup-core", 1611 "qup-config", 1612 "qup-memory"; 1613 1614 power-domains = <&rpmhpd RPMHPD_CX>; 1615 operating-points-v2 = <&qup_opp_table_120mhz>; 1616 1617 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1618 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1619 dma-names = "tx", 1620 "rx"; 1621 1622 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1623 pinctrl-names = "default"; 1624 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 1628 status = "disabled"; 1629 }; 1630 1631 i2c9: i2c@a84000 { 1632 compatible = "qcom,geni-i2c"; 1633 reg = <0 0x00a84000 0 0x4000>; 1634 1635 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1636 1637 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1638 clock-names = "se"; 1639 1640 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1641 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1642 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1643 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1644 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1645 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1646 interconnect-names = "qup-core", 1647 "qup-config", 1648 "qup-memory"; 1649 1650 power-domains = <&rpmhpd RPMHPD_CX>; 1651 required-opps = <&rpmhpd_opp_low_svs>; 1652 1653 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1654 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1655 dma-names = "tx", 1656 "rx"; 1657 1658 pinctrl-0 = <&qup_i2c9_data_clk>; 1659 pinctrl-names = "default"; 1660 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 1664 status = "disabled"; 1665 }; 1666 1667 spi9: spi@a84000 { 1668 compatible = "qcom,geni-spi"; 1669 reg = <0 0x00a84000 0 0x4000>; 1670 1671 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1672 1673 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1674 clock-names = "se"; 1675 1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1677 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1678 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1679 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1680 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1681 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1682 interconnect-names = "qup-core", 1683 "qup-config", 1684 "qup-memory"; 1685 1686 power-domains = <&rpmhpd RPMHPD_CX>; 1687 operating-points-v2 = <&qup_opp_table_120mhz>; 1688 1689 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1690 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1691 dma-names = "tx", 1692 "rx"; 1693 1694 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1695 pinctrl-names = "default"; 1696 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 1700 status = "disabled"; 1701 }; 1702 1703 i2c10: i2c@a88000 { 1704 compatible = "qcom,geni-i2c"; 1705 reg = <0 0x00a88000 0 0x4000>; 1706 1707 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1708 1709 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1710 clock-names = "se"; 1711 1712 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1713 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1714 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1715 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1716 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1717 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1718 interconnect-names = "qup-core", 1719 "qup-config", 1720 "qup-memory"; 1721 1722 power-domains = <&rpmhpd RPMHPD_CX>; 1723 required-opps = <&rpmhpd_opp_low_svs>; 1724 1725 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1726 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1727 dma-names = "tx", 1728 "rx"; 1729 1730 pinctrl-0 = <&qup_i2c10_data_clk>; 1731 pinctrl-names = "default"; 1732 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 status = "disabled"; 1737 }; 1738 1739 spi10: spi@a88000 { 1740 compatible = "qcom,geni-spi"; 1741 reg = <0 0x00a88000 0 0x4000>; 1742 1743 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1744 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1746 clock-names = "se"; 1747 1748 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1749 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1750 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1751 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1752 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1753 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1754 interconnect-names = "qup-core", 1755 "qup-config", 1756 "qup-memory"; 1757 1758 power-domains = <&rpmhpd RPMHPD_CX>; 1759 operating-points-v2 = <&qup_opp_table_100mhz>; 1760 1761 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1762 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1763 dma-names = "tx", 1764 "rx"; 1765 1766 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1767 pinctrl-names = "default"; 1768 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 1772 status = "disabled"; 1773 }; 1774 1775 i2c11: i2c@a8c000 { 1776 compatible = "qcom,geni-i2c"; 1777 reg = <0 0x00a8c000 0 0x4000>; 1778 1779 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1780 1781 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1782 clock-names = "se"; 1783 1784 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1785 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1786 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1787 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1788 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1789 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1790 interconnect-names = "qup-core", 1791 "qup-config", 1792 "qup-memory"; 1793 1794 power-domains = <&rpmhpd RPMHPD_CX>; 1795 required-opps = <&rpmhpd_opp_low_svs>; 1796 1797 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1798 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1799 dma-names = "tx", 1800 "rx"; 1801 1802 pinctrl-0 = <&qup_i2c11_data_clk>; 1803 pinctrl-names = "default"; 1804 1805 #address-cells = <1>; 1806 #size-cells = <0>; 1807 1808 status = "disabled"; 1809 }; 1810 1811 spi11: spi@a8c000 { 1812 compatible = "qcom,geni-spi"; 1813 reg = <0 0x00a8c000 0 0x4000>; 1814 1815 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1816 1817 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1818 clock-names = "se"; 1819 1820 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1821 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1822 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1823 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1824 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1825 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1826 interconnect-names = "qup-core", 1827 "qup-config", 1828 "qup-memory"; 1829 1830 power-domains = <&rpmhpd RPMHPD_CX>; 1831 operating-points-v2 = <&qup_opp_table_100mhz>; 1832 1833 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1834 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1835 dma-names = "tx", 1836 "rx"; 1837 1838 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1839 pinctrl-names = "default"; 1840 1841 #address-cells = <1>; 1842 #size-cells = <0>; 1843 1844 status = "disabled"; 1845 }; 1846 1847 i2c12: i2c@a90000 { 1848 compatible = "qcom,geni-i2c"; 1849 reg = <0 0x00a90000 0 0x4000>; 1850 1851 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1852 1853 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1854 clock-names = "se"; 1855 1856 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1857 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1858 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1859 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1860 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1861 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1862 interconnect-names = "qup-core", 1863 "qup-config", 1864 "qup-memory"; 1865 1866 power-domains = <&rpmhpd RPMHPD_CX>; 1867 required-opps = <&rpmhpd_opp_low_svs>; 1868 1869 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1870 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1871 dma-names = "tx", 1872 "rx"; 1873 1874 pinctrl-0 = <&qup_i2c12_data_clk>; 1875 pinctrl-names = "default"; 1876 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 1880 status = "disabled"; 1881 }; 1882 1883 spi12: spi@a90000 { 1884 compatible = "qcom,geni-spi"; 1885 reg = <0 0x00a90000 0 0x4000>; 1886 1887 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1888 1889 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1890 clock-names = "se"; 1891 1892 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1893 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1894 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1895 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1896 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1897 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1898 interconnect-names = "qup-core", 1899 "qup-config", 1900 "qup-memory"; 1901 1902 power-domains = <&rpmhpd RPMHPD_CX>; 1903 operating-points-v2 = <&qup_opp_table_100mhz>; 1904 1905 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1906 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1907 dma-names = "tx", 1908 "rx"; 1909 1910 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1911 pinctrl-names = "default"; 1912 1913 #address-cells = <1>; 1914 #size-cells = <0>; 1915 1916 status = "disabled"; 1917 }; 1918 1919 i2c13: i2c@a94000 { 1920 compatible = "qcom,geni-i2c"; 1921 reg = <0 0x00a94000 0 0x4000>; 1922 1923 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1924 1925 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1926 clock-names = "se"; 1927 1928 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1929 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1930 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1931 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1932 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1933 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1934 interconnect-names = "qup-core", 1935 "qup-config", 1936 "qup-memory"; 1937 1938 power-domains = <&rpmhpd RPMHPD_CX>; 1939 required-opps = <&rpmhpd_opp_low_svs>; 1940 1941 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1942 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1943 dma-names = "tx", 1944 "rx"; 1945 1946 pinctrl-0 = <&qup_i2c13_data_clk>; 1947 pinctrl-names = "default"; 1948 1949 #address-cells = <1>; 1950 #size-cells = <0>; 1951 1952 status = "disabled"; 1953 }; 1954 1955 spi13: spi@a94000 { 1956 compatible = "qcom,geni-spi"; 1957 reg = <0 0x00a94000 0 0x4000>; 1958 1959 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1960 1961 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1962 clock-names = "se"; 1963 1964 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1965 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1966 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1967 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1968 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1969 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1970 interconnect-names = "qup-core", 1971 "qup-config", 1972 "qup-memory"; 1973 1974 power-domains = <&rpmhpd RPMHPD_CX>; 1975 operating-points-v2 = <&qup_opp_table_100mhz>; 1976 1977 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1978 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1979 dma-names = "tx", 1980 "rx"; 1981 1982 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1983 pinctrl-names = "default"; 1984 1985 #address-cells = <1>; 1986 #size-cells = <0>; 1987 1988 status = "disabled"; 1989 }; 1990 1991 i2c14: i2c@a98000 { 1992 compatible = "qcom,geni-i2c"; 1993 reg = <0 0x00a98000 0 0x4000>; 1994 1995 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1996 1997 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1998 clock-names = "se"; 1999 2000 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2001 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2002 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2003 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2004 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2006 interconnect-names = "qup-core", 2007 "qup-config", 2008 "qup-memory"; 2009 2010 power-domains = <&rpmhpd RPMHPD_CX>; 2011 required-opps = <&rpmhpd_opp_low_svs>; 2012 2013 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2014 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2015 dma-names = "tx", 2016 "rx"; 2017 2018 pinctrl-0 = <&qup_i2c14_data_clk>; 2019 pinctrl-names = "default"; 2020 2021 #address-cells = <1>; 2022 #size-cells = <0>; 2023 2024 status = "disabled"; 2025 }; 2026 2027 spi14: spi@a98000 { 2028 compatible = "qcom,geni-spi"; 2029 reg = <0 0x00a98000 0 0x4000>; 2030 2031 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 2032 2033 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2034 clock-names = "se"; 2035 2036 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2037 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2038 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2039 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2040 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2041 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2042 interconnect-names = "qup-core", 2043 "qup-config", 2044 "qup-memory"; 2045 2046 power-domains = <&rpmhpd RPMHPD_CX>; 2047 operating-points-v2 = <&qup_opp_table_100mhz>; 2048 2049 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2050 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2051 dma-names = "tx", 2052 "rx"; 2053 2054 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2055 pinctrl-names = "default"; 2056 2057 #address-cells = <1>; 2058 #size-cells = <0>; 2059 2060 status = "disabled"; 2061 }; 2062 2063 uart14: serial@a98000 { 2064 compatible = "qcom,geni-uart"; 2065 reg = <0 0x00a98000 0 0x4000>; 2066 2067 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 2068 2069 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2070 clock-names = "se"; 2071 2072 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2073 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2074 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2075 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2076 interconnect-names = "qup-core", 2077 "qup-config"; 2078 2079 power-domains = <&rpmhpd RPMHPD_CX>; 2080 operating-points-v2 = <&qup_opp_table_100mhz>; 2081 2082 pinctrl-0 = <&qup_uart14_default>; 2083 pinctrl-names = "default"; 2084 2085 status = "disabled"; 2086 }; 2087 2088 i2c15: i2c@a9c000 { 2089 compatible = "qcom,geni-i2c"; 2090 reg = <0 0x00a9c000 0 0x4000>; 2091 2092 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2093 2094 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2095 clock-names = "se"; 2096 2097 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2098 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2099 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2100 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2101 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2102 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2103 interconnect-names = "qup-core", 2104 "qup-config", 2105 "qup-memory"; 2106 2107 power-domains = <&rpmhpd RPMHPD_CX>; 2108 required-opps = <&rpmhpd_opp_low_svs>; 2109 2110 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2111 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2112 dma-names = "tx", 2113 "rx"; 2114 2115 pinctrl-0 = <&qup_i2c15_data_clk>; 2116 pinctrl-names = "default"; 2117 2118 #address-cells = <1>; 2119 #size-cells = <0>; 2120 2121 status = "disabled"; 2122 }; 2123 2124 spi15: spi@a9c000 { 2125 compatible = "qcom,geni-spi"; 2126 reg = <0 0x00a9c000 0 0x4000>; 2127 2128 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2129 2130 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2131 clock-names = "se"; 2132 2133 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2134 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2135 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2136 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2137 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2138 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2139 interconnect-names = "qup-core", 2140 "qup-config", 2141 "qup-memory"; 2142 2143 power-domains = <&rpmhpd RPMHPD_CX>; 2144 operating-points-v2 = <&qup_opp_table_100mhz>; 2145 2146 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2147 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2148 dma-names = "tx", 2149 "rx"; 2150 2151 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2152 pinctrl-names = "default"; 2153 2154 #address-cells = <1>; 2155 #size-cells = <0>; 2156 2157 status = "disabled"; 2158 }; 2159 }; 2160 2161 gpi_dma0: dma-controller@b00000 { 2162 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 2163 reg = <0 0x00b00000 0 0x60000>; 2164 2165 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 2177 2178 dma-channels = <12>; 2179 dma-channel-mask = <0x3e>; 2180 #dma-cells = <3>; 2181 2182 iommus = <&apps_smmu 0x456 0x0>; 2183 2184 status = "disabled"; 2185 }; 2186 2187 qupv3_0: geniqup@bc0000 { 2188 compatible = "qcom,geni-se-qup"; 2189 reg = <0 0x00bc0000 0 0x2000>; 2190 2191 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 2192 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 2193 clock-names = "m-ahb", 2194 "s-ahb"; 2195 2196 iommus = <&apps_smmu 0x443 0x0>; 2197 #address-cells = <2>; 2198 #size-cells = <2>; 2199 ranges; 2200 2201 status = "disabled"; 2202 2203 i2c0: i2c@b80000 { 2204 compatible = "qcom,geni-i2c"; 2205 reg = <0 0x00b80000 0 0x4000>; 2206 2207 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2208 2209 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2210 clock-names = "se"; 2211 2212 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2213 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2214 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2215 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2216 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2217 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2218 interconnect-names = "qup-core", 2219 "qup-config", 2220 "qup-memory"; 2221 2222 power-domains = <&rpmhpd RPMHPD_CX>; 2223 required-opps = <&rpmhpd_opp_low_svs>; 2224 2225 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2226 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2227 dma-names = "tx", 2228 "rx"; 2229 2230 pinctrl-0 = <&qup_i2c0_data_clk>; 2231 pinctrl-names = "default"; 2232 2233 #address-cells = <1>; 2234 #size-cells = <0>; 2235 2236 status = "disabled"; 2237 }; 2238 2239 spi0: spi@b80000 { 2240 compatible = "qcom,geni-spi"; 2241 reg = <0 0x00b80000 0 0x4000>; 2242 2243 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2244 2245 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2246 clock-names = "se"; 2247 2248 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2249 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2250 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2251 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2252 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2253 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2254 interconnect-names = "qup-core", 2255 "qup-config", 2256 "qup-memory"; 2257 2258 power-domains = <&rpmhpd RPMHPD_CX>; 2259 operating-points-v2 = <&qup_opp_table_120mhz>; 2260 2261 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2262 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2263 dma-names = "tx", 2264 "rx"; 2265 2266 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2267 pinctrl-names = "default"; 2268 2269 #address-cells = <1>; 2270 #size-cells = <0>; 2271 2272 status = "disabled"; 2273 }; 2274 2275 i2c1: i2c@b84000 { 2276 compatible = "qcom,geni-i2c"; 2277 reg = <0 0x00b84000 0 0x4000>; 2278 2279 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2280 2281 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2282 clock-names = "se"; 2283 2284 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2285 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2286 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2287 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2288 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2289 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2290 interconnect-names = "qup-core", 2291 "qup-config", 2292 "qup-memory"; 2293 2294 power-domains = <&rpmhpd RPMHPD_CX>; 2295 required-opps = <&rpmhpd_opp_low_svs>; 2296 2297 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2298 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2299 dma-names = "tx", 2300 "rx"; 2301 2302 pinctrl-0 = <&qup_i2c1_data_clk>; 2303 pinctrl-names = "default"; 2304 2305 #address-cells = <1>; 2306 #size-cells = <0>; 2307 2308 status = "disabled"; 2309 }; 2310 2311 spi1: spi@b84000 { 2312 compatible = "qcom,geni-spi"; 2313 reg = <0 0x00b84000 0 0x4000>; 2314 2315 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2316 2317 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2318 clock-names = "se"; 2319 2320 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2321 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2322 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2323 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2324 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2325 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2326 interconnect-names = "qup-core", 2327 "qup-config", 2328 "qup-memory"; 2329 2330 power-domains = <&rpmhpd RPMHPD_CX>; 2331 operating-points-v2 = <&qup_opp_table_120mhz>; 2332 2333 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2334 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2335 dma-names = "tx", 2336 "rx"; 2337 2338 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2339 pinctrl-names = "default"; 2340 2341 #address-cells = <1>; 2342 #size-cells = <0>; 2343 2344 status = "disabled"; 2345 }; 2346 2347 i2c2: i2c@b88000 { 2348 compatible = "qcom,geni-i2c"; 2349 reg = <0 0x00b88000 0 0x4000>; 2350 2351 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2352 2353 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2354 clock-names = "se"; 2355 2356 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2357 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2358 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2359 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2360 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2361 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2362 interconnect-names = "qup-core", 2363 "qup-config", 2364 "qup-memory"; 2365 2366 power-domains = <&rpmhpd RPMHPD_CX>; 2367 required-opps = <&rpmhpd_opp_low_svs>; 2368 2369 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2370 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2371 dma-names = "tx", 2372 "rx"; 2373 2374 pinctrl-0 = <&qup_i2c2_data_clk>; 2375 pinctrl-names = "default"; 2376 2377 #address-cells = <1>; 2378 #size-cells = <0>; 2379 2380 status = "disabled"; 2381 }; 2382 2383 uart2: serial@b88000 { 2384 compatible = "qcom,geni-uart"; 2385 reg = <0 0x00b88000 0 0x4000>; 2386 2387 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2388 2389 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2390 clock-names = "se"; 2391 2392 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2393 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2394 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2395 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2396 interconnect-names = "qup-core", 2397 "qup-config"; 2398 2399 power-domains = <&rpmhpd RPMHPD_CX>; 2400 operating-points-v2 = <&qup_opp_table_100mhz>; 2401 2402 pinctrl-0 = <&qup_uart2_default>; 2403 pinctrl-names = "default"; 2404 2405 status = "disabled"; 2406 }; 2407 2408 spi2: spi@b88000 { 2409 compatible = "qcom,geni-spi"; 2410 reg = <0 0x00b88000 0 0x4000>; 2411 2412 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2413 2414 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2415 clock-names = "se"; 2416 2417 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2418 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2419 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2420 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2421 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2422 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2423 interconnect-names = "qup-core", 2424 "qup-config", 2425 "qup-memory"; 2426 2427 power-domains = <&rpmhpd RPMHPD_CX>; 2428 operating-points-v2 = <&qup_opp_table_100mhz>; 2429 2430 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2431 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2432 dma-names = "tx", 2433 "rx"; 2434 2435 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2436 pinctrl-names = "default"; 2437 2438 #address-cells = <1>; 2439 #size-cells = <0>; 2440 2441 status = "disabled"; 2442 }; 2443 2444 i2c3: i2c@b8c000 { 2445 compatible = "qcom,geni-i2c"; 2446 reg = <0 0x00b8c000 0 0x4000>; 2447 2448 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2449 2450 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2451 clock-names = "se"; 2452 2453 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2454 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2455 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2456 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2457 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2458 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2459 interconnect-names = "qup-core", 2460 "qup-config", 2461 "qup-memory"; 2462 2463 power-domains = <&rpmhpd RPMHPD_CX>; 2464 required-opps = <&rpmhpd_opp_low_svs>; 2465 2466 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2467 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2468 dma-names = "tx", 2469 "rx"; 2470 2471 pinctrl-0 = <&qup_i2c3_data_clk>; 2472 pinctrl-names = "default"; 2473 2474 #address-cells = <1>; 2475 #size-cells = <0>; 2476 2477 status = "disabled"; 2478 }; 2479 2480 spi3: spi@b8c000 { 2481 compatible = "qcom,geni-spi"; 2482 reg = <0 0x00b8c000 0 0x4000>; 2483 2484 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2485 2486 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2487 clock-names = "se"; 2488 2489 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2490 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2491 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2492 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2493 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2494 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2495 interconnect-names = "qup-core", 2496 "qup-config", 2497 "qup-memory"; 2498 2499 power-domains = <&rpmhpd RPMHPD_CX>; 2500 operating-points-v2 = <&qup_opp_table_100mhz>; 2501 2502 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2503 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2504 dma-names = "tx", 2505 "rx"; 2506 2507 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2508 pinctrl-names = "default"; 2509 2510 #address-cells = <1>; 2511 #size-cells = <0>; 2512 2513 status = "disabled"; 2514 }; 2515 2516 i2c4: i2c@b90000 { 2517 compatible = "qcom,geni-i2c"; 2518 reg = <0 0x00b90000 0 0x4000>; 2519 2520 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2521 2522 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2523 clock-names = "se"; 2524 2525 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2526 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2527 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2528 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2529 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2530 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2531 interconnect-names = "qup-core", 2532 "qup-config", 2533 "qup-memory"; 2534 2535 power-domains = <&rpmhpd RPMHPD_CX>; 2536 required-opps = <&rpmhpd_opp_low_svs>; 2537 2538 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2539 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2540 dma-names = "tx", 2541 "rx"; 2542 2543 pinctrl-0 = <&qup_i2c4_data_clk>; 2544 pinctrl-names = "default"; 2545 2546 #address-cells = <1>; 2547 #size-cells = <0>; 2548 2549 status = "disabled"; 2550 }; 2551 2552 spi4: spi@b90000 { 2553 compatible = "qcom,geni-spi"; 2554 reg = <0 0x00b90000 0 0x4000>; 2555 2556 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2557 2558 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2559 clock-names = "se"; 2560 2561 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2562 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2563 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2564 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2565 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2566 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2567 interconnect-names = "qup-core", 2568 "qup-config", 2569 "qup-memory"; 2570 2571 power-domains = <&rpmhpd RPMHPD_CX>; 2572 operating-points-v2 = <&qup_opp_table_100mhz>; 2573 2574 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2575 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2576 dma-names = "tx", 2577 "rx"; 2578 2579 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2580 pinctrl-names = "default"; 2581 2582 #address-cells = <1>; 2583 #size-cells = <0>; 2584 2585 status = "disabled"; 2586 }; 2587 2588 i2c5: i2c@b94000 { 2589 compatible = "qcom,geni-i2c"; 2590 reg = <0 0x00b94000 0 0x4000>; 2591 2592 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2593 2594 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2595 clock-names = "se"; 2596 2597 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2598 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2599 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2600 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2601 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2602 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2603 interconnect-names = "qup-core", 2604 "qup-config", 2605 "qup-memory"; 2606 2607 power-domains = <&rpmhpd RPMHPD_CX>; 2608 required-opps = <&rpmhpd_opp_low_svs>; 2609 2610 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2611 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2612 dma-names = "tx", 2613 "rx"; 2614 2615 pinctrl-0 = <&qup_i2c5_data_clk>; 2616 pinctrl-names = "default"; 2617 2618 #address-cells = <1>; 2619 #size-cells = <0>; 2620 2621 status = "disabled"; 2622 }; 2623 2624 spi5: spi@b94000 { 2625 compatible = "qcom,geni-spi"; 2626 reg = <0 0x00b94000 0 0x4000>; 2627 2628 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2629 2630 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2631 clock-names = "se"; 2632 2633 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2634 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2635 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2636 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2637 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2638 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2639 interconnect-names = "qup-core", 2640 "qup-config", 2641 "qup-memory"; 2642 2643 power-domains = <&rpmhpd RPMHPD_CX>; 2644 operating-points-v2 = <&qup_opp_table_100mhz>; 2645 2646 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2647 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2648 dma-names = "tx", 2649 "rx"; 2650 2651 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2652 pinctrl-names = "default"; 2653 2654 #address-cells = <1>; 2655 #size-cells = <0>; 2656 2657 status = "disabled"; 2658 }; 2659 2660 i2c6: i2c@b98000 { 2661 compatible = "qcom,geni-i2c"; 2662 reg = <0 0x00b98000 0 0x4000>; 2663 2664 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2665 2666 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2667 clock-names = "se"; 2668 2669 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2670 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2671 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2672 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2673 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2674 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2675 interconnect-names = "qup-core", 2676 "qup-config", 2677 "qup-memory"; 2678 2679 power-domains = <&rpmhpd RPMHPD_CX>; 2680 required-opps = <&rpmhpd_opp_low_svs>; 2681 2682 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2683 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2684 dma-names = "tx", 2685 "rx"; 2686 2687 pinctrl-0 = <&qup_i2c6_data_clk>; 2688 pinctrl-names = "default"; 2689 2690 #address-cells = <1>; 2691 #size-cells = <0>; 2692 2693 status = "disabled"; 2694 }; 2695 2696 spi6: spi@b98000 { 2697 compatible = "qcom,geni-spi"; 2698 reg = <0 0x00b98000 0 0x4000>; 2699 2700 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2701 2702 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2703 clock-names = "se"; 2704 2705 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2706 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2707 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2708 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2709 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2710 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2711 interconnect-names = "qup-core", 2712 "qup-config", 2713 "qup-memory"; 2714 2715 power-domains = <&rpmhpd RPMHPD_CX>; 2716 operating-points-v2 = <&qup_opp_table_100mhz>; 2717 2718 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2719 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2720 dma-names = "tx", 2721 "rx"; 2722 2723 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2724 pinctrl-names = "default"; 2725 2726 #address-cells = <1>; 2727 #size-cells = <0>; 2728 2729 status = "disabled"; 2730 }; 2731 2732 i2c7: i2c@b9c000 { 2733 compatible = "qcom,geni-i2c"; 2734 reg = <0 0x00b9c000 0 0x4000>; 2735 2736 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2737 2738 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2739 clock-names = "se"; 2740 2741 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2742 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2743 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2744 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2745 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2746 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2747 interconnect-names = "qup-core", 2748 "qup-config", 2749 "qup-memory"; 2750 2751 power-domains = <&rpmhpd RPMHPD_CX>; 2752 required-opps = <&rpmhpd_opp_low_svs>; 2753 2754 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2755 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2756 dma-names = "tx", 2757 "rx"; 2758 2759 pinctrl-0 = <&qup_i2c7_data_clk>; 2760 pinctrl-names = "default"; 2761 2762 #address-cells = <1>; 2763 #size-cells = <0>; 2764 2765 status = "disabled"; 2766 }; 2767 2768 spi7: spi@b9c000 { 2769 compatible = "qcom,geni-spi"; 2770 reg = <0 0x00b9c000 0 0x4000>; 2771 2772 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2773 2774 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2775 clock-names = "se"; 2776 2777 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2778 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2779 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2780 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2781 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2782 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2783 interconnect-names = "qup-core", 2784 "qup-config", 2785 "qup-memory"; 2786 2787 power-domains = <&rpmhpd RPMHPD_CX>; 2788 operating-points-v2 = <&qup_opp_table_100mhz>; 2789 2790 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2791 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2792 dma-names = "tx", 2793 "rx"; 2794 2795 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2796 pinctrl-names = "default"; 2797 2798 #address-cells = <1>; 2799 #size-cells = <0>; 2800 2801 status = "disabled"; 2802 }; 2803 }; 2804 2805 tsens0: thermal-sensor@c271000 { 2806 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2807 reg = <0 0x0c271000 0 0x1000>, 2808 <0 0x0c222000 0 0x1000>; 2809 2810 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2811 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2812 interrupt-names = "uplow", 2813 "critical"; 2814 2815 #qcom,sensors = <16>; 2816 2817 #thermal-sensor-cells = <1>; 2818 }; 2819 2820 tsens1: thermal-sensor@c272000 { 2821 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2822 reg = <0 0x0c272000 0 0x1000>, 2823 <0 0x0c223000 0 0x1000>; 2824 2825 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2826 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2827 interrupt-names = "uplow", 2828 "critical"; 2829 2830 #qcom,sensors = <16>; 2831 2832 #thermal-sensor-cells = <1>; 2833 }; 2834 2835 tsens2: thermal-sensor@c273000 { 2836 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2837 reg = <0 0x0c273000 0 0x1000>, 2838 <0 0x0c224000 0 0x1000>; 2839 2840 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, 2841 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 2842 interrupt-names = "uplow", 2843 "critical"; 2844 2845 #qcom,sensors = <16>; 2846 2847 #thermal-sensor-cells = <1>; 2848 }; 2849 2850 tsens3: thermal-sensor@c274000 { 2851 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2852 reg = <0 0x0c274000 0 0x1000>, 2853 <0 0x0c225000 0 0x1000>; 2854 2855 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, 2856 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 2857 interrupt-names = "uplow", 2858 "critical"; 2859 2860 #qcom,sensors = <16>; 2861 2862 #thermal-sensor-cells = <1>; 2863 }; 2864 2865 usb_1_ss0_hsphy: phy@fd3000 { 2866 compatible = "qcom,x1e80100-snps-eusb2-phy", 2867 "qcom,sm8550-snps-eusb2-phy"; 2868 reg = <0 0x00fd3000 0 0x154>; 2869 #phy-cells = <0>; 2870 2871 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2872 clock-names = "ref"; 2873 2874 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2875 2876 status = "disabled"; 2877 }; 2878 2879 usb_1_ss0_qmpphy: phy@fd5000 { 2880 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2881 reg = <0 0x00fd5000 0 0x4000>; 2882 2883 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2884 <&rpmhcc RPMH_CXO_CLK>, 2885 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2886 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2887 clock-names = "aux", 2888 "ref", 2889 "com_aux", 2890 "usb3_pipe"; 2891 2892 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2893 2894 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2895 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2896 reset-names = "phy", 2897 "common"; 2898 2899 #clock-cells = <1>; 2900 #phy-cells = <1>; 2901 2902 mode-switch; 2903 orientation-switch; 2904 2905 status = "disabled"; 2906 2907 ports { 2908 #address-cells = <1>; 2909 #size-cells = <0>; 2910 2911 port@0 { 2912 reg = <0>; 2913 2914 usb_1_ss0_qmpphy_out: endpoint { 2915 }; 2916 }; 2917 2918 port@1 { 2919 reg = <1>; 2920 2921 usb_1_ss0_qmpphy_usb_ss_in: endpoint { 2922 remote-endpoint = <&usb_1_ss0_dwc3_ss>; 2923 }; 2924 }; 2925 2926 port@2 { 2927 reg = <2>; 2928 2929 usb_1_ss0_qmpphy_dp_in: endpoint { 2930 remote-endpoint = <&mdss_dp0_out>; 2931 }; 2932 }; 2933 }; 2934 }; 2935 2936 usb_1_ss1_hsphy: phy@fd9000 { 2937 compatible = "qcom,x1e80100-snps-eusb2-phy", 2938 "qcom,sm8550-snps-eusb2-phy"; 2939 reg = <0 0x00fd9000 0 0x154>; 2940 #phy-cells = <0>; 2941 2942 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2943 clock-names = "ref"; 2944 2945 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2946 2947 status = "disabled"; 2948 }; 2949 2950 usb_1_ss1_qmpphy: phy@fda000 { 2951 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2952 reg = <0 0x00fda000 0 0x4000>; 2953 2954 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2955 <&tcsr TCSR_USB4_1_CLKREF_EN>, 2956 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2957 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2958 clock-names = "aux", 2959 "ref", 2960 "com_aux", 2961 "usb3_pipe"; 2962 2963 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2964 2965 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2966 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2967 reset-names = "phy", 2968 "common"; 2969 2970 #clock-cells = <1>; 2971 #phy-cells = <1>; 2972 2973 mode-switch; 2974 orientation-switch; 2975 2976 status = "disabled"; 2977 2978 ports { 2979 #address-cells = <1>; 2980 #size-cells = <0>; 2981 2982 port@0 { 2983 reg = <0>; 2984 2985 usb_1_ss1_qmpphy_out: endpoint { 2986 }; 2987 }; 2988 2989 port@1 { 2990 reg = <1>; 2991 2992 usb_1_ss1_qmpphy_usb_ss_in: endpoint { 2993 remote-endpoint = <&usb_1_ss1_dwc3_ss>; 2994 }; 2995 }; 2996 2997 port@2 { 2998 reg = <2>; 2999 3000 usb_1_ss1_qmpphy_dp_in: endpoint { 3001 remote-endpoint = <&mdss_dp1_out>; 3002 }; 3003 }; 3004 }; 3005 }; 3006 3007 usb_1_ss2_hsphy: phy@fde000 { 3008 compatible = "qcom,x1e80100-snps-eusb2-phy", 3009 "qcom,sm8550-snps-eusb2-phy"; 3010 reg = <0 0x00fde000 0 0x154>; 3011 #phy-cells = <0>; 3012 3013 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 3014 clock-names = "ref"; 3015 3016 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 3017 3018 status = "disabled"; 3019 }; 3020 3021 usb_1_ss2_qmpphy: phy@fdf000 { 3022 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 3023 reg = <0 0x00fdf000 0 0x4000>; 3024 3025 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 3026 <&tcsr TCSR_USB4_2_CLKREF_EN>, 3027 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 3028 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 3029 clock-names = "aux", 3030 "ref", 3031 "com_aux", 3032 "usb3_pipe"; 3033 3034 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 3035 3036 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 3037 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 3038 reset-names = "phy", 3039 "common"; 3040 3041 #clock-cells = <1>; 3042 #phy-cells = <1>; 3043 3044 mode-switch; 3045 orientation-switch; 3046 3047 status = "disabled"; 3048 3049 ports { 3050 #address-cells = <1>; 3051 #size-cells = <0>; 3052 3053 port@0 { 3054 reg = <0>; 3055 3056 usb_1_ss2_qmpphy_out: endpoint { 3057 }; 3058 }; 3059 3060 port@1 { 3061 reg = <1>; 3062 3063 usb_1_ss2_qmpphy_usb_ss_in: endpoint { 3064 remote-endpoint = <&usb_1_ss2_dwc3_ss>; 3065 }; 3066 }; 3067 3068 port@2 { 3069 reg = <2>; 3070 3071 usb_1_ss2_qmpphy_dp_in: endpoint { 3072 remote-endpoint = <&mdss_dp2_out>; 3073 }; 3074 }; 3075 }; 3076 }; 3077 3078 rng: rng@10c3000 { 3079 compatible = "qcom,x1e80100-trng", "qcom,trng"; 3080 reg = <0x0 0x010c3000 0x0 0x1000>; 3081 }; 3082 3083 cnoc_main: interconnect@1500000 { 3084 compatible = "qcom,x1e80100-cnoc-main"; 3085 reg = <0 0x01500000 0 0x14400>; 3086 3087 qcom,bcm-voters = <&apps_bcm_voter>; 3088 3089 #interconnect-cells = <2>; 3090 }; 3091 3092 config_noc: interconnect@1600000 { 3093 compatible = "qcom,x1e80100-cnoc-cfg"; 3094 reg = <0 0x01600000 0 0x6600>; 3095 3096 qcom,bcm-voters = <&apps_bcm_voter>; 3097 3098 #interconnect-cells = <2>; 3099 }; 3100 3101 system_noc: interconnect@1680000 { 3102 compatible = "qcom,x1e80100-system-noc"; 3103 reg = <0 0x01680000 0 0x1c080>; 3104 3105 qcom,bcm-voters = <&apps_bcm_voter>; 3106 3107 #interconnect-cells = <2>; 3108 }; 3109 3110 pcie_south_anoc: interconnect@16c0000 { 3111 compatible = "qcom,x1e80100-pcie-south-anoc"; 3112 reg = <0 0x016c0000 0 0xd080>; 3113 3114 qcom,bcm-voters = <&apps_bcm_voter>; 3115 3116 #interconnect-cells = <2>; 3117 }; 3118 3119 pcie_center_anoc: interconnect@16d0000 { 3120 compatible = "qcom,x1e80100-pcie-center-anoc"; 3121 reg = <0 0x016d0000 0 0x7000>; 3122 3123 qcom,bcm-voters = <&apps_bcm_voter>; 3124 3125 #interconnect-cells = <2>; 3126 }; 3127 3128 aggre1_noc: interconnect@16e0000 { 3129 compatible = "qcom,x1e80100-aggre1-noc"; 3130 reg = <0 0x016e0000 0 0x14400>; 3131 3132 qcom,bcm-voters = <&apps_bcm_voter>; 3133 3134 #interconnect-cells = <2>; 3135 }; 3136 3137 aggre2_noc: interconnect@1700000 { 3138 compatible = "qcom,x1e80100-aggre2-noc"; 3139 reg = <0 0x01700000 0 0x1c400>; 3140 3141 qcom,bcm-voters = <&apps_bcm_voter>; 3142 3143 #interconnect-cells = <2>; 3144 }; 3145 3146 pcie_north_anoc: interconnect@1740000 { 3147 compatible = "qcom,x1e80100-pcie-north-anoc"; 3148 reg = <0 0x01740000 0 0x9080>; 3149 3150 qcom,bcm-voters = <&apps_bcm_voter>; 3151 3152 #interconnect-cells = <2>; 3153 }; 3154 3155 usb_center_anoc: interconnect@1750000 { 3156 compatible = "qcom,x1e80100-usb-center-anoc"; 3157 reg = <0 0x01750000 0 0x8800>; 3158 3159 qcom,bcm-voters = <&apps_bcm_voter>; 3160 3161 #interconnect-cells = <2>; 3162 }; 3163 3164 usb_north_anoc: interconnect@1760000 { 3165 compatible = "qcom,x1e80100-usb-north-anoc"; 3166 reg = <0 0x01760000 0 0x7080>; 3167 3168 qcom,bcm-voters = <&apps_bcm_voter>; 3169 3170 #interconnect-cells = <2>; 3171 }; 3172 3173 usb_south_anoc: interconnect@1770000 { 3174 compatible = "qcom,x1e80100-usb-south-anoc"; 3175 reg = <0 0x01770000 0 0xf080>; 3176 3177 qcom,bcm-voters = <&apps_bcm_voter>; 3178 3179 #interconnect-cells = <2>; 3180 }; 3181 3182 mmss_noc: interconnect@1780000 { 3183 compatible = "qcom,x1e80100-mmss-noc"; 3184 reg = <0 0x01780000 0 0x5b800>; 3185 3186 qcom,bcm-voters = <&apps_bcm_voter>; 3187 3188 #interconnect-cells = <2>; 3189 }; 3190 3191 pcie3: pcie@1bd0000 { 3192 device_type = "pci"; 3193 compatible = "qcom,pcie-x1e80100"; 3194 reg = <0x0 0x01bd0000 0x0 0x3000>, 3195 <0x0 0x78000000 0x0 0xf20>, 3196 <0x0 0x78000f40 0x0 0xa8>, 3197 <0x0 0x78001000 0x0 0x1000>, 3198 <0x0 0x78100000 0x0 0x100000>, 3199 <0x0 0x01bd3000 0x0 0x1000>; 3200 reg-names = "parf", 3201 "dbi", 3202 "elbi", 3203 "atu", 3204 "config", 3205 "mhi"; 3206 #address-cells = <3>; 3207 #size-cells = <2>; 3208 ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>, 3209 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>, 3210 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3211 bus-range = <0x00 0xff>; 3212 3213 dma-coherent; 3214 3215 linux,pci-domain = <3>; 3216 num-lanes = <8>; 3217 3218 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 3219 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 3220 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3221 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 3222 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 3223 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 3224 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 3225 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 3226 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3227 interrupt-names = "msi0", 3228 "msi1", 3229 "msi2", 3230 "msi3", 3231 "msi4", 3232 "msi5", 3233 "msi6", 3234 "msi7", 3235 "global"; 3236 3237 #interrupt-cells = <1>; 3238 interrupt-map-mask = <0 0 0 0x7>; 3239 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 3240 <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 3241 <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 3242 <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3243 3244 clocks = <&gcc GCC_PCIE_3_AUX_CLK>, 3245 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3246 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 3247 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 3248 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 3249 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3250 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3251 clock-names = "aux", 3252 "cfg", 3253 "bus_master", 3254 "bus_slave", 3255 "slave_q2a", 3256 "noc_aggr", 3257 "cnoc_sf_axi"; 3258 3259 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 3260 assigned-clock-rates = <19200000>; 3261 3262 interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS 3263 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3264 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3265 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ACTIVE_ONLY>; 3266 interconnect-names = "pcie-mem", 3267 "cpu-pcie"; 3268 3269 resets = <&gcc GCC_PCIE_3_BCR>, 3270 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>; 3271 reset-names = "pci", 3272 "link_down"; 3273 3274 power-domains = <&gcc GCC_PCIE_3_GDSC>; 3275 3276 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 3277 0x5555 0x5555 0x5555 0x5555>; 3278 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; 3279 3280 operating-points-v2 = <&pcie3_opp_table>; 3281 3282 status = "disabled"; 3283 3284 pcie3_opp_table: opp-table { 3285 compatible = "operating-points-v2"; 3286 3287 /* 2.5GT/s x1 */ 3288 opp-2500000-1 { 3289 opp-hz = /bits/ 64 <2500000>; 3290 required-opps = <&rpmhpd_opp_low_svs>; 3291 opp-peak-kBps = <250000 1>; 3292 opp-level = <1>; 3293 }; 3294 3295 /* 2.5 GT/s x2 */ 3296 opp-5000000-1 { 3297 opp-hz = /bits/ 64 <5000000>; 3298 required-opps = <&rpmhpd_opp_low_svs>; 3299 opp-peak-kBps = <500000 1>; 3300 opp-level = <1>; 3301 }; 3302 3303 /* 2.5 GT/s x4 */ 3304 opp-10000000-1 { 3305 opp-hz = /bits/ 64 <10000000>; 3306 required-opps = <&rpmhpd_opp_low_svs>; 3307 opp-peak-kBps = <1000000 1>; 3308 opp-level = <1>; 3309 }; 3310 3311 /* 2.5 GT/s x8 */ 3312 opp-20000000-1 { 3313 opp-hz = /bits/ 64 <20000000>; 3314 required-opps = <&rpmhpd_opp_low_svs>; 3315 opp-peak-kBps = <2000000 1>; 3316 opp-level = <1>; 3317 }; 3318 3319 /* 5 GT/s x1 */ 3320 opp-5000000-2 { 3321 opp-hz = /bits/ 64 <5000000>; 3322 required-opps = <&rpmhpd_opp_low_svs>; 3323 opp-peak-kBps = <500000 1>; 3324 opp-level = <2>; 3325 }; 3326 3327 /* 5 GT/s x2 */ 3328 opp-10000000-2 { 3329 opp-hz = /bits/ 64 <10000000>; 3330 required-opps = <&rpmhpd_opp_low_svs>; 3331 opp-peak-kBps = <1000000 1>; 3332 opp-level = <2>; 3333 }; 3334 3335 /* 5 GT/s x4 */ 3336 opp-20000000-2 { 3337 opp-hz = /bits/ 64 <20000000>; 3338 required-opps = <&rpmhpd_opp_low_svs>; 3339 opp-peak-kBps = <2000000 1>; 3340 opp-level = <2>; 3341 }; 3342 3343 /* 5 GT/s x8 */ 3344 opp-40000000-2 { 3345 opp-hz = /bits/ 64 <40000000>; 3346 required-opps = <&rpmhpd_opp_low_svs>; 3347 opp-peak-kBps = <4000000 1>; 3348 opp-level = <2>; 3349 }; 3350 3351 /* 8 GT/s x1 */ 3352 opp-8000000-3 { 3353 opp-hz = /bits/ 64 <8000000>; 3354 required-opps = <&rpmhpd_opp_svs>; 3355 opp-peak-kBps = <984500 1>; 3356 opp-level = <3>; 3357 }; 3358 3359 /* 8 GT/s x2 */ 3360 opp-16000000-3 { 3361 opp-hz = /bits/ 64 <16000000>; 3362 required-opps = <&rpmhpd_opp_svs>; 3363 opp-peak-kBps = <1969000 1>; 3364 opp-level = <3>; 3365 }; 3366 3367 /* 8 GT/s x4 */ 3368 opp-32000000-3 { 3369 opp-hz = /bits/ 64 <32000000>; 3370 required-opps = <&rpmhpd_opp_svs>; 3371 opp-peak-kBps = <3938000 1>; 3372 opp-level = <3>; 3373 }; 3374 3375 /* 8 GT/s x8 */ 3376 opp-64000000-3 { 3377 opp-hz = /bits/ 64 <64000000>; 3378 required-opps = <&rpmhpd_opp_svs>; 3379 opp-peak-kBps = <7876000 1>; 3380 opp-level = <3>; 3381 }; 3382 3383 /* 16 GT/s x1 */ 3384 opp-16000000-4 { 3385 opp-hz = /bits/ 64 <16000000>; 3386 required-opps = <&rpmhpd_opp_svs>; 3387 opp-peak-kBps = <1969000 1>; 3388 opp-level = <4>; 3389 }; 3390 3391 /* 16 GT/s x2 */ 3392 opp-32000000-4 { 3393 opp-hz = /bits/ 64 <32000000>; 3394 required-opps = <&rpmhpd_opp_svs>; 3395 opp-peak-kBps = <3938000 1>; 3396 opp-level = <4>; 3397 }; 3398 3399 /* 16 GT/s x4 */ 3400 opp-64000000-4 { 3401 opp-hz = /bits/ 64 <64000000>; 3402 required-opps = <&rpmhpd_opp_svs>; 3403 opp-peak-kBps = <7876000 1>; 3404 opp-level = <4>; 3405 }; 3406 3407 /* 16 GT/s x8 */ 3408 opp-128000000-4 { 3409 opp-hz = /bits/ 64 <128000000>; 3410 required-opps = <&rpmhpd_opp_svs>; 3411 opp-peak-kBps = <15753000 1>; 3412 opp-level = <4>; 3413 }; 3414 }; 3415 3416 pcie3_port0: pcie@0 { 3417 device_type = "pci"; 3418 compatible = "pciclass,0604"; 3419 reg = <0x0 0x0 0x0 0x0 0x0>; 3420 bus-range = <0x01 0xff>; 3421 3422 phys = <&pcie3_phy>; 3423 3424 #address-cells = <3>; 3425 #size-cells = <2>; 3426 ranges; 3427 }; 3428 }; 3429 3430 pcie3_phy: phy@1be0000 { 3431 compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy"; 3432 reg = <0 0x01be0000 0 0x10000>; 3433 3434 clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, 3435 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3436 <&tcsr TCSR_PCIE_8L_CLKREF_EN>, 3437 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, 3438 <&gcc GCC_PCIE_3_PIPE_CLK>, 3439 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; 3440 clock-names = "aux", 3441 "cfg_ahb", 3442 "ref", 3443 "rchng", 3444 "pipe", 3445 "pipediv2"; 3446 3447 resets = <&gcc GCC_PCIE_3_PHY_BCR>, 3448 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; 3449 reset-names = "phy", 3450 "phy_nocsr"; 3451 3452 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; 3453 assigned-clock-rates = <100000000>; 3454 3455 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; 3456 3457 #clock-cells = <0>; 3458 clock-output-names = "pcie3_pipe_clk"; 3459 3460 #phy-cells = <0>; 3461 3462 status = "disabled"; 3463 }; 3464 3465 pcie6a: pci@1bf8000 { 3466 device_type = "pci"; 3467 compatible = "qcom,pcie-x1e80100"; 3468 reg = <0 0x01bf8000 0 0x3000>, 3469 <0 0x70000000 0 0xf20>, 3470 <0 0x70000f40 0 0xa8>, 3471 <0 0x70001000 0 0x1000>, 3472 <0 0x70100000 0 0x100000>, 3473 <0 0x01bfb000 0 0x1000>; 3474 reg-names = "parf", 3475 "dbi", 3476 "elbi", 3477 "atu", 3478 "config", 3479 "mhi"; 3480 #address-cells = <3>; 3481 #size-cells = <2>; 3482 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, 3483 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 3484 bus-range = <0x00 0xff>; 3485 3486 dma-coherent; 3487 3488 linux,pci-domain = <6>; 3489 num-lanes = <4>; 3490 3491 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3492 3493 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>; 3502 interrupt-names = "msi0", 3503 "msi1", 3504 "msi2", 3505 "msi3", 3506 "msi4", 3507 "msi5", 3508 "msi6", 3509 "msi7", 3510 "global"; 3511 3512 #interrupt-cells = <1>; 3513 interrupt-map-mask = <0 0 0 0x7>; 3514 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 3515 <0 0 0 2 &intc 0 0 GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 3516 <0 0 0 3 &intc 0 0 GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 3517 <0 0 0 4 &intc 0 0 GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>; 3518 3519 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 3520 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3521 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 3522 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 3523 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 3524 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 3525 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 3526 clock-names = "aux", 3527 "cfg", 3528 "bus_master", 3529 "bus_slave", 3530 "slave_q2a", 3531 "noc_aggr", 3532 "cnoc_sf_axi"; 3533 3534 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 3535 assigned-clock-rates = <19200000>; 3536 3537 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 3538 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3539 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3540 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ACTIVE_ONLY>; 3541 interconnect-names = "pcie-mem", 3542 "cpu-pcie"; 3543 3544 resets = <&gcc GCC_PCIE_6A_BCR>, 3545 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 3546 reset-names = "pci", 3547 "link_down"; 3548 3549 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 3550 required-opps = <&rpmhpd_opp_nom>; 3551 3552 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3553 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3554 3555 status = "disabled"; 3556 3557 pcie6a_port0: pcie@0 { 3558 device_type = "pci"; 3559 reg = <0x0 0x0 0x0 0x0 0x0>; 3560 bus-range = <0x01 0xff>; 3561 3562 phys = <&pcie6a_phy>; 3563 3564 #address-cells = <3>; 3565 #size-cells = <2>; 3566 ranges; 3567 }; 3568 }; 3569 3570 pcie6a_phy: phy@1bfc000 { 3571 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; 3572 reg = <0 0x01bfc000 0 0x2000>, 3573 <0 0x01bfe000 0 0x2000>; 3574 3575 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 3576 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3577 <&tcsr TCSR_PCIE_4L_CLKREF_EN>, 3578 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 3579 <&gcc GCC_PCIE_6A_PIPE_CLK>, 3580 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; 3581 clock-names = "aux", 3582 "cfg_ahb", 3583 "ref", 3584 "rchng", 3585 "pipe", 3586 "pipediv2"; 3587 3588 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 3589 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 3590 reset-names = "phy", 3591 "phy_nocsr"; 3592 3593 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 3594 assigned-clock-rates = <100000000>; 3595 3596 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3597 3598 qcom,4ln-config-sel = <&tcsr 0x1a000 0>; 3599 3600 #clock-cells = <0>; 3601 clock-output-names = "pcie6a_pipe_clk"; 3602 3603 #phy-cells = <0>; 3604 3605 status = "disabled"; 3606 }; 3607 3608 pcie5: pci@1c00000 { 3609 device_type = "pci"; 3610 compatible = "qcom,pcie-x1e80100"; 3611 reg = <0 0x01c00000 0 0x3000>, 3612 <0 0x7e000000 0 0xf1d>, 3613 <0 0x7e000f40 0 0xa8>, 3614 <0 0x7e001000 0 0x1000>, 3615 <0 0x7e100000 0 0x100000>, 3616 <0 0x01c03000 0 0x1000>; 3617 reg-names = "parf", 3618 "dbi", 3619 "elbi", 3620 "atu", 3621 "config", 3622 "mhi"; 3623 #address-cells = <3>; 3624 #size-cells = <2>; 3625 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3626 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>; 3627 bus-range = <0x00 0xff>; 3628 3629 dma-coherent; 3630 3631 linux,pci-domain = <5>; 3632 num-lanes = <2>; 3633 3634 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 3643 interrupt-names = "msi0", 3644 "msi1", 3645 "msi2", 3646 "msi3", 3647 "msi4", 3648 "msi5", 3649 "msi6", 3650 "msi7", 3651 "global"; 3652 3653 #interrupt-cells = <1>; 3654 interrupt-map-mask = <0 0 0 0x7>; 3655 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 3656 <0 0 0 2 &intc 0 0 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 3657 <0 0 0 3 &intc 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 3658 <0 0 0 4 &intc 0 0 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 3659 3660 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3661 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3662 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3663 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3664 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3665 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3666 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3667 clock-names = "aux", 3668 "cfg", 3669 "bus_master", 3670 "bus_slave", 3671 "slave_q2a", 3672 "noc_aggr", 3673 "cnoc_sf_axi"; 3674 3675 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3676 assigned-clock-rates = <19200000>; 3677 3678 interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3679 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3680 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3681 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ACTIVE_ONLY>; 3682 interconnect-names = "pcie-mem", 3683 "cpu-pcie"; 3684 3685 resets = <&gcc GCC_PCIE_5_BCR>, 3686 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3687 reset-names = "pci", 3688 "link_down"; 3689 3690 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3691 required-opps = <&rpmhpd_opp_nom>; 3692 3693 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3694 3695 status = "disabled"; 3696 3697 pcie5_port0: pcie@0 { 3698 device_type = "pci"; 3699 reg = <0x0 0x0 0x0 0x0 0x0>; 3700 bus-range = <0x01 0xff>; 3701 3702 phys = <&pcie5_phy>; 3703 3704 #address-cells = <3>; 3705 #size-cells = <2>; 3706 ranges; 3707 }; 3708 }; 3709 3710 pcie5_phy: phy@1c06000 { 3711 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3712 reg = <0 0x01c06000 0 0x2000>; 3713 3714 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3715 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3716 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>, 3717 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3718 <&gcc GCC_PCIE_5_PIPE_CLK>, 3719 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>; 3720 clock-names = "aux", 3721 "cfg_ahb", 3722 "ref", 3723 "rchng", 3724 "pipe", 3725 "pipediv2"; 3726 3727 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3728 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3729 reset-names = "phy", 3730 "phy_nocsr"; 3731 3732 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3733 assigned-clock-rates = <100000000>; 3734 3735 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3736 3737 #clock-cells = <0>; 3738 clock-output-names = "pcie5_pipe_clk"; 3739 3740 #phy-cells = <0>; 3741 3742 status = "disabled"; 3743 }; 3744 3745 pcie4: pci@1c08000 { 3746 device_type = "pci"; 3747 compatible = "qcom,pcie-x1e80100"; 3748 reg = <0 0x01c08000 0 0x3000>, 3749 <0 0x7c000000 0 0xf1d>, 3750 <0 0x7c000f40 0 0xa8>, 3751 <0 0x7c001000 0 0x1000>, 3752 <0 0x7c100000 0 0x100000>, 3753 <0 0x01c0b000 0 0x1000>; 3754 reg-names = "parf", 3755 "dbi", 3756 "elbi", 3757 "atu", 3758 "config", 3759 "mhi"; 3760 #address-cells = <3>; 3761 #size-cells = <2>; 3762 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, 3763 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; 3764 bus-range = <0x00 0xff>; 3765 3766 dma-coherent; 3767 3768 linux,pci-domain = <4>; 3769 num-lanes = <2>; 3770 3771 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 3772 3773 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 3782 interrupt-names = "msi0", 3783 "msi1", 3784 "msi2", 3785 "msi3", 3786 "msi4", 3787 "msi5", 3788 "msi6", 3789 "msi7", 3790 "global"; 3791 3792 #interrupt-cells = <1>; 3793 interrupt-map-mask = <0 0 0 0x7>; 3794 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 3795 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 3796 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 3797 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 3798 3799 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3800 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3801 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 3802 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 3803 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 3804 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3805 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3806 clock-names = "aux", 3807 "cfg", 3808 "bus_master", 3809 "bus_slave", 3810 "slave_q2a", 3811 "noc_aggr", 3812 "cnoc_sf_axi"; 3813 3814 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 3815 assigned-clock-rates = <19200000>; 3816 3817 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 3818 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3819 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3820 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 3821 interconnect-names = "pcie-mem", 3822 "cpu-pcie"; 3823 3824 resets = <&gcc GCC_PCIE_4_BCR>, 3825 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 3826 reset-names = "pci", 3827 "link_down"; 3828 3829 power-domains = <&gcc GCC_PCIE_4_GDSC>; 3830 required-opps = <&rpmhpd_opp_nom>; 3831 3832 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3833 3834 status = "disabled"; 3835 3836 pcie4_port0: pcie@0 { 3837 device_type = "pci"; 3838 reg = <0x0 0x0 0x0 0x0 0x0>; 3839 bus-range = <0x01 0xff>; 3840 3841 phys = <&pcie4_phy>; 3842 3843 #address-cells = <3>; 3844 #size-cells = <2>; 3845 ranges; 3846 }; 3847 }; 3848 3849 pcie4_phy: phy@1c0e000 { 3850 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3851 reg = <0 0x01c0e000 0 0x2000>; 3852 3853 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3854 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3855 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, 3856 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3857 <&gcc GCC_PCIE_4_PIPE_CLK>, 3858 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 3859 clock-names = "aux", 3860 "cfg_ahb", 3861 "ref", 3862 "rchng", 3863 "pipe", 3864 "pipediv2"; 3865 3866 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 3867 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 3868 reset-names = "phy", 3869 "phy_nocsr"; 3870 3871 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3872 assigned-clock-rates = <100000000>; 3873 3874 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3875 3876 #clock-cells = <0>; 3877 clock-output-names = "pcie4_pipe_clk"; 3878 3879 #phy-cells = <0>; 3880 3881 status = "disabled"; 3882 }; 3883 3884 ufs_mem_phy: phy@1d80000 { 3885 compatible = "qcom,x1e80100-qmp-ufs-phy", 3886 "qcom,sm8550-qmp-ufs-phy"; 3887 reg = <0x0 0x01d80000 0x0 0x2000>; 3888 3889 clocks = <&rpmhcc RPMH_CXO_CLK>, 3890 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3891 <&tcsr TCSR_UFS_PHY_CLKREF_EN>; 3892 3893 clock-names = "ref", 3894 "ref_aux", 3895 "qref"; 3896 resets = <&ufs_mem_hc 0>; 3897 reset-names = "ufsphy"; 3898 3899 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; 3900 3901 #clock-cells = <1>; 3902 #phy-cells = <0>; 3903 3904 status = "disabled"; 3905 }; 3906 3907 ufs_mem_hc: ufshc@1d84000 { 3908 compatible = "qcom,x1e80100-ufshc", 3909 "qcom,sm8550-ufshc", 3910 "qcom,ufshc"; 3911 reg = <0x0 0x01d84000 0x0 0x3000>; 3912 3913 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 3914 3915 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 3916 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3917 <&gcc GCC_UFS_PHY_AHB_CLK>, 3918 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3919 <&rpmhcc RPMH_LN_BB_CLK3>, 3920 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3921 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3922 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 3923 clock-names = "core_clk", 3924 "bus_aggr_clk", 3925 "iface_clk", 3926 "core_clk_unipro", 3927 "ref_clk", 3928 "tx_lane0_sync_clk", 3929 "rx_lane0_sync_clk", 3930 "rx_lane1_sync_clk"; 3931 3932 operating-points-v2 = <&ufs_opp_table>; 3933 3934 resets = <&gcc GCC_UFS_PHY_BCR>; 3935 reset-names = "rst"; 3936 3937 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 3938 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3939 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3940 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3941 interconnect-names = "ufs-ddr", 3942 "cpu-ufs"; 3943 3944 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 3945 required-opps = <&rpmhpd_opp_nom>; 3946 3947 iommus = <&apps_smmu 0x1a0 0>; 3948 dma-coherent; 3949 3950 lanes-per-direction = <2>; 3951 3952 phys = <&ufs_mem_phy>; 3953 phy-names = "ufsphy"; 3954 3955 #reset-cells = <1>; 3956 3957 status = "disabled"; 3958 3959 ufs_opp_table: opp-table { 3960 compatible = "operating-points-v2"; 3961 3962 opp-75000000 { 3963 opp-hz = /bits/ 64 <75000000>, 3964 /bits/ 64 <0>, 3965 /bits/ 64 <0>, 3966 /bits/ 64 <75000000>, 3967 /bits/ 64 <0>, 3968 /bits/ 64 <0>, 3969 /bits/ 64 <0>, 3970 /bits/ 64 <0>; 3971 required-opps = <&rpmhpd_opp_low_svs>; 3972 }; 3973 3974 opp-150000000 { 3975 opp-hz = /bits/ 64 <150000000>, 3976 /bits/ 64 <0>, 3977 /bits/ 64 <0>, 3978 /bits/ 64 <150000000>, 3979 /bits/ 64 <0>, 3980 /bits/ 64 <0>, 3981 /bits/ 64 <0>, 3982 /bits/ 64 <0>; 3983 required-opps = <&rpmhpd_opp_svs>; 3984 }; 3985 3986 opp-300000000 { 3987 opp-hz = /bits/ 64 <300000000>, 3988 /bits/ 64 <0>, 3989 /bits/ 64 <0>, 3990 /bits/ 64 <300000000>, 3991 /bits/ 64 <0>, 3992 /bits/ 64 <0>, 3993 /bits/ 64 <0>, 3994 /bits/ 64 <0>; 3995 required-opps = <&rpmhpd_opp_nom>; 3996 }; 3997 }; 3998 }; 3999 4000 cryptobam: dma-controller@1dc4000 { 4001 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 4002 reg = <0x0 0x01dc4000 0x0 0x28000>; 4003 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 4004 #dma-cells = <1>; 4005 iommus = <&apps_smmu 0x480 0x0>, 4006 <&apps_smmu 0x481 0x0>; 4007 qcom,ee = <0>; 4008 qcom,controlled-remotely; 4009 num-channels = <20>; 4010 qcom,num-ees = <4>; 4011 }; 4012 4013 crypto: crypto@1dfa000 { 4014 compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce"; 4015 reg = <0x0 0x01dfa000 0x0 0x6000>; 4016 dmas = <&cryptobam 4>, <&cryptobam 5>; 4017 dma-names = "rx", 4018 "tx"; 4019 iommus = <&apps_smmu 0x480 0x0>, 4020 <&apps_smmu 0x481 0x0>; 4021 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 4022 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4023 interconnect-names = "memory"; 4024 }; 4025 4026 tcsr_mutex: hwlock@1f40000 { 4027 compatible = "qcom,tcsr-mutex"; 4028 reg = <0 0x01f40000 0 0x20000>; 4029 #hwlock-cells = <1>; 4030 }; 4031 4032 tcsr: clock-controller@1fc0000 { 4033 compatible = "qcom,x1e80100-tcsr", "syscon"; 4034 reg = <0 0x01fc0000 0 0x30000>; 4035 clocks = <&rpmhcc RPMH_CXO_CLK>; 4036 #clock-cells = <1>; 4037 #reset-cells = <1>; 4038 }; 4039 4040 gpu: gpu@3d00000 { 4041 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 4042 reg = <0x0 0x03d00000 0x0 0x40000>, 4043 <0x0 0x03d9e000 0x0 0x1000>, 4044 <0x0 0x03d61000 0x0 0x800>; 4045 4046 reg-names = "kgsl_3d0_reg_memory", 4047 "cx_mem", 4048 "cx_dbgc"; 4049 4050 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4051 4052 iommus = <&adreno_smmu 0 0x0>, 4053 <&adreno_smmu 1 0x0>; 4054 4055 operating-points-v2 = <&gpu_opp_table>; 4056 4057 qcom,gmu = <&gmu>; 4058 #cooling-cells = <2>; 4059 4060 nvmem-cells = <&gpu_speed_bin>; 4061 nvmem-cell-names = "speed_bin"; 4062 4063 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 4064 interconnect-names = "gfx-mem"; 4065 4066 status = "disabled"; 4067 4068 gpu_zap_shader: zap-shader { 4069 memory-region = <&gpu_microcode_mem>; 4070 }; 4071 4072 gpu_opp_table: opp-table { 4073 compatible = "operating-points-v2-adreno", "operating-points-v2"; 4074 4075 opp-1500000000 { 4076 opp-hz = /bits/ 64 <1500000000>; 4077 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>; 4078 opp-peak-kBps = <16500000>; 4079 qcom,opp-acd-level = <0xa82a5ffd>; 4080 opp-supported-hw = <0x03>; 4081 }; 4082 4083 opp-1375000000 { 4084 opp-hz = /bits/ 64 <1375000000>; 4085 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 4086 opp-peak-kBps = <16500000>; 4087 qcom,opp-acd-level = <0xa82a5ffd>; 4088 opp-supported-hw = <0x03>; 4089 }; 4090 4091 opp-1250000000 { 4092 opp-hz = /bits/ 64 <1250000000>; 4093 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 4094 opp-peak-kBps = <16500000>; 4095 qcom,opp-acd-level = <0xa82a5ffd>; 4096 opp-supported-hw = <0x07>; 4097 }; 4098 4099 opp-1175000000 { 4100 opp-hz = /bits/ 64 <1175000000>; 4101 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 4102 opp-peak-kBps = <14398438>; 4103 qcom,opp-acd-level = <0xa82a5ffd>; 4104 opp-supported-hw = <0x07>; 4105 }; 4106 4107 opp-1100000000-0 { 4108 opp-hz = /bits/ 64 <1100000000>; 4109 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4110 opp-peak-kBps = <14398438>; 4111 qcom,opp-acd-level = <0xa82a5ffd>; 4112 opp-supported-hw = <0x07>; 4113 }; 4114 4115 /* Only applicable for SKUs which has 1100Mhz as Fmax */ 4116 opp-1100000000-1 { 4117 opp-hz = /bits/ 64 <1100000000>; 4118 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4119 opp-peak-kBps = <16500000>; 4120 qcom,opp-acd-level = <0xa82a5ffd>; 4121 opp-supported-hw = <0x08>; 4122 }; 4123 4124 opp-1000000000 { 4125 opp-hz = /bits/ 64 <1000000000>; 4126 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4127 opp-peak-kBps = <14398438>; 4128 qcom,opp-acd-level = <0xa82b5ffd>; 4129 opp-supported-hw = <0x0f>; 4130 }; 4131 4132 opp-925000000 { 4133 opp-hz = /bits/ 64 <925000000>; 4134 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4135 opp-peak-kBps = <14398438>; 4136 qcom,opp-acd-level = <0xa82b5ffd>; 4137 opp-supported-hw = <0x0f>; 4138 }; 4139 4140 opp-800000000 { 4141 opp-hz = /bits/ 64 <800000000>; 4142 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4143 opp-peak-kBps = <12449219>; 4144 qcom,opp-acd-level = <0xa82c5ffd>; 4145 opp-supported-hw = <0x0f>; 4146 }; 4147 4148 opp-744000000 { 4149 opp-hz = /bits/ 64 <744000000>; 4150 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4151 opp-peak-kBps = <10687500>; 4152 qcom,opp-acd-level = <0x882e5ffd>; 4153 opp-supported-hw = <0x0f>; 4154 }; 4155 4156 opp-687000000-0 { 4157 opp-hz = /bits/ 64 <687000000>; 4158 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4159 opp-peak-kBps = <8171875>; 4160 qcom,opp-acd-level = <0x882e5ffd>; 4161 opp-supported-hw = <0x0f>; 4162 }; 4163 4164 /* Only applicable for SKUs which has 687Mhz as Fmax */ 4165 opp-687000000-1 { 4166 opp-hz = /bits/ 64 <687000000>; 4167 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4168 opp-peak-kBps = <16500000>; 4169 qcom,opp-acd-level = <0x882e5ffd>; 4170 opp-supported-hw = <0x10>; 4171 }; 4172 4173 opp-550000000 { 4174 opp-hz = /bits/ 64 <550000000>; 4175 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4176 opp-peak-kBps = <6074219>; 4177 qcom,opp-acd-level = <0xc0285ffd>; 4178 opp-supported-hw = <0x1f>; 4179 }; 4180 4181 opp-390000000 { 4182 opp-hz = /bits/ 64 <390000000>; 4183 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4184 opp-peak-kBps = <3000000>; 4185 qcom,opp-acd-level = <0xc0285ffd>; 4186 opp-supported-hw = <0x1f>; 4187 }; 4188 4189 opp-300000000 { 4190 opp-hz = /bits/ 64 <300000000>; 4191 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4192 opp-peak-kBps = <2136719>; 4193 qcom,opp-acd-level = <0xc02b5ffd>; 4194 opp-supported-hw = <0x1f>; 4195 }; 4196 }; 4197 }; 4198 4199 gmu: gmu@3d6a000 { 4200 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; 4201 reg = <0x0 0x03d6a000 0x0 0x35000>, 4202 <0x0 0x03d50000 0x0 0x10000>, 4203 <0x0 0x0b280000 0x0 0x10000>; 4204 reg-names = "gmu", "rscc", "gmu_pdc"; 4205 4206 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4208 interrupt-names = "hfi", "gmu"; 4209 4210 clocks = <&gpucc GPU_CC_AHB_CLK>, 4211 <&gpucc GPU_CC_CX_GMU_CLK>, 4212 <&gpucc GPU_CC_CXO_CLK>, 4213 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4214 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4215 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4216 <&gpucc GPU_CC_DEMET_CLK>; 4217 clock-names = "ahb", 4218 "gmu", 4219 "cxo", 4220 "axi", 4221 "memnoc", 4222 "hub", 4223 "demet"; 4224 4225 power-domains = <&gpucc GPU_CX_GDSC>, 4226 <&gpucc GPU_GX_GDSC>; 4227 power-domain-names = "cx", 4228 "gx"; 4229 4230 iommus = <&adreno_smmu 5 0x0>; 4231 4232 qcom,qmp = <&aoss_qmp>; 4233 4234 operating-points-v2 = <&gmu_opp_table>; 4235 4236 gmu_opp_table: opp-table { 4237 compatible = "operating-points-v2"; 4238 4239 opp-550000000 { 4240 opp-hz = /bits/ 64 <550000000>; 4241 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4242 }; 4243 4244 opp-220000000 { 4245 opp-hz = /bits/ 64 <220000000>; 4246 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4247 }; 4248 }; 4249 }; 4250 4251 gpucc: clock-controller@3d90000 { 4252 compatible = "qcom,x1e80100-gpucc"; 4253 reg = <0 0x03d90000 0 0xa000>; 4254 clocks = <&bi_tcxo_div2>, 4255 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, 4256 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; 4257 #clock-cells = <1>; 4258 #reset-cells = <1>; 4259 #power-domain-cells = <1>; 4260 }; 4261 4262 adreno_smmu: iommu@3da0000 { 4263 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", 4264 "qcom,smmu-500", "arm,mmu-500"; 4265 reg = <0x0 0x03da0000 0x0 0x40000>; 4266 #iommu-cells = <2>; 4267 #global-interrupts = <1>; 4268 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4269 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4270 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4271 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4273 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4274 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4275 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4276 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4278 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 4279 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 4280 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4281 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 4282 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 4283 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 4284 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 4285 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 4286 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 4287 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 4288 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 4289 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 4290 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 4291 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 4293 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 4294 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4295 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4296 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4297 <&gpucc GPU_CC_AHB_CLK>; 4298 clock-names = "hlos", 4299 "bus", 4300 "iface", 4301 "ahb"; 4302 power-domains = <&gpucc GPU_CX_GDSC>; 4303 dma-coherent; 4304 }; 4305 4306 gem_noc: interconnect@26400000 { 4307 compatible = "qcom,x1e80100-gem-noc"; 4308 reg = <0 0x26400000 0 0x311200>; 4309 4310 qcom,bcm-voters = <&apps_bcm_voter>; 4311 4312 #interconnect-cells = <2>; 4313 }; 4314 4315 nsp_noc: interconnect@320c0000 { 4316 compatible = "qcom,x1e80100-nsp-noc"; 4317 reg = <0 0x320c0000 0 0xe080>; 4318 4319 qcom,bcm-voters = <&apps_bcm_voter>; 4320 4321 #interconnect-cells = <2>; 4322 }; 4323 4324 remoteproc_adsp: remoteproc@6800000 { 4325 compatible = "qcom,x1e80100-adsp-pas"; 4326 reg = <0x0 0x06800000 0x0 0x10000>; 4327 4328 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4329 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4330 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4331 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4332 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4333 interrupt-names = "wdog", 4334 "fatal", 4335 "ready", 4336 "handover", 4337 "stop-ack"; 4338 4339 clocks = <&rpmhcc RPMH_CXO_CLK>; 4340 clock-names = "xo"; 4341 4342 power-domains = <&rpmhpd RPMHPD_LCX>, 4343 <&rpmhpd RPMHPD_LMX>; 4344 power-domain-names = "lcx", 4345 "lmx"; 4346 4347 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4348 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4349 4350 memory-region = <&adspslpi_mem>, 4351 <&q6_adsp_dtb_mem>; 4352 4353 qcom,qmp = <&aoss_qmp>; 4354 4355 qcom,smem-states = <&smp2p_adsp_out 0>; 4356 qcom,smem-state-names = "stop"; 4357 4358 status = "disabled"; 4359 4360 glink-edge { 4361 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4362 IPCC_MPROC_SIGNAL_GLINK_QMP 4363 IRQ_TYPE_EDGE_RISING>; 4364 mboxes = <&ipcc IPCC_CLIENT_LPASS 4365 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4366 4367 label = "lpass"; 4368 qcom,remote-pid = <2>; 4369 4370 fastrpc { 4371 compatible = "qcom,fastrpc"; 4372 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4373 label = "adsp"; 4374 qcom,non-secure-domain; 4375 #address-cells = <1>; 4376 #size-cells = <0>; 4377 4378 compute-cb@3 { 4379 compatible = "qcom,fastrpc-compute-cb"; 4380 reg = <3>; 4381 iommus = <&apps_smmu 0x1003 0x80>, 4382 <&apps_smmu 0x1063 0x0>; 4383 dma-coherent; 4384 }; 4385 4386 compute-cb@4 { 4387 compatible = "qcom,fastrpc-compute-cb"; 4388 reg = <4>; 4389 iommus = <&apps_smmu 0x1004 0x80>, 4390 <&apps_smmu 0x1064 0x0>; 4391 dma-coherent; 4392 }; 4393 4394 compute-cb@5 { 4395 compatible = "qcom,fastrpc-compute-cb"; 4396 reg = <5>; 4397 iommus = <&apps_smmu 0x1005 0x80>, 4398 <&apps_smmu 0x1065 0x0>; 4399 dma-coherent; 4400 }; 4401 4402 compute-cb@6 { 4403 compatible = "qcom,fastrpc-compute-cb"; 4404 reg = <6>; 4405 iommus = <&apps_smmu 0x1006 0x80>, 4406 <&apps_smmu 0x1066 0x0>; 4407 dma-coherent; 4408 }; 4409 4410 compute-cb@7 { 4411 compatible = "qcom,fastrpc-compute-cb"; 4412 reg = <7>; 4413 iommus = <&apps_smmu 0x1007 0x80>, 4414 <&apps_smmu 0x1067 0x0>; 4415 dma-coherent; 4416 }; 4417 }; 4418 4419 gpr { 4420 compatible = "qcom,gpr"; 4421 qcom,glink-channels = "adsp_apps"; 4422 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4423 qcom,intents = <512 20>; 4424 #address-cells = <1>; 4425 #size-cells = <0>; 4426 4427 q6apm: service@1 { 4428 compatible = "qcom,q6apm"; 4429 reg = <GPR_APM_MODULE_IID>; 4430 #sound-dai-cells = <0>; 4431 qcom,protection-domain = "avs/audio", 4432 "msm/adsp/audio_pd"; 4433 4434 q6apmbedai: bedais { 4435 compatible = "qcom,q6apm-lpass-dais"; 4436 #sound-dai-cells = <1>; 4437 }; 4438 4439 q6apmdai: dais { 4440 compatible = "qcom,q6apm-dais"; 4441 iommus = <&apps_smmu 0x1001 0x80>, 4442 <&apps_smmu 0x1061 0x0>; 4443 }; 4444 }; 4445 4446 q6prm: service@2 { 4447 compatible = "qcom,q6prm"; 4448 reg = <GPR_PRM_MODULE_IID>; 4449 qcom,protection-domain = "avs/audio", 4450 "msm/adsp/audio_pd"; 4451 4452 q6prmcc: clock-controller { 4453 compatible = "qcom,q6prm-lpass-clocks"; 4454 #clock-cells = <2>; 4455 }; 4456 }; 4457 }; 4458 }; 4459 }; 4460 4461 lpass_wsa2macro: codec@6aa0000 { 4462 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4463 reg = <0 0x06aa0000 0 0x1000>; 4464 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4465 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4466 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4467 <&lpass_vamacro>; 4468 clock-names = "mclk", 4469 "macro", 4470 "dcodec", 4471 "fsgen"; 4472 4473 #clock-cells = <0>; 4474 clock-output-names = "wsa2-mclk"; 4475 #sound-dai-cells = <1>; 4476 sound-name-prefix = "WSA2"; 4477 }; 4478 4479 swr3: soundwire@6ab0000 { 4480 compatible = "qcom,soundwire-v2.0.0"; 4481 reg = <0 0x06ab0000 0 0x10000>; 4482 clocks = <&lpass_wsa2macro>; 4483 clock-names = "iface"; 4484 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 4485 label = "WSA2"; 4486 4487 pinctrl-0 = <&wsa2_swr_active>; 4488 pinctrl-names = "default"; 4489 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; 4490 reset-names = "swr_audio_cgcr"; 4491 4492 qcom,din-ports = <4>; 4493 qcom,dout-ports = <9>; 4494 4495 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4496 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4497 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4498 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4499 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4500 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4501 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4502 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4503 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4504 4505 #address-cells = <2>; 4506 #size-cells = <0>; 4507 #sound-dai-cells = <1>; 4508 status = "disabled"; 4509 }; 4510 4511 lpass_rxmacro: codec@6ac0000 { 4512 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4513 reg = <0 0x06ac0000 0 0x1000>; 4514 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4515 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4516 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4517 <&lpass_vamacro>; 4518 clock-names = "mclk", 4519 "macro", 4520 "dcodec", 4521 "fsgen"; 4522 4523 #clock-cells = <0>; 4524 clock-output-names = "mclk"; 4525 #sound-dai-cells = <1>; 4526 }; 4527 4528 swr1: soundwire@6ad0000 { 4529 compatible = "qcom,soundwire-v2.0.0"; 4530 reg = <0 0x06ad0000 0 0x10000>; 4531 clocks = <&lpass_rxmacro>; 4532 clock-names = "iface"; 4533 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 4534 label = "RX"; 4535 4536 pinctrl-0 = <&rx_swr_active>; 4537 pinctrl-names = "default"; 4538 4539 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 4540 reset-names = "swr_audio_cgcr"; 4541 qcom,din-ports = <1>; 4542 qcom,dout-ports = <11>; 4543 4544 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4545 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4546 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4547 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4548 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4549 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4550 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4551 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4552 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4553 4554 #address-cells = <2>; 4555 #size-cells = <0>; 4556 #sound-dai-cells = <1>; 4557 status = "disabled"; 4558 }; 4559 4560 lpass_txmacro: codec@6ae0000 { 4561 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4562 reg = <0 0x06ae0000 0 0x1000>; 4563 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4564 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4565 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4566 <&lpass_vamacro>; 4567 clock-names = "mclk", 4568 "macro", 4569 "dcodec", 4570 "fsgen"; 4571 4572 #clock-cells = <0>; 4573 clock-output-names = "mclk"; 4574 #sound-dai-cells = <1>; 4575 }; 4576 4577 lpass_wsamacro: codec@6b00000 { 4578 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4579 reg = <0 0x06b00000 0 0x1000>; 4580 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4581 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4582 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4583 <&lpass_vamacro>; 4584 clock-names = "mclk", 4585 "macro", 4586 "dcodec", 4587 "fsgen"; 4588 4589 #clock-cells = <0>; 4590 clock-output-names = "mclk"; 4591 #sound-dai-cells = <1>; 4592 sound-name-prefix = "WSA"; 4593 }; 4594 4595 swr0: soundwire@6b10000 { 4596 compatible = "qcom,soundwire-v2.0.0"; 4597 reg = <0 0x06b10000 0 0x10000>; 4598 clocks = <&lpass_wsamacro>; 4599 clock-names = "iface"; 4600 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4601 label = "WSA"; 4602 4603 pinctrl-0 = <&wsa_swr_active>; 4604 pinctrl-names = "default"; 4605 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 4606 reset-names = "swr_audio_cgcr"; 4607 4608 qcom,din-ports = <4>; 4609 qcom,dout-ports = <9>; 4610 4611 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4612 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4613 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4614 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4615 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4616 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4617 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4618 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4619 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4620 4621 #address-cells = <2>; 4622 #size-cells = <0>; 4623 #sound-dai-cells = <1>; 4624 status = "disabled"; 4625 }; 4626 4627 lpass_audiocc: clock-controller@6b6c000 { 4628 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; 4629 reg = <0 0x06b6c000 0 0x1000>; 4630 #clock-cells = <1>; 4631 #reset-cells = <1>; 4632 }; 4633 4634 swr2: soundwire@6d30000 { 4635 compatible = "qcom,soundwire-v2.0.0"; 4636 reg = <0 0x06d30000 0 0x10000>; 4637 clocks = <&lpass_txmacro>; 4638 clock-names = "iface"; 4639 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 4640 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 4641 interrupt-names = "core", "wakeup"; 4642 label = "TX"; 4643 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 4644 reset-names = "swr_audio_cgcr"; 4645 4646 pinctrl-0 = <&tx_swr_active>; 4647 pinctrl-names = "default"; 4648 4649 qcom,din-ports = <4>; 4650 qcom,dout-ports = <1>; 4651 4652 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 4653 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 4654 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 4655 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4656 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4657 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4658 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4659 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4660 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 4661 4662 #address-cells = <2>; 4663 #size-cells = <0>; 4664 #sound-dai-cells = <1>; 4665 status = "disabled"; 4666 }; 4667 4668 lpass_vamacro: codec@6d44000 { 4669 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4670 reg = <0 0x06d44000 0 0x1000>; 4671 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4672 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4673 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4674 clock-names = "mclk", 4675 "macro", 4676 "dcodec"; 4677 4678 #clock-cells = <0>; 4679 clock-output-names = "fsgen"; 4680 #sound-dai-cells = <1>; 4681 }; 4682 4683 lpass_tlmm: pinctrl@6e80000 { 4684 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 4685 reg = <0 0x06e80000 0 0x20000>, 4686 <0 0x07250000 0 0x10000>; 4687 4688 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4689 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4690 clock-names = "core", "audio"; 4691 4692 gpio-controller; 4693 #gpio-cells = <2>; 4694 gpio-ranges = <&lpass_tlmm 0 0 23>; 4695 4696 tx_swr_active: tx-swr-active-state { 4697 clk-pins { 4698 pins = "gpio0"; 4699 function = "swr_tx_clk"; 4700 drive-strength = <2>; 4701 slew-rate = <1>; 4702 bias-disable; 4703 }; 4704 4705 data-pins { 4706 pins = "gpio1", "gpio2"; 4707 function = "swr_tx_data"; 4708 drive-strength = <2>; 4709 slew-rate = <1>; 4710 bias-bus-hold; 4711 }; 4712 }; 4713 4714 rx_swr_active: rx-swr-active-state { 4715 clk-pins { 4716 pins = "gpio3"; 4717 function = "swr_rx_clk"; 4718 drive-strength = <2>; 4719 slew-rate = <1>; 4720 bias-disable; 4721 }; 4722 4723 data-pins { 4724 pins = "gpio4", "gpio5"; 4725 function = "swr_rx_data"; 4726 drive-strength = <2>; 4727 slew-rate = <1>; 4728 bias-bus-hold; 4729 }; 4730 }; 4731 4732 dmic01_default: dmic01-default-state { 4733 clk-pins { 4734 pins = "gpio6"; 4735 function = "dmic1_clk"; 4736 drive-strength = <8>; 4737 output-high; 4738 }; 4739 4740 data-pins { 4741 pins = "gpio7"; 4742 function = "dmic1_data"; 4743 drive-strength = <8>; 4744 input-enable; 4745 }; 4746 }; 4747 4748 dmic23_default: dmic23-default-state { 4749 clk-pins { 4750 pins = "gpio8"; 4751 function = "dmic2_clk"; 4752 drive-strength = <8>; 4753 output-high; 4754 }; 4755 4756 data-pins { 4757 pins = "gpio9"; 4758 function = "dmic2_data"; 4759 drive-strength = <8>; 4760 input-enable; 4761 }; 4762 }; 4763 4764 wsa_swr_active: wsa-swr-active-state { 4765 clk-pins { 4766 pins = "gpio10"; 4767 function = "wsa_swr_clk"; 4768 drive-strength = <2>; 4769 slew-rate = <1>; 4770 bias-disable; 4771 }; 4772 4773 data-pins { 4774 pins = "gpio11"; 4775 function = "wsa_swr_data"; 4776 drive-strength = <2>; 4777 slew-rate = <1>; 4778 bias-bus-hold; 4779 }; 4780 }; 4781 4782 wsa2_swr_active: wsa2-swr-active-state { 4783 clk-pins { 4784 pins = "gpio15"; 4785 function = "wsa2_swr_clk"; 4786 drive-strength = <2>; 4787 slew-rate = <1>; 4788 bias-disable; 4789 }; 4790 4791 data-pins { 4792 pins = "gpio16"; 4793 function = "wsa2_swr_data"; 4794 drive-strength = <2>; 4795 slew-rate = <1>; 4796 bias-bus-hold; 4797 }; 4798 }; 4799 }; 4800 4801 lpasscc: clock-controller@6ea0000 { 4802 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; 4803 reg = <0 0x06ea0000 0 0x12000>; 4804 #clock-cells = <1>; 4805 #reset-cells = <1>; 4806 }; 4807 4808 lpass_ag_noc: interconnect@7e40000 { 4809 compatible = "qcom,x1e80100-lpass-ag-noc"; 4810 reg = <0 0x07e40000 0 0xe080>; 4811 4812 qcom,bcm-voters = <&apps_bcm_voter>; 4813 4814 #interconnect-cells = <2>; 4815 }; 4816 4817 lpass_lpiaon_noc: interconnect@7400000 { 4818 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 4819 reg = <0 0x07400000 0 0x19080>; 4820 4821 qcom,bcm-voters = <&apps_bcm_voter>; 4822 4823 #interconnect-cells = <2>; 4824 }; 4825 4826 lpass_lpicx_noc: interconnect@7430000 { 4827 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 4828 reg = <0 0x07430000 0 0x3a200>; 4829 4830 qcom,bcm-voters = <&apps_bcm_voter>; 4831 4832 #interconnect-cells = <2>; 4833 }; 4834 4835 sdhc_2: mmc@8804000 { 4836 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4837 reg = <0 0x08804000 0 0x1000>; 4838 4839 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4840 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4841 interrupt-names = "hc_irq", "pwr_irq"; 4842 4843 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4844 <&gcc GCC_SDCC2_APPS_CLK>, 4845 <&bi_tcxo_div2>; 4846 clock-names = "iface", "core", "xo"; 4847 iommus = <&apps_smmu 0x520 0>; 4848 qcom,dll-config = <0x0007642c>; 4849 qcom,ddr-config = <0x80040868>; 4850 power-domains = <&rpmhpd RPMHPD_CX>; 4851 operating-points-v2 = <&sdhc2_opp_table>; 4852 4853 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4855 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4856 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4857 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4858 bus-width = <4>; 4859 dma-coherent; 4860 4861 status = "disabled"; 4862 4863 sdhc2_opp_table: opp-table { 4864 compatible = "operating-points-v2"; 4865 4866 opp-19200000 { 4867 opp-hz = /bits/ 64 <19200000>; 4868 required-opps = <&rpmhpd_opp_min_svs>; 4869 }; 4870 4871 opp-50000000 { 4872 opp-hz = /bits/ 64 <50000000>; 4873 required-opps = <&rpmhpd_opp_low_svs>; 4874 }; 4875 4876 opp-100000000 { 4877 opp-hz = /bits/ 64 <100000000>; 4878 required-opps = <&rpmhpd_opp_svs>; 4879 }; 4880 4881 opp-202000000 { 4882 opp-hz = /bits/ 64 <202000000>; 4883 required-opps = <&rpmhpd_opp_svs_l1>; 4884 }; 4885 }; 4886 }; 4887 4888 sdhc_4: mmc@8844000 { 4889 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4890 reg = <0 0x08844000 0 0x1000>; 4891 4892 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4893 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 4894 interrupt-names = "hc_irq", "pwr_irq"; 4895 4896 clocks = <&gcc GCC_SDCC4_AHB_CLK>, 4897 <&gcc GCC_SDCC4_APPS_CLK>, 4898 <&bi_tcxo_div2>; 4899 clock-names = "iface", "core", "xo"; 4900 iommus = <&apps_smmu 0x160 0>; 4901 qcom,dll-config = <0x0007642c>; 4902 qcom,ddr-config = <0x80040868>; 4903 power-domains = <&rpmhpd RPMHPD_CX>; 4904 operating-points-v2 = <&sdhc4_opp_table>; 4905 4906 interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS 4907 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4908 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4909 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 4910 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4911 bus-width = <4>; 4912 dma-coherent; 4913 4914 status = "disabled"; 4915 4916 sdhc4_opp_table: opp-table { 4917 compatible = "operating-points-v2"; 4918 4919 opp-19200000 { 4920 opp-hz = /bits/ 64 <19200000>; 4921 required-opps = <&rpmhpd_opp_min_svs>; 4922 }; 4923 4924 opp-50000000 { 4925 opp-hz = /bits/ 64 <50000000>; 4926 required-opps = <&rpmhpd_opp_low_svs>; 4927 }; 4928 4929 opp-100000000 { 4930 opp-hz = /bits/ 64 <100000000>; 4931 required-opps = <&rpmhpd_opp_svs>; 4932 }; 4933 4934 opp-202000000 { 4935 opp-hz = /bits/ 64 <202000000>; 4936 required-opps = <&rpmhpd_opp_svs_l1>; 4937 }; 4938 }; 4939 }; 4940 4941 usb_2_hsphy: phy@88e0000 { 4942 compatible = "qcom,x1e80100-snps-eusb2-phy", 4943 "qcom,sm8550-snps-eusb2-phy"; 4944 reg = <0 0x088e0000 0 0x154>; 4945 #phy-cells = <0>; 4946 4947 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 4948 clock-names = "ref"; 4949 4950 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 4951 4952 status = "disabled"; 4953 }; 4954 4955 usb_mp_hsphy0: phy@88e1000 { 4956 compatible = "qcom,x1e80100-snps-eusb2-phy", 4957 "qcom,sm8550-snps-eusb2-phy"; 4958 reg = <0 0x088e1000 0 0x154>; 4959 #phy-cells = <0>; 4960 4961 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>; 4962 clock-names = "ref"; 4963 4964 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 4965 4966 status = "disabled"; 4967 }; 4968 4969 usb_mp_hsphy1: phy@88e2000 { 4970 compatible = "qcom,x1e80100-snps-eusb2-phy", 4971 "qcom,sm8550-snps-eusb2-phy"; 4972 reg = <0 0x088e2000 0 0x154>; 4973 #phy-cells = <0>; 4974 4975 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>; 4976 clock-names = "ref"; 4977 4978 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 4979 4980 status = "disabled"; 4981 }; 4982 4983 usb_mp_qmpphy0: phy@88e3000 { 4984 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4985 reg = <0 0x088e3000 0 0x2000>; 4986 4987 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4988 <&rpmhcc RPMH_CXO_CLK>, 4989 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4990 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 4991 clock-names = "aux", 4992 "ref", 4993 "com_aux", 4994 "pipe"; 4995 4996 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 4997 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 4998 reset-names = "phy", 4999 "phy_phy"; 5000 5001 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 5002 5003 #clock-cells = <0>; 5004 clock-output-names = "usb_mp_phy0_pipe_clk"; 5005 5006 #phy-cells = <0>; 5007 5008 status = "disabled"; 5009 }; 5010 5011 usb_mp_qmpphy1: phy@88e5000 { 5012 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 5013 reg = <0 0x088e5000 0 0x2000>; 5014 5015 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 5016 <&rpmhcc RPMH_CXO_CLK>, 5017 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 5018 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 5019 clock-names = "aux", 5020 "ref", 5021 "com_aux", 5022 "pipe"; 5023 5024 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 5025 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 5026 reset-names = "phy", 5027 "phy_phy"; 5028 5029 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 5030 5031 #clock-cells = <0>; 5032 clock-output-names = "usb_mp_phy1_pipe_clk"; 5033 5034 #phy-cells = <0>; 5035 5036 status = "disabled"; 5037 }; 5038 5039 usb_1_ss2: usb@a000000 { 5040 compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; 5041 reg = <0 0x0a000000 0 0xfc100>; 5042 5043 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 5044 <&gcc GCC_USB30_TERT_MASTER_CLK>, 5045 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 5046 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 5047 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 5048 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5049 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5050 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5051 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5052 clock-names = "cfg_noc", 5053 "core", 5054 "iface", 5055 "sleep", 5056 "mock_utmi", 5057 "noc_aggr", 5058 "noc_aggr_north", 5059 "noc_aggr_south", 5060 "noc_sys"; 5061 5062 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 5063 <&gcc GCC_USB30_TERT_MASTER_CLK>; 5064 assigned-clock-rates = <19200000>, 5065 <200000000>; 5066 5067 interrupts-extended = <&intc GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 5068 <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 5069 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 5070 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 5071 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 5072 interrupt-names = "dwc_usb3", 5073 "pwr_event", 5074 "dp_hs_phy_irq", 5075 "dm_hs_phy_irq", 5076 "ss_phy_irq"; 5077 5078 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 5079 required-opps = <&rpmhpd_opp_nom>; 5080 5081 resets = <&gcc GCC_USB30_TERT_BCR>; 5082 5083 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 5084 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5085 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5086 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 5087 interconnect-names = "usb-ddr", 5088 "apps-usb"; 5089 5090 wakeup-source; 5091 5092 iommus = <&apps_smmu 0x14a0 0x0>; 5093 5094 phys = <&usb_1_ss2_hsphy>, 5095 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 5096 phy-names = "usb2-phy", 5097 "usb3-phy"; 5098 5099 snps,dis_u2_susphy_quirk; 5100 snps,dis_enblslpm_quirk; 5101 snps,usb3_lpm_capable; 5102 snps,dis-u1-entry-quirk; 5103 snps,dis-u2-entry-quirk; 5104 5105 dma-coherent; 5106 5107 status = "disabled"; 5108 5109 ports { 5110 #address-cells = <1>; 5111 #size-cells = <0>; 5112 5113 port@0 { 5114 reg = <0>; 5115 5116 usb_1_ss2_dwc3_hs: endpoint { 5117 }; 5118 }; 5119 5120 port@1 { 5121 reg = <1>; 5122 5123 usb_1_ss2_dwc3_ss: endpoint { 5124 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; 5125 }; 5126 }; 5127 }; 5128 }; 5129 5130 usb_2: usb@a200000 { 5131 compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; 5132 reg = <0 0x0a200000 0 0xfc100>; 5133 5134 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 5135 <&gcc GCC_USB20_MASTER_CLK>, 5136 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 5137 <&gcc GCC_USB20_SLEEP_CLK>, 5138 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5139 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5140 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5141 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5142 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5143 clock-names = "cfg_noc", 5144 "core", 5145 "iface", 5146 "sleep", 5147 "mock_utmi", 5148 "noc_aggr", 5149 "noc_aggr_north", 5150 "noc_aggr_south", 5151 "noc_sys"; 5152 5153 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5154 <&gcc GCC_USB20_MASTER_CLK>; 5155 assigned-clock-rates = <19200000>, <200000000>; 5156 5157 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 5158 <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 5159 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 5160 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 5161 interrupt-names = "dwc_usb3", 5162 "pwr_event", 5163 "dp_hs_phy_irq", 5164 "dm_hs_phy_irq"; 5165 5166 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 5167 required-opps = <&rpmhpd_opp_nom>; 5168 5169 resets = <&gcc GCC_USB20_PRIM_BCR>; 5170 5171 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 5172 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5173 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5174 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 5175 interconnect-names = "usb-ddr", 5176 "apps-usb"; 5177 5178 qcom,select-utmi-as-pipe-clk; 5179 wakeup-source; 5180 5181 iommus = <&apps_smmu 0x14e0 0x0>; 5182 phys = <&usb_2_hsphy>; 5183 phy-names = "usb2-phy"; 5184 maximum-speed = "high-speed"; 5185 snps,dis-u1-entry-quirk; 5186 snps,dis-u2-entry-quirk; 5187 5188 dma-coherent; 5189 5190 status = "disabled"; 5191 5192 port { 5193 usb_2_dwc3_hs: endpoint { 5194 }; 5195 }; 5196 }; 5197 5198 usb_mp: usb@a400000 { 5199 compatible = "qcom,x1e80100-dwc3-mp", "qcom,snps-dwc3"; 5200 reg = <0 0x0a400000 0 0xfc100>; 5201 5202 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 5203 <&gcc GCC_USB30_MP_MASTER_CLK>, 5204 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 5205 <&gcc GCC_USB30_MP_SLEEP_CLK>, 5206 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 5207 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5208 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5209 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5210 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5211 clock-names = "cfg_noc", 5212 "core", 5213 "iface", 5214 "sleep", 5215 "mock_utmi", 5216 "noc_aggr", 5217 "noc_aggr_north", 5218 "noc_aggr_south", 5219 "noc_sys"; 5220 5221 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 5222 <&gcc GCC_USB30_MP_MASTER_CLK>; 5223 assigned-clock-rates = <19200000>, 5224 <200000000>; 5225 5226 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 5227 <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 5228 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 5229 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 5230 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 5231 <&pdc 52 IRQ_TYPE_EDGE_BOTH>, 5232 <&pdc 51 IRQ_TYPE_EDGE_BOTH>, 5233 <&pdc 54 IRQ_TYPE_EDGE_BOTH>, 5234 <&pdc 53 IRQ_TYPE_EDGE_BOTH>, 5235 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, 5236 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; 5237 interrupt-names = "dwc_usb3", 5238 "pwr_event_1", "pwr_event_2", 5239 "hs_phy_1", "hs_phy_2", 5240 "dp_hs_phy_1", "dm_hs_phy_1", 5241 "dp_hs_phy_2", "dm_hs_phy_2", 5242 "ss_phy_1", "ss_phy_2"; 5243 5244 power-domains = <&gcc GCC_USB30_MP_GDSC>; 5245 required-opps = <&rpmhpd_opp_nom>; 5246 5247 resets = <&gcc GCC_USB30_MP_BCR>; 5248 5249 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS 5250 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5251 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5252 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>; 5253 interconnect-names = "usb-ddr", 5254 "apps-usb"; 5255 5256 wakeup-source; 5257 5258 iommus = <&apps_smmu 0x1400 0x0>; 5259 5260 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, 5261 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; 5262 phy-names = "usb2-0", "usb3-0", 5263 "usb2-1", "usb3-1"; 5264 dr_mode = "host"; 5265 5266 snps,dis_u2_susphy_quirk; 5267 snps,dis_enblslpm_quirk; 5268 snps,usb3_lpm_capable; 5269 snps,dis-u1-entry-quirk; 5270 snps,dis-u2-entry-quirk; 5271 5272 dma-coherent; 5273 5274 status = "disabled"; 5275 }; 5276 5277 usb_1_ss0: usb@a600000 { 5278 compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; 5279 reg = <0 0x0a600000 0 0xfc100>; 5280 5281 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5282 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5283 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5284 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5285 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5286 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5287 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 5288 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 5289 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5290 clock-names = "cfg_noc", 5291 "core", 5292 "iface", 5293 "sleep", 5294 "mock_utmi", 5295 "noc_aggr", 5296 "noc_aggr_north", 5297 "noc_aggr_south", 5298 "noc_sys"; 5299 5300 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5301 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5302 assigned-clock-rates = <19200000>, 5303 <200000000>; 5304 5305 interrupts-extended = <&intc GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 5306 <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 5307 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 5308 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5309 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5310 interrupt-names = "dwc_usb3", 5311 "pwr_event", 5312 "dp_hs_phy_irq", 5313 "dm_hs_phy_irq", 5314 "ss_phy_irq"; 5315 5316 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 5317 required-opps = <&rpmhpd_opp_nom>; 5318 5319 resets = <&gcc GCC_USB30_PRIM_BCR>; 5320 5321 wakeup-source; 5322 5323 iommus = <&apps_smmu 0x1420 0x0>; 5324 5325 phys = <&usb_1_ss0_hsphy>, 5326 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 5327 phy-names = "usb2-phy", 5328 "usb3-phy"; 5329 5330 snps,dis_u2_susphy_quirk; 5331 snps,dis_enblslpm_quirk; 5332 snps,usb3_lpm_capable; 5333 snps,dis-u1-entry-quirk; 5334 snps,dis-u2-entry-quirk; 5335 5336 dma-coherent; 5337 5338 status = "disabled"; 5339 5340 ports { 5341 #address-cells = <1>; 5342 #size-cells = <0>; 5343 5344 port@0 { 5345 reg = <0>; 5346 5347 usb_1_ss0_dwc3_hs: endpoint { 5348 }; 5349 }; 5350 5351 port@1 { 5352 reg = <1>; 5353 5354 usb_1_ss0_dwc3_ss: endpoint { 5355 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; 5356 }; 5357 }; 5358 }; 5359 }; 5360 5361 usb_1_ss1: usb@a800000 { 5362 compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; 5363 reg = <0 0x0a800000 0 0xfc100>; 5364 5365 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 5366 <&gcc GCC_USB30_SEC_MASTER_CLK>, 5367 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 5368 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 5369 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5370 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5371 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5372 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5373 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5374 clock-names = "cfg_noc", 5375 "core", 5376 "iface", 5377 "sleep", 5378 "mock_utmi", 5379 "noc_aggr", 5380 "noc_aggr_north", 5381 "noc_aggr_south", 5382 "noc_sys"; 5383 5384 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5385 <&gcc GCC_USB30_SEC_MASTER_CLK>; 5386 assigned-clock-rates = <19200000>, 5387 <200000000>; 5388 5389 interrupts-extended = <&intc GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 5390 <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 5391 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 5392 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 5393 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 5394 interrupt-names = "dwc_usb3", 5395 "pwr_event", 5396 "dp_hs_phy_irq", 5397 "dm_hs_phy_irq", 5398 "ss_phy_irq"; 5399 5400 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 5401 required-opps = <&rpmhpd_opp_nom>; 5402 5403 resets = <&gcc GCC_USB30_SEC_BCR>; 5404 5405 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 5406 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5407 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5408 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5409 interconnect-names = "usb-ddr", 5410 "apps-usb"; 5411 5412 wakeup-source; 5413 5414 iommus = <&apps_smmu 0x1460 0x0>; 5415 5416 phys = <&usb_1_ss1_hsphy>, 5417 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 5418 phy-names = "usb2-phy", 5419 "usb3-phy"; 5420 5421 snps,dis_u2_susphy_quirk; 5422 snps,dis_enblslpm_quirk; 5423 snps,usb3_lpm_capable; 5424 snps,dis-u1-entry-quirk; 5425 snps,dis-u2-entry-quirk; 5426 5427 dma-coherent; 5428 5429 status = "disabled"; 5430 5431 ports { 5432 #address-cells = <1>; 5433 #size-cells = <0>; 5434 5435 port@0 { 5436 reg = <0>; 5437 5438 usb_1_ss1_dwc3_hs: endpoint { 5439 }; 5440 }; 5441 5442 port@1 { 5443 reg = <1>; 5444 5445 usb_1_ss1_dwc3_ss: endpoint { 5446 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 5447 }; 5448 }; 5449 }; 5450 }; 5451 5452 iris: video-codec@aa00000 { 5453 compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris"; 5454 5455 reg = <0 0x0aa00000 0 0xf0000>; 5456 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 5457 5458 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5459 <&videocc VIDEO_CC_MVS0_GDSC>, 5460 <&rpmhpd RPMHPD_MXC>, 5461 <&rpmhpd RPMHPD_MMCX>; 5462 power-domain-names = "venus", 5463 "vcodec0", 5464 "mxc", 5465 "mmcx"; 5466 operating-points-v2 = <&iris_opp_table>; 5467 5468 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5469 <&videocc VIDEO_CC_MVS0C_CLK>, 5470 <&videocc VIDEO_CC_MVS0_CLK>; 5471 clock-names = "iface", 5472 "core", 5473 "vcodec0_core"; 5474 5475 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5476 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5477 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 5478 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5479 interconnect-names = "cpu-cfg", 5480 "video-mem"; 5481 5482 memory-region = <&video_mem>; 5483 5484 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 5485 reset-names = "bus"; 5486 5487 iommus = <&apps_smmu 0x1940 0>, 5488 <&apps_smmu 0x1947 0>; 5489 dma-coherent; 5490 5491 /* 5492 * IRIS firmware is signed by vendors, only 5493 * enable on boards where the proper signed firmware 5494 * is available. 5495 */ 5496 status = "disabled"; 5497 5498 iris_opp_table: opp-table { 5499 compatible = "operating-points-v2"; 5500 5501 opp-192000000 { 5502 opp-hz = /bits/ 64 <192000000>; 5503 required-opps = <&rpmhpd_opp_low_svs_d1>, 5504 <&rpmhpd_opp_low_svs_d1>; 5505 }; 5506 5507 opp-240000000 { 5508 opp-hz = /bits/ 64 <240000000>; 5509 required-opps = <&rpmhpd_opp_svs>, 5510 <&rpmhpd_opp_low_svs>; 5511 }; 5512 5513 opp-338000000 { 5514 opp-hz = /bits/ 64 <338000000>; 5515 required-opps = <&rpmhpd_opp_svs>, 5516 <&rpmhpd_opp_svs>; 5517 }; 5518 5519 opp-366000000 { 5520 opp-hz = /bits/ 64 <366000000>; 5521 required-opps = <&rpmhpd_opp_svs>, 5522 <&rpmhpd_opp_svs_l1>; 5523 }; 5524 5525 opp-444000000 { 5526 opp-hz = /bits/ 64 <444000000>; 5527 required-opps = <&rpmhpd_opp_svs_l1>, 5528 <&rpmhpd_opp_nom>; 5529 }; 5530 5531 opp-481000000 { 5532 opp-hz = /bits/ 64 <481000000>; 5533 required-opps = <&rpmhpd_opp_svs_l1>, 5534 <&rpmhpd_opp_turbo>; 5535 }; 5536 }; 5537 }; 5538 5539 videocc: clock-controller@aaf0000 { 5540 compatible = "qcom,x1e80100-videocc"; 5541 reg = <0 0x0aaf0000 0 0x10000>; 5542 clocks = <&bi_tcxo_div2>, 5543 <&gcc GCC_VIDEO_AHB_CLK>; 5544 power-domains = <&rpmhpd RPMHPD_MMCX>, 5545 <&rpmhpd RPMHPD_MXC>; 5546 required-opps = <&rpmhpd_opp_low_svs>, 5547 <&rpmhpd_opp_low_svs>; 5548 #clock-cells = <1>; 5549 #reset-cells = <1>; 5550 #power-domain-cells = <1>; 5551 }; 5552 5553 mdss: display-subsystem@ae00000 { 5554 compatible = "qcom,x1e80100-mdss"; 5555 reg = <0 0x0ae00000 0 0x1000>; 5556 reg-names = "mdss"; 5557 5558 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5559 5560 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5561 <&gcc GCC_DISP_HF_AXI_CLK>, 5562 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5563 5564 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5565 5566 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5567 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 5568 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 5569 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5570 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5571 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5572 interconnect-names = "mdp0-mem", 5573 "mdp1-mem", 5574 "cpu-cfg"; 5575 5576 power-domains = <&dispcc MDSS_GDSC>; 5577 5578 iommus = <&apps_smmu 0x1c00 0x2>; 5579 5580 interrupt-controller; 5581 #interrupt-cells = <1>; 5582 5583 #address-cells = <2>; 5584 #size-cells = <2>; 5585 ranges; 5586 5587 status = "disabled"; 5588 5589 mdss_mdp: display-controller@ae01000 { 5590 compatible = "qcom,x1e80100-dpu"; 5591 reg = <0 0x0ae01000 0 0x8f000>, 5592 <0 0x0aeb0000 0 0x2008>; 5593 reg-names = "mdp", 5594 "vbif"; 5595 5596 interrupts-extended = <&mdss 0>; 5597 5598 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5599 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5600 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5601 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5602 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5603 clock-names = "nrt_bus", 5604 "iface", 5605 "lut", 5606 "core", 5607 "vsync"; 5608 5609 operating-points-v2 = <&mdp_opp_table>; 5610 5611 power-domains = <&rpmhpd RPMHPD_MMCX>; 5612 5613 ports { 5614 #address-cells = <1>; 5615 #size-cells = <0>; 5616 5617 port@0 { 5618 reg = <0>; 5619 5620 mdss_intf0_out: endpoint { 5621 remote-endpoint = <&mdss_dp0_in>; 5622 }; 5623 }; 5624 5625 port@4 { 5626 reg = <4>; 5627 5628 mdss_intf4_out: endpoint { 5629 remote-endpoint = <&mdss_dp1_in>; 5630 }; 5631 }; 5632 5633 port@5 { 5634 reg = <5>; 5635 5636 mdss_intf5_out: endpoint { 5637 remote-endpoint = <&mdss_dp3_in>; 5638 }; 5639 }; 5640 5641 port@6 { 5642 reg = <6>; 5643 5644 mdss_intf6_out: endpoint { 5645 remote-endpoint = <&mdss_dp2_in>; 5646 }; 5647 }; 5648 }; 5649 5650 mdp_opp_table: opp-table { 5651 compatible = "operating-points-v2"; 5652 5653 opp-200000000 { 5654 opp-hz = /bits/ 64 <200000000>; 5655 required-opps = <&rpmhpd_opp_low_svs>; 5656 }; 5657 5658 opp-325000000 { 5659 opp-hz = /bits/ 64 <325000000>; 5660 required-opps = <&rpmhpd_opp_svs>; 5661 }; 5662 5663 opp-375000000 { 5664 opp-hz = /bits/ 64 <375000000>; 5665 required-opps = <&rpmhpd_opp_svs_l1>; 5666 }; 5667 5668 opp-514000000 { 5669 opp-hz = /bits/ 64 <514000000>; 5670 required-opps = <&rpmhpd_opp_nom>; 5671 }; 5672 5673 opp-575000000 { 5674 opp-hz = /bits/ 64 <575000000>; 5675 required-opps = <&rpmhpd_opp_nom_l1>; 5676 }; 5677 }; 5678 }; 5679 5680 mdss_dp0: displayport-controller@ae90000 { 5681 compatible = "qcom,x1e80100-dp"; 5682 reg = <0 0x0ae90000 0 0x200>, 5683 <0 0x0ae90200 0 0x200>, 5684 <0 0x0ae90400 0 0xc00>, 5685 <0 0x0ae91000 0 0x400>, 5686 <0 0x0ae91400 0 0x400>; 5687 5688 interrupts-extended = <&mdss 12>; 5689 5690 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5691 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5692 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5693 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5694 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5695 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 5696 clock-names = "core_iface", 5697 "core_aux", 5698 "ctrl_link", 5699 "ctrl_link_iface", 5700 "stream_pixel", 5701 "stream_1_pixel"; 5702 5703 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5704 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5705 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 5706 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5707 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5708 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5709 5710 operating-points-v2 = <&mdss_dp0_opp_table>; 5711 5712 power-domains = <&rpmhpd RPMHPD_MMCX>; 5713 5714 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 5715 phy-names = "dp"; 5716 5717 #sound-dai-cells = <0>; 5718 sound-name-prefix = "DisplayPort0"; 5719 5720 status = "disabled"; 5721 5722 ports { 5723 #address-cells = <1>; 5724 #size-cells = <0>; 5725 5726 port@0 { 5727 reg = <0>; 5728 5729 mdss_dp0_in: endpoint { 5730 remote-endpoint = <&mdss_intf0_out>; 5731 }; 5732 }; 5733 5734 port@1 { 5735 reg = <1>; 5736 5737 mdss_dp0_out: endpoint { 5738 data-lanes = <0 1 2 3>; 5739 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; 5740 }; 5741 }; 5742 }; 5743 5744 mdss_dp0_opp_table: opp-table { 5745 compatible = "operating-points-v2"; 5746 5747 opp-162000000 { 5748 opp-hz = /bits/ 64 <162000000>; 5749 required-opps = <&rpmhpd_opp_low_svs>; 5750 }; 5751 5752 opp-270000000 { 5753 opp-hz = /bits/ 64 <270000000>; 5754 required-opps = <&rpmhpd_opp_svs>; 5755 }; 5756 5757 opp-540000000 { 5758 opp-hz = /bits/ 64 <540000000>; 5759 required-opps = <&rpmhpd_opp_svs_l1>; 5760 }; 5761 5762 opp-810000000 { 5763 opp-hz = /bits/ 64 <810000000>; 5764 required-opps = <&rpmhpd_opp_nom>; 5765 }; 5766 }; 5767 }; 5768 5769 mdss_dp1: displayport-controller@ae98000 { 5770 compatible = "qcom,x1e80100-dp"; 5771 reg = <0 0x0ae98000 0 0x200>, 5772 <0 0x0ae98200 0 0x200>, 5773 <0 0x0ae98400 0 0xc00>, 5774 <0 0x0ae99000 0 0x400>, 5775 <0 0x0ae99400 0 0x400>; 5776 5777 interrupts-extended = <&mdss 13>; 5778 5779 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5780 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 5781 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 5782 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5783 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5784 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5785 clock-names = "core_iface", 5786 "core_aux", 5787 "ctrl_link", 5788 "ctrl_link_iface", 5789 "stream_pixel", 5790 "stream_1_pixel"; 5791 5792 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5793 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5794 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5795 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5796 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5797 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5798 5799 operating-points-v2 = <&mdss_dp1_opp_table>; 5800 5801 power-domains = <&rpmhpd RPMHPD_MMCX>; 5802 5803 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 5804 phy-names = "dp"; 5805 5806 #sound-dai-cells = <0>; 5807 sound-name-prefix = "DisplayPort1"; 5808 5809 status = "disabled"; 5810 5811 ports { 5812 #address-cells = <1>; 5813 #size-cells = <0>; 5814 5815 port@0 { 5816 reg = <0>; 5817 5818 mdss_dp1_in: endpoint { 5819 remote-endpoint = <&mdss_intf4_out>; 5820 }; 5821 }; 5822 5823 port@1 { 5824 reg = <1>; 5825 5826 mdss_dp1_out: endpoint { 5827 data-lanes = <0 1 2 3>; 5828 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; 5829 }; 5830 }; 5831 }; 5832 5833 mdss_dp1_opp_table: opp-table { 5834 compatible = "operating-points-v2"; 5835 5836 opp-162000000 { 5837 opp-hz = /bits/ 64 <162000000>; 5838 required-opps = <&rpmhpd_opp_low_svs>; 5839 }; 5840 5841 opp-270000000 { 5842 opp-hz = /bits/ 64 <270000000>; 5843 required-opps = <&rpmhpd_opp_svs>; 5844 }; 5845 5846 opp-540000000 { 5847 opp-hz = /bits/ 64 <540000000>; 5848 required-opps = <&rpmhpd_opp_svs_l1>; 5849 }; 5850 5851 opp-810000000 { 5852 opp-hz = /bits/ 64 <810000000>; 5853 required-opps = <&rpmhpd_opp_nom>; 5854 }; 5855 }; 5856 }; 5857 5858 mdss_dp2: displayport-controller@ae9a000 { 5859 compatible = "qcom,x1e80100-dp"; 5860 reg = <0 0x0ae9a000 0 0x200>, 5861 <0 0x0ae9a200 0 0x200>, 5862 <0 0x0ae9a400 0 0xc00>, 5863 <0 0x0ae9b000 0 0x400>, 5864 <0 0x0ae9b400 0 0x400>; 5865 5866 interrupts-extended = <&mdss 14>; 5867 5868 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5869 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5870 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 5871 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5872 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 5873 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 5874 clock-names = "core_iface", 5875 "core_aux", 5876 "ctrl_link", 5877 "ctrl_link_iface", 5878 "stream_pixel", 5879 "stream_1_pixel"; 5880 5881 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5882 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 5883 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 5884 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5885 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5886 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5887 5888 operating-points-v2 = <&mdss_dp2_opp_table>; 5889 5890 power-domains = <&rpmhpd RPMHPD_MMCX>; 5891 5892 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; 5893 phy-names = "dp"; 5894 5895 #sound-dai-cells = <0>; 5896 sound-name-prefix = "DisplayPort2"; 5897 5898 status = "disabled"; 5899 5900 ports { 5901 #address-cells = <1>; 5902 #size-cells = <0>; 5903 5904 port@0 { 5905 reg = <0>; 5906 mdss_dp2_in: endpoint { 5907 remote-endpoint = <&mdss_intf6_out>; 5908 }; 5909 }; 5910 5911 port@1 { 5912 reg = <1>; 5913 5914 mdss_dp2_out: endpoint { 5915 data-lanes = <0 1 2 3>; 5916 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; 5917 }; 5918 }; 5919 }; 5920 5921 mdss_dp2_opp_table: opp-table { 5922 compatible = "operating-points-v2"; 5923 5924 opp-162000000 { 5925 opp-hz = /bits/ 64 <162000000>; 5926 required-opps = <&rpmhpd_opp_low_svs>; 5927 }; 5928 5929 opp-270000000 { 5930 opp-hz = /bits/ 64 <270000000>; 5931 required-opps = <&rpmhpd_opp_svs>; 5932 }; 5933 5934 opp-540000000 { 5935 opp-hz = /bits/ 64 <540000000>; 5936 required-opps = <&rpmhpd_opp_svs_l1>; 5937 }; 5938 5939 opp-810000000 { 5940 opp-hz = /bits/ 64 <810000000>; 5941 required-opps = <&rpmhpd_opp_nom>; 5942 }; 5943 }; 5944 }; 5945 5946 mdss_dp3: displayport-controller@aea0000 { 5947 compatible = "qcom,x1e80100-dp"; 5948 reg = <0 0x0aea0000 0 0x200>, 5949 <0 0x0aea0200 0 0x200>, 5950 <0 0x0aea0400 0 0xc00>, 5951 <0 0x0aea1000 0 0x400>, 5952 <0 0x0aea1400 0 0x400>; 5953 5954 interrupts-extended = <&mdss 15>; 5955 5956 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5957 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5958 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 5959 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5960 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5961 clock-names = "core_iface", 5962 "core_aux", 5963 "ctrl_link", 5964 "ctrl_link_iface", 5965 "stream_pixel"; 5966 5967 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5968 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5969 assigned-clock-parents = <&mdss_dp3_phy 0>, 5970 <&mdss_dp3_phy 1>; 5971 5972 operating-points-v2 = <&mdss_dp3_opp_table>; 5973 5974 power-domains = <&rpmhpd RPMHPD_MMCX>; 5975 5976 phys = <&mdss_dp3_phy>; 5977 phy-names = "dp"; 5978 5979 #sound-dai-cells = <0>; 5980 sound-name-prefix = "DisplayPort3"; 5981 5982 status = "disabled"; 5983 5984 ports { 5985 #address-cells = <1>; 5986 #size-cells = <0>; 5987 5988 port@0 { 5989 reg = <0>; 5990 5991 mdss_dp3_in: endpoint { 5992 remote-endpoint = <&mdss_intf5_out>; 5993 }; 5994 }; 5995 5996 port@1 { 5997 reg = <1>; 5998 5999 mdss_dp3_out: endpoint { 6000 }; 6001 }; 6002 }; 6003 6004 mdss_dp3_opp_table: opp-table { 6005 compatible = "operating-points-v2"; 6006 6007 opp-162000000 { 6008 opp-hz = /bits/ 64 <162000000>; 6009 required-opps = <&rpmhpd_opp_low_svs>; 6010 }; 6011 6012 opp-270000000 { 6013 opp-hz = /bits/ 64 <270000000>; 6014 required-opps = <&rpmhpd_opp_svs>; 6015 }; 6016 6017 opp-540000000 { 6018 opp-hz = /bits/ 64 <540000000>; 6019 required-opps = <&rpmhpd_opp_svs_l1>; 6020 }; 6021 6022 opp-810000000 { 6023 opp-hz = /bits/ 64 <810000000>; 6024 required-opps = <&rpmhpd_opp_nom>; 6025 }; 6026 }; 6027 }; 6028 6029 }; 6030 6031 mdss_dp2_phy: phy@aec2a00 { 6032 compatible = "qcom,x1e80100-dp-phy"; 6033 reg = <0 0x0aec2a00 0 0x19c>, 6034 <0 0x0aec2200 0 0xec>, 6035 <0 0x0aec2600 0 0xec>, 6036 <0 0x0aec2000 0 0x1c8>; 6037 6038 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 6039 <&dispcc DISP_CC_MDSS_AHB_CLK>, 6040 <&tcsr TCSR_EDP_CLKREF_EN>; 6041 clock-names = "aux", 6042 "cfg_ahb", 6043 "ref"; 6044 6045 power-domains = <&rpmhpd RPMHPD_MX>; 6046 6047 #clock-cells = <1>; 6048 #phy-cells = <0>; 6049 6050 status = "disabled"; 6051 }; 6052 6053 mdss_dp3_phy: phy@aec5a00 { 6054 compatible = "qcom,x1e80100-dp-phy"; 6055 reg = <0 0x0aec5a00 0 0x19c>, 6056 <0 0x0aec5200 0 0xec>, 6057 <0 0x0aec5600 0 0xec>, 6058 <0 0x0aec5000 0 0x1c8>; 6059 6060 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 6061 <&dispcc DISP_CC_MDSS_AHB_CLK>, 6062 <&tcsr TCSR_EDP_CLKREF_EN>; 6063 clock-names = "aux", 6064 "cfg_ahb", 6065 "ref"; 6066 6067 power-domains = <&rpmhpd RPMHPD_MX>; 6068 6069 #clock-cells = <1>; 6070 #phy-cells = <0>; 6071 6072 status = "disabled"; 6073 }; 6074 6075 dispcc: clock-controller@af00000 { 6076 compatible = "qcom,x1e80100-dispcc"; 6077 reg = <0 0x0af00000 0 0x20000>; 6078 clocks = <&bi_tcxo_div2>, 6079 <&bi_tcxo_ao_div2>, 6080 <&gcc GCC_DISP_AHB_CLK>, 6081 <&sleep_clk>, 6082 <0>, /* dsi0 */ 6083 <0>, 6084 <0>, /* dsi1 */ 6085 <0>, 6086 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 6087 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 6088 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 6089 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 6090 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 6091 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 6092 <&mdss_dp3_phy 0>, /* dp3 */ 6093 <&mdss_dp3_phy 1>; 6094 power-domains = <&rpmhpd RPMHPD_MMCX>; 6095 required-opps = <&rpmhpd_opp_low_svs>; 6096 #clock-cells = <1>; 6097 #reset-cells = <1>; 6098 #power-domain-cells = <1>; 6099 }; 6100 6101 pdc: interrupt-controller@b220000 { 6102 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 6103 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 6104 6105 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 6106 <47 522 52>, <99 609 32>, 6107 <131 717 12>, <143 816 19>; 6108 #interrupt-cells = <2>; 6109 interrupt-parent = <&intc>; 6110 interrupt-controller; 6111 }; 6112 6113 aoss_qmp: power-management@c300000 { 6114 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 6115 reg = <0 0x0c300000 0 0x400>; 6116 interrupt-parent = <&ipcc>; 6117 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 6118 IRQ_TYPE_EDGE_RISING>; 6119 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 6120 6121 #clock-cells = <0>; 6122 }; 6123 6124 sram@c3f0000 { 6125 compatible = "qcom,rpmh-stats"; 6126 reg = <0 0x0c3f0000 0 0x400>; 6127 }; 6128 6129 spmi: arbiter@c400000 { 6130 compatible = "qcom,x1e80100-spmi-pmic-arb"; 6131 reg = <0 0x0c400000 0 0x3000>, 6132 <0 0x0c500000 0 0x400000>, 6133 <0 0x0c440000 0 0x80000>; 6134 reg-names = "core", "chnls", "obsrvr"; 6135 6136 qcom,ee = <0>; 6137 qcom,channel = <0>; 6138 6139 #address-cells = <2>; 6140 #size-cells = <2>; 6141 ranges; 6142 6143 spmi_bus0: spmi@c42d000 { 6144 reg = <0 0x0c42d000 0 0x4000>, 6145 <0 0x0c4c0000 0 0x10000>; 6146 reg-names = "cnfg", "intr"; 6147 6148 interrupt-names = "periph_irq"; 6149 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 6150 interrupt-controller; 6151 #interrupt-cells = <4>; 6152 6153 #address-cells = <2>; 6154 #size-cells = <0>; 6155 }; 6156 6157 spmi_bus1: spmi@c432000 { 6158 reg = <0 0x0c432000 0 0x4000>, 6159 <0 0x0c4d0000 0 0x10000>; 6160 reg-names = "cnfg", "intr"; 6161 6162 interrupt-names = "periph_irq"; 6163 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 6164 interrupt-controller; 6165 #interrupt-cells = <4>; 6166 6167 #address-cells = <2>; 6168 #size-cells = <0>; 6169 }; 6170 }; 6171 6172 tlmm: pinctrl@f100000 { 6173 compatible = "qcom,x1e80100-tlmm"; 6174 reg = <0 0x0f100000 0 0xf00000>; 6175 6176 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 6177 6178 gpio-controller; 6179 #gpio-cells = <2>; 6180 6181 interrupt-controller; 6182 #interrupt-cells = <2>; 6183 6184 gpio-ranges = <&tlmm 0 0 239>; 6185 wakeup-parent = <&pdc>; 6186 6187 edp0_hpd_default: edp0-hpd-default-state { 6188 pins = "gpio119"; 6189 function = "edp0_hot"; 6190 bias-disable; 6191 }; 6192 6193 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6194 /* SDA, SCL */ 6195 pins = "gpio0", "gpio1"; 6196 function = "qup0_se0"; 6197 drive-strength = <2>; 6198 bias-pull-up = <2200>; 6199 }; 6200 6201 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6202 /* SDA, SCL */ 6203 pins = "gpio4", "gpio5"; 6204 function = "qup0_se1"; 6205 drive-strength = <2>; 6206 bias-pull-up = <2200>; 6207 }; 6208 6209 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6210 /* SDA, SCL */ 6211 pins = "gpio8", "gpio9"; 6212 function = "qup0_se2"; 6213 drive-strength = <2>; 6214 bias-pull-up = <2200>; 6215 }; 6216 6217 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6218 /* SDA, SCL */ 6219 pins = "gpio12", "gpio13"; 6220 function = "qup0_se3"; 6221 drive-strength = <2>; 6222 bias-pull-up = <2200>; 6223 }; 6224 6225 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6226 /* SDA, SCL */ 6227 pins = "gpio16", "gpio17"; 6228 function = "qup0_se4"; 6229 drive-strength = <2>; 6230 bias-pull-up = <2200>; 6231 }; 6232 6233 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6234 /* SDA, SCL */ 6235 pins = "gpio20", "gpio21"; 6236 function = "qup0_se5"; 6237 drive-strength = <2>; 6238 bias-pull-up = <2200>; 6239 }; 6240 6241 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6242 /* SDA, SCL */ 6243 pins = "gpio24", "gpio25"; 6244 function = "qup0_se6"; 6245 drive-strength = <2>; 6246 bias-pull-up = <2200>; 6247 }; 6248 6249 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 6250 /* SDA, SCL */ 6251 pins = "gpio14", "gpio15"; 6252 function = "qup0_se7"; 6253 drive-strength = <2>; 6254 bias-pull-up = <2200>; 6255 }; 6256 6257 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6258 /* SDA, SCL */ 6259 pins = "gpio32", "gpio33"; 6260 function = "qup1_se0"; 6261 drive-strength = <2>; 6262 bias-pull-up = <2200>; 6263 }; 6264 6265 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6266 /* SDA, SCL */ 6267 pins = "gpio36", "gpio37"; 6268 function = "qup1_se1"; 6269 drive-strength = <2>; 6270 bias-pull-up = <2200>; 6271 }; 6272 6273 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6274 /* SDA, SCL */ 6275 pins = "gpio40", "gpio41"; 6276 function = "qup1_se2"; 6277 drive-strength = <2>; 6278 bias-pull-up = <2200>; 6279 }; 6280 6281 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6282 /* SDA, SCL */ 6283 pins = "gpio44", "gpio45"; 6284 function = "qup1_se3"; 6285 drive-strength = <2>; 6286 bias-pull-up = <2200>; 6287 }; 6288 6289 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6290 /* SDA, SCL */ 6291 pins = "gpio48", "gpio49"; 6292 function = "qup1_se4"; 6293 drive-strength = <2>; 6294 bias-pull-up = <2200>; 6295 }; 6296 6297 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6298 /* SDA, SCL */ 6299 pins = "gpio52", "gpio53"; 6300 function = "qup1_se5"; 6301 drive-strength = <2>; 6302 bias-pull-up = <2200>; 6303 }; 6304 6305 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6306 /* SDA, SCL */ 6307 pins = "gpio56", "gpio57"; 6308 function = "qup1_se6"; 6309 drive-strength = <2>; 6310 bias-pull-up = <2200>; 6311 }; 6312 6313 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 6314 /* SDA, SCL */ 6315 pins = "gpio54", "gpio55"; 6316 function = "qup1_se7"; 6317 drive-strength = <2>; 6318 bias-pull-up = <2200>; 6319 }; 6320 6321 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 6322 /* SDA, SCL */ 6323 pins = "gpio64", "gpio65"; 6324 function = "qup2_se0"; 6325 drive-strength = <2>; 6326 bias-pull-up = <2200>; 6327 }; 6328 6329 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 6330 /* SDA, SCL */ 6331 pins = "gpio68", "gpio69"; 6332 function = "qup2_se1"; 6333 drive-strength = <2>; 6334 bias-pull-up = <2200>; 6335 }; 6336 6337 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 6338 /* SDA, SCL */ 6339 pins = "gpio72", "gpio73"; 6340 function = "qup2_se2"; 6341 drive-strength = <2>; 6342 bias-pull-up = <2200>; 6343 }; 6344 6345 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 6346 /* SDA, SCL */ 6347 pins = "gpio76", "gpio77"; 6348 function = "qup2_se3"; 6349 drive-strength = <2>; 6350 bias-pull-up = <2200>; 6351 }; 6352 6353 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 6354 /* SDA, SCL */ 6355 pins = "gpio80", "gpio81"; 6356 function = "qup2_se4"; 6357 drive-strength = <2>; 6358 bias-pull-up = <2200>; 6359 }; 6360 6361 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 6362 /* SDA, SCL */ 6363 pins = "gpio84", "gpio85"; 6364 function = "qup2_se5"; 6365 drive-strength = <2>; 6366 bias-pull-up = <2200>; 6367 }; 6368 6369 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 6370 /* SDA, SCL */ 6371 pins = "gpio88", "gpio89"; 6372 function = "qup2_se6"; 6373 drive-strength = <2>; 6374 bias-pull-up = <2200>; 6375 }; 6376 6377 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 6378 /* SDA, SCL */ 6379 pins = "gpio86", "gpio87"; 6380 function = "qup2_se7"; 6381 drive-strength = <2>; 6382 bias-pull-up = <2200>; 6383 }; 6384 6385 qup_spi0_cs: qup-spi0-cs-state { 6386 pins = "gpio3"; 6387 function = "qup0_se0"; 6388 drive-strength = <6>; 6389 bias-disable; 6390 }; 6391 6392 qup_spi0_data_clk: qup-spi0-data-clk-state { 6393 /* MISO, MOSI, CLK */ 6394 pins = "gpio0", "gpio1", "gpio2"; 6395 function = "qup0_se0"; 6396 drive-strength = <6>; 6397 bias-disable; 6398 }; 6399 6400 qup_spi1_cs: qup-spi1-cs-state { 6401 pins = "gpio7"; 6402 function = "qup0_se1"; 6403 drive-strength = <6>; 6404 bias-disable; 6405 }; 6406 6407 qup_spi1_data_clk: qup-spi1-data-clk-state { 6408 /* MISO, MOSI, CLK */ 6409 pins = "gpio4", "gpio5", "gpio6"; 6410 function = "qup0_se1"; 6411 drive-strength = <6>; 6412 bias-disable; 6413 }; 6414 6415 qup_spi2_cs: qup-spi2-cs-state { 6416 pins = "gpio11"; 6417 function = "qup0_se2"; 6418 drive-strength = <6>; 6419 bias-disable; 6420 }; 6421 6422 qup_spi2_data_clk: qup-spi2-data-clk-state { 6423 /* MISO, MOSI, CLK */ 6424 pins = "gpio8", "gpio9", "gpio10"; 6425 function = "qup0_se2"; 6426 drive-strength = <6>; 6427 bias-disable; 6428 }; 6429 6430 qup_spi3_cs: qup-spi3-cs-state { 6431 pins = "gpio15"; 6432 function = "qup0_se3"; 6433 drive-strength = <6>; 6434 bias-disable; 6435 }; 6436 6437 qup_spi3_data_clk: qup-spi3-data-clk-state { 6438 /* MISO, MOSI, CLK */ 6439 pins = "gpio12", "gpio13", "gpio14"; 6440 function = "qup0_se3"; 6441 drive-strength = <6>; 6442 bias-disable; 6443 }; 6444 6445 qup_spi4_cs: qup-spi4-cs-state { 6446 pins = "gpio19"; 6447 function = "qup0_se4"; 6448 drive-strength = <6>; 6449 bias-disable; 6450 }; 6451 6452 qup_spi4_data_clk: qup-spi4-data-clk-state { 6453 /* MISO, MOSI, CLK */ 6454 pins = "gpio16", "gpio17", "gpio18"; 6455 function = "qup0_se4"; 6456 drive-strength = <6>; 6457 bias-disable; 6458 }; 6459 6460 qup_spi5_cs: qup-spi5-cs-state { 6461 pins = "gpio23"; 6462 function = "qup0_se5"; 6463 drive-strength = <6>; 6464 bias-disable; 6465 }; 6466 6467 qup_spi5_data_clk: qup-spi5-data-clk-state { 6468 /* MISO, MOSI, CLK */ 6469 pins = "gpio20", "gpio21", "gpio22"; 6470 function = "qup0_se5"; 6471 drive-strength = <6>; 6472 bias-disable; 6473 }; 6474 6475 qup_spi6_cs: qup-spi6-cs-state { 6476 pins = "gpio27"; 6477 function = "qup0_se6"; 6478 drive-strength = <6>; 6479 bias-disable; 6480 }; 6481 6482 qup_spi6_data_clk: qup-spi6-data-clk-state { 6483 /* MISO, MOSI, CLK */ 6484 pins = "gpio24", "gpio25", "gpio26"; 6485 function = "qup0_se6"; 6486 drive-strength = <6>; 6487 bias-disable; 6488 }; 6489 6490 qup_spi7_cs: qup-spi7-cs-state { 6491 pins = "gpio13"; 6492 function = "qup0_se7"; 6493 drive-strength = <6>; 6494 bias-disable; 6495 }; 6496 6497 qup_spi7_data_clk: qup-spi7-data-clk-state { 6498 /* MISO, MOSI, CLK */ 6499 pins = "gpio14", "gpio15", "gpio12"; 6500 function = "qup0_se7"; 6501 drive-strength = <6>; 6502 bias-disable; 6503 }; 6504 6505 qup_spi8_cs: qup-spi8-cs-state { 6506 pins = "gpio35"; 6507 function = "qup1_se0"; 6508 drive-strength = <6>; 6509 bias-disable; 6510 }; 6511 6512 qup_spi8_data_clk: qup-spi8-data-clk-state { 6513 /* MISO, MOSI, CLK */ 6514 pins = "gpio32", "gpio33", "gpio34"; 6515 function = "qup1_se0"; 6516 drive-strength = <6>; 6517 bias-disable; 6518 }; 6519 6520 qup_spi9_cs: qup-spi9-cs-state { 6521 pins = "gpio39"; 6522 function = "qup1_se1"; 6523 drive-strength = <6>; 6524 bias-disable; 6525 }; 6526 6527 qup_spi9_data_clk: qup-spi9-data-clk-state { 6528 /* MISO, MOSI, CLK */ 6529 pins = "gpio36", "gpio37", "gpio38"; 6530 function = "qup1_se1"; 6531 drive-strength = <6>; 6532 bias-disable; 6533 }; 6534 6535 qup_spi10_cs: qup-spi10-cs-state { 6536 pins = "gpio43"; 6537 function = "qup1_se2"; 6538 drive-strength = <6>; 6539 bias-disable; 6540 }; 6541 6542 qup_spi10_data_clk: qup-spi10-data-clk-state { 6543 /* MISO, MOSI, CLK */ 6544 pins = "gpio40", "gpio41", "gpio42"; 6545 function = "qup1_se2"; 6546 drive-strength = <6>; 6547 bias-disable; 6548 }; 6549 6550 qup_spi11_cs: qup-spi11-cs-state { 6551 pins = "gpio47"; 6552 function = "qup1_se3"; 6553 drive-strength = <6>; 6554 bias-disable; 6555 }; 6556 6557 qup_spi11_data_clk: qup-spi11-data-clk-state { 6558 /* MISO, MOSI, CLK */ 6559 pins = "gpio44", "gpio45", "gpio46"; 6560 function = "qup1_se3"; 6561 drive-strength = <6>; 6562 bias-disable; 6563 }; 6564 6565 qup_spi12_cs: qup-spi12-cs-state { 6566 pins = "gpio51"; 6567 function = "qup1_se4"; 6568 drive-strength = <6>; 6569 bias-disable; 6570 }; 6571 6572 qup_spi12_data_clk: qup-spi12-data-clk-state { 6573 /* MISO, MOSI, CLK */ 6574 pins = "gpio48", "gpio49", "gpio50"; 6575 function = "qup1_se4"; 6576 drive-strength = <6>; 6577 bias-disable; 6578 }; 6579 6580 qup_spi13_cs: qup-spi13-cs-state { 6581 pins = "gpio55"; 6582 function = "qup1_se5"; 6583 drive-strength = <6>; 6584 bias-disable; 6585 }; 6586 6587 qup_spi13_data_clk: qup-spi13-data-clk-state { 6588 /* MISO, MOSI, CLK */ 6589 pins = "gpio52", "gpio53", "gpio54"; 6590 function = "qup1_se5"; 6591 drive-strength = <6>; 6592 bias-disable; 6593 }; 6594 6595 qup_spi14_cs: qup-spi14-cs-state { 6596 pins = "gpio59"; 6597 function = "qup1_se6"; 6598 drive-strength = <6>; 6599 bias-disable; 6600 }; 6601 6602 qup_spi14_data_clk: qup-spi14-data-clk-state { 6603 /* MISO, MOSI, CLK */ 6604 pins = "gpio56", "gpio57", "gpio58"; 6605 function = "qup1_se6"; 6606 drive-strength = <6>; 6607 bias-disable; 6608 }; 6609 6610 qup_spi15_cs: qup-spi15-cs-state { 6611 pins = "gpio53"; 6612 function = "qup1_se7"; 6613 drive-strength = <6>; 6614 bias-disable; 6615 }; 6616 6617 qup_spi15_data_clk: qup-spi15-data-clk-state { 6618 /* MISO, MOSI, CLK */ 6619 pins = "gpio54", "gpio55", "gpio52"; 6620 function = "qup1_se7"; 6621 drive-strength = <6>; 6622 bias-disable; 6623 }; 6624 6625 qup_spi16_cs: qup-spi16-cs-state { 6626 pins = "gpio67"; 6627 function = "qup2_se0"; 6628 drive-strength = <6>; 6629 bias-disable; 6630 }; 6631 6632 qup_spi16_data_clk: qup-spi16-data-clk-state { 6633 /* MISO, MOSI, CLK */ 6634 pins = "gpio64", "gpio65", "gpio66"; 6635 function = "qup2_se0"; 6636 drive-strength = <6>; 6637 bias-disable; 6638 }; 6639 6640 qup_spi17_cs: qup-spi17-cs-state { 6641 pins = "gpio71"; 6642 function = "qup2_se1"; 6643 drive-strength = <6>; 6644 bias-disable; 6645 }; 6646 6647 qup_spi17_data_clk: qup-spi17-data-clk-state { 6648 /* MISO, MOSI, CLK */ 6649 pins = "gpio68", "gpio69", "gpio70"; 6650 function = "qup2_se1"; 6651 drive-strength = <6>; 6652 bias-disable; 6653 }; 6654 6655 qup_spi18_cs: qup-spi18-cs-state { 6656 pins = "gpio75"; 6657 function = "qup2_se2"; 6658 drive-strength = <6>; 6659 bias-disable; 6660 }; 6661 6662 qup_spi18_data_clk: qup-spi18-data-clk-state { 6663 /* MISO, MOSI, CLK */ 6664 pins = "gpio72", "gpio73", "gpio74"; 6665 function = "qup2_se2"; 6666 drive-strength = <6>; 6667 bias-disable; 6668 }; 6669 6670 qup_spi19_cs: qup-spi19-cs-state { 6671 pins = "gpio79"; 6672 function = "qup2_se3"; 6673 drive-strength = <6>; 6674 bias-disable; 6675 }; 6676 6677 qup_spi19_data_clk: qup-spi19-data-clk-state { 6678 /* MISO, MOSI, CLK */ 6679 pins = "gpio76", "gpio77", "gpio78"; 6680 function = "qup2_se3"; 6681 drive-strength = <6>; 6682 bias-disable; 6683 }; 6684 6685 qup_spi20_cs: qup-spi20-cs-state { 6686 pins = "gpio83"; 6687 function = "qup2_se4"; 6688 drive-strength = <6>; 6689 bias-disable; 6690 }; 6691 6692 qup_spi20_data_clk: qup-spi20-data-clk-state { 6693 /* MISO, MOSI, CLK */ 6694 pins = "gpio80", "gpio81", "gpio82"; 6695 function = "qup2_se4"; 6696 drive-strength = <6>; 6697 bias-disable; 6698 }; 6699 6700 qup_spi21_cs: qup-spi21-cs-state { 6701 pins = "gpio87"; 6702 function = "qup2_se5"; 6703 drive-strength = <6>; 6704 bias-disable; 6705 }; 6706 6707 qup_spi21_data_clk: qup-spi21-data-clk-state { 6708 /* MISO, MOSI, CLK */ 6709 pins = "gpio84", "gpio85", "gpio86"; 6710 function = "qup2_se5"; 6711 drive-strength = <6>; 6712 bias-disable; 6713 }; 6714 6715 qup_spi22_cs: qup-spi22-cs-state { 6716 pins = "gpio91"; 6717 function = "qup2_se6"; 6718 drive-strength = <6>; 6719 bias-disable; 6720 }; 6721 6722 qup_spi22_data_clk: qup-spi22-data-clk-state { 6723 /* MISO, MOSI, CLK */ 6724 pins = "gpio88", "gpio89", "gpio90"; 6725 function = "qup2_se6"; 6726 drive-strength = <6>; 6727 bias-disable; 6728 }; 6729 6730 qup_spi23_cs: qup-spi23-cs-state { 6731 pins = "gpio85"; 6732 function = "qup2_se7"; 6733 drive-strength = <6>; 6734 bias-disable; 6735 }; 6736 6737 qup_spi23_data_clk: qup-spi23-data-clk-state { 6738 /* MISO, MOSI, CLK */ 6739 pins = "gpio86", "gpio87", "gpio84"; 6740 function = "qup2_se7"; 6741 drive-strength = <6>; 6742 bias-disable; 6743 }; 6744 6745 qup_uart2_default: qup-uart2-default-state { 6746 cts-pins { 6747 pins = "gpio8"; 6748 function = "qup0_se2"; 6749 drive-strength = <2>; 6750 bias-disable; 6751 }; 6752 6753 rts-pins { 6754 pins = "gpio9"; 6755 function = "qup0_se2"; 6756 drive-strength = <2>; 6757 bias-disable; 6758 }; 6759 6760 tx-pins { 6761 pins = "gpio10"; 6762 function = "qup0_se2"; 6763 drive-strength = <2>; 6764 bias-disable; 6765 }; 6766 6767 rx-pins { 6768 pins = "gpio11"; 6769 function = "qup0_se2"; 6770 drive-strength = <2>; 6771 bias-disable; 6772 }; 6773 }; 6774 6775 qup_uart14_default: qup-uart14-default-state { 6776 cts-pins { 6777 pins = "gpio56"; 6778 function = "qup1_se6"; 6779 bias-bus-hold; 6780 }; 6781 6782 rts-pins { 6783 pins = "gpio57"; 6784 function = "qup1_se6"; 6785 drive-strength = <2>; 6786 bias-disable; 6787 }; 6788 6789 tx-pins { 6790 pins = "gpio58"; 6791 function = "qup1_se6"; 6792 drive-strength = <2>; 6793 bias-disable; 6794 }; 6795 6796 rx-pins { 6797 pins = "gpio59"; 6798 function = "qup1_se6"; 6799 bias-pull-up; 6800 }; 6801 }; 6802 6803 qup_uart21_default: qup-uart21-default-state { 6804 tx-pins { 6805 pins = "gpio86"; 6806 function = "qup2_se5"; 6807 drive-strength = <2>; 6808 bias-disable; 6809 }; 6810 6811 rx-pins { 6812 pins = "gpio87"; 6813 function = "qup2_se5"; 6814 drive-strength = <2>; 6815 bias-disable; 6816 }; 6817 }; 6818 6819 sdc2_default: sdc2-default-state { 6820 clk-pins { 6821 pins = "sdc2_clk"; 6822 drive-strength = <16>; 6823 bias-disable; 6824 }; 6825 6826 cmd-pins { 6827 pins = "sdc2_cmd"; 6828 drive-strength = <10>; 6829 bias-pull-up; 6830 }; 6831 6832 data-pins { 6833 pins = "sdc2_data"; 6834 drive-strength = <10>; 6835 bias-pull-up; 6836 }; 6837 }; 6838 6839 sdc2_sleep: sdc2-sleep-state { 6840 clk-pins { 6841 pins = "sdc2_clk"; 6842 drive-strength = <2>; 6843 bias-disable; 6844 }; 6845 6846 cmd-pins { 6847 pins = "sdc2_cmd"; 6848 drive-strength = <2>; 6849 bias-pull-up; 6850 }; 6851 6852 data-pins { 6853 pins = "sdc2_data"; 6854 drive-strength = <2>; 6855 bias-pull-up; 6856 }; 6857 }; 6858 }; 6859 6860 stm@10002000 { 6861 compatible = "arm,coresight-stm", "arm,primecell"; 6862 reg = <0x0 0x10002000 0x0 0x1000>, 6863 <0x0 0x16280000 0x0 0x180000>; 6864 reg-names = "stm-base", 6865 "stm-stimulus-base"; 6866 6867 clocks = <&aoss_qmp>; 6868 clock-names = "apb_pclk"; 6869 6870 out-ports { 6871 port { 6872 stm_out: endpoint { 6873 remote-endpoint = <&funnel0_in7>; 6874 }; 6875 }; 6876 }; 6877 }; 6878 6879 tpdm@10003000 { 6880 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6881 reg = <0x0 0x10003000 0x0 0x1000>; 6882 6883 clocks = <&aoss_qmp>; 6884 clock-names = "apb_pclk"; 6885 6886 qcom,cmb-element-bits = <32>; 6887 qcom,cmb-msrs-num = <32>; 6888 status = "disabled"; 6889 6890 out-ports { 6891 port { 6892 dcc_tpdm_out: endpoint { 6893 remote-endpoint = <&qdss_tpda_in0>; 6894 }; 6895 }; 6896 }; 6897 }; 6898 6899 tpda@10004000 { 6900 compatible = "qcom,coresight-tpda", "arm,primecell"; 6901 reg = <0x0 0x10004000 0x0 0x1000>; 6902 6903 clocks = <&aoss_qmp>; 6904 clock-names = "apb_pclk"; 6905 6906 in-ports { 6907 #address-cells = <1>; 6908 #size-cells = <0>; 6909 6910 port@0 { 6911 reg = <0>; 6912 6913 qdss_tpda_in0: endpoint { 6914 remote-endpoint = <&dcc_tpdm_out>; 6915 }; 6916 }; 6917 6918 port@1 { 6919 reg = <1>; 6920 6921 qdss_tpda_in1: endpoint { 6922 remote-endpoint = <&qdss_tpdm_out>; 6923 }; 6924 }; 6925 }; 6926 6927 out-ports { 6928 port { 6929 qdss_tpda_out: endpoint { 6930 remote-endpoint = <&funnel0_in6>; 6931 }; 6932 }; 6933 }; 6934 }; 6935 6936 tpdm@1000f000 { 6937 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6938 reg = <0x0 0x1000f000 0x0 0x1000>; 6939 6940 clocks = <&aoss_qmp>; 6941 clock-names = "apb_pclk"; 6942 6943 qcom,cmb-element-bits = <32>; 6944 qcom,cmb-msrs-num = <32>; 6945 6946 out-ports { 6947 port { 6948 qdss_tpdm_out: endpoint { 6949 remote-endpoint = <&qdss_tpda_in1>; 6950 }; 6951 }; 6952 }; 6953 }; 6954 6955 funnel@10041000 { 6956 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6957 reg = <0x0 0x10041000 0x0 0x1000>; 6958 6959 clocks = <&aoss_qmp>; 6960 clock-names = "apb_pclk"; 6961 6962 in-ports { 6963 #address-cells = <1>; 6964 #size-cells = <0>; 6965 6966 port@6 { 6967 reg = <6>; 6968 6969 funnel0_in6: endpoint { 6970 remote-endpoint = <&qdss_tpda_out>; 6971 }; 6972 }; 6973 6974 port@7 { 6975 reg = <7>; 6976 6977 funnel0_in7: endpoint { 6978 remote-endpoint = <&stm_out>; 6979 }; 6980 }; 6981 }; 6982 6983 out-ports { 6984 port { 6985 funnel0_out: endpoint { 6986 remote-endpoint = <&qdss_funnel_in0>; 6987 }; 6988 }; 6989 }; 6990 }; 6991 6992 funnel@10042000 { 6993 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6994 reg = <0x0 0x10042000 0x0 0x1000>; 6995 6996 clocks = <&aoss_qmp>; 6997 clock-names = "apb_pclk"; 6998 6999 in-ports { 7000 #address-cells = <1>; 7001 #size-cells = <0>; 7002 7003 port@2 { 7004 reg = <2>; 7005 7006 funnel1_in2: endpoint { 7007 remote-endpoint = <&tmess_funnel_out>; 7008 }; 7009 }; 7010 7011 port@5 { 7012 reg = <5>; 7013 7014 funnel1_in5: endpoint { 7015 remote-endpoint = <&dlst_funnel_out>; 7016 }; 7017 }; 7018 7019 port@6 { 7020 reg = <6>; 7021 7022 funnel1_in6: endpoint { 7023 remote-endpoint = <&dlct1_funnel_out>; 7024 }; 7025 }; 7026 }; 7027 7028 out-ports { 7029 port { 7030 funnel1_out: endpoint { 7031 remote-endpoint = <&qdss_funnel_in1>; 7032 }; 7033 }; 7034 }; 7035 }; 7036 7037 funnel@10045000 { 7038 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7039 reg = <0x0 0x10045000 0x0 0x1000>; 7040 7041 clocks = <&aoss_qmp>; 7042 clock-names = "apb_pclk"; 7043 7044 in-ports { 7045 #address-cells = <1>; 7046 #size-cells = <0>; 7047 7048 port@0 { 7049 reg = <0>; 7050 7051 qdss_funnel_in0: endpoint { 7052 remote-endpoint = <&funnel0_out>; 7053 }; 7054 }; 7055 7056 port@1 { 7057 reg = <1>; 7058 7059 qdss_funnel_in1: endpoint { 7060 remote-endpoint = <&funnel1_out>; 7061 }; 7062 }; 7063 }; 7064 7065 out-ports { 7066 port { 7067 qdss_funnel_out: endpoint { 7068 remote-endpoint = <&aoss_funnel_in7>; 7069 }; 7070 }; 7071 }; 7072 }; 7073 7074 tpdm@10800000 { 7075 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7076 reg = <0x0 0x10800000 0x0 0x1000>; 7077 7078 clocks = <&aoss_qmp>; 7079 clock-names = "apb_pclk"; 7080 7081 qcom,cmb-element-bits = <64>; 7082 qcom,cmb-msrs-num = <32>; 7083 7084 out-ports { 7085 port { 7086 mxa_tpdm_out: endpoint { 7087 remote-endpoint = <&dlct2_tpda_in15>; 7088 }; 7089 }; 7090 }; 7091 }; 7092 7093 tpdm@1082c000 { 7094 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7095 reg = <0x0 0x1082c000 0x0 0x1000>; 7096 7097 clocks = <&aoss_qmp>; 7098 clock-names = "apb_pclk"; 7099 7100 qcom,dsb-element-bits = <32>; 7101 qcom,dsb-msrs-num = <32>; 7102 7103 out-ports { 7104 port { 7105 gcc_tpdm_out: endpoint { 7106 remote-endpoint = <&dlct1_tpda_in21>; 7107 }; 7108 }; 7109 }; 7110 }; 7111 7112 tpdm@10841000 { 7113 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7114 reg = <0x0 0x10841000 0x0 0x1000>; 7115 7116 clocks = <&aoss_qmp>; 7117 clock-names = "apb_pclk"; 7118 7119 qcom,cmb-element-bits = <32>; 7120 qcom,cmb-msrs-num = <32>; 7121 7122 out-ports { 7123 port { 7124 prng_tpdm_out: endpoint { 7125 remote-endpoint = <&dlct1_tpda_in19>; 7126 }; 7127 }; 7128 }; 7129 }; 7130 7131 tpdm@10844000 { 7132 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7133 reg = <0x0 0x10844000 0x0 0x1000>; 7134 7135 clocks = <&aoss_qmp>; 7136 clock-names = "apb_pclk"; 7137 7138 qcom,dsb-element-bits = <32>; 7139 qcom,dsb-msrs-num = <32>; 7140 7141 out-ports { 7142 port { 7143 lpass_cx_tpdm_out: endpoint { 7144 remote-endpoint = <&lpass_cx_funnel_in0>; 7145 }; 7146 }; 7147 }; 7148 }; 7149 7150 funnel@10846000 { 7151 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7152 reg = <0x0 0x10846000 0x0 0x1000>; 7153 7154 clocks = <&aoss_qmp>; 7155 clock-names = "apb_pclk"; 7156 7157 in-ports { 7158 port { 7159 lpass_cx_funnel_in0: endpoint { 7160 remote-endpoint = <&lpass_cx_tpdm_out>; 7161 }; 7162 }; 7163 }; 7164 7165 out-ports { 7166 port { 7167 lpass_cx_funnel_out: endpoint { 7168 remote-endpoint = <&dlct1_tpda_in4>; 7169 }; 7170 }; 7171 }; 7172 }; 7173 7174 cti@1098b000 { 7175 compatible = "arm,coresight-cti", "arm,primecell"; 7176 reg = <0x0 0x1098b000 0x0 0x1000>; 7177 7178 clocks = <&aoss_qmp>; 7179 clock-names = "apb_pclk"; 7180 }; 7181 7182 tpdm@109d0000 { 7183 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7184 reg = <0x0 0x109d0000 0x0 0x1000>; 7185 7186 clocks = <&aoss_qmp>; 7187 clock-names = "apb_pclk"; 7188 7189 qcom,dsb-element-bits = <32>; 7190 qcom,dsb-msrs-num = <32>; 7191 status = "disabled"; 7192 7193 out-ports { 7194 port { 7195 qm_tpdm_out: endpoint { 7196 remote-endpoint = <&dlct1_tpda_in20>; 7197 }; 7198 }; 7199 }; 7200 }; 7201 7202 tpdm@10ac0000 { 7203 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7204 reg = <0x0 0x10ac0000 0x0 0x1000>; 7205 7206 clocks = <&aoss_qmp>; 7207 clock-names = "apb_pclk"; 7208 7209 qcom,dsb-element-bits = <32>; 7210 qcom,dsb-msrs-num = <32>; 7211 status = "disabled"; 7212 7213 out-ports { 7214 port { 7215 dlst_tpdm0_out: endpoint { 7216 remote-endpoint = <&dlst_tpda_in8>; 7217 }; 7218 }; 7219 }; 7220 }; 7221 7222 tpdm@10ac1000 { 7223 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7224 reg = <0x0 0x10ac1000 0x0 0x1000>; 7225 7226 clocks = <&aoss_qmp>; 7227 clock-names = "apb_pclk"; 7228 7229 qcom,cmb-element-bits = <64>; 7230 qcom,cmb-msrs-num = <32>; 7231 7232 out-ports { 7233 port { 7234 dlst_tpdm1_out: endpoint { 7235 remote-endpoint = <&dlst_tpda_in9>; 7236 }; 7237 }; 7238 }; 7239 }; 7240 7241 tpda@10ac4000 { 7242 compatible = "qcom,coresight-tpda", "arm,primecell"; 7243 reg = <0x0 0x10ac4000 0x0 0x1000>; 7244 7245 clocks = <&aoss_qmp>; 7246 clock-names = "apb_pclk"; 7247 7248 in-ports { 7249 #address-cells = <1>; 7250 #size-cells = <0>; 7251 7252 port@8 { 7253 reg = <8>; 7254 7255 dlst_tpda_in8: endpoint { 7256 remote-endpoint = <&dlst_tpdm0_out>; 7257 }; 7258 }; 7259 7260 port@9 { 7261 reg = <9>; 7262 7263 dlst_tpda_in9: endpoint { 7264 remote-endpoint = <&dlst_tpdm1_out>; 7265 }; 7266 }; 7267 }; 7268 7269 out-ports { 7270 port { 7271 dlst_tpda_out: endpoint { 7272 remote-endpoint = <&dlst_funnel_in0>; 7273 }; 7274 }; 7275 }; 7276 }; 7277 7278 funnel@10ac5000 { 7279 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7280 reg = <0x0 0x10ac5000 0x0 0x1000>; 7281 7282 clocks = <&aoss_qmp>; 7283 clock-names = "apb_pclk"; 7284 7285 in-ports { 7286 port { 7287 dlst_funnel_in0: endpoint { 7288 remote-endpoint = <&dlst_tpda_out>; 7289 }; 7290 }; 7291 }; 7292 7293 out-ports { 7294 port { 7295 dlst_funnel_out: endpoint { 7296 remote-endpoint = <&funnel1_in5>; 7297 }; 7298 }; 7299 }; 7300 }; 7301 7302 funnel@10b04000 { 7303 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7304 reg = <0x0 0x10b04000 0x0 0x1000>; 7305 7306 clocks = <&aoss_qmp>; 7307 clock-names = "apb_pclk"; 7308 7309 in-ports { 7310 #address-cells = <1>; 7311 #size-cells = <0>; 7312 7313 port@3 { 7314 reg = <3>; 7315 7316 aoss_funnel_in3: endpoint { 7317 remote-endpoint = <&ddr_lpi_funnel_out>; 7318 }; 7319 }; 7320 7321 port@6 { 7322 reg = <6>; 7323 7324 aoss_funnel_in6: endpoint { 7325 remote-endpoint = <&aoss_tpda_out>; 7326 }; 7327 }; 7328 7329 port@7 { 7330 reg = <7>; 7331 7332 aoss_funnel_in7: endpoint { 7333 remote-endpoint = <&qdss_funnel_out>; 7334 }; 7335 }; 7336 }; 7337 7338 out-ports { 7339 port { 7340 aoss_funnel_out: endpoint { 7341 remote-endpoint = <&etf0_in>; 7342 }; 7343 }; 7344 }; 7345 }; 7346 7347 etf0: tmc@10b05000 { 7348 compatible = "arm,coresight-tmc", "arm,primecell"; 7349 reg = <0x0 0x10b05000 0x0 0x1000>; 7350 7351 clocks = <&aoss_qmp>; 7352 clock-names = "apb_pclk"; 7353 7354 in-ports { 7355 port { 7356 etf0_in: endpoint { 7357 remote-endpoint = <&aoss_funnel_out>; 7358 }; 7359 }; 7360 }; 7361 7362 out-ports { 7363 port { 7364 etf0_out: endpoint { 7365 remote-endpoint = <&swao_rep_in>; 7366 }; 7367 }; 7368 }; 7369 }; 7370 7371 replicator@10b06000 { 7372 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 7373 reg = <0x0 0x10b06000 0x0 0x1000>; 7374 7375 clocks = <&aoss_qmp>; 7376 clock-names = "apb_pclk"; 7377 7378 in-ports { 7379 port { 7380 swao_rep_in: endpoint { 7381 remote-endpoint = <&etf0_out>; 7382 }; 7383 }; 7384 }; 7385 7386 out-ports { 7387 port { 7388 swao_rep_out1: endpoint { 7389 remote-endpoint = <&eud_in>; 7390 }; 7391 }; 7392 }; 7393 }; 7394 7395 tpda@10b08000 { 7396 compatible = "qcom,coresight-tpda", "arm,primecell"; 7397 reg = <0x0 0x10b08000 0x0 0x1000>; 7398 7399 clocks = <&aoss_qmp>; 7400 clock-names = "apb_pclk"; 7401 7402 in-ports { 7403 #address-cells = <1>; 7404 #size-cells = <0>; 7405 7406 port@0 { 7407 reg = <0>; 7408 7409 aoss_tpda_in0: endpoint { 7410 remote-endpoint = <&aoss_tpdm0_out>; 7411 }; 7412 }; 7413 7414 port@1 { 7415 reg = <1>; 7416 7417 aoss_tpda_in1: endpoint { 7418 remote-endpoint = <&aoss_tpdm1_out>; 7419 }; 7420 }; 7421 7422 port@2 { 7423 reg = <2>; 7424 7425 aoss_tpda_in2: endpoint { 7426 remote-endpoint = <&aoss_tpdm2_out>; 7427 }; 7428 }; 7429 7430 port@3 { 7431 reg = <3>; 7432 7433 aoss_tpda_in3: endpoint { 7434 remote-endpoint = <&aoss_tpdm3_out>; 7435 }; 7436 }; 7437 7438 port@4 { 7439 reg = <4>; 7440 7441 aoss_tpda_in4: endpoint { 7442 remote-endpoint = <&aoss_tpdm4_out>; 7443 }; 7444 }; 7445 }; 7446 7447 out-ports { 7448 port { 7449 aoss_tpda_out: endpoint { 7450 remote-endpoint = <&aoss_funnel_in6>; 7451 }; 7452 }; 7453 }; 7454 }; 7455 7456 tpdm@10b09000 { 7457 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7458 reg = <0x0 0x10b09000 0x0 0x1000>; 7459 7460 clocks = <&aoss_qmp>; 7461 clock-names = "apb_pclk"; 7462 7463 qcom,cmb-element-bits = <64>; 7464 qcom,cmb-msrs-num = <32>; 7465 7466 out-ports { 7467 port { 7468 aoss_tpdm0_out: endpoint { 7469 remote-endpoint = <&aoss_tpda_in0>; 7470 }; 7471 }; 7472 }; 7473 }; 7474 7475 tpdm@10b0a000 { 7476 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7477 reg = <0x0 0x10b0a000 0x0 0x1000>; 7478 7479 clocks = <&aoss_qmp>; 7480 clock-names = "apb_pclk"; 7481 7482 qcom,cmb-element-bits = <64>; 7483 qcom,cmb-msrs-num = <32>; 7484 7485 out-ports { 7486 port { 7487 aoss_tpdm1_out: endpoint { 7488 remote-endpoint = <&aoss_tpda_in1>; 7489 }; 7490 }; 7491 }; 7492 }; 7493 7494 tpdm@10b0b000 { 7495 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7496 reg = <0x0 0x10b0b000 0x0 0x1000>; 7497 7498 clocks = <&aoss_qmp>; 7499 clock-names = "apb_pclk"; 7500 7501 qcom,cmb-element-bits = <64>; 7502 qcom,cmb-msrs-num = <32>; 7503 7504 out-ports { 7505 port { 7506 aoss_tpdm2_out: endpoint { 7507 remote-endpoint = <&aoss_tpda_in2>; 7508 }; 7509 }; 7510 }; 7511 }; 7512 7513 tpdm@10b0c000 { 7514 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7515 reg = <0x0 0x10b0c000 0x0 0x1000>; 7516 7517 clocks = <&aoss_qmp>; 7518 clock-names = "apb_pclk"; 7519 7520 qcom,cmb-element-bits = <64>; 7521 qcom,cmb-msrs-num = <32>; 7522 7523 out-ports { 7524 port { 7525 aoss_tpdm3_out: endpoint { 7526 remote-endpoint = <&aoss_tpda_in3>; 7527 }; 7528 }; 7529 }; 7530 }; 7531 7532 tpdm@10b0d000 { 7533 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7534 reg = <0x0 0x10b0d000 0x0 0x1000>; 7535 7536 clocks = <&aoss_qmp>; 7537 clock-names = "apb_pclk"; 7538 7539 qcom,dsb-element-bits = <32>; 7540 qcom,dsb-msrs-num = <32>; 7541 7542 out-ports { 7543 port { 7544 aoss_tpdm4_out: endpoint { 7545 remote-endpoint = <&aoss_tpda_in4>; 7546 }; 7547 }; 7548 }; 7549 }; 7550 7551 tpdm@10b20000 { 7552 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7553 reg = <0x0 0x10b20000 0x0 0x1000>; 7554 7555 clocks = <&aoss_qmp>; 7556 clock-names = "apb_pclk"; 7557 7558 qcom,dsb-element-bits = <32>; 7559 qcom,dsb-msrs-num = <32>; 7560 status = "disabled"; 7561 7562 out-ports { 7563 port { 7564 lpicc_tpdm_out: endpoint { 7565 remote-endpoint = <&ddr_lpi_tpda_in>; 7566 }; 7567 }; 7568 }; 7569 }; 7570 7571 tpda@10b23000 { 7572 compatible = "qcom,coresight-tpda", "arm,primecell"; 7573 reg = <0x0 0x10b23000 0x0 0x1000>; 7574 7575 clocks = <&aoss_qmp>; 7576 clock-names = "apb_pclk"; 7577 status = "disabled"; 7578 7579 in-ports { 7580 port { 7581 ddr_lpi_tpda_in: endpoint { 7582 remote-endpoint = <&lpicc_tpdm_out>; 7583 }; 7584 }; 7585 }; 7586 7587 out-ports { 7588 port { 7589 ddr_lpi_tpda_out: endpoint { 7590 remote-endpoint = <&ddr_lpi_funnel_in0>; 7591 }; 7592 }; 7593 }; 7594 }; 7595 7596 funnel@10b24000 { 7597 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7598 reg = <0x0 0x10b24000 0x0 0x1000>; 7599 7600 clocks = <&aoss_qmp>; 7601 clock-names = "apb_pclk"; 7602 status = "disabled"; 7603 7604 in-ports { 7605 port { 7606 ddr_lpi_funnel_in0: endpoint { 7607 remote-endpoint = <&ddr_lpi_tpda_out>; 7608 }; 7609 }; 7610 }; 7611 7612 out-ports { 7613 port { 7614 ddr_lpi_funnel_out: endpoint { 7615 remote-endpoint = <&aoss_funnel_in3>; 7616 }; 7617 }; 7618 }; 7619 }; 7620 7621 tpdm@10c08000 { 7622 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7623 reg = <0x0 0x10c08000 0x0 0x1000>; 7624 7625 clocks = <&aoss_qmp>; 7626 clock-names = "apb_pclk"; 7627 7628 qcom,dsb-element-bits = <32>; 7629 qcom,dsb-msrs-num = <32>; 7630 7631 out-ports { 7632 port { 7633 mm_tpdm_out: endpoint { 7634 remote-endpoint = <&mm_funnel_in4>; 7635 }; 7636 }; 7637 }; 7638 }; 7639 7640 funnel@10c0b000 { 7641 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7642 reg = <0x0 0x10c0b000 0x0 0x1000>; 7643 7644 clocks = <&aoss_qmp>; 7645 clock-names = "apb_pclk"; 7646 7647 in-ports { 7648 #address-cells = <1>; 7649 #size-cells = <0>; 7650 7651 port@4 { 7652 reg = <4>; 7653 7654 mm_funnel_in4: endpoint { 7655 remote-endpoint = <&mm_tpdm_out>; 7656 }; 7657 }; 7658 }; 7659 7660 out-ports { 7661 port { 7662 mm_funnel_out: endpoint { 7663 remote-endpoint = <&dlct2_tpda_in4>; 7664 }; 7665 }; 7666 }; 7667 }; 7668 7669 tpdm@10c28000 { 7670 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7671 reg = <0x0 0x10c28000 0x0 0x1000>; 7672 7673 clocks = <&aoss_qmp>; 7674 clock-names = "apb_pclk"; 7675 7676 qcom,dsb-element-bits = <32>; 7677 qcom,dsb-msrs-num = <32>; 7678 7679 out-ports { 7680 port { 7681 dlct1_tpdm_out: endpoint { 7682 remote-endpoint = <&dlct1_tpda_in26>; 7683 }; 7684 }; 7685 }; 7686 }; 7687 7688 tpdm@10c29000 { 7689 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7690 reg = <0x0 0x10c29000 0x0 0x1000>; 7691 7692 clocks = <&aoss_qmp>; 7693 clock-names = "apb_pclk"; 7694 7695 qcom,cmb-element-bits = <64>; 7696 qcom,cmb-msrs-num = <32>; 7697 7698 out-ports { 7699 port { 7700 ipcc_tpdm_out: endpoint { 7701 remote-endpoint = <&dlct1_tpda_in27>; 7702 }; 7703 }; 7704 }; 7705 }; 7706 7707 tpda@10c2b000 { 7708 compatible = "qcom,coresight-tpda", "arm,primecell"; 7709 reg = <0x0 0x10c2b000 0x0 0x1000>; 7710 7711 clocks = <&aoss_qmp>; 7712 clock-names = "apb_pclk"; 7713 7714 in-ports { 7715 #address-cells = <1>; 7716 #size-cells = <0>; 7717 7718 port@4 { 7719 reg = <4>; 7720 7721 dlct1_tpda_in4: endpoint { 7722 remote-endpoint = <&lpass_cx_funnel_out>; 7723 }; 7724 }; 7725 7726 port@13 { 7727 reg = <19>; 7728 7729 dlct1_tpda_in19: endpoint { 7730 remote-endpoint = <&prng_tpdm_out>; 7731 }; 7732 }; 7733 7734 port@14 { 7735 reg = <20>; 7736 7737 dlct1_tpda_in20: endpoint { 7738 remote-endpoint = <&qm_tpdm_out>; 7739 }; 7740 }; 7741 7742 port@15 { 7743 reg = <21>; 7744 7745 dlct1_tpda_in21: endpoint { 7746 remote-endpoint = <&gcc_tpdm_out>; 7747 }; 7748 }; 7749 7750 port@1a { 7751 reg = <26>; 7752 7753 dlct1_tpda_in26: endpoint { 7754 remote-endpoint = <&dlct1_tpdm_out>; 7755 }; 7756 }; 7757 7758 port@1b { 7759 reg = <27>; 7760 7761 dlct1_tpda_in27: endpoint { 7762 remote-endpoint = <&ipcc_tpdm_out>; 7763 }; 7764 }; 7765 }; 7766 7767 out-ports { 7768 port { 7769 dlct1_tpda_out: endpoint { 7770 remote-endpoint = <&dlct1_funnel_in0>; 7771 }; 7772 }; 7773 }; 7774 }; 7775 7776 funnel@10c2c000 { 7777 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7778 reg = <0x0 0x10c2c000 0x0 0x1000>; 7779 7780 clocks = <&aoss_qmp>; 7781 clock-names = "apb_pclk"; 7782 7783 in-ports { 7784 #address-cells = <1>; 7785 #size-cells = <0>; 7786 7787 port@0 { 7788 reg = <0>; 7789 7790 dlct1_funnel_in0: endpoint { 7791 remote-endpoint = <&dlct1_tpda_out>; 7792 }; 7793 }; 7794 7795 port@4 { 7796 reg = <4>; 7797 7798 dlct1_funnel_in4: endpoint { 7799 remote-endpoint = <&dlct2_funnel_out>; 7800 }; 7801 }; 7802 7803 port@5 { 7804 reg = <5>; 7805 7806 dlct1_funnel_in5: endpoint { 7807 remote-endpoint = <&ddr_funnel0_out>; 7808 }; 7809 }; 7810 }; 7811 7812 out-ports { 7813 port { 7814 dlct1_funnel_out: endpoint { 7815 remote-endpoint = <&funnel1_in6>; 7816 }; 7817 }; 7818 }; 7819 }; 7820 7821 tpdm@10c38000 { 7822 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7823 reg = <0x0 0x10c38000 0x0 0x1000>; 7824 7825 clocks = <&aoss_qmp>; 7826 clock-names = "apb_pclk"; 7827 7828 qcom,cmb-element-bits = <64>; 7829 qcom,cmb-msrs-num = <32>; 7830 7831 out-ports { 7832 port { 7833 dlct2_tpdm0_out: endpoint { 7834 remote-endpoint = <&dlct2_tpda_in16>; 7835 }; 7836 }; 7837 }; 7838 }; 7839 7840 tpdm@10c39000 { 7841 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7842 reg = <0x0 0x10c39000 0x0 0x1000>; 7843 7844 clocks = <&aoss_qmp>; 7845 clock-names = "apb_pclk"; 7846 7847 qcom,cmb-element-bits = <64>; 7848 qcom,cmb-msrs-num = <32>; 7849 7850 out-ports { 7851 port { 7852 dlct2_tpdm1_out: endpoint { 7853 remote-endpoint = <&dlct2_tpda_in17>; 7854 }; 7855 }; 7856 }; 7857 }; 7858 7859 tpda@10c3c000 { 7860 compatible = "qcom,coresight-tpda", "arm,primecell"; 7861 reg = <0x0 0x10c3c000 0x0 0x1000>; 7862 7863 clocks = <&aoss_qmp>; 7864 clock-names = "apb_pclk"; 7865 7866 in-ports { 7867 #address-cells = <1>; 7868 #size-cells = <0>; 7869 7870 port@4 { 7871 reg = <4>; 7872 7873 dlct2_tpda_in4: endpoint { 7874 remote-endpoint = <&mm_funnel_out>; 7875 }; 7876 }; 7877 7878 port@f { 7879 reg = <15>; 7880 7881 dlct2_tpda_in15: endpoint { 7882 remote-endpoint = <&mxa_tpdm_out>; 7883 }; 7884 }; 7885 7886 port@10 { 7887 reg = <16>; 7888 7889 dlct2_tpda_in16: endpoint { 7890 remote-endpoint = <&dlct2_tpdm0_out>; 7891 }; 7892 }; 7893 7894 port@11 { 7895 reg = <17>; 7896 7897 dlct2_tpda_in17: endpoint { 7898 remote-endpoint = <&dlct2_tpdm1_out>; 7899 }; 7900 }; 7901 }; 7902 7903 out-ports { 7904 port { 7905 dlct2_tpda_out: endpoint { 7906 remote-endpoint = <&dlct2_funnel_in0>; 7907 }; 7908 }; 7909 }; 7910 }; 7911 7912 funnel@10c3d000 { 7913 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7914 reg = <0x0 0x10c3d000 0x0 0x1000>; 7915 7916 clocks = <&aoss_qmp>; 7917 clock-names = "apb_pclk"; 7918 7919 in-ports { 7920 port { 7921 dlct2_funnel_in0: endpoint { 7922 remote-endpoint = <&dlct2_tpda_out>; 7923 }; 7924 }; 7925 }; 7926 7927 out-ports { 7928 port { 7929 dlct2_funnel_out: endpoint { 7930 remote-endpoint = <&dlct1_funnel_in4>; 7931 }; 7932 }; 7933 }; 7934 }; 7935 7936 tpdm@10cc1000 { 7937 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7938 reg = <0x0 0x10cc1000 0x0 0x1000>; 7939 7940 clocks = <&aoss_qmp>; 7941 clock-names = "apb_pclk"; 7942 7943 qcom,cmb-element-bits = <64>; 7944 qcom,cmb-msrs-num = <32>; 7945 qcom,dsb-element-bits = <32>; 7946 qcom,dsb-msrs-num = <32>; 7947 status = "disabled"; 7948 7949 out-ports { 7950 port { 7951 tmess_tpdm1_out: endpoint { 7952 remote-endpoint = <&tmess_tpda_in2>; 7953 }; 7954 }; 7955 }; 7956 }; 7957 7958 tpda@10cc4000 { 7959 compatible = "qcom,coresight-tpda", "arm,primecell"; 7960 reg = <0x0 0x10cc4000 0x0 0x1000>; 7961 7962 clocks = <&aoss_qmp>; 7963 clock-names = "apb_pclk"; 7964 7965 in-ports { 7966 #address-cells = <1>; 7967 #size-cells = <0>; 7968 7969 port@2 { 7970 reg = <2>; 7971 7972 tmess_tpda_in2: endpoint { 7973 remote-endpoint = <&tmess_tpdm1_out>; 7974 }; 7975 }; 7976 }; 7977 7978 out-ports { 7979 port { 7980 tmess_tpda_out: endpoint { 7981 remote-endpoint = <&tmess_funnel_in0>; 7982 }; 7983 }; 7984 }; 7985 }; 7986 7987 funnel@10cc5000 { 7988 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7989 reg = <0x0 0x10cc5000 0x0 0x1000>; 7990 7991 clocks = <&aoss_qmp>; 7992 clock-names = "apb_pclk"; 7993 7994 in-ports { 7995 port { 7996 tmess_funnel_in0: endpoint { 7997 remote-endpoint = <&tmess_tpda_out>; 7998 }; 7999 }; 8000 }; 8001 8002 out-ports { 8003 port { 8004 tmess_funnel_out: endpoint { 8005 remote-endpoint = <&funnel1_in2>; 8006 }; 8007 }; 8008 }; 8009 }; 8010 8011 funnel@10d04000 { 8012 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 8013 reg = <0x0 0x10d04000 0x0 0x1000>; 8014 8015 clocks = <&aoss_qmp>; 8016 clock-names = "apb_pclk"; 8017 8018 in-ports { 8019 #address-cells = <1>; 8020 #size-cells = <0>; 8021 8022 port@6 { 8023 reg = <6>; 8024 8025 ddr_funnel0_in6: endpoint { 8026 remote-endpoint = <&ddr_funnel1_out>; 8027 }; 8028 }; 8029 }; 8030 8031 out-ports { 8032 port { 8033 ddr_funnel0_out: endpoint { 8034 remote-endpoint = <&dlct1_funnel_in5>; 8035 }; 8036 }; 8037 }; 8038 }; 8039 8040 tpdm@10d08000 { 8041 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8042 reg = <0x0 0x10d08000 0x0 0x1000>; 8043 8044 clocks = <&aoss_qmp>; 8045 clock-names = "apb_pclk"; 8046 8047 qcom,cmb-element-bits = <32>; 8048 qcom,cmb-msrs-num = <32>; 8049 8050 out-ports { 8051 port { 8052 llcc0_tpdm_out: endpoint { 8053 remote-endpoint = <&llcc_tpda_in0>; 8054 }; 8055 }; 8056 }; 8057 }; 8058 8059 tpdm@10d09000 { 8060 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8061 reg = <0x0 0x10d09000 0x0 0x1000>; 8062 8063 clocks = <&aoss_qmp>; 8064 clock-names = "apb_pclk"; 8065 8066 qcom,cmb-element-bits = <32>; 8067 qcom,cmb-msrs-num = <32>; 8068 8069 out-ports { 8070 port { 8071 llcc1_tpdm_out: endpoint { 8072 remote-endpoint = <&llcc_tpda_in1>; 8073 }; 8074 }; 8075 }; 8076 }; 8077 8078 tpdm@10d0a000 { 8079 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8080 reg = <0x0 0x10d0a000 0x0 0x1000>; 8081 8082 clocks = <&aoss_qmp>; 8083 clock-names = "apb_pclk"; 8084 8085 qcom,cmb-element-bits = <32>; 8086 qcom,cmb-msrs-num = <32>; 8087 8088 out-ports { 8089 port { 8090 llcc2_tpdm_out: endpoint { 8091 remote-endpoint = <&llcc_tpda_in2>; 8092 }; 8093 }; 8094 }; 8095 }; 8096 8097 tpdm@10d0b000 { 8098 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8099 reg = <0x0 0x10d0b000 0x0 0x1000>; 8100 8101 clocks = <&aoss_qmp>; 8102 clock-names = "apb_pclk"; 8103 8104 qcom,cmb-element-bits = <32>; 8105 qcom,cmb-msrs-num = <32>; 8106 8107 out-ports { 8108 port { 8109 llcc3_tpdm_out: endpoint { 8110 remote-endpoint = <&llcc_tpda_in3>; 8111 }; 8112 }; 8113 }; 8114 }; 8115 8116 tpdm@10d0c000 { 8117 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8118 reg = <0x0 0x10d0c000 0x0 0x1000>; 8119 8120 clocks = <&aoss_qmp>; 8121 clock-names = "apb_pclk"; 8122 8123 qcom,cmb-element-bits = <32>; 8124 qcom,cmb-msrs-num = <32>; 8125 8126 out-ports { 8127 port { 8128 llcc4_tpdm_out: endpoint { 8129 remote-endpoint = <&llcc_tpda_in4>; 8130 }; 8131 }; 8132 }; 8133 }; 8134 8135 tpdm@10d0d000 { 8136 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8137 reg = <0x0 0x10d0d000 0x0 0x1000>; 8138 8139 clocks = <&aoss_qmp>; 8140 clock-names = "apb_pclk"; 8141 8142 qcom,cmb-element-bits = <32>; 8143 qcom,cmb-msrs-num = <32>; 8144 8145 out-ports { 8146 port { 8147 llcc5_tpdm_out: endpoint { 8148 remote-endpoint = <&llcc_tpda_in5>; 8149 }; 8150 }; 8151 }; 8152 }; 8153 8154 tpdm@10d0e000 { 8155 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8156 reg = <0x0 0x10d0e000 0x0 0x1000>; 8157 8158 clocks = <&aoss_qmp>; 8159 clock-names = "apb_pclk"; 8160 8161 qcom,cmb-element-bits = <32>; 8162 qcom,cmb-msrs-num = <32>; 8163 8164 out-ports { 8165 port { 8166 llcc6_tpdm_out: endpoint { 8167 remote-endpoint = <&llcc_tpda_in6>; 8168 }; 8169 }; 8170 }; 8171 }; 8172 8173 tpdm@10d0f000 { 8174 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8175 reg = <0x0 0x10d0f000 0x0 0x1000>; 8176 8177 clocks = <&aoss_qmp>; 8178 clock-names = "apb_pclk"; 8179 8180 qcom,cmb-element-bits = <32>; 8181 qcom,cmb-msrs-num = <32>; 8182 8183 out-ports { 8184 port { 8185 llcc7_tpdm_out: endpoint { 8186 remote-endpoint = <&llcc_tpda_in7>; 8187 }; 8188 }; 8189 }; 8190 }; 8191 8192 tpda@10d12000 { 8193 compatible = "qcom,coresight-tpda", "arm,primecell"; 8194 reg = <0x0 0x10d12000 0x0 0x1000>; 8195 8196 clocks = <&aoss_qmp>; 8197 clock-names = "apb_pclk"; 8198 8199 in-ports { 8200 #address-cells = <1>; 8201 #size-cells = <0>; 8202 8203 port@0 { 8204 reg = <0>; 8205 8206 llcc_tpda_in0: endpoint { 8207 remote-endpoint = <&llcc0_tpdm_out>; 8208 }; 8209 }; 8210 8211 port@1 { 8212 reg = <1>; 8213 8214 llcc_tpda_in1: endpoint { 8215 remote-endpoint = <&llcc1_tpdm_out>; 8216 }; 8217 }; 8218 8219 port@2 { 8220 reg = <2>; 8221 8222 llcc_tpda_in2: endpoint { 8223 remote-endpoint = <&llcc2_tpdm_out>; 8224 }; 8225 }; 8226 8227 port@3 { 8228 reg = <3>; 8229 8230 llcc_tpda_in3: endpoint { 8231 remote-endpoint = <&llcc3_tpdm_out>; 8232 }; 8233 }; 8234 8235 port@4 { 8236 reg = <4>; 8237 8238 llcc_tpda_in4: endpoint { 8239 remote-endpoint = <&llcc4_tpdm_out>; 8240 }; 8241 }; 8242 8243 port@5 { 8244 reg = <5>; 8245 8246 llcc_tpda_in5: endpoint { 8247 remote-endpoint = <&llcc5_tpdm_out>; 8248 }; 8249 }; 8250 8251 port@6 { 8252 reg = <6>; 8253 8254 llcc_tpda_in6: endpoint { 8255 remote-endpoint = <&llcc6_tpdm_out>; 8256 }; 8257 }; 8258 8259 port@7 { 8260 reg = <7>; 8261 8262 llcc_tpda_in7: endpoint { 8263 remote-endpoint = <&llcc7_tpdm_out>; 8264 }; 8265 }; 8266 }; 8267 8268 out-ports { 8269 port { 8270 llcc_tpda_out: endpoint { 8271 remote-endpoint = <&ddr_funnel1_in0>; 8272 }; 8273 }; 8274 }; 8275 }; 8276 8277 funnel@10d13000 { 8278 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 8279 reg = <0x0 0x10d13000 0x0 0x1000>; 8280 8281 clocks = <&aoss_qmp>; 8282 clock-names = "apb_pclk"; 8283 8284 in-ports { 8285 port { 8286 ddr_funnel1_in0: endpoint { 8287 remote-endpoint = <&llcc_tpda_out>; 8288 }; 8289 }; 8290 }; 8291 8292 out-ports { 8293 port { 8294 ddr_funnel1_out: endpoint { 8295 remote-endpoint = <&ddr_funnel0_in6>; 8296 }; 8297 }; 8298 }; 8299 }; 8300 8301 apps_smmu: iommu@15000000 { 8302 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 8303 reg = <0 0x15000000 0 0x100000>; 8304 8305 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 8306 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 8307 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 8308 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 8309 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 8310 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 8311 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 8312 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 8313 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 8314 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 8315 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 8316 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 8317 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 8318 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 8319 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 8320 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 8321 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 8322 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 8323 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 8324 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 8325 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 8326 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 8327 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 8328 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 8329 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 8330 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 8331 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 8332 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 8333 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 8334 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 8335 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 8336 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 8337 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 8338 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 8339 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 8340 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 8341 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 8342 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 8343 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 8344 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 8345 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 8346 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 8347 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 8348 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 8349 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 8350 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 8351 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 8352 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 8353 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 8354 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 8355 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 8356 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 8357 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 8358 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 8359 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 8360 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 8361 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 8362 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 8363 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 8364 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 8365 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 8366 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 8367 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 8368 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 8369 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 8370 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 8371 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 8372 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 8373 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 8374 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 8375 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 8376 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 8377 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 8378 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 8379 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 8380 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 8381 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 8382 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 8383 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 8384 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 8385 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 8386 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 8387 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 8388 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 8389 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 8390 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 8391 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 8392 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 8393 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 8394 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 8395 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 8396 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 8397 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 8398 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 8399 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 8400 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 8401 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 8402 8403 #iommu-cells = <2>; 8404 #global-interrupts = <1>; 8405 8406 dma-coherent; 8407 }; 8408 8409 pcie_smmu: iommu@15400000 { 8410 compatible = "arm,smmu-v3"; 8411 reg = <0 0x15400000 0 0x80000>; 8412 #iommu-cells = <1>; 8413 interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 8414 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 8415 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>; 8416 interrupt-names = "eventq", 8417 "gerror", 8418 "cmdq-sync"; 8419 dma-coherent; 8420 status = "reserved"; /* Controlled by Gunyah. */ 8421 }; 8422 8423 intc: interrupt-controller@17000000 { 8424 compatible = "arm,gic-v3"; 8425 reg = <0 0x17000000 0 0x10000>, /* GICD */ 8426 <0 0x17080000 0 0x300000>; /* GICR * 12 */ 8427 8428 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 8429 8430 #interrupt-cells = <3>; 8431 interrupt-controller; 8432 8433 #redistributor-regions = <1>; 8434 redistributor-stride = <0x0 0x40000>; 8435 8436 #address-cells = <2>; 8437 #size-cells = <2>; 8438 ranges; 8439 8440 gic_its: msi-controller@17040000 { 8441 compatible = "arm,gic-v3-its"; 8442 reg = <0 0x17040000 0 0x40000>; 8443 8444 msi-controller; 8445 #msi-cells = <1>; 8446 }; 8447 }; 8448 8449 apss_watchdog: watchdog@17410000 { 8450 compatible = "qcom,apss-wdt-x1e80100", "qcom,kpss-wdt"; 8451 reg = <0x0 0x17410000 0x0 0x1000>; 8452 clocks = <&sleep_clk>; 8453 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 8454 status = "reserved"; /* Reserved by Gunyah */ 8455 }; 8456 8457 cpucp_mbox: mailbox@17430000 { 8458 compatible = "qcom,x1e80100-cpucp-mbox"; 8459 reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; 8460 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8461 #mbox-cells = <1>; 8462 }; 8463 8464 apps_rsc: rsc@17500000 { 8465 compatible = "qcom,rpmh-rsc"; 8466 reg = <0 0x17500000 0 0x10000>, 8467 <0 0x17510000 0 0x10000>, 8468 <0 0x17520000 0 0x10000>; 8469 reg-names = "drv-0", "drv-1", "drv-2"; 8470 8471 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 8472 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 8473 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 8474 qcom,tcs-offset = <0xd00>; 8475 qcom,drv-id = <2>; 8476 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 8477 <WAKE_TCS 2>, <CONTROL_TCS 0>; 8478 8479 label = "apps_rsc"; 8480 power-domains = <&system_pd>; 8481 8482 apps_bcm_voter: bcm-voter { 8483 compatible = "qcom,bcm-voter"; 8484 }; 8485 8486 rpmhcc: clock-controller { 8487 compatible = "qcom,x1e80100-rpmh-clk"; 8488 8489 clocks = <&xo_board>; 8490 clock-names = "xo"; 8491 8492 #clock-cells = <1>; 8493 }; 8494 8495 rpmhpd: power-controller { 8496 compatible = "qcom,x1e80100-rpmhpd"; 8497 8498 operating-points-v2 = <&rpmhpd_opp_table>; 8499 8500 #power-domain-cells = <1>; 8501 8502 rpmhpd_opp_table: opp-table { 8503 compatible = "operating-points-v2"; 8504 8505 rpmhpd_opp_ret: opp-16 { 8506 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 8507 }; 8508 8509 rpmhpd_opp_min_svs: opp-48 { 8510 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 8511 }; 8512 8513 rpmhpd_opp_low_svs_d2: opp-52 { 8514 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 8515 }; 8516 8517 rpmhpd_opp_low_svs_d1: opp-56 { 8518 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 8519 }; 8520 8521 rpmhpd_opp_low_svs_d0: opp-60 { 8522 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 8523 }; 8524 8525 rpmhpd_opp_low_svs: opp-64 { 8526 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 8527 }; 8528 8529 rpmhpd_opp_low_svs_l1: opp-80 { 8530 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 8531 }; 8532 8533 rpmhpd_opp_svs: opp-128 { 8534 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 8535 }; 8536 8537 rpmhpd_opp_svs_l0: opp-144 { 8538 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 8539 }; 8540 8541 rpmhpd_opp_svs_l1: opp-192 { 8542 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 8543 }; 8544 8545 rpmhpd_opp_nom: opp-256 { 8546 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 8547 }; 8548 8549 rpmhpd_opp_nom_l1: opp-320 { 8550 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 8551 }; 8552 8553 rpmhpd_opp_nom_l2: opp-336 { 8554 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 8555 }; 8556 8557 rpmhpd_opp_turbo: opp-384 { 8558 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 8559 }; 8560 8561 rpmhpd_opp_turbo_l1: opp-416 { 8562 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 8563 }; 8564 }; 8565 }; 8566 }; 8567 8568 timer@17800000 { 8569 compatible = "arm,armv7-timer-mem"; 8570 reg = <0 0x17800000 0 0x1000>; 8571 8572 #address-cells = <2>; 8573 #size-cells = <1>; 8574 ranges = <0 0 0 0 0x20000000>; 8575 8576 frame@17801000 { 8577 reg = <0 0x17801000 0x1000>, 8578 <0 0x17802000 0x1000>; 8579 8580 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 8581 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 8582 8583 frame-number = <0>; 8584 }; 8585 8586 frame@17803000 { 8587 reg = <0 0x17803000 0x1000>; 8588 8589 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 8590 8591 frame-number = <1>; 8592 8593 status = "disabled"; 8594 }; 8595 8596 frame@17805000 { 8597 reg = <0 0x17805000 0x1000>; 8598 8599 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 8600 8601 frame-number = <2>; 8602 8603 status = "disabled"; 8604 }; 8605 8606 frame@17807000 { 8607 reg = <0 0x17807000 0x1000>; 8608 8609 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 8610 8611 frame-number = <3>; 8612 8613 status = "disabled"; 8614 }; 8615 8616 frame@17809000 { 8617 reg = <0 0x17809000 0x1000>; 8618 8619 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 8620 8621 frame-number = <4>; 8622 8623 status = "disabled"; 8624 }; 8625 8626 frame@1780b000 { 8627 reg = <0 0x1780b000 0x1000>; 8628 8629 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8630 8631 frame-number = <5>; 8632 8633 status = "disabled"; 8634 }; 8635 8636 frame@1780d000 { 8637 reg = <0 0x1780d000 0x1000>; 8638 8639 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8640 8641 frame-number = <6>; 8642 8643 status = "disabled"; 8644 }; 8645 }; 8646 8647 sram: sram@18b4e000 { 8648 compatible = "mmio-sram"; 8649 reg = <0x0 0x18b4e000 0x0 0x400>; 8650 8651 #address-cells = <1>; 8652 #size-cells = <1>; 8653 ranges = <0x0 0x0 0x18b4e000 0x400>; 8654 8655 cpu_scp_lpri0: scp-sram-section@0 { 8656 compatible = "arm,scmi-shmem"; 8657 reg = <0x0 0x200>; 8658 }; 8659 8660 cpu_scp_lpri1: scp-sram-section@200 { 8661 compatible = "arm,scmi-shmem"; 8662 reg = <0x200 0x200>; 8663 }; 8664 }; 8665 8666 sbsa_watchdog: watchdog@1c840000 { 8667 compatible = "arm,sbsa-gwdt"; 8668 reg = <0 0x1c840000 0 0x1000>, 8669 <0 0x1c850000 0 0x1000>; 8670 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 8671 }; 8672 8673 qfprom: efuse@221c8000 { 8674 compatible = "qcom,x1e80100-qfprom", "qcom,qfprom"; 8675 reg = <0 0x221c8000 0 0x1000>; 8676 #address-cells = <1>; 8677 #size-cells = <1>; 8678 8679 gpu_speed_bin: gpu-speed-bin@119 { 8680 reg = <0x119 0x2>; 8681 bits = <7 8>; 8682 }; 8683 }; 8684 8685 pmu@24091000 { 8686 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 8687 reg = <0 0x24091000 0 0x1000>; 8688 8689 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 8690 8691 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 8692 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 8693 8694 operating-points-v2 = <&llcc_bwmon_opp_table>; 8695 8696 llcc_bwmon_opp_table: opp-table { 8697 compatible = "operating-points-v2"; 8698 8699 opp-0 { 8700 opp-peak-kBps = <800000>; 8701 }; 8702 8703 opp-1 { 8704 opp-peak-kBps = <2188000>; 8705 }; 8706 8707 opp-2 { 8708 opp-peak-kBps = <3072000>; 8709 }; 8710 8711 opp-3 { 8712 opp-peak-kBps = <6220800>; 8713 }; 8714 8715 opp-4 { 8716 opp-peak-kBps = <6835200>; 8717 }; 8718 8719 opp-5 { 8720 opp-peak-kBps = <8371200>; 8721 }; 8722 8723 opp-6 { 8724 opp-peak-kBps = <10944000>; 8725 }; 8726 8727 opp-7 { 8728 opp-peak-kBps = <12748800>; 8729 }; 8730 8731 opp-8 { 8732 opp-peak-kBps = <14745600>; 8733 }; 8734 8735 opp-9 { 8736 opp-peak-kBps = <16896000>; 8737 }; 8738 }; 8739 }; 8740 8741 /* cluster0 */ 8742 bwmon_cluster0: pmu@240b3400 { 8743 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8744 reg = <0 0x240b3400 0 0x600>; 8745 8746 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8747 8748 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8749 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8750 8751 operating-points-v2 = <&cpu_bwmon_opp_table>; 8752 }; 8753 8754 /* cluster2 */ 8755 bwmon_cluster2: pmu@240b5400 { 8756 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8757 reg = <0 0x240b5400 0 0x600>; 8758 8759 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8760 8761 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8762 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8763 8764 operating-points-v2 = <&cpu_bwmon_opp_table>; 8765 8766 cpu_bwmon_opp_table: opp-table { 8767 compatible = "operating-points-v2"; 8768 8769 opp-0 { 8770 opp-peak-kBps = <4800000>; 8771 }; 8772 8773 opp-1 { 8774 opp-peak-kBps = <7464000>; 8775 }; 8776 8777 opp-2 { 8778 opp-peak-kBps = <9600000>; 8779 }; 8780 8781 opp-3 { 8782 opp-peak-kBps = <12896000>; 8783 }; 8784 8785 opp-4 { 8786 opp-peak-kBps = <14928000>; 8787 }; 8788 8789 opp-5 { 8790 opp-peak-kBps = <17064000>; 8791 }; 8792 }; 8793 }; 8794 8795 /* cluster1 */ 8796 pmu@240b6400 { 8797 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8798 reg = <0 0x240b6400 0 0x600>; 8799 8800 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8801 8802 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8803 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8804 8805 operating-points-v2 = <&cpu_bwmon_opp_table>; 8806 }; 8807 8808 system-cache-controller@25000000 { 8809 compatible = "qcom,x1e80100-llcc"; 8810 reg = <0 0x25000000 0 0x200000>, 8811 <0 0x25200000 0 0x200000>, 8812 <0 0x25400000 0 0x200000>, 8813 <0 0x25600000 0 0x200000>, 8814 <0 0x25800000 0 0x200000>, 8815 <0 0x25a00000 0 0x200000>, 8816 <0 0x25c00000 0 0x200000>, 8817 <0 0x25e00000 0 0x200000>, 8818 <0 0x26000000 0 0x200000>, 8819 <0 0x26200000 0 0x200000>; 8820 reg-names = "llcc0_base", 8821 "llcc1_base", 8822 "llcc2_base", 8823 "llcc3_base", 8824 "llcc4_base", 8825 "llcc5_base", 8826 "llcc6_base", 8827 "llcc7_base", 8828 "llcc_broadcast_base", 8829 "llcc_broadcast_and_base"; 8830 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 8831 }; 8832 8833 remoteproc_cdsp: remoteproc@32300000 { 8834 compatible = "qcom,x1e80100-cdsp-pas"; 8835 reg = <0x0 0x32300000 0x0 0x10000>; 8836 8837 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 8838 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 8839 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 8840 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 8841 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 8842 interrupt-names = "wdog", 8843 "fatal", 8844 "ready", 8845 "handover", 8846 "stop-ack"; 8847 8848 clocks = <&rpmhcc RPMH_CXO_CLK>; 8849 clock-names = "xo"; 8850 8851 power-domains = <&rpmhpd RPMHPD_CX>, 8852 <&rpmhpd RPMHPD_MXC>, 8853 <&rpmhpd RPMHPD_NSP>; 8854 power-domain-names = "cx", 8855 "mxc", 8856 "nsp"; 8857 8858 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 8859 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 8860 8861 memory-region = <&cdsp_mem>, 8862 <&q6_cdsp_dtb_mem>; 8863 8864 qcom,qmp = <&aoss_qmp>; 8865 8866 qcom,smem-states = <&smp2p_cdsp_out 0>; 8867 qcom,smem-state-names = "stop"; 8868 8869 status = "disabled"; 8870 8871 glink-edge { 8872 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 8873 IPCC_MPROC_SIGNAL_GLINK_QMP 8874 IRQ_TYPE_EDGE_RISING>; 8875 mboxes = <&ipcc IPCC_CLIENT_CDSP 8876 IPCC_MPROC_SIGNAL_GLINK_QMP>; 8877 8878 label = "cdsp"; 8879 qcom,remote-pid = <5>; 8880 8881 fastrpc { 8882 compatible = "qcom,fastrpc"; 8883 qcom,glink-channels = "fastrpcglink-apps-dsp"; 8884 label = "cdsp"; 8885 qcom,non-secure-domain; 8886 #address-cells = <1>; 8887 #size-cells = <0>; 8888 8889 compute-cb@1 { 8890 compatible = "qcom,fastrpc-compute-cb"; 8891 reg = <1>; 8892 iommus = <&apps_smmu 0x0c01 0x20>; 8893 dma-coherent; 8894 }; 8895 8896 compute-cb@2 { 8897 compatible = "qcom,fastrpc-compute-cb"; 8898 reg = <2>; 8899 iommus = <&apps_smmu 0x0c02 0x20>; 8900 dma-coherent; 8901 }; 8902 8903 compute-cb@3 { 8904 compatible = "qcom,fastrpc-compute-cb"; 8905 reg = <3>; 8906 iommus = <&apps_smmu 0x0c03 0x20>; 8907 dma-coherent; 8908 }; 8909 8910 compute-cb@4 { 8911 compatible = "qcom,fastrpc-compute-cb"; 8912 reg = <4>; 8913 iommus = <&apps_smmu 0x0c04 0x20>; 8914 dma-coherent; 8915 }; 8916 8917 compute-cb@5 { 8918 compatible = "qcom,fastrpc-compute-cb"; 8919 reg = <5>; 8920 iommus = <&apps_smmu 0x0c05 0x20>; 8921 dma-coherent; 8922 }; 8923 8924 compute-cb@6 { 8925 compatible = "qcom,fastrpc-compute-cb"; 8926 reg = <6>; 8927 iommus = <&apps_smmu 0x0c06 0x20>; 8928 dma-coherent; 8929 }; 8930 8931 compute-cb@7 { 8932 compatible = "qcom,fastrpc-compute-cb"; 8933 reg = <7>; 8934 iommus = <&apps_smmu 0x0c07 0x20>; 8935 dma-coherent; 8936 }; 8937 8938 compute-cb@8 { 8939 compatible = "qcom,fastrpc-compute-cb"; 8940 reg = <8>; 8941 iommus = <&apps_smmu 0x0c08 0x20>; 8942 dma-coherent; 8943 }; 8944 8945 /* note: compute-cb@9 is secure */ 8946 8947 compute-cb@10 { 8948 compatible = "qcom,fastrpc-compute-cb"; 8949 reg = <10>; 8950 iommus = <&apps_smmu 0x0c0c 0x20>; 8951 dma-coherent; 8952 }; 8953 8954 compute-cb@11 { 8955 compatible = "qcom,fastrpc-compute-cb"; 8956 reg = <11>; 8957 iommus = <&apps_smmu 0x0c0d 0x20>; 8958 dma-coherent; 8959 }; 8960 8961 compute-cb@12 { 8962 compatible = "qcom,fastrpc-compute-cb"; 8963 reg = <12>; 8964 iommus = <&apps_smmu 0x0c0e 0x20>; 8965 dma-coherent; 8966 }; 8967 8968 compute-cb@13 { 8969 compatible = "qcom,fastrpc-compute-cb"; 8970 reg = <13>; 8971 iommus = <&apps_smmu 0x0c0f 0x20>; 8972 dma-coherent; 8973 }; 8974 }; 8975 }; 8976 }; 8977 }; 8978 8979 timer { 8980 compatible = "arm,armv8-timer"; 8981 8982 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8983 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8984 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8985 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 8986 }; 8987 8988 thermal_zones: thermal-zones { 8989 aoss0-thermal { 8990 thermal-sensors = <&tsens0 0>; 8991 8992 trips { 8993 trip-point0 { 8994 temperature = <90000>; 8995 hysteresis = <2000>; 8996 type = "hot"; 8997 }; 8998 8999 aoss0-critical { 9000 temperature = <115000>; 9001 hysteresis = <1000>; 9002 type = "critical"; 9003 }; 9004 }; 9005 }; 9006 9007 cpu0-0-top-thermal { 9008 thermal-sensors = <&tsens0 1>; 9009 9010 trips { 9011 cpu-critical { 9012 temperature = <115000>; 9013 hysteresis = <1000>; 9014 type = "critical"; 9015 }; 9016 }; 9017 }; 9018 9019 cpu0-0-btm-thermal { 9020 thermal-sensors = <&tsens0 2>; 9021 9022 trips { 9023 cpu-critical { 9024 temperature = <115000>; 9025 hysteresis = <1000>; 9026 type = "critical"; 9027 }; 9028 }; 9029 }; 9030 9031 cpu0-1-top-thermal { 9032 thermal-sensors = <&tsens0 3>; 9033 9034 trips { 9035 cpu-critical { 9036 temperature = <115000>; 9037 hysteresis = <1000>; 9038 type = "critical"; 9039 }; 9040 }; 9041 }; 9042 9043 cpu0-1-btm-thermal { 9044 thermal-sensors = <&tsens0 4>; 9045 9046 trips { 9047 cpu-critical { 9048 temperature = <115000>; 9049 hysteresis = <1000>; 9050 type = "critical"; 9051 }; 9052 }; 9053 }; 9054 9055 cpu0-2-top-thermal { 9056 thermal-sensors = <&tsens0 5>; 9057 9058 trips { 9059 cpu-critical { 9060 temperature = <115000>; 9061 hysteresis = <1000>; 9062 type = "critical"; 9063 }; 9064 }; 9065 }; 9066 9067 cpu0-2-btm-thermal { 9068 thermal-sensors = <&tsens0 6>; 9069 9070 trips { 9071 cpu-critical { 9072 temperature = <115000>; 9073 hysteresis = <1000>; 9074 type = "critical"; 9075 }; 9076 }; 9077 }; 9078 9079 cpu0-3-top-thermal { 9080 thermal-sensors = <&tsens0 7>; 9081 9082 trips { 9083 cpu-critical { 9084 temperature = <115000>; 9085 hysteresis = <1000>; 9086 type = "critical"; 9087 }; 9088 }; 9089 }; 9090 9091 cpu0-3-btm-thermal { 9092 thermal-sensors = <&tsens0 8>; 9093 9094 trips { 9095 cpu-critical { 9096 temperature = <115000>; 9097 hysteresis = <1000>; 9098 type = "critical"; 9099 }; 9100 }; 9101 }; 9102 9103 cpuss0-top-thermal { 9104 thermal-sensors = <&tsens0 9>; 9105 9106 trips { 9107 cpuss2-critical { 9108 temperature = <115000>; 9109 hysteresis = <1000>; 9110 type = "critical"; 9111 }; 9112 }; 9113 }; 9114 9115 cpuss0-btm-thermal { 9116 thermal-sensors = <&tsens0 10>; 9117 9118 trips { 9119 cpuss2-critical { 9120 temperature = <115000>; 9121 hysteresis = <1000>; 9122 type = "critical"; 9123 }; 9124 }; 9125 }; 9126 9127 mem-thermal { 9128 thermal-sensors = <&tsens0 11>; 9129 9130 trips { 9131 trip-point0 { 9132 temperature = <90000>; 9133 hysteresis = <2000>; 9134 type = "hot"; 9135 }; 9136 9137 mem-critical { 9138 temperature = <115000>; 9139 hysteresis = <0>; 9140 type = "critical"; 9141 }; 9142 }; 9143 }; 9144 9145 video-thermal { 9146 thermal-sensors = <&tsens0 12>; 9147 9148 trips { 9149 trip-point0 { 9150 temperature = <90000>; 9151 hysteresis = <2000>; 9152 type = "hot"; 9153 }; 9154 9155 video-critical { 9156 temperature = <115000>; 9157 hysteresis = <1000>; 9158 type = "critical"; 9159 }; 9160 }; 9161 }; 9162 9163 aoss1-thermal { 9164 thermal-sensors = <&tsens1 0>; 9165 9166 trips { 9167 trip-point0 { 9168 temperature = <90000>; 9169 hysteresis = <2000>; 9170 type = "hot"; 9171 }; 9172 9173 aoss0-critical { 9174 temperature = <115000>; 9175 hysteresis = <1000>; 9176 type = "critical"; 9177 }; 9178 }; 9179 }; 9180 9181 cpu1-0-top-thermal { 9182 thermal-sensors = <&tsens1 1>; 9183 9184 trips { 9185 cpu-critical { 9186 temperature = <115000>; 9187 hysteresis = <1000>; 9188 type = "critical"; 9189 }; 9190 }; 9191 }; 9192 9193 cpu1-0-btm-thermal { 9194 thermal-sensors = <&tsens1 2>; 9195 9196 trips { 9197 cpu-critical { 9198 temperature = <115000>; 9199 hysteresis = <1000>; 9200 type = "critical"; 9201 }; 9202 }; 9203 }; 9204 9205 cpu1-1-top-thermal { 9206 thermal-sensors = <&tsens1 3>; 9207 9208 trips { 9209 cpu-critical { 9210 temperature = <115000>; 9211 hysteresis = <1000>; 9212 type = "critical"; 9213 }; 9214 }; 9215 }; 9216 9217 cpu1-1-btm-thermal { 9218 thermal-sensors = <&tsens1 4>; 9219 9220 trips { 9221 cpu-critical { 9222 temperature = <115000>; 9223 hysteresis = <1000>; 9224 type = "critical"; 9225 }; 9226 }; 9227 }; 9228 9229 cpu1-2-top-thermal { 9230 thermal-sensors = <&tsens1 5>; 9231 9232 trips { 9233 cpu-critical { 9234 temperature = <115000>; 9235 hysteresis = <1000>; 9236 type = "critical"; 9237 }; 9238 }; 9239 }; 9240 9241 cpu1-2-btm-thermal { 9242 thermal-sensors = <&tsens1 6>; 9243 9244 trips { 9245 cpu-critical { 9246 temperature = <115000>; 9247 hysteresis = <1000>; 9248 type = "critical"; 9249 }; 9250 }; 9251 }; 9252 9253 cpu1-3-top-thermal { 9254 thermal-sensors = <&tsens1 7>; 9255 9256 trips { 9257 cpu-critical { 9258 temperature = <115000>; 9259 hysteresis = <1000>; 9260 type = "critical"; 9261 }; 9262 }; 9263 }; 9264 9265 cpu1-3-btm-thermal { 9266 thermal-sensors = <&tsens1 8>; 9267 9268 trips { 9269 cpu-critical { 9270 temperature = <115000>; 9271 hysteresis = <1000>; 9272 type = "critical"; 9273 }; 9274 }; 9275 }; 9276 9277 cpuss1-top-thermal { 9278 thermal-sensors = <&tsens1 9>; 9279 9280 trips { 9281 cpuss2-critical { 9282 temperature = <115000>; 9283 hysteresis = <1000>; 9284 type = "critical"; 9285 }; 9286 }; 9287 }; 9288 9289 cpuss1-btm-thermal { 9290 thermal-sensors = <&tsens1 10>; 9291 9292 trips { 9293 cpuss2-critical { 9294 temperature = <115000>; 9295 hysteresis = <1000>; 9296 type = "critical"; 9297 }; 9298 }; 9299 }; 9300 9301 aoss2-thermal { 9302 thermal-sensors = <&tsens2 0>; 9303 9304 trips { 9305 trip-point0 { 9306 temperature = <90000>; 9307 hysteresis = <2000>; 9308 type = "hot"; 9309 }; 9310 9311 aoss0-critical { 9312 temperature = <115000>; 9313 hysteresis = <1000>; 9314 type = "critical"; 9315 }; 9316 }; 9317 }; 9318 9319 thermal_cpu2_0_top: cpu2-0-top-thermal { 9320 thermal-sensors = <&tsens2 1>; 9321 9322 trips { 9323 cpu-critical { 9324 temperature = <115000>; 9325 hysteresis = <1000>; 9326 type = "critical"; 9327 }; 9328 }; 9329 }; 9330 9331 thermal_cpu2_0_btm: cpu2-0-btm-thermal { 9332 thermal-sensors = <&tsens2 2>; 9333 9334 trips { 9335 cpu-critical { 9336 temperature = <115000>; 9337 hysteresis = <1000>; 9338 type = "critical"; 9339 }; 9340 }; 9341 }; 9342 9343 thermal_cpu2_1_top: cpu2-1-top-thermal { 9344 thermal-sensors = <&tsens2 3>; 9345 9346 trips { 9347 cpu-critical { 9348 temperature = <115000>; 9349 hysteresis = <1000>; 9350 type = "critical"; 9351 }; 9352 }; 9353 }; 9354 9355 thermal_cpu2_1_btm: cpu2-1-btm-thermal { 9356 thermal-sensors = <&tsens2 4>; 9357 9358 trips { 9359 cpu-critical { 9360 temperature = <115000>; 9361 hysteresis = <1000>; 9362 type = "critical"; 9363 }; 9364 }; 9365 }; 9366 9367 thermal_cpu2_2_top: cpu2-2-top-thermal { 9368 thermal-sensors = <&tsens2 5>; 9369 9370 trips { 9371 cpu-critical { 9372 temperature = <115000>; 9373 hysteresis = <1000>; 9374 type = "critical"; 9375 }; 9376 }; 9377 }; 9378 9379 thermal_cpu2_2_btm: cpu2-2-btm-thermal { 9380 thermal-sensors = <&tsens2 6>; 9381 9382 trips { 9383 cpu-critical { 9384 temperature = <115000>; 9385 hysteresis = <1000>; 9386 type = "critical"; 9387 }; 9388 }; 9389 }; 9390 9391 thermal_cpu2_3_top: cpu2-3-top-thermal { 9392 thermal-sensors = <&tsens2 7>; 9393 9394 trips { 9395 cpu-critical { 9396 temperature = <115000>; 9397 hysteresis = <1000>; 9398 type = "critical"; 9399 }; 9400 }; 9401 }; 9402 9403 thermal_cpu2_3_btm: cpu2-3-btm-thermal { 9404 thermal-sensors = <&tsens2 8>; 9405 9406 trips { 9407 cpu-critical { 9408 temperature = <115000>; 9409 hysteresis = <1000>; 9410 type = "critical"; 9411 }; 9412 }; 9413 }; 9414 9415 thermal_cpuss2_top: cpuss2-top-thermal { 9416 thermal-sensors = <&tsens2 9>; 9417 9418 trips { 9419 cpuss2-critical { 9420 temperature = <115000>; 9421 hysteresis = <1000>; 9422 type = "critical"; 9423 }; 9424 }; 9425 }; 9426 9427 thermal_cpuss2_btm: cpuss2-btm-thermal { 9428 thermal-sensors = <&tsens2 10>; 9429 9430 trips { 9431 cpuss2-critical { 9432 temperature = <115000>; 9433 hysteresis = <1000>; 9434 type = "critical"; 9435 }; 9436 }; 9437 }; 9438 9439 thermal_aoss3: aoss3-thermal { 9440 thermal-sensors = <&tsens3 0>; 9441 9442 trips { 9443 trip-point0 { 9444 temperature = <90000>; 9445 hysteresis = <2000>; 9446 type = "hot"; 9447 }; 9448 9449 aoss0-critical { 9450 temperature = <115000>; 9451 hysteresis = <1000>; 9452 type = "critical"; 9453 }; 9454 }; 9455 }; 9456 9457 thermal_nsp0: nsp0-thermal { 9458 thermal-sensors = <&tsens3 1>; 9459 9460 trips { 9461 trip-point0 { 9462 temperature = <90000>; 9463 hysteresis = <2000>; 9464 type = "hot"; 9465 }; 9466 9467 nsp0-critical { 9468 temperature = <115000>; 9469 hysteresis = <1000>; 9470 type = "critical"; 9471 }; 9472 }; 9473 }; 9474 9475 thermal_nsp1: nsp1-thermal { 9476 thermal-sensors = <&tsens3 2>; 9477 9478 trips { 9479 trip-point0 { 9480 temperature = <90000>; 9481 hysteresis = <2000>; 9482 type = "hot"; 9483 }; 9484 9485 nsp1-critical { 9486 temperature = <115000>; 9487 hysteresis = <1000>; 9488 type = "critical"; 9489 }; 9490 }; 9491 }; 9492 9493 thermal_nsp2: nsp2-thermal { 9494 thermal-sensors = <&tsens3 3>; 9495 9496 trips { 9497 trip-point0 { 9498 temperature = <90000>; 9499 hysteresis = <2000>; 9500 type = "hot"; 9501 }; 9502 9503 nsp2-critical { 9504 temperature = <115000>; 9505 hysteresis = <1000>; 9506 type = "critical"; 9507 }; 9508 }; 9509 }; 9510 9511 thermal_nsp3: nsp3-thermal { 9512 thermal-sensors = <&tsens3 4>; 9513 9514 trips { 9515 trip-point0 { 9516 temperature = <90000>; 9517 hysteresis = <2000>; 9518 type = "hot"; 9519 }; 9520 9521 nsp3-critical { 9522 temperature = <115000>; 9523 hysteresis = <1000>; 9524 type = "critical"; 9525 }; 9526 }; 9527 }; 9528 9529 thermal_gpuss_0: gpuss-0-thermal { 9530 polling-delay-passive = <200>; 9531 9532 thermal-sensors = <&tsens3 5>; 9533 9534 cooling-maps { 9535 map0 { 9536 trip = <&gpuss0_alert0>; 9537 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9538 }; 9539 }; 9540 9541 trips { 9542 gpuss0_alert0: trip-point0 { 9543 temperature = <95000>; 9544 hysteresis = <1000>; 9545 type = "passive"; 9546 }; 9547 9548 gpu-critical { 9549 temperature = <115000>; 9550 hysteresis = <1000>; 9551 type = "critical"; 9552 }; 9553 }; 9554 }; 9555 9556 thermal_gpuss_1: gpuss-1-thermal { 9557 polling-delay-passive = <200>; 9558 9559 thermal-sensors = <&tsens3 6>; 9560 9561 cooling-maps { 9562 map0 { 9563 trip = <&gpuss1_alert0>; 9564 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9565 }; 9566 }; 9567 9568 trips { 9569 gpuss1_alert0: trip-point0 { 9570 temperature = <95000>; 9571 hysteresis = <1000>; 9572 type = "passive"; 9573 }; 9574 9575 gpu-critical { 9576 temperature = <115000>; 9577 hysteresis = <1000>; 9578 type = "critical"; 9579 }; 9580 }; 9581 }; 9582 9583 thermal_gpuss_2: gpuss-2-thermal { 9584 polling-delay-passive = <200>; 9585 9586 thermal-sensors = <&tsens3 7>; 9587 9588 cooling-maps { 9589 map0 { 9590 trip = <&gpuss2_alert0>; 9591 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9592 }; 9593 }; 9594 9595 trips { 9596 gpuss2_alert0: trip-point0 { 9597 temperature = <95000>; 9598 hysteresis = <1000>; 9599 type = "passive"; 9600 }; 9601 9602 gpu-critical { 9603 temperature = <115000>; 9604 hysteresis = <1000>; 9605 type = "critical"; 9606 }; 9607 }; 9608 }; 9609 9610 thermal_gpuss_3: gpuss-3-thermal { 9611 polling-delay-passive = <200>; 9612 9613 thermal-sensors = <&tsens3 8>; 9614 9615 cooling-maps { 9616 map0 { 9617 trip = <&gpuss3_alert0>; 9618 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9619 }; 9620 }; 9621 9622 trips { 9623 gpuss3_alert0: trip-point0 { 9624 temperature = <95000>; 9625 hysteresis = <1000>; 9626 type = "passive"; 9627 }; 9628 9629 gpu-critical { 9630 temperature = <115000>; 9631 hysteresis = <1000>; 9632 type = "critical"; 9633 }; 9634 }; 9635 }; 9636 9637 thermal_gpuss_4: gpuss-4-thermal { 9638 polling-delay-passive = <200>; 9639 9640 thermal-sensors = <&tsens3 9>; 9641 9642 cooling-maps { 9643 map0 { 9644 trip = <&gpuss4_alert0>; 9645 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9646 }; 9647 }; 9648 9649 trips { 9650 gpuss4_alert0: trip-point0 { 9651 temperature = <95000>; 9652 hysteresis = <1000>; 9653 type = "passive"; 9654 }; 9655 9656 gpu-critical { 9657 temperature = <115000>; 9658 hysteresis = <1000>; 9659 type = "critical"; 9660 }; 9661 }; 9662 }; 9663 9664 thermal_gpuss_5: gpuss-5-thermal { 9665 polling-delay-passive = <200>; 9666 9667 thermal-sensors = <&tsens3 10>; 9668 9669 cooling-maps { 9670 map0 { 9671 trip = <&gpuss5_alert0>; 9672 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9673 }; 9674 }; 9675 9676 trips { 9677 gpuss5_alert0: trip-point0 { 9678 temperature = <95000>; 9679 hysteresis = <1000>; 9680 type = "passive"; 9681 }; 9682 9683 gpu-critical { 9684 temperature = <115000>; 9685 hysteresis = <1000>; 9686 type = "critical"; 9687 }; 9688 }; 9689 }; 9690 9691 thermal_gpuss_6: gpuss-6-thermal { 9692 polling-delay-passive = <200>; 9693 9694 thermal-sensors = <&tsens3 11>; 9695 9696 cooling-maps { 9697 map0 { 9698 trip = <&gpuss6_alert0>; 9699 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9700 }; 9701 }; 9702 9703 trips { 9704 gpuss6_alert0: trip-point0 { 9705 temperature = <95000>; 9706 hysteresis = <1000>; 9707 type = "passive"; 9708 }; 9709 9710 gpu-critical { 9711 temperature = <115000>; 9712 hysteresis = <1000>; 9713 type = "critical"; 9714 }; 9715 }; 9716 }; 9717 9718 thermal_gpuss_7: gpuss-7-thermal { 9719 polling-delay-passive = <200>; 9720 9721 thermal-sensors = <&tsens3 12>; 9722 9723 cooling-maps { 9724 map0 { 9725 trip = <&gpuss7_alert0>; 9726 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9727 }; 9728 }; 9729 9730 trips { 9731 gpuss7_alert0: trip-point0 { 9732 temperature = <95000>; 9733 hysteresis = <1000>; 9734 type = "passive"; 9735 }; 9736 9737 gpu-critical { 9738 temperature = <115000>; 9739 hysteresis = <1000>; 9740 type = "critical"; 9741 }; 9742 }; 9743 }; 9744 9745 thermal_camera0: camera0-thermal { 9746 thermal-sensors = <&tsens3 13>; 9747 9748 trips { 9749 trip-point0 { 9750 temperature = <90000>; 9751 hysteresis = <2000>; 9752 type = "hot"; 9753 }; 9754 9755 camera0-critical { 9756 temperature = <115000>; 9757 hysteresis = <1000>; 9758 type = "critical"; 9759 }; 9760 }; 9761 }; 9762 9763 thermal_camera1: camera1-thermal { 9764 thermal-sensors = <&tsens3 14>; 9765 9766 trips { 9767 trip-point0 { 9768 temperature = <90000>; 9769 hysteresis = <2000>; 9770 type = "hot"; 9771 }; 9772 9773 camera0-critical { 9774 temperature = <115000>; 9775 hysteresis = <1000>; 9776 type = "critical"; 9777 }; 9778 }; 9779 }; 9780 }; 9781}; 9782