1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/usb/pd.h> 10#include "imx8qm.dtsi" 11 12/ { 13 model = "Freescale i.MX8QM MEK"; 14 compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; 15 16 chosen { 17 stdout-path = &lpuart0; 18 }; 19 20 cpus { 21 /delete-node/ cpu-map; 22 /delete-node/ cpu@100; 23 /delete-node/ cpu@101; 24 }; 25 26 thermal-zones { 27 /delete-node/ cpu1-thermal; 28 }; 29 30 memory@80000000 { 31 device_type = "memory"; 32 reg = <0x00000000 0x80000000 0 0x40000000>; 33 }; 34 35 xtal24m: clock-xtal24m { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <24000000>; 39 clock-output-names = "xtal_24MHz"; 40 }; 41 42 reserved-memory { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 vdev0vring0: memory@90000000 { 48 reg = <0 0x90000000 0 0x8000>; 49 no-map; 50 }; 51 52 vdev0vring1: memory@90008000 { 53 reg = <0 0x90008000 0 0x8000>; 54 no-map; 55 }; 56 57 vdev1vring0: memory@90010000 { 58 reg = <0 0x90010000 0 0x8000>; 59 no-map; 60 }; 61 62 vdev1vring1: memory@90018000 { 63 reg = <0 0x90018000 0 0x8000>; 64 no-map; 65 }; 66 67 rsc_table0: memory@900ff000 { 68 reg = <0 0x900ff000 0 0x1000>; 69 no-map; 70 }; 71 72 vdev2vring0: memory@90100000 { 73 reg = <0 0x90100000 0 0x8000>; 74 no-map; 75 }; 76 77 vdev2vring1: memory@90108000 { 78 reg = <0 0x90108000 0 0x8000>; 79 no-map; 80 }; 81 82 vdev3vring0: memory@90110000 { 83 reg = <0 0x90110000 0 0x8000>; 84 no-map; 85 }; 86 87 vdev3vring1: memory@90118000 { 88 reg = <0 0x90118000 0 0x8000>; 89 no-map; 90 }; 91 92 rsc_table1: memory@901ff000 { 93 reg = <0 0x901ff000 0 0x1000>; 94 no-map; 95 }; 96 97 vdevbuffer: memory@90400000 { 98 compatible = "shared-dma-pool"; 99 reg = <0 0x90400000 0 0x100000>; 100 no-map; 101 }; 102 103 dsp_reserved: memory@92400000 { 104 reg = <0 0x92400000 0 0x1000000>; 105 no-map; 106 }; 107 108 dsp_vdev0vring0: memory@942f0000 { 109 reg = <0 0x942f0000 0 0x8000>; 110 no-map; 111 }; 112 113 dsp_vdev0vring1: memory@942f8000 { 114 reg = <0 0x942f8000 0 0x8000>; 115 no-map; 116 }; 117 118 dsp_vdev0buffer: memory@94300000 { 119 compatible = "shared-dma-pool"; 120 reg = <0 0x94300000 0 0x100000>; 121 no-map; 122 }; 123 124 /* global autoconfigured region for contiguous allocations */ 125 linux,cma { 126 compatible = "shared-dma-pool"; 127 alloc-ranges = <0 0xc0000000 0 0x3c000000>; 128 size = <0 0x3c000000>; 129 linux,cma-default; 130 reusable; 131 }; 132 }; 133 134 lvds_backlight0: backlight-lvds0 { 135 compatible = "pwm-backlight"; 136 pwms = <&qm_pwm_lvds0 0 100000 0>; 137 brightness-levels = <0 100>; 138 num-interpolated-steps = <100>; 139 default-brightness-level = <80>; 140 }; 141 142 lvds_backlight1: backlight-lvds1 { 143 compatible = "pwm-backlight"; 144 pwms = <&pwm_lvds1 0 100000 0>; 145 brightness-levels = <0 100>; 146 num-interpolated-steps = <100>; 147 default-brightness-level = <80>; 148 }; 149 150 i2c-mux { 151 compatible = "i2c-mux-gpio"; 152 mux-gpios = <&lsio_gpio5 3 GPIO_ACTIVE_HIGH>; /* needs to be an unused GPIO */ 153 i2c-parent = <&i2c1>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 i2c@0 { 158 reg = <0>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 162 wm8960: audio-codec@1a { 163 compatible = "wlf,wm8960"; 164 reg = <0x1a>; 165 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 166 clock-names = "mclk"; 167 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 168 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 169 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 170 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 171 assigned-clock-rates = <786432000>, 172 <49152000>, 173 <12288000>, 174 <12288000>; 175 wlf,shared-lrclk; 176 wlf,hp-cfg = <2 2 3>; 177 wlf,gpio-cfg = <1 3>; 178 AVDD-supply = <®_audio_3v3>; 179 DBVDD-supply = <®_audio_1v8>; 180 DCVDD-supply = <®_audio_1v8>; 181 SPKVDD1-supply = <®_audio_5v>; 182 SPKVDD2-supply = <®_audio_5v>; 183 }; 184 }; 185 186 i2c@1 { 187 reg = <1>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 wm8962: wm8962@1a { 192 compatible = "wlf,wm8962"; 193 reg = <0x1a>; 194 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 195 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 196 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 197 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 198 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 199 assigned-clock-rates = <786432000>, 200 <49152000>, 201 <12288000>, 202 <12288000>; 203 DCVDD-supply = <®_audio_1v8>; 204 DBVDD-supply = <®_audio_1v8>; 205 AVDD-supply = <®_audio_1v8>; 206 CPVDD-supply = <®_audio_1v8>; 207 MICVDD-supply = <®_audio_3v3>; 208 PLLVDD-supply = <®_audio_1v8>; 209 SPKVDD1-supply = <®_audio_5v>; 210 SPKVDD2-supply = <®_audio_5v>; 211 }; 212 }; 213 214 }; 215 216 mux-controller { 217 compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_typec_mux>; 220 select-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_HIGH>; 221 enable-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_LOW>; 222 orientation-switch; 223 224 port { 225 usb3_data_ss: endpoint { 226 remote-endpoint = <&typec_con_ss>; 227 }; 228 }; 229 }; 230 231 reg_1v5: regulator-1v5 { 232 compatible = "regulator-fixed"; 233 regulator-name = "1v5"; 234 regulator-min-microvolt = <1500000>; 235 regulator-max-microvolt = <1500000>; 236 }; 237 238 reg_1v8: regulator-1v8 { 239 compatible = "regulator-fixed"; 240 regulator-name = "1v8"; 241 regulator-min-microvolt = <1800000>; 242 regulator-max-microvolt = <1800000>; 243 }; 244 245 reg_2v8: regulator-2v8 { 246 compatible = "regulator-fixed"; 247 regulator-name = "2v8"; 248 regulator-min-microvolt = <2800000>; 249 regulator-max-microvolt = <2800000>; 250 }; 251 252 reg_3v3: regulator-3v3 { 253 compatible = "regulator-fixed"; 254 regulator-name = "3v3"; 255 regulator-min-microvolt = <3300000>; 256 regulator-max-microvolt = <3300000>; 257 }; 258 259 reg_usdhc2_vmmc: usdhc2-vmmc { 260 compatible = "regulator-fixed"; 261 regulator-name = "SD1_SPWR"; 262 regulator-min-microvolt = <3000000>; 263 regulator-max-microvolt = <3000000>; 264 gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; 265 enable-active-high; 266 off-on-delay-us = <4800>; 267 }; 268 269 reg_audio: regulator-audio { 270 compatible = "regulator-fixed"; 271 regulator-name = "cs42888_supply"; 272 regulator-min-microvolt = <3300000>; 273 regulator-max-microvolt = <3300000>; 274 }; 275 276 reg_fec2_supply: regulator-fec2-nvcc { 277 compatible = "regulator-fixed"; 278 regulator-name = "fec2_nvcc"; 279 regulator-min-microvolt = <1800000>; 280 regulator-max-microvolt = <1800000>; 281 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; 282 enable-active-high; 283 }; 284 285 reg_can01_en: regulator-can01-gen { 286 compatible = "regulator-fixed"; 287 regulator-name = "can01-en"; 288 regulator-min-microvolt = <3300000>; 289 regulator-max-microvolt = <3300000>; 290 gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; 291 enable-active-high; 292 }; 293 294 reg_can2_en: regulator-can2-gen { 295 compatible = "regulator-fixed"; 296 regulator-name = "can2-en"; 297 regulator-min-microvolt = <3300000>; 298 regulator-max-microvolt = <3300000>; 299 gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; 300 enable-active-high; 301 }; 302 303 reg_can01_stby: regulator-can01-stby { 304 compatible = "regulator-fixed"; 305 regulator-name = "can01-stby"; 306 regulator-min-microvolt = <3300000>; 307 regulator-max-microvolt = <3300000>; 308 gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; 309 enable-active-high; 310 vin-supply = <®_can01_en>; 311 }; 312 313 reg_can2_stby: regulator-can2-stby { 314 compatible = "regulator-fixed"; 315 regulator-name = "can2-stby"; 316 regulator-min-microvolt = <3300000>; 317 regulator-max-microvolt = <3300000>; 318 gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; 319 enable-active-high; 320 vin-supply = <®_can2_en>; 321 }; 322 323 reg_pciea: regulator-pcie { 324 compatible = "regulator-fixed"; 325 pinctrl-0 = <&pinctrl_pciea_reg>; 326 pinctrl-names = "default"; 327 regulator-max-microvolt = <3300000>; 328 regulator-min-microvolt = <3300000>; 329 regulator-name = "mpcie_3v3"; 330 gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>; 331 enable-active-high; 332 }; 333 334 reg_usb_otg1_vbus: regulator-usbotg1-vbus { 335 compatible = "regulator-fixed"; 336 regulator-name = "usb_otg1_vbus"; 337 regulator-min-microvolt = <5000000>; 338 regulator-max-microvolt = <5000000>; 339 gpio = <&lsio_gpio4 3 GPIO_ACTIVE_HIGH>; 340 enable-active-high; 341 }; 342 343 reg_vref_1v8: regulator-adc-vref { 344 compatible = "regulator-fixed"; 345 regulator-name = "vref_1v8"; 346 regulator-min-microvolt = <1800000>; 347 regulator-max-microvolt = <1800000>; 348 }; 349 350 reg_audio_5v: regulator-audio-pwr { 351 compatible = "regulator-fixed"; 352 regulator-name = "audio-5v"; 353 regulator-min-microvolt = <5000000>; 354 regulator-max-microvolt = <5000000>; 355 regulator-always-on; 356 regulator-boot-on; 357 }; 358 359 reg_audio_3v3: regulator-audio-3v3 { 360 compatible = "regulator-fixed"; 361 regulator-name = "audio-3v3"; 362 regulator-min-microvolt = <3300000>; 363 regulator-max-microvolt = <3300000>; 364 regulator-always-on; 365 regulator-boot-on; 366 }; 367 368 reg_audio_1v8: regulator-audio-1v8 { 369 compatible = "regulator-fixed"; 370 regulator-name = "audio-1v8"; 371 regulator-min-microvolt = <1800000>; 372 regulator-max-microvolt = <1800000>; 373 regulator-always-on; 374 regulator-boot-on; 375 }; 376 377 bt_sco_codec: audio-codec-bt { 378 compatible = "linux,bt-sco"; 379 #sound-dai-cells = <1>; 380 }; 381 382 sound-bt-sco { 383 compatible = "simple-audio-card"; 384 simple-audio-card,name = "bt-sco-audio"; 385 simple-audio-card,format = "dsp_a"; 386 simple-audio-card,bitclock-inversion; 387 simple-audio-card,frame-master = <&btcpu>; 388 simple-audio-card,bitclock-master = <&btcpu>; 389 390 btcpu: simple-audio-card,cpu { 391 sound-dai = <&sai0>; 392 dai-tdm-slot-num = <2>; 393 dai-tdm-slot-width = <16>; 394 }; 395 396 simple-audio-card,codec { 397 sound-dai = <&bt_sco_codec 1>; 398 }; 399 }; 400 401 sound-cs42888 { 402 compatible = "fsl,imx-audio-cs42888"; 403 model = "imx-cs42888"; 404 audio-cpu = <&esai0>; 405 audio-codec = <&cs42888>; 406 audio-asrc = <&asrc0>; 407 audio-routing = "Line Out Jack", "AOUT1L", 408 "Line Out Jack", "AOUT1R", 409 "Line Out Jack", "AOUT2L", 410 "Line Out Jack", "AOUT2R", 411 "Line Out Jack", "AOUT3L", 412 "Line Out Jack", "AOUT3R", 413 "Line Out Jack", "AOUT4L", 414 "Line Out Jack", "AOUT4R", 415 "AIN1L", "Line In Jack", 416 "AIN1R", "Line In Jack", 417 "AIN2L", "Line In Jack", 418 "AIN2R", "Line In Jack"; 419 }; 420 421 sound-wm8960 { 422 compatible = "fsl,imx-audio-wm8960"; 423 model = "wm8960-audio"; 424 audio-cpu = <&sai1>; 425 audio-codec = <&wm8960>; 426 hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; 427 audio-routing = "Headphone Jack", "HP_L", 428 "Headphone Jack", "HP_R", 429 "Ext Spk", "SPK_LP", 430 "Ext Spk", "SPK_LN", 431 "Ext Spk", "SPK_RP", 432 "Ext Spk", "SPK_RN", 433 "LINPUT1", "Mic Jack", 434 "Mic Jack", "MICB"; 435 }; 436 437 sound-wm8962 { 438 compatible = "fsl,imx-audio-wm8962"; 439 model = "wm8962-audio"; 440 audio-cpu = <&sai1>; 441 audio-codec = <&wm8962>; 442 hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; 443 audio-routing = "Headphone Jack", "HPOUTL", 444 "Headphone Jack", "HPOUTR", 445 "Ext Spk", "SPKOUTL", 446 "Ext Spk", "SPKOUTR", 447 "AMIC", "MICBIAS", 448 "IN1R", "AMIC", 449 "IN3R", "AMIC"; 450 }; 451 452 imx8qm-cm4-0 { 453 compatible = "fsl,imx8qm-cm4"; 454 clocks = <&clk_dummy>; 455 mbox-names = "tx", "rx", "rxdb"; 456 mboxes = <&lsio_mu5 0 1 457 &lsio_mu5 1 1 458 &lsio_mu5 3 1>; 459 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 460 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table0>; 461 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>; 462 463 fsl,resource-id = <IMX_SC_R_M4_0_PID0>; 464 fsl,entry-address = <0x34fe0000>; 465 }; 466 467 imx8qm-cm4-1 { 468 compatible = "fsl,imx8qm-cm4"; 469 clocks = <&clk_dummy>; 470 mbox-names = "tx", "rx", "rxdb"; 471 mboxes = <&lsio_mu6 0 1 472 &lsio_mu6 1 1 473 &lsio_mu6 3 1>; 474 memory-region = <&vdevbuffer>, <&vdev2vring0>, <&vdev2vring1>, 475 <&vdev3vring0>, <&vdev3vring1>, <&rsc_table1>; 476 power-domains = <&pd IMX_SC_R_M4_1_PID0>, <&pd IMX_SC_R_M4_1_MU_1A>; 477 478 fsl,resource-id = <IMX_SC_R_M4_1_PID0>; 479 fsl,entry-address = <0x38fe0000>; 480 }; 481 482}; 483 484&adc0 { 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pinctrl_adc0>; 487 vref-supply = <®_vref_1v8>; 488 status = "okay"; 489}; 490 491&amix { 492 status = "okay"; 493}; 494 495&asrc0 { 496 fsl,asrc-rate = <48000>; 497 status = "okay"; 498}; 499 500&cm41_i2c { 501 #address-cells = <1>; 502 #size-cells = <0>; 503 clock-frequency = <100000>; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pinctrl_cm41_i2c>; 506 status = "okay"; 507 508 pca6416: gpio@20 { 509 compatible = "ti,tca6416"; 510 reg = <0x20>; 511 gpio-controller; 512 #gpio-cells = <2>; 513 }; 514 515 cs42888: audio-codec@48 { 516 compatible = "cirrus,cs42888"; 517 reg = <0x48>; 518 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 519 clock-names = "mclk"; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&pinctrl_cs42888_reset>; 522 VA-supply = <®_audio>; 523 VD-supply = <®_audio>; 524 VLS-supply = <®_audio>; 525 VLC-supply = <®_audio>; 526 reset-gpios = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; 527 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 528 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 529 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 530 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 531 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 532 }; 533}; 534 535&cm41_intmux { 536 status = "okay"; 537}; 538 539&esai0 { 540 pinctrl-names = "default"; 541 pinctrl-0 = <&pinctrl_esai0>; 542 assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, 543 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 544 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 545 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 546 <&esai0_lpcg IMX_LPCG_CLK_4>; 547 assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; 548 assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; 549 status = "okay"; 550}; 551 552&hsio_phy { 553 fsl,hsio-cfg = "pciea-pcieb-sata"; 554 fsl,refclk-pad-mode = "input"; 555 status = "okay"; 556}; 557 558&i2c0 { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 clock-frequency = <100000>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&pinctrl_i2c0>; 564 status = "okay"; 565 566 accelerometer@19 { 567 compatible = "st,lsm303agr-accel"; 568 reg = <0x19>; 569 }; 570 571 gyrometer@20 { 572 compatible = "nxp,fxas21002c"; 573 reg = <0x20>; 574 }; 575 576 light-sensor@44 { 577 compatible = "isil,isl29023"; 578 reg = <0x44>; 579 interrupt-parent = <&lsio_gpio4>; 580 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 581 }; 582 583 pressure-sensor@60 { 584 compatible = "fsl,mpl3115"; 585 reg = <0x60>; 586 vdd-supply = <®_3v3>; 587 vddio-supply = <®_3v3>; 588 }; 589 590 max7322: gpio@68 { 591 compatible = "maxim,max7322"; 592 reg = <0x68>; 593 gpio-controller; 594 #gpio-cells = <2>; 595 }; 596 597 gyrometer@69 { 598 compatible = "st,l3g4200d-gyro"; 599 reg = <0x69>; 600 }; 601 602 ptn5110: tcpc@51 { 603 compatible = "nxp,ptn5110", "tcpci"; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_typec>; 606 reg = <0x51>; 607 interrupt-parent = <&lsio_gpio4>; 608 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 609 status = "okay"; 610 611 usb_con1: connector { 612 compatible = "usb-c-connector"; 613 label = "USB-C"; 614 power-role = "source"; 615 data-role = "dual"; 616 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 617 618 ports { 619 #address-cells = <1>; 620 #size-cells = <0>; 621 622 port@0 { 623 reg = <0>; 624 625 typec_dr_sw: endpoint { 626 remote-endpoint = <&usb3_drd_sw>; 627 }; 628 }; 629 630 port@1 { 631 reg = <1>; 632 typec_con_ss: endpoint { 633 remote-endpoint = <&usb3_data_ss>; 634 }; 635 }; 636 }; 637 }; 638 }; 639}; 640 641&i2c1 { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 clock-frequency = <100000>; 645 pinctrl-names = "default", "gpio"; 646 pinctrl-0 = <&pinctrl_i2c1>; 647 pinctrl-1 = <&pinctrl_i2c1_gpio>; 648 scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; 649 sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; 650 status = "okay"; 651}; 652 653&i2c1_lvds0 { 654 pinctrl-names = "default"; 655 pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; 656 clock-frequency = <100000>; 657 status = "okay"; 658}; 659 660&i2c1_lvds1 { 661 pinctrl-names = "default"; 662 pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; 663 clock-frequency = <100000>; 664 status = "okay"; 665}; 666 667&i2c0_mipi0 { 668 pinctrl-names = "default"; 669 pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; 670 clock-frequency = <100000>; 671 status = "okay"; 672}; 673 674&i2c0_mipi1 { 675 pinctrl-names = "default"; 676 pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; 677 clock-frequency = <100000>; 678 status = "okay"; 679}; 680 681&flexcan1 { 682 pinctrl-names = "default"; 683 pinctrl-0 = <&pinctrl_flexcan1>; 684 xceiver-supply = <®_can01_stby>; 685 status = "okay"; 686}; 687 688&flexcan2 { 689 pinctrl-names = "default"; 690 pinctrl-0 = <&pinctrl_flexcan2>; 691 xceiver-supply = <®_can01_stby>; 692 status = "okay"; 693}; 694 695&flexcan3 { 696 pinctrl-names = "default"; 697 pinctrl-0 = <&pinctrl_flexcan3>; 698 xceiver-supply = <®_can2_stby>; 699 status = "okay"; 700}; 701 702&lpuart0 { 703 pinctrl-names = "default"; 704 pinctrl-0 = <&pinctrl_lpuart0>; 705 status = "okay"; 706}; 707 708&lpuart1 { 709 pinctrl-names = "default"; 710 pinctrl-0 = <&pinctrl_lpuart1>; 711 status = "okay"; 712 713 bluetooth { 714 compatible = "nxp,88w8987-bt"; 715 }; 716}; 717 718&lpuart2 { 719 pinctrl-names = "default"; 720 pinctrl-0 = <&pinctrl_lpuart2>; 721 status = "okay"; 722}; 723 724&lpuart3 { 725 pinctrl-names = "default"; 726 pinctrl-0 = <&pinctrl_lpuart3>; 727 status = "okay"; 728}; 729 730&lpspi2 { 731 #address-cells = <1>; 732 #size-cells = <0>; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; 735 cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; 736 status = "okay"; 737}; 738 739&lsio_mu5 { 740 status = "okay"; 741}; 742 743&lsio_mu6 { 744 status = "okay"; 745}; 746 747&flexspi0 { 748 pinctrl-names = "default"; 749 pinctrl-0 = <&pinctrl_flexspi0>; 750 status = "okay"; 751 752 flash0: flash@0 { 753 reg = <0>; 754 #address-cells = <1>; 755 #size-cells = <1>; 756 compatible = "jedec,spi-nor"; 757 spi-max-frequency = <133000000>; 758 spi-tx-bus-width = <8>; 759 spi-rx-bus-width = <8>; 760 }; 761}; 762 763&fec1 { 764 pinctrl-names = "default"; 765 pinctrl-0 = <&pinctrl_fec1>; 766 phy-mode = "rgmii-id"; 767 phy-handle = <ðphy0>; 768 fsl,magic-packet; 769 status = "okay"; 770 771 mdio { 772 #address-cells = <1>; 773 #size-cells = <0>; 774 775 ethphy0: ethernet-phy@0 { 776 compatible = "ethernet-phy-ieee802.3-c22"; 777 reg = <0>; 778 }; 779 780 ethphy1: ethernet-phy@1 { 781 compatible = "ethernet-phy-ieee802.3-c22"; 782 reg = <1>; 783 }; 784 }; 785}; 786 787&fec2 { 788 pinctrl-names = "default"; 789 pinctrl-0 = <&pinctrl_fec2>; 790 phy-mode = "rgmii-txid"; 791 phy-handle = <ðphy1>; 792 phy-supply = <®_fec2_supply>; 793 nvmem-cells = <&fec_mac1>; 794 nvmem-cell-names = "mac-address"; 795 rx-internal-delay-ps = <2000>; 796 fsl,magic-packet; 797 status = "okay"; 798}; 799 800&pciea { 801 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 802 phy-names = "pcie-phy"; 803 pinctrl-0 = <&pinctrl_pciea>; 804 pinctrl-names = "default"; 805 reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; 806 vpcie-supply = <®_pciea>; 807 vpcie3v3aux-supply = <®_pciea>; 808 supports-clkreq; 809 status = "okay"; 810}; 811 812&pcieb { 813 phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; 814 phy-names = "pcie-phy"; 815 pinctrl-0 = <&pinctrl_pcieb>; 816 pinctrl-names = "default"; 817 reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; 818 status = "disabled"; 819}; 820 821&qm_pwm_lvds0 { 822 pinctrl-names = "default"; 823 pinctrl-0 = <&pinctrl_pwm_lvds0>; 824 status = "okay"; 825}; 826 827&pwm_lvds1 { 828 pinctrl-names = "default"; 829 pinctrl-0 = <&pinctrl_pwm_lvds1>; 830 status = "okay"; 831}; 832 833&usdhc1 { 834 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; 835 assigned-clock-rates = <400000000>; 836 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 837 pinctrl-0 = <&pinctrl_usdhc1>; 838 pinctrl-1 = <&pinctrl_usdhc1>; 839 pinctrl-2 = <&pinctrl_usdhc1>; 840 bus-width = <8>; 841 no-sd; 842 no-sdio; 843 non-removable; 844 status = "okay"; 845}; 846 847&usdhc2 { 848 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 849 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 850 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 851 pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 852 bus-width = <4>; 853 vmmc-supply = <®_usdhc2_vmmc>; 854 cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; 855 wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; 856 status = "okay"; 857}; 858 859&usbphy1 { 860 status = "okay"; 861}; 862 863&usb3_phy { 864 status = "okay"; 865}; 866 867&usbotg1 { 868 vbus-supply = <®_usb_otg1_vbus>; 869 pinctrl-names = "default"; 870 pinctrl-0 = <&pinctrl_usbotg1>; 871 srp-disable; 872 hnp-disable; 873 adp-disable; 874 disable-over-current; 875 status = "okay"; 876}; 877 878&usbotg3 { 879 status = "okay"; 880}; 881 882&usbotg3_cdns3 { 883 dr_mode = "otg"; 884 usb-role-switch; 885 status = "okay"; 886 887 port { 888 usb3_drd_sw: endpoint { 889 remote-endpoint = <&typec_dr_sw>; 890 }; 891 }; 892}; 893 894&sai0 { 895 #sound-dai-cells = <0>; 896 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 897 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 898 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 899 <&sai0_lpcg IMX_LPCG_CLK_4>; 900 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 901 pinctrl-names = "default"; 902 pinctrl-0 = <&pinctrl_sai0>; 903 status = "okay"; 904}; 905 906&sai1 { 907 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 908 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 909 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 910 <&sai1_lpcg IMX_LPCG_CLK_4>; 911 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&pinctrl_sai1>; 914 status = "okay"; 915}; 916 917&sai6 { 918 assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, 919 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 920 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 921 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 922 <&sai6_lpcg IMX_LPCG_CLK_4>; 923 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 924 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 925 fsl,sai-asynchronous; 926 status = "okay"; 927}; 928 929&sai7 { 930 assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, 931 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 932 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 933 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 934 <&sai7_lpcg IMX_LPCG_CLK_4>; 935 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 936 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 937 fsl,sai-asynchronous; 938 status = "okay"; 939}; 940 941&sata { 942 status = "okay"; 943}; 944 945&vpu_dsp { 946 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 947 <&dsp_vdev0vring1>, <&dsp_reserved>; 948 status = "okay"; 949}; 950 951&thermal_zones { 952 pmic-thermal { 953 polling-delay-passive = <250>; 954 polling-delay = <2000>; 955 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 956 957 trips { 958 pmic_alert0: trip0 { 959 temperature = <110000>; 960 hysteresis = <2000>; 961 type = "passive"; 962 }; 963 964 pmic_crit0: trip1 { 965 temperature = <125000>; 966 hysteresis = <2000>; 967 type = "critical"; 968 }; 969 }; 970 971 cooling-maps { 972 map0 { 973 trip = <&pmic_alert0>; 974 cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 975 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 976 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 977 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 978 }; 979 }; 980 }; 981}; 982 983&iomuxc { 984 pinctrl-names = "default"; 985 pinctrl-0 = <&pinctrl_hog>; 986 987 pinctrl_hog: hoggrp { 988 fsl,pins = < 989 IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c 990 IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c 991 >; 992 }; 993 994 pinctrl_cs42888_reset: cs42888_resetgrp { 995 fsl,pins = < 996 IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c 997 >; 998 }; 999 1000 pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp { 1001 fsl,pins = < 1002 IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 1003 IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 1004 >; 1005 }; 1006 1007 pinctrl_i2c_mipi_csi1: i2c-mipi-csi1grp { 1008 fsl,pins = < 1009 IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 1010 IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 1011 >; 1012 }; 1013 1014 pinctrl_i2c0: i2c0grp { 1015 fsl,pins = < 1016 IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 1017 IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 1018 >; 1019 }; 1020 1021 pinctrl_i2c1: i2c1grp { 1022 fsl,pins = < 1023 IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c 1024 IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c 1025 >; 1026 }; 1027 1028 pinctrl_i2c1_gpio: i2c1gpio-grp { 1029 fsl,pins = < 1030 IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c 1031 IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c 1032 >; 1033 }; 1034 1035 pinctrl_adc0: adc0grp { 1036 fsl,pins = < 1037 IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 1038 >; 1039 }; 1040 1041 pinctrl_cm41_i2c: cm41i2cgrp { 1042 fsl,pins = < 1043 IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c 1044 IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c 1045 >; 1046 }; 1047 1048 pinctrl_esai0: esai0grp { 1049 fsl,pins = < 1050 IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 1051 IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 1052 IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 1053 IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 1054 IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 1055 IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 1056 IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 1057 IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 1058 IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 1059 IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 1060 >; 1061 }; 1062 1063 pinctrl_fec1: fec1grp { 1064 fsl,pins = < 1065 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 1066 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 1067 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 1068 IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 1069 IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 1070 IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 1071 IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 1072 IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 1073 IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 1074 IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 1075 IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 1076 IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 1077 IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 1078 IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 1079 >; 1080 }; 1081 1082 pinctrl_lpspi2: lpspi2grp { 1083 fsl,pins = < 1084 IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040 1085 IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040 1086 IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040 1087 >; 1088 }; 1089 1090 pinctrl_lpspi2_cs: lpspi2csgrp { 1091 fsl,pins = < 1092 IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 1093 >; 1094 }; 1095 1096 pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { 1097 fsl,pins = < 1098 IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 1099 IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 1100 IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 1101 >; 1102 }; 1103 1104 pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { 1105 fsl,pins = < 1106 IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 1107 IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 1108 IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 1109 >; 1110 }; 1111 1112 pinctrl_flexspi0: flexspi0grp { 1113 fsl,pins = < 1114 IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 1115 IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 1116 IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 1117 IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 1118 IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 1119 IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 1120 IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 1121 IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 1122 IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 1123 IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 1124 IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 1125 IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 1126 IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 1127 IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 1128 IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 1129 IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 1130 >; 1131 }; 1132 1133 pinctrl_fec2: fec2grp { 1134 fsl,pins = < 1135 IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 1136 IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 1137 IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 1138 IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 1139 IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 1140 IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 1141 IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 1142 IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 1143 IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 1144 IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 1145 IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 1146 IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 1147 IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 1148 >; 1149 }; 1150 1151 pinctrl_flexcan1: flexcan0grp { 1152 fsl,pins = < 1153 IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 1154 IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 1155 >; 1156 }; 1157 1158 pinctrl_flexcan2: flexcan1grp { 1159 fsl,pins = < 1160 IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 1161 IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 1162 >; 1163 }; 1164 1165 pinctrl_flexcan3: flexcan3grp { 1166 fsl,pins = < 1167 IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 1168 IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 1169 >; 1170 }; 1171 1172 pinctrl_lpuart0: lpuart0grp { 1173 fsl,pins = < 1174 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 1175 IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 1176 >; 1177 }; 1178 1179 pinctrl_lpuart1: lpuart1grp { 1180 fsl,pins = < 1181 IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 1182 IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 1183 IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 1184 IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 1185 >; 1186 }; 1187 1188 pinctrl_lpuart2: lpuart2grp { 1189 fsl,pins = < 1190 IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 1191 IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 1192 >; 1193 }; 1194 1195 pinctrl_lpuart3: lpuart3grp { 1196 fsl,pins = < 1197 IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 1198 IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 1199 >; 1200 }; 1201 1202 pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { 1203 fsl,pins = < 1204 IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c 1205 IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c 1206 >; 1207 }; 1208 1209 pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { 1210 fsl,pins = < 1211 IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c 1212 IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c 1213 >; 1214 }; 1215 1216 pinctrl_mipi_csi0: mipi-csi0grp { 1217 fsl,pins = < 1218 IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xc0000041 1219 IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xc0000041 1220 IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xc0000041 1221 >; 1222 }; 1223 1224 pinctrl_mipi_csi1: mipi-csi1grp { 1225 fsl,pins = < 1226 IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xc0000041 1227 IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xc0000041 1228 IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xc0000041 1229 >; 1230 }; 1231 1232 pinctrl_pciea: pcieagrp { 1233 fsl,pins = < 1234 IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 1235 IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 1236 IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 1237 >; 1238 }; 1239 1240 pinctrl_pciea_reg: pcieareggrp { 1241 fsl,pins = < 1242 IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000021 1243 >; 1244 }; 1245 1246 pinctrl_pcieb: pciebgrp { 1247 fsl,pins = < 1248 IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B 0x06000021 1249 IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 1250 IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 1251 >; 1252 }; 1253 1254 pinctrl_pwm_lvds0: pwmlvds0grp { 1255 fsl,pins = < 1256 IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 1257 >; 1258 }; 1259 1260 pinctrl_pwm_lvds1: pwmlvds1grp { 1261 fsl,pins = < 1262 IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 1263 >; 1264 }; 1265 1266 pinctrl_sai0: sai0grp { 1267 fsl,pins = < 1268 IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c 1269 IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c 1270 IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c 1271 IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c 1272 >; 1273 }; 1274 1275 pinctrl_sai1: sai1grp { 1276 fsl,pins = < 1277 IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 1278 IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 1279 IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 1280 IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 1281 >; 1282 }; 1283 1284 pinctrl_typec: typecgrp { 1285 fsl,pins = < 1286 IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 1287 >; 1288 }; 1289 1290 pinctrl_typec_mux: typecmuxgrp { 1291 fsl,pins = < 1292 IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 1293 IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 1294 >; 1295 }; 1296 1297 pinctrl_usbotg1: usbotg1grp { 1298 fsl,pins = < 1299 IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 1300 >; 1301 }; 1302 1303 pinctrl_usdhc1: usdhc1grp { 1304 fsl,pins = < 1305 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 1306 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 1307 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 1308 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 1309 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 1310 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 1311 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 1312 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 1313 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 1314 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 1315 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 1316 >; 1317 }; 1318 1319 pinctrl_usdhc2: usdhc2grp { 1320 fsl,pins = < 1321 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 1322 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 1323 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 1324 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 1325 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 1326 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 1327 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 1328 >; 1329 }; 1330 1331 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 1332 fsl,pins = < 1333 IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 1334 IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 1335 IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 1336 >; 1337 }; 1338}; 1339