1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77951 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2015-2019 Renesas Electronics Corporation
6 */
7
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10 #include <linux/sys_soc.h>
11
12 #include "sh_pfc.h"
13
14 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
15
16 #define CPU_ALL_GP(fn, sfx) \
17 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
18 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
19 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
20 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
26 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
29
30 #define CPU_ALL_NOGP(fn) \
31 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
32 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
33 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
34 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
35 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
36 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
37 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
38 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
51 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
70 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
71 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
72 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
74
75 /*
76 * F_() : just information
77 * FM() : macro for FN_xxx / xxx_MARK
78 */
79
80 /* GPSR0 */
81 #define GPSR0_15 F_(D15, IP7_11_8)
82 #define GPSR0_14 F_(D14, IP7_7_4)
83 #define GPSR0_13 F_(D13, IP7_3_0)
84 #define GPSR0_12 F_(D12, IP6_31_28)
85 #define GPSR0_11 F_(D11, IP6_27_24)
86 #define GPSR0_10 F_(D10, IP6_23_20)
87 #define GPSR0_9 F_(D9, IP6_19_16)
88 #define GPSR0_8 F_(D8, IP6_15_12)
89 #define GPSR0_7 F_(D7, IP6_11_8)
90 #define GPSR0_6 F_(D6, IP6_7_4)
91 #define GPSR0_5 F_(D5, IP6_3_0)
92 #define GPSR0_4 F_(D4, IP5_31_28)
93 #define GPSR0_3 F_(D3, IP5_27_24)
94 #define GPSR0_2 F_(D2, IP5_23_20)
95 #define GPSR0_1 F_(D1, IP5_19_16)
96 #define GPSR0_0 F_(D0, IP5_15_12)
97
98 /* GPSR1 */
99 #define GPSR1_28 FM(CLKOUT)
100 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
101 #define GPSR1_26 F_(WE1_N, IP5_7_4)
102 #define GPSR1_25 F_(WE0_N, IP5_3_0)
103 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
104 #define GPSR1_23 F_(RD_N, IP4_27_24)
105 #define GPSR1_22 F_(BS_N, IP4_23_20)
106 #define GPSR1_21 F_(CS1_N, IP4_19_16)
107 #define GPSR1_20 F_(CS0_N, IP4_15_12)
108 #define GPSR1_19 F_(A19, IP4_11_8)
109 #define GPSR1_18 F_(A18, IP4_7_4)
110 #define GPSR1_17 F_(A17, IP4_3_0)
111 #define GPSR1_16 F_(A16, IP3_31_28)
112 #define GPSR1_15 F_(A15, IP3_27_24)
113 #define GPSR1_14 F_(A14, IP3_23_20)
114 #define GPSR1_13 F_(A13, IP3_19_16)
115 #define GPSR1_12 F_(A12, IP3_15_12)
116 #define GPSR1_11 F_(A11, IP3_11_8)
117 #define GPSR1_10 F_(A10, IP3_7_4)
118 #define GPSR1_9 F_(A9, IP3_3_0)
119 #define GPSR1_8 F_(A8, IP2_31_28)
120 #define GPSR1_7 F_(A7, IP2_27_24)
121 #define GPSR1_6 F_(A6, IP2_23_20)
122 #define GPSR1_5 F_(A5, IP2_19_16)
123 #define GPSR1_4 F_(A4, IP2_15_12)
124 #define GPSR1_3 F_(A3, IP2_11_8)
125 #define GPSR1_2 F_(A2, IP2_7_4)
126 #define GPSR1_1 F_(A1, IP2_3_0)
127 #define GPSR1_0 F_(A0, IP1_31_28)
128
129 /* GPSR2 */
130 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
131 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
132 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
133 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
134 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
135 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
136 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
137 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
138 #define GPSR2_6 F_(PWM0, IP1_19_16)
139 #define GPSR2_5 F_(IRQ5, IP1_15_12)
140 #define GPSR2_4 F_(IRQ4, IP1_11_8)
141 #define GPSR2_3 F_(IRQ3, IP1_7_4)
142 #define GPSR2_2 F_(IRQ2, IP1_3_0)
143 #define GPSR2_1 F_(IRQ1, IP0_31_28)
144 #define GPSR2_0 F_(IRQ0, IP0_27_24)
145
146 /* GPSR3 */
147 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
148 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
149 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
150 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
151 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
152 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
153 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
154 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
155 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
156 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
157 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
158 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
159 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
160 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
161 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
162 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
163
164 /* GPSR4 */
165 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
166 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
167 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
168 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
169 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
170 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
171 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
172 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
173 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
174 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
175 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
176 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
177 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
178 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
179 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
180 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
181 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
182 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
183
184 /* GPSR5 */
185 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
186 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
187 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
188 #define GPSR5_22 FM(MSIOF0_RXD)
189 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
190 #define GPSR5_20 FM(MSIOF0_TXD)
191 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
192 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
193 #define GPSR5_17 FM(MSIOF0_SCK)
194 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
195 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
196 #define GPSR5_14 F_(HTX0, IP13_19_16)
197 #define GPSR5_13 F_(HRX0, IP13_15_12)
198 #define GPSR5_12 F_(HSCK0, IP13_11_8)
199 #define GPSR5_11 F_(RX2_A, IP13_7_4)
200 #define GPSR5_10 F_(TX2_A, IP13_3_0)
201 #define GPSR5_9 F_(SCK2, IP12_31_28)
202 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
203 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
204 #define GPSR5_6 F_(TX1_A, IP12_19_16)
205 #define GPSR5_5 F_(RX1_A, IP12_15_12)
206 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
207 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
208 #define GPSR5_2 F_(TX0, IP12_3_0)
209 #define GPSR5_1 F_(RX0, IP11_31_28)
210 #define GPSR5_0 F_(SCK0, IP11_27_24)
211
212 /* GPSR6 */
213 #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
214 #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
215 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
216 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
217 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
218 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
219 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
220 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
221 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
222 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
223 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
224 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
225 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
226 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
227 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
228 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
229 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
230 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
231 #define GPSR6_13 FM(SSI_SDATA5)
232 #define GPSR6_12 FM(SSI_WS5)
233 #define GPSR6_11 FM(SSI_SCK5)
234 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
235 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
236 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
237 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
238 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
239 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
240 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
241 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
242 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
243 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
244 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
245
246 /* GPSR7 */
247 #define GPSR7_3 FM(GP7_03)
248 #define GPSR7_2 FM(GP7_02)
249 #define GPSR7_1 FM(AVS2)
250 #define GPSR7_0 FM(AVS1)
251
252 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
253 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272
273 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
274 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315
316 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
317 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347
348 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
349 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
370 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377
378 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
379 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
399 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
400 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
401 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
402 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
403 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
405 #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
406
407 #define PINMUX_GPSR \
408 \
409 GPSR6_31 \
410 GPSR6_30 \
411 GPSR6_29 \
412 GPSR1_28 GPSR6_28 \
413 GPSR1_27 GPSR6_27 \
414 GPSR1_26 GPSR6_26 \
415 GPSR1_25 GPSR5_25 GPSR6_25 \
416 GPSR1_24 GPSR5_24 GPSR6_24 \
417 GPSR1_23 GPSR5_23 GPSR6_23 \
418 GPSR1_22 GPSR5_22 GPSR6_22 \
419 GPSR1_21 GPSR5_21 GPSR6_21 \
420 GPSR1_20 GPSR5_20 GPSR6_20 \
421 GPSR1_19 GPSR5_19 GPSR6_19 \
422 GPSR1_18 GPSR5_18 GPSR6_18 \
423 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
424 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
425 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
426 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
427 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
428 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
429 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
430 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
431 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
432 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
433 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
434 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
435 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
436 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
437 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
438 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
439 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
440 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
441
442 #define PINMUX_IPSR \
443 \
444 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
445 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
446 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
447 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
448 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
449 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
450 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
451 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
452 \
453 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
454 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
455 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
456 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
457 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
458 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
459 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
460 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
461 \
462 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
463 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
464 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
465 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
466 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
467 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
468 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
469 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
470 \
471 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
472 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
473 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
474 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
475 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
476 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
477 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
478 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
479 \
480 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
481 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
482 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
483 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
484 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
485 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
486 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
487 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
488
489 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
490 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
491 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
492 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
493 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
494 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
495 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
496 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
497 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
498 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
499 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
500 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
501 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
502 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
503 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
504 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
505 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
506 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
507 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
508
509 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
510 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
511 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
512 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
513 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
514 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
515 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
516 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
517 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
518 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
519 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
520 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
521 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
522 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
523 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
524 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
525 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
526 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
527 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
528 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
529 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
530 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
531 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
532
533 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
534 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
535 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
536 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
537 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
538 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
539 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
540 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
541 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
542 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
543 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
544 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
545 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
546
547 #define PINMUX_MOD_SELS \
548 \
549 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
550 MOD_SEL2_30 \
551 MOD_SEL1_29_28_27 MOD_SEL2_29 \
552 MOD_SEL0_28_27 MOD_SEL2_28_27 \
553 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
554 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
555 MOD_SEL0_23 MOD_SEL1_23_22_21 \
556 MOD_SEL0_22 \
557 MOD_SEL0_21 MOD_SEL2_21 \
558 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
559 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
560 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
561 MOD_SEL2_17 \
562 MOD_SEL0_16 MOD_SEL1_16 \
563 MOD_SEL1_15_14 \
564 MOD_SEL0_14_13 \
565 MOD_SEL1_13 \
566 MOD_SEL0_12 MOD_SEL1_12 \
567 MOD_SEL0_11 MOD_SEL1_11 \
568 MOD_SEL0_10 MOD_SEL1_10 \
569 MOD_SEL0_9_8 MOD_SEL1_9 \
570 MOD_SEL0_7_6 \
571 MOD_SEL1_6 \
572 MOD_SEL0_5 MOD_SEL1_5 \
573 MOD_SEL0_4_3 MOD_SEL1_4 \
574 MOD_SEL1_3 \
575 MOD_SEL1_2 \
576 MOD_SEL1_1 \
577 MOD_SEL1_0 MOD_SEL2_0
578
579 /*
580 * These pins are not able to be muxed but have other properties
581 * that can be set, such as drive-strength or pull-up/pull-down enable.
582 */
583 #define PINMUX_STATIC \
584 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
585 FM(QSPI0_IO2) FM(QSPI0_IO3) \
586 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
587 FM(QSPI1_IO2) FM(QSPI1_IO3) \
588 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
589 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
590 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
591 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
592 FM(PRESETOUT) \
593 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
594 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
595
596 #define PINMUX_PHYS \
597 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
598
599 enum {
600 PINMUX_RESERVED = 0,
601
602 PINMUX_DATA_BEGIN,
603 GP_ALL(DATA),
604 PINMUX_DATA_END,
605
606 #define F_(x, y)
607 #define FM(x) FN_##x,
608 PINMUX_FUNCTION_BEGIN,
609 GP_ALL(FN),
610 PINMUX_GPSR
611 PINMUX_IPSR
612 PINMUX_MOD_SELS
613 PINMUX_FUNCTION_END,
614 #undef F_
615 #undef FM
616
617 #define F_(x, y)
618 #define FM(x) x##_MARK,
619 PINMUX_MARK_BEGIN,
620 PINMUX_GPSR
621 PINMUX_IPSR
622 PINMUX_MOD_SELS
623 PINMUX_STATIC
624 PINMUX_PHYS
625 PINMUX_MARK_END,
626 #undef F_
627 #undef FM
628 };
629
630 static const u16 pinmux_data[] = {
631 PINMUX_DATA_GP_ALL(),
632
633 PINMUX_SINGLE(AVS1),
634 PINMUX_SINGLE(AVS2),
635 PINMUX_SINGLE(CLKOUT),
636 PINMUX_SINGLE(GP7_02),
637 PINMUX_SINGLE(GP7_03),
638 PINMUX_SINGLE(MSIOF0_RXD),
639 PINMUX_SINGLE(MSIOF0_SCK),
640 PINMUX_SINGLE(MSIOF0_TXD),
641 PINMUX_SINGLE(SSI_SCK5),
642 PINMUX_SINGLE(SSI_SDATA5),
643 PINMUX_SINGLE(SSI_WS5),
644
645 /* IPSR0 */
646 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
647 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
648
649 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
650 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
651 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
652
653 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
654 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
655 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
656
657 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
658 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
659 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
660
661 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
662 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
663 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
664 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
665 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
666
667 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
668 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
669 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
670 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
671
672 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
673 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
674 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
675 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
676 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
677 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
678 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
679
680 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
681 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
682 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
683 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
685 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
686 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
687
688 /* IPSR1 */
689 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
690 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
691 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
692 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
693 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
694 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
695
696 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
697 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
698 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
699 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
700 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
701 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
702
703 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
704 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
705 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
706 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
707 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
708 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
709
710 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
711 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
712 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
713 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
714 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
715 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
716 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
717
718 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
719 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
720 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
721 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
722
723 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
724 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
725 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
726 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
727 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
728
729 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
730 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
731 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
732 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
733
734 PINMUX_IPSR_GPSR(IP1_31_28, A0),
735 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
736 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
737 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
738 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
739 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
740
741 /* IPSR2 */
742 PINMUX_IPSR_GPSR(IP2_3_0, A1),
743 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
744 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
745 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
746 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
747 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
748
749 PINMUX_IPSR_GPSR(IP2_7_4, A2),
750 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
751 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
752 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
753 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
754 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
755
756 PINMUX_IPSR_GPSR(IP2_11_8, A3),
757 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
758 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
759 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
760 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
761 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
762
763 PINMUX_IPSR_GPSR(IP2_15_12, A4),
764 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
765 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
766 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
767 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
768 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
769
770 PINMUX_IPSR_GPSR(IP2_19_16, A5),
771 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
772 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
773 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
774 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
775 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
776 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
777
778 PINMUX_IPSR_GPSR(IP2_23_20, A6),
779 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
780 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
781 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
782 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
783 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
784 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
785
786 PINMUX_IPSR_GPSR(IP2_27_24, A7),
787 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
788 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
789 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
790 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
791 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
792 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
793
794 PINMUX_IPSR_GPSR(IP2_31_28, A8),
795 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
796 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
797 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
798 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
799 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
800 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
801
802 /* IPSR3 */
803 PINMUX_IPSR_GPSR(IP3_3_0, A9),
804 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
805 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
806 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
807
808 PINMUX_IPSR_GPSR(IP3_7_4, A10),
809 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
810 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
811 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
812
813 PINMUX_IPSR_GPSR(IP3_11_8, A11),
814 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
815 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
816 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
817 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
818 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
819 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
820 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
821 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
822
823 PINMUX_IPSR_GPSR(IP3_15_12, A12),
824 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
825 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
826 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
827 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
828 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
829
830 PINMUX_IPSR_GPSR(IP3_19_16, A13),
831 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
832 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
833 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
834 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
835 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
836
837 PINMUX_IPSR_GPSR(IP3_23_20, A14),
838 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
839 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
840 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
841 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
842 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
843
844 PINMUX_IPSR_GPSR(IP3_27_24, A15),
845 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
846 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
847 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
848 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
849 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
850
851 PINMUX_IPSR_GPSR(IP3_31_28, A16),
852 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
853 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
854 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
855
856 /* IPSR4 */
857 PINMUX_IPSR_GPSR(IP4_3_0, A17),
858 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
859 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
860 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
861
862 PINMUX_IPSR_GPSR(IP4_7_4, A18),
863 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
864 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
865 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
866
867 PINMUX_IPSR_GPSR(IP4_11_8, A19),
868 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
869 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
870 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
871
872 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
873 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
874
875 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
876 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
877 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
878
879 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
880 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
881 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
882 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
883 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
884 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
885 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
886 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
887
888 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
889 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
890 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
891 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
892 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
893 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
894
895 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
896 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
897 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
898 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
899 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
900 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
901
902 /* IPSR5 */
903 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
904 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
905 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
906 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
907 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
908 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
909 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
910
911 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
912 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
913 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
914 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
915 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
916 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
917 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
918 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
919
920 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
921 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
922 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
923 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
924
925 PINMUX_IPSR_GPSR(IP5_15_12, D0),
926 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
927 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
928 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
929 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
930
931 PINMUX_IPSR_GPSR(IP5_19_16, D1),
932 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
933 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
934 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
935 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
936
937 PINMUX_IPSR_GPSR(IP5_23_20, D2),
938 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
939 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
940 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
941
942 PINMUX_IPSR_GPSR(IP5_27_24, D3),
943 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
944 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
945 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
946
947 PINMUX_IPSR_GPSR(IP5_31_28, D4),
948 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
949 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
950 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
951
952 /* IPSR6 */
953 PINMUX_IPSR_GPSR(IP6_3_0, D5),
954 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
955 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
956 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
957
958 PINMUX_IPSR_GPSR(IP6_7_4, D6),
959 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
960 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
961 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
962
963 PINMUX_IPSR_GPSR(IP6_11_8, D7),
964 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
965 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
966 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
967
968 PINMUX_IPSR_GPSR(IP6_15_12, D8),
969 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
970 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
971 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
972 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
973 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
974
975 PINMUX_IPSR_GPSR(IP6_19_16, D9),
976 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
977 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
978 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
979 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
980
981 PINMUX_IPSR_GPSR(IP6_23_20, D10),
982 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
983 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
984 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
985 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
986 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
987 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
988
989 PINMUX_IPSR_GPSR(IP6_27_24, D11),
990 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
991 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
992 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
993 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
994 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
995 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
996
997 PINMUX_IPSR_GPSR(IP6_31_28, D12),
998 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
999 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1000 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1001 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1002 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1003
1004 /* IPSR7 */
1005 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1006 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1007 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1008 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1009 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1010 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1011
1012 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1013 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1014 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1015 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1016 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1017 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1018 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1019
1020 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1021 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1022 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1023 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1024 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1025 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1026 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1027
1028 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1029 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1030 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1031
1032 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1033 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1034 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1035
1036 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1037 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1038 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1039 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1040
1041 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1042 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1043 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1044 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1045
1046 /* IPSR8 */
1047 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1048 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1049 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1050 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1051
1052 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1053 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1054 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1055 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1056
1057 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1058 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1059 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1060
1061 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1062 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1063 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1064 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1065 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1066
1067 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1068 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1069 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1070 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1071 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1072 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1073
1074 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1075 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1076 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1077 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1078 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1079 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1080
1081 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1082 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1083 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1084 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1085 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1086 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1087
1088 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1089 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1090 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1091 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1092 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1093 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1094
1095 /* IPSR9 */
1096 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1097 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1098
1099 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1100 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1101
1102 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1103 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1104
1105 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1106 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1107
1108 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1109 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1110
1111 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1112 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1113
1114 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1115 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1116 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1117
1118 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1119 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1120
1121 /* IPSR10 */
1122 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1123 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1124
1125 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1126 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1127
1128 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1129 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1130
1131 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1132 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1133
1134 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1135 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1136
1137 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1138 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1139 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1140
1141 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1142 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1143 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1144
1145 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1146 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1147 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1148
1149 /* IPSR11 */
1150 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1151 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1152 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1153
1154 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1155 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1156
1157 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1158 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1159 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1160
1161 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1162 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1163
1164 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1165 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1166 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1167
1168 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1169 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1170 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1171
1172 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1173 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1174 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1175 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
1176 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1177 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1178 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1179 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1180 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1181 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1182
1183 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1184 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1185 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1186 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1187 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1188
1189 /* IPSR12 */
1190 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1191 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1192 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1193 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1194 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1195
1196 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1197 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1198 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1199 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1200 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1201 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1202 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1203 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1204
1205 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1206 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1207 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1208 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
1209 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1210 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1211 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1212 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1213
1214 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1215 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1216 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1217 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1218 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1219
1220 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1221 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1222 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1223 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1224 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1225
1226 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1227 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1228 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1229 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1230 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1231 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1232 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1233
1234 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1235 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1236 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1237 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1238 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1239 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1240 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1241
1242 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1243 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1244 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1245 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1246 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1247 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1248 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1249
1250 /* IPSR13 */
1251 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1252 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1253 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1254 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1255 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1256 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1257
1258 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1259 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1260 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1261 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1262 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1263 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1264
1265 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1266 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1267 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
1268 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1269 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1270 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1271 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1272 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1273
1274 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1275 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1276 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1277 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1278 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1279 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1280
1281 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1282 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1283 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1284 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1285 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1286 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1287
1288 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1289 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1290 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1291 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1292 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1293 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1294 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1295 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1296
1297 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1298 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1299 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1300 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1301 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1302 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1303 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1304
1305 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1306 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1307 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1308 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1309
1310 /* IPSR14 */
1311 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1312 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1313 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
1314 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
1315 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1316 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1317 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1318 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1319
1320 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1321 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1322 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1323 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
1324 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1325 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1326 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1327 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1328
1329 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1330 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1331 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1332
1333 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1334 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1335 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1336 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1337
1338 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1339 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1340 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1341
1342 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1343 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1344
1345 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1346 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1347
1348 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1349 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1350
1351 /* IPSR15 */
1352 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1353
1354 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1355 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1356
1357 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1358 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1359 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1360
1361 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1362 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1363 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1364 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1365
1366 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1367 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1368 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1369 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1370 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1371 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1372 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1373
1374 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1375 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1376 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1377 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1378 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1379 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1380 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1381
1382 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1383 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1384 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1385 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1386 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1387 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1388 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1389
1390 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1391 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1392 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1393 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1394 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1395 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1396 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1397
1398 /* IPSR16 */
1399 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1400 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1401 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1402
1403 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1404 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1405 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1406
1407 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1408 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1409 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1410
1411 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1412 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1413 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1414 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1415 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1416 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1417 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1418
1419 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1420 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1421 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1422 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1423 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1424 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1425 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1426
1427 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1428 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1429 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1430 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1431 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1432 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1433 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1434 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1435
1436 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1437 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1438 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1439 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1440 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1441 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1442 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1443
1444 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1445 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1446 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1447 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1448 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1449 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1450 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1451 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1452
1453 /* IPSR17 */
1454 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
1455
1456 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
1457 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1458 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1459 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1460 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1461
1462 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1463 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1464 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1465 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1466 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1467 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1468 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1469
1470 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1471 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1472 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1473 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1474 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1475 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1476
1477 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1478 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1479 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1480 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1481 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1482 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1483 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1484 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1485 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1486
1487 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1488 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1489 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1490 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1491 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1492 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1493 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1495 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1496
1497 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1498 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1499 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1500 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1501 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1502 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1503 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1504 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1505 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1506 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1507 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1508
1509 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1510 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1511 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1512 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1513 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1514 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1515 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1516 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1517 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1518
1519 /* IPSR18 */
1520 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1521 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1522 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1523 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1524 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1525 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1526 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1527 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1528 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1529
1530 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1531 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1532 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1533 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1534 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1535 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1536 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1537 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1538 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1539
1540 /*
1541 * Static pins can not be muxed between different functions but
1542 * still need mark entries in the pinmux list. Add each static
1543 * pin to the list without an associated function. The sh-pfc
1544 * core will do the right thing and skip trying to mux the pin
1545 * while still applying configuration to it.
1546 */
1547 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1548 PINMUX_STATIC
1549 #undef FM
1550 };
1551
1552 /*
1553 * Pins not associated with a GPIO port.
1554 */
1555 enum {
1556 GP_ASSIGN_LAST(),
1557 NOGP_ALL(),
1558 };
1559
1560 static const struct sh_pfc_pin pinmux_pins[] = {
1561 PINMUX_GPIO_GP_ALL(),
1562 PINMUX_NOGP_ALL(),
1563 };
1564
1565 /* - AUDIO CLOCK ------------------------------------------------------------ */
1566 static const unsigned int audio_clk_a_a_pins[] = {
1567 /* CLK A */
1568 RCAR_GP_PIN(6, 22),
1569 };
1570 static const unsigned int audio_clk_a_a_mux[] = {
1571 AUDIO_CLKA_A_MARK,
1572 };
1573 static const unsigned int audio_clk_a_b_pins[] = {
1574 /* CLK A */
1575 RCAR_GP_PIN(5, 4),
1576 };
1577 static const unsigned int audio_clk_a_b_mux[] = {
1578 AUDIO_CLKA_B_MARK,
1579 };
1580 static const unsigned int audio_clk_a_c_pins[] = {
1581 /* CLK A */
1582 RCAR_GP_PIN(5, 19),
1583 };
1584 static const unsigned int audio_clk_a_c_mux[] = {
1585 AUDIO_CLKA_C_MARK,
1586 };
1587 static const unsigned int audio_clk_b_a_pins[] = {
1588 /* CLK B */
1589 RCAR_GP_PIN(5, 12),
1590 };
1591 static const unsigned int audio_clk_b_a_mux[] = {
1592 AUDIO_CLKB_A_MARK,
1593 };
1594 static const unsigned int audio_clk_b_b_pins[] = {
1595 /* CLK B */
1596 RCAR_GP_PIN(6, 23),
1597 };
1598 static const unsigned int audio_clk_b_b_mux[] = {
1599 AUDIO_CLKB_B_MARK,
1600 };
1601 static const unsigned int audio_clk_c_a_pins[] = {
1602 /* CLK C */
1603 RCAR_GP_PIN(5, 21),
1604 };
1605 static const unsigned int audio_clk_c_a_mux[] = {
1606 AUDIO_CLKC_A_MARK,
1607 };
1608 static const unsigned int audio_clk_c_b_pins[] = {
1609 /* CLK C */
1610 RCAR_GP_PIN(5, 0),
1611 };
1612 static const unsigned int audio_clk_c_b_mux[] = {
1613 AUDIO_CLKC_B_MARK,
1614 };
1615 static const unsigned int audio_clkout_a_pins[] = {
1616 /* CLKOUT */
1617 RCAR_GP_PIN(5, 18),
1618 };
1619 static const unsigned int audio_clkout_a_mux[] = {
1620 AUDIO_CLKOUT_A_MARK,
1621 };
1622 static const unsigned int audio_clkout_b_pins[] = {
1623 /* CLKOUT */
1624 RCAR_GP_PIN(6, 28),
1625 };
1626 static const unsigned int audio_clkout_b_mux[] = {
1627 AUDIO_CLKOUT_B_MARK,
1628 };
1629 static const unsigned int audio_clkout_c_pins[] = {
1630 /* CLKOUT */
1631 RCAR_GP_PIN(5, 3),
1632 };
1633 static const unsigned int audio_clkout_c_mux[] = {
1634 AUDIO_CLKOUT_C_MARK,
1635 };
1636 static const unsigned int audio_clkout_d_pins[] = {
1637 /* CLKOUT */
1638 RCAR_GP_PIN(5, 21),
1639 };
1640 static const unsigned int audio_clkout_d_mux[] = {
1641 AUDIO_CLKOUT_D_MARK,
1642 };
1643 static const unsigned int audio_clkout1_a_pins[] = {
1644 /* CLKOUT1 */
1645 RCAR_GP_PIN(5, 15),
1646 };
1647 static const unsigned int audio_clkout1_a_mux[] = {
1648 AUDIO_CLKOUT1_A_MARK,
1649 };
1650 static const unsigned int audio_clkout1_b_pins[] = {
1651 /* CLKOUT1 */
1652 RCAR_GP_PIN(6, 29),
1653 };
1654 static const unsigned int audio_clkout1_b_mux[] = {
1655 AUDIO_CLKOUT1_B_MARK,
1656 };
1657 static const unsigned int audio_clkout2_a_pins[] = {
1658 /* CLKOUT2 */
1659 RCAR_GP_PIN(5, 16),
1660 };
1661 static const unsigned int audio_clkout2_a_mux[] = {
1662 AUDIO_CLKOUT2_A_MARK,
1663 };
1664 static const unsigned int audio_clkout2_b_pins[] = {
1665 /* CLKOUT2 */
1666 RCAR_GP_PIN(6, 30),
1667 };
1668 static const unsigned int audio_clkout2_b_mux[] = {
1669 AUDIO_CLKOUT2_B_MARK,
1670 };
1671 static const unsigned int audio_clkout3_a_pins[] = {
1672 /* CLKOUT3 */
1673 RCAR_GP_PIN(5, 19),
1674 };
1675 static const unsigned int audio_clkout3_a_mux[] = {
1676 AUDIO_CLKOUT3_A_MARK,
1677 };
1678 static const unsigned int audio_clkout3_b_pins[] = {
1679 /* CLKOUT3 */
1680 RCAR_GP_PIN(6, 31),
1681 };
1682 static const unsigned int audio_clkout3_b_mux[] = {
1683 AUDIO_CLKOUT3_B_MARK,
1684 };
1685
1686 /* - EtherAVB --------------------------------------------------------------- */
1687 static const unsigned int avb_link_pins[] = {
1688 /* AVB_LINK */
1689 RCAR_GP_PIN(2, 12),
1690 };
1691 static const unsigned int avb_link_mux[] = {
1692 AVB_LINK_MARK,
1693 };
1694 static const unsigned int avb_magic_pins[] = {
1695 /* AVB_MAGIC_ */
1696 RCAR_GP_PIN(2, 10),
1697 };
1698 static const unsigned int avb_magic_mux[] = {
1699 AVB_MAGIC_MARK,
1700 };
1701 static const unsigned int avb_phy_int_pins[] = {
1702 /* AVB_PHY_INT */
1703 RCAR_GP_PIN(2, 11),
1704 };
1705 static const unsigned int avb_phy_int_mux[] = {
1706 AVB_PHY_INT_MARK,
1707 };
1708 static const unsigned int avb_mdio_pins[] = {
1709 /* AVB_MDC, AVB_MDIO */
1710 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1711 };
1712 static const unsigned int avb_mdio_mux[] = {
1713 AVB_MDC_MARK, AVB_MDIO_MARK,
1714 };
1715 static const unsigned int avb_mii_pins[] = {
1716 /*
1717 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1718 * AVB_TD1, AVB_TD2, AVB_TD3,
1719 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1720 * AVB_RD1, AVB_RD2, AVB_RD3,
1721 * AVB_TXCREFCLK
1722 */
1723 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1724 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1725 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1726 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1727 PIN_AVB_TXCREFCLK,
1728 };
1729 static const unsigned int avb_mii_mux[] = {
1730 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1731 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1732 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1733 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1734 AVB_TXCREFCLK_MARK,
1735 };
1736 static const unsigned int avb_avtp_pps_pins[] = {
1737 /* AVB_AVTP_PPS */
1738 RCAR_GP_PIN(2, 6),
1739 };
1740 static const unsigned int avb_avtp_pps_mux[] = {
1741 AVB_AVTP_PPS_MARK,
1742 };
1743 static const unsigned int avb_avtp_match_a_pins[] = {
1744 /* AVB_AVTP_MATCH_A */
1745 RCAR_GP_PIN(2, 13),
1746 };
1747 static const unsigned int avb_avtp_match_a_mux[] = {
1748 AVB_AVTP_MATCH_A_MARK,
1749 };
1750 static const unsigned int avb_avtp_capture_a_pins[] = {
1751 /* AVB_AVTP_CAPTURE_A */
1752 RCAR_GP_PIN(2, 14),
1753 };
1754 static const unsigned int avb_avtp_capture_a_mux[] = {
1755 AVB_AVTP_CAPTURE_A_MARK,
1756 };
1757 static const unsigned int avb_avtp_match_b_pins[] = {
1758 /* AVB_AVTP_MATCH_B */
1759 RCAR_GP_PIN(1, 8),
1760 };
1761 static const unsigned int avb_avtp_match_b_mux[] = {
1762 AVB_AVTP_MATCH_B_MARK,
1763 };
1764 static const unsigned int avb_avtp_capture_b_pins[] = {
1765 /* AVB_AVTP_CAPTURE_B */
1766 RCAR_GP_PIN(1, 11),
1767 };
1768 static const unsigned int avb_avtp_capture_b_mux[] = {
1769 AVB_AVTP_CAPTURE_B_MARK,
1770 };
1771
1772 /* - CAN ------------------------------------------------------------------ */
1773 static const unsigned int can0_data_a_pins[] = {
1774 /* TX, RX */
1775 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1776 };
1777 static const unsigned int can0_data_a_mux[] = {
1778 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1779 };
1780 static const unsigned int can0_data_b_pins[] = {
1781 /* TX, RX */
1782 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1783 };
1784 static const unsigned int can0_data_b_mux[] = {
1785 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1786 };
1787 static const unsigned int can1_data_pins[] = {
1788 /* TX, RX */
1789 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1790 };
1791 static const unsigned int can1_data_mux[] = {
1792 CAN1_TX_MARK, CAN1_RX_MARK,
1793 };
1794
1795 /* - CAN Clock -------------------------------------------------------------- */
1796 static const unsigned int can_clk_pins[] = {
1797 /* CLK */
1798 RCAR_GP_PIN(1, 25),
1799 };
1800 static const unsigned int can_clk_mux[] = {
1801 CAN_CLK_MARK,
1802 };
1803
1804 /* - CAN FD --------------------------------------------------------------- */
1805 static const unsigned int canfd0_data_a_pins[] = {
1806 /* TX, RX */
1807 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1808 };
1809 static const unsigned int canfd0_data_a_mux[] = {
1810 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1811 };
1812 static const unsigned int canfd0_data_b_pins[] = {
1813 /* TX, RX */
1814 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1815 };
1816 static const unsigned int canfd0_data_b_mux[] = {
1817 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1818 };
1819 static const unsigned int canfd1_data_pins[] = {
1820 /* TX, RX */
1821 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1822 };
1823 static const unsigned int canfd1_data_mux[] = {
1824 CANFD1_TX_MARK, CANFD1_RX_MARK,
1825 };
1826
1827 #ifdef CONFIG_PINCTRL_PFC_R8A77951
1828 /* - DRIF0 --------------------------------------------------------------- */
1829 static const unsigned int drif0_ctrl_a_pins[] = {
1830 /* CLK, SYNC */
1831 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1832 };
1833 static const unsigned int drif0_ctrl_a_mux[] = {
1834 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1835 };
1836 static const unsigned int drif0_data0_a_pins[] = {
1837 /* D0 */
1838 RCAR_GP_PIN(6, 10),
1839 };
1840 static const unsigned int drif0_data0_a_mux[] = {
1841 RIF0_D0_A_MARK,
1842 };
1843 static const unsigned int drif0_data1_a_pins[] = {
1844 /* D1 */
1845 RCAR_GP_PIN(6, 7),
1846 };
1847 static const unsigned int drif0_data1_a_mux[] = {
1848 RIF0_D1_A_MARK,
1849 };
1850 static const unsigned int drif0_ctrl_b_pins[] = {
1851 /* CLK, SYNC */
1852 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1853 };
1854 static const unsigned int drif0_ctrl_b_mux[] = {
1855 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1856 };
1857 static const unsigned int drif0_data0_b_pins[] = {
1858 /* D0 */
1859 RCAR_GP_PIN(5, 1),
1860 };
1861 static const unsigned int drif0_data0_b_mux[] = {
1862 RIF0_D0_B_MARK,
1863 };
1864 static const unsigned int drif0_data1_b_pins[] = {
1865 /* D1 */
1866 RCAR_GP_PIN(5, 2),
1867 };
1868 static const unsigned int drif0_data1_b_mux[] = {
1869 RIF0_D1_B_MARK,
1870 };
1871 static const unsigned int drif0_ctrl_c_pins[] = {
1872 /* CLK, SYNC */
1873 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1874 };
1875 static const unsigned int drif0_ctrl_c_mux[] = {
1876 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1877 };
1878 static const unsigned int drif0_data0_c_pins[] = {
1879 /* D0 */
1880 RCAR_GP_PIN(5, 13),
1881 };
1882 static const unsigned int drif0_data0_c_mux[] = {
1883 RIF0_D0_C_MARK,
1884 };
1885 static const unsigned int drif0_data1_c_pins[] = {
1886 /* D1 */
1887 RCAR_GP_PIN(5, 14),
1888 };
1889 static const unsigned int drif0_data1_c_mux[] = {
1890 RIF0_D1_C_MARK,
1891 };
1892 /* - DRIF1 --------------------------------------------------------------- */
1893 static const unsigned int drif1_ctrl_a_pins[] = {
1894 /* CLK, SYNC */
1895 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1896 };
1897 static const unsigned int drif1_ctrl_a_mux[] = {
1898 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1899 };
1900 static const unsigned int drif1_data0_a_pins[] = {
1901 /* D0 */
1902 RCAR_GP_PIN(6, 19),
1903 };
1904 static const unsigned int drif1_data0_a_mux[] = {
1905 RIF1_D0_A_MARK,
1906 };
1907 static const unsigned int drif1_data1_a_pins[] = {
1908 /* D1 */
1909 RCAR_GP_PIN(6, 20),
1910 };
1911 static const unsigned int drif1_data1_a_mux[] = {
1912 RIF1_D1_A_MARK,
1913 };
1914 static const unsigned int drif1_ctrl_b_pins[] = {
1915 /* CLK, SYNC */
1916 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1917 };
1918 static const unsigned int drif1_ctrl_b_mux[] = {
1919 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1920 };
1921 static const unsigned int drif1_data0_b_pins[] = {
1922 /* D0 */
1923 RCAR_GP_PIN(5, 7),
1924 };
1925 static const unsigned int drif1_data0_b_mux[] = {
1926 RIF1_D0_B_MARK,
1927 };
1928 static const unsigned int drif1_data1_b_pins[] = {
1929 /* D1 */
1930 RCAR_GP_PIN(5, 8),
1931 };
1932 static const unsigned int drif1_data1_b_mux[] = {
1933 RIF1_D1_B_MARK,
1934 };
1935 static const unsigned int drif1_ctrl_c_pins[] = {
1936 /* CLK, SYNC */
1937 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1938 };
1939 static const unsigned int drif1_ctrl_c_mux[] = {
1940 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1941 };
1942 static const unsigned int drif1_data0_c_pins[] = {
1943 /* D0 */
1944 RCAR_GP_PIN(5, 6),
1945 };
1946 static const unsigned int drif1_data0_c_mux[] = {
1947 RIF1_D0_C_MARK,
1948 };
1949 static const unsigned int drif1_data1_c_pins[] = {
1950 /* D1 */
1951 RCAR_GP_PIN(5, 10),
1952 };
1953 static const unsigned int drif1_data1_c_mux[] = {
1954 RIF1_D1_C_MARK,
1955 };
1956 /* - DRIF2 --------------------------------------------------------------- */
1957 static const unsigned int drif2_ctrl_a_pins[] = {
1958 /* CLK, SYNC */
1959 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1960 };
1961 static const unsigned int drif2_ctrl_a_mux[] = {
1962 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1963 };
1964 static const unsigned int drif2_data0_a_pins[] = {
1965 /* D0 */
1966 RCAR_GP_PIN(6, 7),
1967 };
1968 static const unsigned int drif2_data0_a_mux[] = {
1969 RIF2_D0_A_MARK,
1970 };
1971 static const unsigned int drif2_data1_a_pins[] = {
1972 /* D1 */
1973 RCAR_GP_PIN(6, 10),
1974 };
1975 static const unsigned int drif2_data1_a_mux[] = {
1976 RIF2_D1_A_MARK,
1977 };
1978 static const unsigned int drif2_ctrl_b_pins[] = {
1979 /* CLK, SYNC */
1980 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1981 };
1982 static const unsigned int drif2_ctrl_b_mux[] = {
1983 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1984 };
1985 static const unsigned int drif2_data0_b_pins[] = {
1986 /* D0 */
1987 RCAR_GP_PIN(6, 30),
1988 };
1989 static const unsigned int drif2_data0_b_mux[] = {
1990 RIF2_D0_B_MARK,
1991 };
1992 static const unsigned int drif2_data1_b_pins[] = {
1993 /* D1 */
1994 RCAR_GP_PIN(6, 31),
1995 };
1996 static const unsigned int drif2_data1_b_mux[] = {
1997 RIF2_D1_B_MARK,
1998 };
1999 /* - DRIF3 --------------------------------------------------------------- */
2000 static const unsigned int drif3_ctrl_a_pins[] = {
2001 /* CLK, SYNC */
2002 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2003 };
2004 static const unsigned int drif3_ctrl_a_mux[] = {
2005 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2006 };
2007 static const unsigned int drif3_data0_a_pins[] = {
2008 /* D0 */
2009 RCAR_GP_PIN(6, 19),
2010 };
2011 static const unsigned int drif3_data0_a_mux[] = {
2012 RIF3_D0_A_MARK,
2013 };
2014 static const unsigned int drif3_data1_a_pins[] = {
2015 /* D1 */
2016 RCAR_GP_PIN(6, 20),
2017 };
2018 static const unsigned int drif3_data1_a_mux[] = {
2019 RIF3_D1_A_MARK,
2020 };
2021 static const unsigned int drif3_ctrl_b_pins[] = {
2022 /* CLK, SYNC */
2023 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2024 };
2025 static const unsigned int drif3_ctrl_b_mux[] = {
2026 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2027 };
2028 static const unsigned int drif3_data0_b_pins[] = {
2029 /* D0 */
2030 RCAR_GP_PIN(6, 28),
2031 };
2032 static const unsigned int drif3_data0_b_mux[] = {
2033 RIF3_D0_B_MARK,
2034 };
2035 static const unsigned int drif3_data1_b_pins[] = {
2036 /* D1 */
2037 RCAR_GP_PIN(6, 29),
2038 };
2039 static const unsigned int drif3_data1_b_mux[] = {
2040 RIF3_D1_B_MARK,
2041 };
2042 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
2043
2044 /* - DU --------------------------------------------------------------------- */
2045 static const unsigned int du_rgb666_pins[] = {
2046 /* R[7:2], G[7:2], B[7:2] */
2047 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2048 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2049 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2050 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2051 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2052 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2053 };
2054 static const unsigned int du_rgb666_mux[] = {
2055 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2056 DU_DR3_MARK, DU_DR2_MARK,
2057 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2058 DU_DG3_MARK, DU_DG2_MARK,
2059 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2060 DU_DB3_MARK, DU_DB2_MARK,
2061 };
2062 static const unsigned int du_rgb888_pins[] = {
2063 /* R[7:0], G[7:0], B[7:0] */
2064 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2065 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2066 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2067 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2068 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2069 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2070 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2071 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2072 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2073 };
2074 static const unsigned int du_rgb888_mux[] = {
2075 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2076 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2077 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2078 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2079 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2080 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2081 };
2082 static const unsigned int du_clk_out_0_pins[] = {
2083 /* CLKOUT */
2084 RCAR_GP_PIN(1, 27),
2085 };
2086 static const unsigned int du_clk_out_0_mux[] = {
2087 DU_DOTCLKOUT0_MARK
2088 };
2089 static const unsigned int du_clk_out_1_pins[] = {
2090 /* CLKOUT */
2091 RCAR_GP_PIN(2, 3),
2092 };
2093 static const unsigned int du_clk_out_1_mux[] = {
2094 DU_DOTCLKOUT1_MARK
2095 };
2096 static const unsigned int du_sync_pins[] = {
2097 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2098 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2099 };
2100 static const unsigned int du_sync_mux[] = {
2101 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2102 };
2103 static const unsigned int du_oddf_pins[] = {
2104 /* EXDISP/EXODDF/EXCDE */
2105 RCAR_GP_PIN(2, 2),
2106 };
2107 static const unsigned int du_oddf_mux[] = {
2108 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2109 };
2110 static const unsigned int du_cde_pins[] = {
2111 /* CDE */
2112 RCAR_GP_PIN(2, 0),
2113 };
2114 static const unsigned int du_cde_mux[] = {
2115 DU_CDE_MARK,
2116 };
2117 static const unsigned int du_disp_pins[] = {
2118 /* DISP */
2119 RCAR_GP_PIN(2, 1),
2120 };
2121 static const unsigned int du_disp_mux[] = {
2122 DU_DISP_MARK,
2123 };
2124
2125 /* - HSCIF0 ----------------------------------------------------------------- */
2126 static const unsigned int hscif0_data_pins[] = {
2127 /* RX, TX */
2128 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2129 };
2130 static const unsigned int hscif0_data_mux[] = {
2131 HRX0_MARK, HTX0_MARK,
2132 };
2133 static const unsigned int hscif0_clk_pins[] = {
2134 /* SCK */
2135 RCAR_GP_PIN(5, 12),
2136 };
2137 static const unsigned int hscif0_clk_mux[] = {
2138 HSCK0_MARK,
2139 };
2140 static const unsigned int hscif0_ctrl_pins[] = {
2141 /* RTS, CTS */
2142 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2143 };
2144 static const unsigned int hscif0_ctrl_mux[] = {
2145 HRTS0_N_MARK, HCTS0_N_MARK,
2146 };
2147 /* - HSCIF1 ----------------------------------------------------------------- */
2148 static const unsigned int hscif1_data_a_pins[] = {
2149 /* RX, TX */
2150 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2151 };
2152 static const unsigned int hscif1_data_a_mux[] = {
2153 HRX1_A_MARK, HTX1_A_MARK,
2154 };
2155 static const unsigned int hscif1_clk_a_pins[] = {
2156 /* SCK */
2157 RCAR_GP_PIN(6, 21),
2158 };
2159 static const unsigned int hscif1_clk_a_mux[] = {
2160 HSCK1_A_MARK,
2161 };
2162 static const unsigned int hscif1_ctrl_a_pins[] = {
2163 /* RTS, CTS */
2164 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2165 };
2166 static const unsigned int hscif1_ctrl_a_mux[] = {
2167 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2168 };
2169
2170 static const unsigned int hscif1_data_b_pins[] = {
2171 /* RX, TX */
2172 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2173 };
2174 static const unsigned int hscif1_data_b_mux[] = {
2175 HRX1_B_MARK, HTX1_B_MARK,
2176 };
2177 static const unsigned int hscif1_clk_b_pins[] = {
2178 /* SCK */
2179 RCAR_GP_PIN(5, 0),
2180 };
2181 static const unsigned int hscif1_clk_b_mux[] = {
2182 HSCK1_B_MARK,
2183 };
2184 static const unsigned int hscif1_ctrl_b_pins[] = {
2185 /* RTS, CTS */
2186 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2187 };
2188 static const unsigned int hscif1_ctrl_b_mux[] = {
2189 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2190 };
2191 /* - HSCIF2 ----------------------------------------------------------------- */
2192 static const unsigned int hscif2_data_a_pins[] = {
2193 /* RX, TX */
2194 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2195 };
2196 static const unsigned int hscif2_data_a_mux[] = {
2197 HRX2_A_MARK, HTX2_A_MARK,
2198 };
2199 static const unsigned int hscif2_clk_a_pins[] = {
2200 /* SCK */
2201 RCAR_GP_PIN(6, 10),
2202 };
2203 static const unsigned int hscif2_clk_a_mux[] = {
2204 HSCK2_A_MARK,
2205 };
2206 static const unsigned int hscif2_ctrl_a_pins[] = {
2207 /* RTS, CTS */
2208 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2209 };
2210 static const unsigned int hscif2_ctrl_a_mux[] = {
2211 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2212 };
2213
2214 static const unsigned int hscif2_data_b_pins[] = {
2215 /* RX, TX */
2216 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2217 };
2218 static const unsigned int hscif2_data_b_mux[] = {
2219 HRX2_B_MARK, HTX2_B_MARK,
2220 };
2221 static const unsigned int hscif2_clk_b_pins[] = {
2222 /* SCK */
2223 RCAR_GP_PIN(6, 21),
2224 };
2225 static const unsigned int hscif2_clk_b_mux[] = {
2226 HSCK2_B_MARK,
2227 };
2228 static const unsigned int hscif2_ctrl_b_pins[] = {
2229 /* RTS, CTS */
2230 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2231 };
2232 static const unsigned int hscif2_ctrl_b_mux[] = {
2233 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2234 };
2235
2236 static const unsigned int hscif2_data_c_pins[] = {
2237 /* RX, TX */
2238 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2239 };
2240 static const unsigned int hscif2_data_c_mux[] = {
2241 HRX2_C_MARK, HTX2_C_MARK,
2242 };
2243 static const unsigned int hscif2_clk_c_pins[] = {
2244 /* SCK */
2245 RCAR_GP_PIN(6, 24),
2246 };
2247 static const unsigned int hscif2_clk_c_mux[] = {
2248 HSCK2_C_MARK,
2249 };
2250 static const unsigned int hscif2_ctrl_c_pins[] = {
2251 /* RTS, CTS */
2252 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2253 };
2254 static const unsigned int hscif2_ctrl_c_mux[] = {
2255 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2256 };
2257 /* - HSCIF3 ----------------------------------------------------------------- */
2258 static const unsigned int hscif3_data_a_pins[] = {
2259 /* RX, TX */
2260 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2261 };
2262 static const unsigned int hscif3_data_a_mux[] = {
2263 HRX3_A_MARK, HTX3_A_MARK,
2264 };
2265 static const unsigned int hscif3_clk_pins[] = {
2266 /* SCK */
2267 RCAR_GP_PIN(1, 22),
2268 };
2269 static const unsigned int hscif3_clk_mux[] = {
2270 HSCK3_MARK,
2271 };
2272 static const unsigned int hscif3_ctrl_pins[] = {
2273 /* RTS, CTS */
2274 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2275 };
2276 static const unsigned int hscif3_ctrl_mux[] = {
2277 HRTS3_N_MARK, HCTS3_N_MARK,
2278 };
2279
2280 static const unsigned int hscif3_data_b_pins[] = {
2281 /* RX, TX */
2282 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2283 };
2284 static const unsigned int hscif3_data_b_mux[] = {
2285 HRX3_B_MARK, HTX3_B_MARK,
2286 };
2287 static const unsigned int hscif3_data_c_pins[] = {
2288 /* RX, TX */
2289 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2290 };
2291 static const unsigned int hscif3_data_c_mux[] = {
2292 HRX3_C_MARK, HTX3_C_MARK,
2293 };
2294 static const unsigned int hscif3_data_d_pins[] = {
2295 /* RX, TX */
2296 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2297 };
2298 static const unsigned int hscif3_data_d_mux[] = {
2299 HRX3_D_MARK, HTX3_D_MARK,
2300 };
2301 /* - HSCIF4 ----------------------------------------------------------------- */
2302 static const unsigned int hscif4_data_a_pins[] = {
2303 /* RX, TX */
2304 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2305 };
2306 static const unsigned int hscif4_data_a_mux[] = {
2307 HRX4_A_MARK, HTX4_A_MARK,
2308 };
2309 static const unsigned int hscif4_clk_pins[] = {
2310 /* SCK */
2311 RCAR_GP_PIN(1, 11),
2312 };
2313 static const unsigned int hscif4_clk_mux[] = {
2314 HSCK4_MARK,
2315 };
2316 static const unsigned int hscif4_ctrl_pins[] = {
2317 /* RTS, CTS */
2318 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2319 };
2320 static const unsigned int hscif4_ctrl_mux[] = {
2321 HRTS4_N_MARK, HCTS4_N_MARK,
2322 };
2323
2324 static const unsigned int hscif4_data_b_pins[] = {
2325 /* RX, TX */
2326 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2327 };
2328 static const unsigned int hscif4_data_b_mux[] = {
2329 HRX4_B_MARK, HTX4_B_MARK,
2330 };
2331
2332 /* - I2C -------------------------------------------------------------------- */
2333 static const unsigned int i2c0_pins[] = {
2334 /* SCL, SDA */
2335 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2336 };
2337
2338 static const unsigned int i2c0_mux[] = {
2339 SCL0_MARK, SDA0_MARK,
2340 };
2341
2342 static const unsigned int i2c1_a_pins[] = {
2343 /* SDA, SCL */
2344 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2345 };
2346 static const unsigned int i2c1_a_mux[] = {
2347 SDA1_A_MARK, SCL1_A_MARK,
2348 };
2349 static const unsigned int i2c1_b_pins[] = {
2350 /* SDA, SCL */
2351 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2352 };
2353 static const unsigned int i2c1_b_mux[] = {
2354 SDA1_B_MARK, SCL1_B_MARK,
2355 };
2356 static const unsigned int i2c2_a_pins[] = {
2357 /* SDA, SCL */
2358 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2359 };
2360 static const unsigned int i2c2_a_mux[] = {
2361 SDA2_A_MARK, SCL2_A_MARK,
2362 };
2363 static const unsigned int i2c2_b_pins[] = {
2364 /* SDA, SCL */
2365 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2366 };
2367 static const unsigned int i2c2_b_mux[] = {
2368 SDA2_B_MARK, SCL2_B_MARK,
2369 };
2370
2371 static const unsigned int i2c3_pins[] = {
2372 /* SCL, SDA */
2373 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2374 };
2375
2376 static const unsigned int i2c3_mux[] = {
2377 SCL3_MARK, SDA3_MARK,
2378 };
2379
2380 static const unsigned int i2c5_pins[] = {
2381 /* SCL, SDA */
2382 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2383 };
2384
2385 static const unsigned int i2c5_mux[] = {
2386 SCL5_MARK, SDA5_MARK,
2387 };
2388
2389 static const unsigned int i2c6_a_pins[] = {
2390 /* SDA, SCL */
2391 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2392 };
2393 static const unsigned int i2c6_a_mux[] = {
2394 SDA6_A_MARK, SCL6_A_MARK,
2395 };
2396 static const unsigned int i2c6_b_pins[] = {
2397 /* SDA, SCL */
2398 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2399 };
2400 static const unsigned int i2c6_b_mux[] = {
2401 SDA6_B_MARK, SCL6_B_MARK,
2402 };
2403 static const unsigned int i2c6_c_pins[] = {
2404 /* SDA, SCL */
2405 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2406 };
2407 static const unsigned int i2c6_c_mux[] = {
2408 SDA6_C_MARK, SCL6_C_MARK,
2409 };
2410
2411 /* - INTC-EX ---------------------------------------------------------------- */
2412 static const unsigned int intc_ex_irq0_pins[] = {
2413 /* IRQ0 */
2414 RCAR_GP_PIN(2, 0),
2415 };
2416 static const unsigned int intc_ex_irq0_mux[] = {
2417 IRQ0_MARK,
2418 };
2419 static const unsigned int intc_ex_irq1_pins[] = {
2420 /* IRQ1 */
2421 RCAR_GP_PIN(2, 1),
2422 };
2423 static const unsigned int intc_ex_irq1_mux[] = {
2424 IRQ1_MARK,
2425 };
2426 static const unsigned int intc_ex_irq2_pins[] = {
2427 /* IRQ2 */
2428 RCAR_GP_PIN(2, 2),
2429 };
2430 static const unsigned int intc_ex_irq2_mux[] = {
2431 IRQ2_MARK,
2432 };
2433 static const unsigned int intc_ex_irq3_pins[] = {
2434 /* IRQ3 */
2435 RCAR_GP_PIN(2, 3),
2436 };
2437 static const unsigned int intc_ex_irq3_mux[] = {
2438 IRQ3_MARK,
2439 };
2440 static const unsigned int intc_ex_irq4_pins[] = {
2441 /* IRQ4 */
2442 RCAR_GP_PIN(2, 4),
2443 };
2444 static const unsigned int intc_ex_irq4_mux[] = {
2445 IRQ4_MARK,
2446 };
2447 static const unsigned int intc_ex_irq5_pins[] = {
2448 /* IRQ5 */
2449 RCAR_GP_PIN(2, 5),
2450 };
2451 static const unsigned int intc_ex_irq5_mux[] = {
2452 IRQ5_MARK,
2453 };
2454
2455 #ifdef CONFIG_PINCTRL_PFC_R8A77951
2456 /* - MLB+ ------------------------------------------------------------------- */
2457 static const unsigned int mlb_3pin_pins[] = {
2458 RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2459 };
2460 static const unsigned int mlb_3pin_mux[] = {
2461 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2462 };
2463 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
2464
2465 /* - MSIOF0 ----------------------------------------------------------------- */
2466 static const unsigned int msiof0_clk_pins[] = {
2467 /* SCK */
2468 RCAR_GP_PIN(5, 17),
2469 };
2470 static const unsigned int msiof0_clk_mux[] = {
2471 MSIOF0_SCK_MARK,
2472 };
2473 static const unsigned int msiof0_sync_pins[] = {
2474 /* SYNC */
2475 RCAR_GP_PIN(5, 18),
2476 };
2477 static const unsigned int msiof0_sync_mux[] = {
2478 MSIOF0_SYNC_MARK,
2479 };
2480 static const unsigned int msiof0_ss1_pins[] = {
2481 /* SS1 */
2482 RCAR_GP_PIN(5, 19),
2483 };
2484 static const unsigned int msiof0_ss1_mux[] = {
2485 MSIOF0_SS1_MARK,
2486 };
2487 static const unsigned int msiof0_ss2_pins[] = {
2488 /* SS2 */
2489 RCAR_GP_PIN(5, 21),
2490 };
2491 static const unsigned int msiof0_ss2_mux[] = {
2492 MSIOF0_SS2_MARK,
2493 };
2494 static const unsigned int msiof0_txd_pins[] = {
2495 /* TXD */
2496 RCAR_GP_PIN(5, 20),
2497 };
2498 static const unsigned int msiof0_txd_mux[] = {
2499 MSIOF0_TXD_MARK,
2500 };
2501 static const unsigned int msiof0_rxd_pins[] = {
2502 /* RXD */
2503 RCAR_GP_PIN(5, 22),
2504 };
2505 static const unsigned int msiof0_rxd_mux[] = {
2506 MSIOF0_RXD_MARK,
2507 };
2508 /* - MSIOF1 ----------------------------------------------------------------- */
2509 static const unsigned int msiof1_clk_a_pins[] = {
2510 /* SCK */
2511 RCAR_GP_PIN(6, 8),
2512 };
2513 static const unsigned int msiof1_clk_a_mux[] = {
2514 MSIOF1_SCK_A_MARK,
2515 };
2516 static const unsigned int msiof1_sync_a_pins[] = {
2517 /* SYNC */
2518 RCAR_GP_PIN(6, 9),
2519 };
2520 static const unsigned int msiof1_sync_a_mux[] = {
2521 MSIOF1_SYNC_A_MARK,
2522 };
2523 static const unsigned int msiof1_ss1_a_pins[] = {
2524 /* SS1 */
2525 RCAR_GP_PIN(6, 5),
2526 };
2527 static const unsigned int msiof1_ss1_a_mux[] = {
2528 MSIOF1_SS1_A_MARK,
2529 };
2530 static const unsigned int msiof1_ss2_a_pins[] = {
2531 /* SS2 */
2532 RCAR_GP_PIN(6, 6),
2533 };
2534 static const unsigned int msiof1_ss2_a_mux[] = {
2535 MSIOF1_SS2_A_MARK,
2536 };
2537 static const unsigned int msiof1_txd_a_pins[] = {
2538 /* TXD */
2539 RCAR_GP_PIN(6, 7),
2540 };
2541 static const unsigned int msiof1_txd_a_mux[] = {
2542 MSIOF1_TXD_A_MARK,
2543 };
2544 static const unsigned int msiof1_rxd_a_pins[] = {
2545 /* RXD */
2546 RCAR_GP_PIN(6, 10),
2547 };
2548 static const unsigned int msiof1_rxd_a_mux[] = {
2549 MSIOF1_RXD_A_MARK,
2550 };
2551 static const unsigned int msiof1_clk_b_pins[] = {
2552 /* SCK */
2553 RCAR_GP_PIN(5, 9),
2554 };
2555 static const unsigned int msiof1_clk_b_mux[] = {
2556 MSIOF1_SCK_B_MARK,
2557 };
2558 static const unsigned int msiof1_sync_b_pins[] = {
2559 /* SYNC */
2560 RCAR_GP_PIN(5, 3),
2561 };
2562 static const unsigned int msiof1_sync_b_mux[] = {
2563 MSIOF1_SYNC_B_MARK,
2564 };
2565 static const unsigned int msiof1_ss1_b_pins[] = {
2566 /* SS1 */
2567 RCAR_GP_PIN(5, 4),
2568 };
2569 static const unsigned int msiof1_ss1_b_mux[] = {
2570 MSIOF1_SS1_B_MARK,
2571 };
2572 static const unsigned int msiof1_ss2_b_pins[] = {
2573 /* SS2 */
2574 RCAR_GP_PIN(5, 0),
2575 };
2576 static const unsigned int msiof1_ss2_b_mux[] = {
2577 MSIOF1_SS2_B_MARK,
2578 };
2579 static const unsigned int msiof1_txd_b_pins[] = {
2580 /* TXD */
2581 RCAR_GP_PIN(5, 8),
2582 };
2583 static const unsigned int msiof1_txd_b_mux[] = {
2584 MSIOF1_TXD_B_MARK,
2585 };
2586 static const unsigned int msiof1_rxd_b_pins[] = {
2587 /* RXD */
2588 RCAR_GP_PIN(5, 7),
2589 };
2590 static const unsigned int msiof1_rxd_b_mux[] = {
2591 MSIOF1_RXD_B_MARK,
2592 };
2593 static const unsigned int msiof1_clk_c_pins[] = {
2594 /* SCK */
2595 RCAR_GP_PIN(6, 17),
2596 };
2597 static const unsigned int msiof1_clk_c_mux[] = {
2598 MSIOF1_SCK_C_MARK,
2599 };
2600 static const unsigned int msiof1_sync_c_pins[] = {
2601 /* SYNC */
2602 RCAR_GP_PIN(6, 18),
2603 };
2604 static const unsigned int msiof1_sync_c_mux[] = {
2605 MSIOF1_SYNC_C_MARK,
2606 };
2607 static const unsigned int msiof1_ss1_c_pins[] = {
2608 /* SS1 */
2609 RCAR_GP_PIN(6, 21),
2610 };
2611 static const unsigned int msiof1_ss1_c_mux[] = {
2612 MSIOF1_SS1_C_MARK,
2613 };
2614 static const unsigned int msiof1_ss2_c_pins[] = {
2615 /* SS2 */
2616 RCAR_GP_PIN(6, 27),
2617 };
2618 static const unsigned int msiof1_ss2_c_mux[] = {
2619 MSIOF1_SS2_C_MARK,
2620 };
2621 static const unsigned int msiof1_txd_c_pins[] = {
2622 /* TXD */
2623 RCAR_GP_PIN(6, 20),
2624 };
2625 static const unsigned int msiof1_txd_c_mux[] = {
2626 MSIOF1_TXD_C_MARK,
2627 };
2628 static const unsigned int msiof1_rxd_c_pins[] = {
2629 /* RXD */
2630 RCAR_GP_PIN(6, 19),
2631 };
2632 static const unsigned int msiof1_rxd_c_mux[] = {
2633 MSIOF1_RXD_C_MARK,
2634 };
2635 static const unsigned int msiof1_clk_d_pins[] = {
2636 /* SCK */
2637 RCAR_GP_PIN(5, 12),
2638 };
2639 static const unsigned int msiof1_clk_d_mux[] = {
2640 MSIOF1_SCK_D_MARK,
2641 };
2642 static const unsigned int msiof1_sync_d_pins[] = {
2643 /* SYNC */
2644 RCAR_GP_PIN(5, 15),
2645 };
2646 static const unsigned int msiof1_sync_d_mux[] = {
2647 MSIOF1_SYNC_D_MARK,
2648 };
2649 static const unsigned int msiof1_ss1_d_pins[] = {
2650 /* SS1 */
2651 RCAR_GP_PIN(5, 16),
2652 };
2653 static const unsigned int msiof1_ss1_d_mux[] = {
2654 MSIOF1_SS1_D_MARK,
2655 };
2656 static const unsigned int msiof1_ss2_d_pins[] = {
2657 /* SS2 */
2658 RCAR_GP_PIN(5, 21),
2659 };
2660 static const unsigned int msiof1_ss2_d_mux[] = {
2661 MSIOF1_SS2_D_MARK,
2662 };
2663 static const unsigned int msiof1_txd_d_pins[] = {
2664 /* TXD */
2665 RCAR_GP_PIN(5, 14),
2666 };
2667 static const unsigned int msiof1_txd_d_mux[] = {
2668 MSIOF1_TXD_D_MARK,
2669 };
2670 static const unsigned int msiof1_rxd_d_pins[] = {
2671 /* RXD */
2672 RCAR_GP_PIN(5, 13),
2673 };
2674 static const unsigned int msiof1_rxd_d_mux[] = {
2675 MSIOF1_RXD_D_MARK,
2676 };
2677 static const unsigned int msiof1_clk_e_pins[] = {
2678 /* SCK */
2679 RCAR_GP_PIN(3, 0),
2680 };
2681 static const unsigned int msiof1_clk_e_mux[] = {
2682 MSIOF1_SCK_E_MARK,
2683 };
2684 static const unsigned int msiof1_sync_e_pins[] = {
2685 /* SYNC */
2686 RCAR_GP_PIN(3, 1),
2687 };
2688 static const unsigned int msiof1_sync_e_mux[] = {
2689 MSIOF1_SYNC_E_MARK,
2690 };
2691 static const unsigned int msiof1_ss1_e_pins[] = {
2692 /* SS1 */
2693 RCAR_GP_PIN(3, 4),
2694 };
2695 static const unsigned int msiof1_ss1_e_mux[] = {
2696 MSIOF1_SS1_E_MARK,
2697 };
2698 static const unsigned int msiof1_ss2_e_pins[] = {
2699 /* SS2 */
2700 RCAR_GP_PIN(3, 5),
2701 };
2702 static const unsigned int msiof1_ss2_e_mux[] = {
2703 MSIOF1_SS2_E_MARK,
2704 };
2705 static const unsigned int msiof1_txd_e_pins[] = {
2706 /* TXD */
2707 RCAR_GP_PIN(3, 3),
2708 };
2709 static const unsigned int msiof1_txd_e_mux[] = {
2710 MSIOF1_TXD_E_MARK,
2711 };
2712 static const unsigned int msiof1_rxd_e_pins[] = {
2713 /* RXD */
2714 RCAR_GP_PIN(3, 2),
2715 };
2716 static const unsigned int msiof1_rxd_e_mux[] = {
2717 MSIOF1_RXD_E_MARK,
2718 };
2719 static const unsigned int msiof1_clk_f_pins[] = {
2720 /* SCK */
2721 RCAR_GP_PIN(5, 23),
2722 };
2723 static const unsigned int msiof1_clk_f_mux[] = {
2724 MSIOF1_SCK_F_MARK,
2725 };
2726 static const unsigned int msiof1_sync_f_pins[] = {
2727 /* SYNC */
2728 RCAR_GP_PIN(5, 24),
2729 };
2730 static const unsigned int msiof1_sync_f_mux[] = {
2731 MSIOF1_SYNC_F_MARK,
2732 };
2733 static const unsigned int msiof1_ss1_f_pins[] = {
2734 /* SS1 */
2735 RCAR_GP_PIN(6, 1),
2736 };
2737 static const unsigned int msiof1_ss1_f_mux[] = {
2738 MSIOF1_SS1_F_MARK,
2739 };
2740 static const unsigned int msiof1_ss2_f_pins[] = {
2741 /* SS2 */
2742 RCAR_GP_PIN(6, 2),
2743 };
2744 static const unsigned int msiof1_ss2_f_mux[] = {
2745 MSIOF1_SS2_F_MARK,
2746 };
2747 static const unsigned int msiof1_txd_f_pins[] = {
2748 /* TXD */
2749 RCAR_GP_PIN(6, 0),
2750 };
2751 static const unsigned int msiof1_txd_f_mux[] = {
2752 MSIOF1_TXD_F_MARK,
2753 };
2754 static const unsigned int msiof1_rxd_f_pins[] = {
2755 /* RXD */
2756 RCAR_GP_PIN(5, 25),
2757 };
2758 static const unsigned int msiof1_rxd_f_mux[] = {
2759 MSIOF1_RXD_F_MARK,
2760 };
2761 static const unsigned int msiof1_clk_g_pins[] = {
2762 /* SCK */
2763 RCAR_GP_PIN(3, 6),
2764 };
2765 static const unsigned int msiof1_clk_g_mux[] = {
2766 MSIOF1_SCK_G_MARK,
2767 };
2768 static const unsigned int msiof1_sync_g_pins[] = {
2769 /* SYNC */
2770 RCAR_GP_PIN(3, 7),
2771 };
2772 static const unsigned int msiof1_sync_g_mux[] = {
2773 MSIOF1_SYNC_G_MARK,
2774 };
2775 static const unsigned int msiof1_ss1_g_pins[] = {
2776 /* SS1 */
2777 RCAR_GP_PIN(3, 10),
2778 };
2779 static const unsigned int msiof1_ss1_g_mux[] = {
2780 MSIOF1_SS1_G_MARK,
2781 };
2782 static const unsigned int msiof1_ss2_g_pins[] = {
2783 /* SS2 */
2784 RCAR_GP_PIN(3, 11),
2785 };
2786 static const unsigned int msiof1_ss2_g_mux[] = {
2787 MSIOF1_SS2_G_MARK,
2788 };
2789 static const unsigned int msiof1_txd_g_pins[] = {
2790 /* TXD */
2791 RCAR_GP_PIN(3, 9),
2792 };
2793 static const unsigned int msiof1_txd_g_mux[] = {
2794 MSIOF1_TXD_G_MARK,
2795 };
2796 static const unsigned int msiof1_rxd_g_pins[] = {
2797 /* RXD */
2798 RCAR_GP_PIN(3, 8),
2799 };
2800 static const unsigned int msiof1_rxd_g_mux[] = {
2801 MSIOF1_RXD_G_MARK,
2802 };
2803 /* - MSIOF2 ----------------------------------------------------------------- */
2804 static const unsigned int msiof2_clk_a_pins[] = {
2805 /* SCK */
2806 RCAR_GP_PIN(1, 9),
2807 };
2808 static const unsigned int msiof2_clk_a_mux[] = {
2809 MSIOF2_SCK_A_MARK,
2810 };
2811 static const unsigned int msiof2_sync_a_pins[] = {
2812 /* SYNC */
2813 RCAR_GP_PIN(1, 8),
2814 };
2815 static const unsigned int msiof2_sync_a_mux[] = {
2816 MSIOF2_SYNC_A_MARK,
2817 };
2818 static const unsigned int msiof2_ss1_a_pins[] = {
2819 /* SS1 */
2820 RCAR_GP_PIN(1, 6),
2821 };
2822 static const unsigned int msiof2_ss1_a_mux[] = {
2823 MSIOF2_SS1_A_MARK,
2824 };
2825 static const unsigned int msiof2_ss2_a_pins[] = {
2826 /* SS2 */
2827 RCAR_GP_PIN(1, 7),
2828 };
2829 static const unsigned int msiof2_ss2_a_mux[] = {
2830 MSIOF2_SS2_A_MARK,
2831 };
2832 static const unsigned int msiof2_txd_a_pins[] = {
2833 /* TXD */
2834 RCAR_GP_PIN(1, 11),
2835 };
2836 static const unsigned int msiof2_txd_a_mux[] = {
2837 MSIOF2_TXD_A_MARK,
2838 };
2839 static const unsigned int msiof2_rxd_a_pins[] = {
2840 /* RXD */
2841 RCAR_GP_PIN(1, 10),
2842 };
2843 static const unsigned int msiof2_rxd_a_mux[] = {
2844 MSIOF2_RXD_A_MARK,
2845 };
2846 static const unsigned int msiof2_clk_b_pins[] = {
2847 /* SCK */
2848 RCAR_GP_PIN(0, 4),
2849 };
2850 static const unsigned int msiof2_clk_b_mux[] = {
2851 MSIOF2_SCK_B_MARK,
2852 };
2853 static const unsigned int msiof2_sync_b_pins[] = {
2854 /* SYNC */
2855 RCAR_GP_PIN(0, 5),
2856 };
2857 static const unsigned int msiof2_sync_b_mux[] = {
2858 MSIOF2_SYNC_B_MARK,
2859 };
2860 static const unsigned int msiof2_ss1_b_pins[] = {
2861 /* SS1 */
2862 RCAR_GP_PIN(0, 0),
2863 };
2864 static const unsigned int msiof2_ss1_b_mux[] = {
2865 MSIOF2_SS1_B_MARK,
2866 };
2867 static const unsigned int msiof2_ss2_b_pins[] = {
2868 /* SS2 */
2869 RCAR_GP_PIN(0, 1),
2870 };
2871 static const unsigned int msiof2_ss2_b_mux[] = {
2872 MSIOF2_SS2_B_MARK,
2873 };
2874 static const unsigned int msiof2_txd_b_pins[] = {
2875 /* TXD */
2876 RCAR_GP_PIN(0, 7),
2877 };
2878 static const unsigned int msiof2_txd_b_mux[] = {
2879 MSIOF2_TXD_B_MARK,
2880 };
2881 static const unsigned int msiof2_rxd_b_pins[] = {
2882 /* RXD */
2883 RCAR_GP_PIN(0, 6),
2884 };
2885 static const unsigned int msiof2_rxd_b_mux[] = {
2886 MSIOF2_RXD_B_MARK,
2887 };
2888 static const unsigned int msiof2_clk_c_pins[] = {
2889 /* SCK */
2890 RCAR_GP_PIN(2, 12),
2891 };
2892 static const unsigned int msiof2_clk_c_mux[] = {
2893 MSIOF2_SCK_C_MARK,
2894 };
2895 static const unsigned int msiof2_sync_c_pins[] = {
2896 /* SYNC */
2897 RCAR_GP_PIN(2, 11),
2898 };
2899 static const unsigned int msiof2_sync_c_mux[] = {
2900 MSIOF2_SYNC_C_MARK,
2901 };
2902 static const unsigned int msiof2_ss1_c_pins[] = {
2903 /* SS1 */
2904 RCAR_GP_PIN(2, 10),
2905 };
2906 static const unsigned int msiof2_ss1_c_mux[] = {
2907 MSIOF2_SS1_C_MARK,
2908 };
2909 static const unsigned int msiof2_ss2_c_pins[] = {
2910 /* SS2 */
2911 RCAR_GP_PIN(2, 9),
2912 };
2913 static const unsigned int msiof2_ss2_c_mux[] = {
2914 MSIOF2_SS2_C_MARK,
2915 };
2916 static const unsigned int msiof2_txd_c_pins[] = {
2917 /* TXD */
2918 RCAR_GP_PIN(2, 14),
2919 };
2920 static const unsigned int msiof2_txd_c_mux[] = {
2921 MSIOF2_TXD_C_MARK,
2922 };
2923 static const unsigned int msiof2_rxd_c_pins[] = {
2924 /* RXD */
2925 RCAR_GP_PIN(2, 13),
2926 };
2927 static const unsigned int msiof2_rxd_c_mux[] = {
2928 MSIOF2_RXD_C_MARK,
2929 };
2930 static const unsigned int msiof2_clk_d_pins[] = {
2931 /* SCK */
2932 RCAR_GP_PIN(0, 8),
2933 };
2934 static const unsigned int msiof2_clk_d_mux[] = {
2935 MSIOF2_SCK_D_MARK,
2936 };
2937 static const unsigned int msiof2_sync_d_pins[] = {
2938 /* SYNC */
2939 RCAR_GP_PIN(0, 9),
2940 };
2941 static const unsigned int msiof2_sync_d_mux[] = {
2942 MSIOF2_SYNC_D_MARK,
2943 };
2944 static const unsigned int msiof2_ss1_d_pins[] = {
2945 /* SS1 */
2946 RCAR_GP_PIN(0, 12),
2947 };
2948 static const unsigned int msiof2_ss1_d_mux[] = {
2949 MSIOF2_SS1_D_MARK,
2950 };
2951 static const unsigned int msiof2_ss2_d_pins[] = {
2952 /* SS2 */
2953 RCAR_GP_PIN(0, 13),
2954 };
2955 static const unsigned int msiof2_ss2_d_mux[] = {
2956 MSIOF2_SS2_D_MARK,
2957 };
2958 static const unsigned int msiof2_txd_d_pins[] = {
2959 /* TXD */
2960 RCAR_GP_PIN(0, 11),
2961 };
2962 static const unsigned int msiof2_txd_d_mux[] = {
2963 MSIOF2_TXD_D_MARK,
2964 };
2965 static const unsigned int msiof2_rxd_d_pins[] = {
2966 /* RXD */
2967 RCAR_GP_PIN(0, 10),
2968 };
2969 static const unsigned int msiof2_rxd_d_mux[] = {
2970 MSIOF2_RXD_D_MARK,
2971 };
2972 /* - MSIOF3 ----------------------------------------------------------------- */
2973 static const unsigned int msiof3_clk_a_pins[] = {
2974 /* SCK */
2975 RCAR_GP_PIN(0, 0),
2976 };
2977 static const unsigned int msiof3_clk_a_mux[] = {
2978 MSIOF3_SCK_A_MARK,
2979 };
2980 static const unsigned int msiof3_sync_a_pins[] = {
2981 /* SYNC */
2982 RCAR_GP_PIN(0, 1),
2983 };
2984 static const unsigned int msiof3_sync_a_mux[] = {
2985 MSIOF3_SYNC_A_MARK,
2986 };
2987 static const unsigned int msiof3_ss1_a_pins[] = {
2988 /* SS1 */
2989 RCAR_GP_PIN(0, 14),
2990 };
2991 static const unsigned int msiof3_ss1_a_mux[] = {
2992 MSIOF3_SS1_A_MARK,
2993 };
2994 static const unsigned int msiof3_ss2_a_pins[] = {
2995 /* SS2 */
2996 RCAR_GP_PIN(0, 15),
2997 };
2998 static const unsigned int msiof3_ss2_a_mux[] = {
2999 MSIOF3_SS2_A_MARK,
3000 };
3001 static const unsigned int msiof3_txd_a_pins[] = {
3002 /* TXD */
3003 RCAR_GP_PIN(0, 3),
3004 };
3005 static const unsigned int msiof3_txd_a_mux[] = {
3006 MSIOF3_TXD_A_MARK,
3007 };
3008 static const unsigned int msiof3_rxd_a_pins[] = {
3009 /* RXD */
3010 RCAR_GP_PIN(0, 2),
3011 };
3012 static const unsigned int msiof3_rxd_a_mux[] = {
3013 MSIOF3_RXD_A_MARK,
3014 };
3015 static const unsigned int msiof3_clk_b_pins[] = {
3016 /* SCK */
3017 RCAR_GP_PIN(1, 2),
3018 };
3019 static const unsigned int msiof3_clk_b_mux[] = {
3020 MSIOF3_SCK_B_MARK,
3021 };
3022 static const unsigned int msiof3_sync_b_pins[] = {
3023 /* SYNC */
3024 RCAR_GP_PIN(1, 0),
3025 };
3026 static const unsigned int msiof3_sync_b_mux[] = {
3027 MSIOF3_SYNC_B_MARK,
3028 };
3029 static const unsigned int msiof3_ss1_b_pins[] = {
3030 /* SS1 */
3031 RCAR_GP_PIN(1, 4),
3032 };
3033 static const unsigned int msiof3_ss1_b_mux[] = {
3034 MSIOF3_SS1_B_MARK,
3035 };
3036 static const unsigned int msiof3_ss2_b_pins[] = {
3037 /* SS2 */
3038 RCAR_GP_PIN(1, 5),
3039 };
3040 static const unsigned int msiof3_ss2_b_mux[] = {
3041 MSIOF3_SS2_B_MARK,
3042 };
3043 static const unsigned int msiof3_txd_b_pins[] = {
3044 /* TXD */
3045 RCAR_GP_PIN(1, 1),
3046 };
3047 static const unsigned int msiof3_txd_b_mux[] = {
3048 MSIOF3_TXD_B_MARK,
3049 };
3050 static const unsigned int msiof3_rxd_b_pins[] = {
3051 /* RXD */
3052 RCAR_GP_PIN(1, 3),
3053 };
3054 static const unsigned int msiof3_rxd_b_mux[] = {
3055 MSIOF3_RXD_B_MARK,
3056 };
3057 static const unsigned int msiof3_clk_c_pins[] = {
3058 /* SCK */
3059 RCAR_GP_PIN(1, 12),
3060 };
3061 static const unsigned int msiof3_clk_c_mux[] = {
3062 MSIOF3_SCK_C_MARK,
3063 };
3064 static const unsigned int msiof3_sync_c_pins[] = {
3065 /* SYNC */
3066 RCAR_GP_PIN(1, 13),
3067 };
3068 static const unsigned int msiof3_sync_c_mux[] = {
3069 MSIOF3_SYNC_C_MARK,
3070 };
3071 static const unsigned int msiof3_txd_c_pins[] = {
3072 /* TXD */
3073 RCAR_GP_PIN(1, 15),
3074 };
3075 static const unsigned int msiof3_txd_c_mux[] = {
3076 MSIOF3_TXD_C_MARK,
3077 };
3078 static const unsigned int msiof3_rxd_c_pins[] = {
3079 /* RXD */
3080 RCAR_GP_PIN(1, 14),
3081 };
3082 static const unsigned int msiof3_rxd_c_mux[] = {
3083 MSIOF3_RXD_C_MARK,
3084 };
3085 static const unsigned int msiof3_clk_d_pins[] = {
3086 /* SCK */
3087 RCAR_GP_PIN(1, 22),
3088 };
3089 static const unsigned int msiof3_clk_d_mux[] = {
3090 MSIOF3_SCK_D_MARK,
3091 };
3092 static const unsigned int msiof3_sync_d_pins[] = {
3093 /* SYNC */
3094 RCAR_GP_PIN(1, 23),
3095 };
3096 static const unsigned int msiof3_sync_d_mux[] = {
3097 MSIOF3_SYNC_D_MARK,
3098 };
3099 static const unsigned int msiof3_ss1_d_pins[] = {
3100 /* SS1 */
3101 RCAR_GP_PIN(1, 26),
3102 };
3103 static const unsigned int msiof3_ss1_d_mux[] = {
3104 MSIOF3_SS1_D_MARK,
3105 };
3106 static const unsigned int msiof3_txd_d_pins[] = {
3107 /* TXD */
3108 RCAR_GP_PIN(1, 25),
3109 };
3110 static const unsigned int msiof3_txd_d_mux[] = {
3111 MSIOF3_TXD_D_MARK,
3112 };
3113 static const unsigned int msiof3_rxd_d_pins[] = {
3114 /* RXD */
3115 RCAR_GP_PIN(1, 24),
3116 };
3117 static const unsigned int msiof3_rxd_d_mux[] = {
3118 MSIOF3_RXD_D_MARK,
3119 };
3120 static const unsigned int msiof3_clk_e_pins[] = {
3121 /* SCK */
3122 RCAR_GP_PIN(2, 3),
3123 };
3124 static const unsigned int msiof3_clk_e_mux[] = {
3125 MSIOF3_SCK_E_MARK,
3126 };
3127 static const unsigned int msiof3_sync_e_pins[] = {
3128 /* SYNC */
3129 RCAR_GP_PIN(2, 2),
3130 };
3131 static const unsigned int msiof3_sync_e_mux[] = {
3132 MSIOF3_SYNC_E_MARK,
3133 };
3134 static const unsigned int msiof3_ss1_e_pins[] = {
3135 /* SS1 */
3136 RCAR_GP_PIN(2, 1),
3137 };
3138 static const unsigned int msiof3_ss1_e_mux[] = {
3139 MSIOF3_SS1_E_MARK,
3140 };
3141 static const unsigned int msiof3_ss2_e_pins[] = {
3142 /* SS2 */
3143 RCAR_GP_PIN(2, 0),
3144 };
3145 static const unsigned int msiof3_ss2_e_mux[] = {
3146 MSIOF3_SS2_E_MARK,
3147 };
3148 static const unsigned int msiof3_txd_e_pins[] = {
3149 /* TXD */
3150 RCAR_GP_PIN(2, 5),
3151 };
3152 static const unsigned int msiof3_txd_e_mux[] = {
3153 MSIOF3_TXD_E_MARK,
3154 };
3155 static const unsigned int msiof3_rxd_e_pins[] = {
3156 /* RXD */
3157 RCAR_GP_PIN(2, 4),
3158 };
3159 static const unsigned int msiof3_rxd_e_mux[] = {
3160 MSIOF3_RXD_E_MARK,
3161 };
3162
3163 /* - PWM0 --------------------------------------------------------------------*/
3164 static const unsigned int pwm0_pins[] = {
3165 /* PWM */
3166 RCAR_GP_PIN(2, 6),
3167 };
3168 static const unsigned int pwm0_mux[] = {
3169 PWM0_MARK,
3170 };
3171 /* - PWM1 --------------------------------------------------------------------*/
3172 static const unsigned int pwm1_a_pins[] = {
3173 /* PWM */
3174 RCAR_GP_PIN(2, 7),
3175 };
3176 static const unsigned int pwm1_a_mux[] = {
3177 PWM1_A_MARK,
3178 };
3179 static const unsigned int pwm1_b_pins[] = {
3180 /* PWM */
3181 RCAR_GP_PIN(1, 8),
3182 };
3183 static const unsigned int pwm1_b_mux[] = {
3184 PWM1_B_MARK,
3185 };
3186 /* - PWM2 --------------------------------------------------------------------*/
3187 static const unsigned int pwm2_a_pins[] = {
3188 /* PWM */
3189 RCAR_GP_PIN(2, 8),
3190 };
3191 static const unsigned int pwm2_a_mux[] = {
3192 PWM2_A_MARK,
3193 };
3194 static const unsigned int pwm2_b_pins[] = {
3195 /* PWM */
3196 RCAR_GP_PIN(1, 11),
3197 };
3198 static const unsigned int pwm2_b_mux[] = {
3199 PWM2_B_MARK,
3200 };
3201 /* - PWM3 --------------------------------------------------------------------*/
3202 static const unsigned int pwm3_a_pins[] = {
3203 /* PWM */
3204 RCAR_GP_PIN(1, 0),
3205 };
3206 static const unsigned int pwm3_a_mux[] = {
3207 PWM3_A_MARK,
3208 };
3209 static const unsigned int pwm3_b_pins[] = {
3210 /* PWM */
3211 RCAR_GP_PIN(2, 2),
3212 };
3213 static const unsigned int pwm3_b_mux[] = {
3214 PWM3_B_MARK,
3215 };
3216 /* - PWM4 --------------------------------------------------------------------*/
3217 static const unsigned int pwm4_a_pins[] = {
3218 /* PWM */
3219 RCAR_GP_PIN(1, 1),
3220 };
3221 static const unsigned int pwm4_a_mux[] = {
3222 PWM4_A_MARK,
3223 };
3224 static const unsigned int pwm4_b_pins[] = {
3225 /* PWM */
3226 RCAR_GP_PIN(2, 3),
3227 };
3228 static const unsigned int pwm4_b_mux[] = {
3229 PWM4_B_MARK,
3230 };
3231 /* - PWM5 --------------------------------------------------------------------*/
3232 static const unsigned int pwm5_a_pins[] = {
3233 /* PWM */
3234 RCAR_GP_PIN(1, 2),
3235 };
3236 static const unsigned int pwm5_a_mux[] = {
3237 PWM5_A_MARK,
3238 };
3239 static const unsigned int pwm5_b_pins[] = {
3240 /* PWM */
3241 RCAR_GP_PIN(2, 4),
3242 };
3243 static const unsigned int pwm5_b_mux[] = {
3244 PWM5_B_MARK,
3245 };
3246 /* - PWM6 --------------------------------------------------------------------*/
3247 static const unsigned int pwm6_a_pins[] = {
3248 /* PWM */
3249 RCAR_GP_PIN(1, 3),
3250 };
3251 static const unsigned int pwm6_a_mux[] = {
3252 PWM6_A_MARK,
3253 };
3254 static const unsigned int pwm6_b_pins[] = {
3255 /* PWM */
3256 RCAR_GP_PIN(2, 5),
3257 };
3258 static const unsigned int pwm6_b_mux[] = {
3259 PWM6_B_MARK,
3260 };
3261
3262 /* - QSPI0 ------------------------------------------------------------------ */
3263 static const unsigned int qspi0_ctrl_pins[] = {
3264 /* QSPI0_SPCLK, QSPI0_SSL */
3265 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3266 };
3267 static const unsigned int qspi0_ctrl_mux[] = {
3268 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3269 };
3270 static const unsigned int qspi0_data_pins[] = {
3271 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3272 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3273 /* QSPI0_IO2, QSPI0_IO3 */
3274 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3275 };
3276 static const unsigned int qspi0_data_mux[] = {
3277 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3278 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3279 };
3280 /* - QSPI1 ------------------------------------------------------------------ */
3281 static const unsigned int qspi1_ctrl_pins[] = {
3282 /* QSPI1_SPCLK, QSPI1_SSL */
3283 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3284 };
3285 static const unsigned int qspi1_ctrl_mux[] = {
3286 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3287 };
3288 static const unsigned int qspi1_data_pins[] = {
3289 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3290 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3291 /* QSPI1_IO2, QSPI1_IO3 */
3292 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3293 };
3294 static const unsigned int qspi1_data_mux[] = {
3295 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3296 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3297 };
3298
3299 /* - SATA --------------------------------------------------------------------*/
3300 static const unsigned int sata0_devslp_a_pins[] = {
3301 /* DEVSLP */
3302 RCAR_GP_PIN(6, 16),
3303 };
3304 static const unsigned int sata0_devslp_a_mux[] = {
3305 SATA_DEVSLP_A_MARK,
3306 };
3307 static const unsigned int sata0_devslp_b_pins[] = {
3308 /* DEVSLP */
3309 RCAR_GP_PIN(4, 6),
3310 };
3311 static const unsigned int sata0_devslp_b_mux[] = {
3312 SATA_DEVSLP_B_MARK,
3313 };
3314
3315 /* - SCIF0 ------------------------------------------------------------------ */
3316 static const unsigned int scif0_data_pins[] = {
3317 /* RX, TX */
3318 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3319 };
3320 static const unsigned int scif0_data_mux[] = {
3321 RX0_MARK, TX0_MARK,
3322 };
3323 static const unsigned int scif0_clk_pins[] = {
3324 /* SCK */
3325 RCAR_GP_PIN(5, 0),
3326 };
3327 static const unsigned int scif0_clk_mux[] = {
3328 SCK0_MARK,
3329 };
3330 static const unsigned int scif0_ctrl_pins[] = {
3331 /* RTS, CTS */
3332 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3333 };
3334 static const unsigned int scif0_ctrl_mux[] = {
3335 RTS0_N_MARK, CTS0_N_MARK,
3336 };
3337 /* - SCIF1 ------------------------------------------------------------------ */
3338 static const unsigned int scif1_data_a_pins[] = {
3339 /* RX, TX */
3340 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3341 };
3342 static const unsigned int scif1_data_a_mux[] = {
3343 RX1_A_MARK, TX1_A_MARK,
3344 };
3345 static const unsigned int scif1_clk_pins[] = {
3346 /* SCK */
3347 RCAR_GP_PIN(6, 21),
3348 };
3349 static const unsigned int scif1_clk_mux[] = {
3350 SCK1_MARK,
3351 };
3352 static const unsigned int scif1_ctrl_pins[] = {
3353 /* RTS, CTS */
3354 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3355 };
3356 static const unsigned int scif1_ctrl_mux[] = {
3357 RTS1_N_MARK, CTS1_N_MARK,
3358 };
3359
3360 static const unsigned int scif1_data_b_pins[] = {
3361 /* RX, TX */
3362 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3363 };
3364 static const unsigned int scif1_data_b_mux[] = {
3365 RX1_B_MARK, TX1_B_MARK,
3366 };
3367 /* - SCIF2 ------------------------------------------------------------------ */
3368 static const unsigned int scif2_data_a_pins[] = {
3369 /* RX, TX */
3370 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3371 };
3372 static const unsigned int scif2_data_a_mux[] = {
3373 RX2_A_MARK, TX2_A_MARK,
3374 };
3375 static const unsigned int scif2_clk_pins[] = {
3376 /* SCK */
3377 RCAR_GP_PIN(5, 9),
3378 };
3379 static const unsigned int scif2_clk_mux[] = {
3380 SCK2_MARK,
3381 };
3382 static const unsigned int scif2_data_b_pins[] = {
3383 /* RX, TX */
3384 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3385 };
3386 static const unsigned int scif2_data_b_mux[] = {
3387 RX2_B_MARK, TX2_B_MARK,
3388 };
3389 /* - SCIF3 ------------------------------------------------------------------ */
3390 static const unsigned int scif3_data_a_pins[] = {
3391 /* RX, TX */
3392 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3393 };
3394 static const unsigned int scif3_data_a_mux[] = {
3395 RX3_A_MARK, TX3_A_MARK,
3396 };
3397 static const unsigned int scif3_clk_pins[] = {
3398 /* SCK */
3399 RCAR_GP_PIN(1, 22),
3400 };
3401 static const unsigned int scif3_clk_mux[] = {
3402 SCK3_MARK,
3403 };
3404 static const unsigned int scif3_ctrl_pins[] = {
3405 /* RTS, CTS */
3406 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3407 };
3408 static const unsigned int scif3_ctrl_mux[] = {
3409 RTS3_N_MARK, CTS3_N_MARK,
3410 };
3411 static const unsigned int scif3_data_b_pins[] = {
3412 /* RX, TX */
3413 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3414 };
3415 static const unsigned int scif3_data_b_mux[] = {
3416 RX3_B_MARK, TX3_B_MARK,
3417 };
3418 /* - SCIF4 ------------------------------------------------------------------ */
3419 static const unsigned int scif4_data_a_pins[] = {
3420 /* RX, TX */
3421 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3422 };
3423 static const unsigned int scif4_data_a_mux[] = {
3424 RX4_A_MARK, TX4_A_MARK,
3425 };
3426 static const unsigned int scif4_clk_a_pins[] = {
3427 /* SCK */
3428 RCAR_GP_PIN(2, 10),
3429 };
3430 static const unsigned int scif4_clk_a_mux[] = {
3431 SCK4_A_MARK,
3432 };
3433 static const unsigned int scif4_ctrl_a_pins[] = {
3434 /* RTS, CTS */
3435 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3436 };
3437 static const unsigned int scif4_ctrl_a_mux[] = {
3438 RTS4_N_A_MARK, CTS4_N_A_MARK,
3439 };
3440 static const unsigned int scif4_data_b_pins[] = {
3441 /* RX, TX */
3442 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3443 };
3444 static const unsigned int scif4_data_b_mux[] = {
3445 RX4_B_MARK, TX4_B_MARK,
3446 };
3447 static const unsigned int scif4_clk_b_pins[] = {
3448 /* SCK */
3449 RCAR_GP_PIN(1, 5),
3450 };
3451 static const unsigned int scif4_clk_b_mux[] = {
3452 SCK4_B_MARK,
3453 };
3454 static const unsigned int scif4_ctrl_b_pins[] = {
3455 /* RTS, CTS */
3456 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3457 };
3458 static const unsigned int scif4_ctrl_b_mux[] = {
3459 RTS4_N_B_MARK, CTS4_N_B_MARK,
3460 };
3461 static const unsigned int scif4_data_c_pins[] = {
3462 /* RX, TX */
3463 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3464 };
3465 static const unsigned int scif4_data_c_mux[] = {
3466 RX4_C_MARK, TX4_C_MARK,
3467 };
3468 static const unsigned int scif4_clk_c_pins[] = {
3469 /* SCK */
3470 RCAR_GP_PIN(0, 8),
3471 };
3472 static const unsigned int scif4_clk_c_mux[] = {
3473 SCK4_C_MARK,
3474 };
3475 static const unsigned int scif4_ctrl_c_pins[] = {
3476 /* RTS, CTS */
3477 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3478 };
3479 static const unsigned int scif4_ctrl_c_mux[] = {
3480 RTS4_N_C_MARK, CTS4_N_C_MARK,
3481 };
3482 /* - SCIF5 ------------------------------------------------------------------ */
3483 static const unsigned int scif5_data_a_pins[] = {
3484 /* RX, TX */
3485 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3486 };
3487 static const unsigned int scif5_data_a_mux[] = {
3488 RX5_A_MARK, TX5_A_MARK,
3489 };
3490 static const unsigned int scif5_clk_a_pins[] = {
3491 /* SCK */
3492 RCAR_GP_PIN(6, 21),
3493 };
3494 static const unsigned int scif5_clk_a_mux[] = {
3495 SCK5_A_MARK,
3496 };
3497 static const unsigned int scif5_data_b_pins[] = {
3498 /* RX, TX */
3499 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3500 };
3501 static const unsigned int scif5_data_b_mux[] = {
3502 RX5_B_MARK, TX5_B_MARK,
3503 };
3504 static const unsigned int scif5_clk_b_pins[] = {
3505 /* SCK */
3506 RCAR_GP_PIN(5, 0),
3507 };
3508 static const unsigned int scif5_clk_b_mux[] = {
3509 SCK5_B_MARK,
3510 };
3511
3512 /* - SCIF Clock ------------------------------------------------------------- */
3513 static const unsigned int scif_clk_a_pins[] = {
3514 /* SCIF_CLK */
3515 RCAR_GP_PIN(6, 23),
3516 };
3517 static const unsigned int scif_clk_a_mux[] = {
3518 SCIF_CLK_A_MARK,
3519 };
3520 static const unsigned int scif_clk_b_pins[] = {
3521 /* SCIF_CLK */
3522 RCAR_GP_PIN(5, 9),
3523 };
3524 static const unsigned int scif_clk_b_mux[] = {
3525 SCIF_CLK_B_MARK,
3526 };
3527
3528 /* - SDHI0 ------------------------------------------------------------------ */
3529 static const unsigned int sdhi0_data_pins[] = {
3530 /* D[0:3] */
3531 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3532 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3533 };
3534 static const unsigned int sdhi0_data_mux[] = {
3535 SD0_DAT0_MARK, SD0_DAT1_MARK,
3536 SD0_DAT2_MARK, SD0_DAT3_MARK,
3537 };
3538 static const unsigned int sdhi0_ctrl_pins[] = {
3539 /* CLK, CMD */
3540 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3541 };
3542 static const unsigned int sdhi0_ctrl_mux[] = {
3543 SD0_CLK_MARK, SD0_CMD_MARK,
3544 };
3545 static const unsigned int sdhi0_cd_pins[] = {
3546 /* CD */
3547 RCAR_GP_PIN(3, 12),
3548 };
3549 static const unsigned int sdhi0_cd_mux[] = {
3550 SD0_CD_MARK,
3551 };
3552 static const unsigned int sdhi0_wp_pins[] = {
3553 /* WP */
3554 RCAR_GP_PIN(3, 13),
3555 };
3556 static const unsigned int sdhi0_wp_mux[] = {
3557 SD0_WP_MARK,
3558 };
3559 /* - SDHI1 ------------------------------------------------------------------ */
3560 static const unsigned int sdhi1_data_pins[] = {
3561 /* D[0:3] */
3562 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3563 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3564 };
3565 static const unsigned int sdhi1_data_mux[] = {
3566 SD1_DAT0_MARK, SD1_DAT1_MARK,
3567 SD1_DAT2_MARK, SD1_DAT3_MARK,
3568 };
3569 static const unsigned int sdhi1_ctrl_pins[] = {
3570 /* CLK, CMD */
3571 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3572 };
3573 static const unsigned int sdhi1_ctrl_mux[] = {
3574 SD1_CLK_MARK, SD1_CMD_MARK,
3575 };
3576 static const unsigned int sdhi1_cd_pins[] = {
3577 /* CD */
3578 RCAR_GP_PIN(3, 14),
3579 };
3580 static const unsigned int sdhi1_cd_mux[] = {
3581 SD1_CD_MARK,
3582 };
3583 static const unsigned int sdhi1_wp_pins[] = {
3584 /* WP */
3585 RCAR_GP_PIN(3, 15),
3586 };
3587 static const unsigned int sdhi1_wp_mux[] = {
3588 SD1_WP_MARK,
3589 };
3590 /* - SDHI2 ------------------------------------------------------------------ */
3591 static const unsigned int sdhi2_data_pins[] = {
3592 /* D[0:7] */
3593 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3594 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3595 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3596 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3597 };
3598 static const unsigned int sdhi2_data_mux[] = {
3599 SD2_DAT0_MARK, SD2_DAT1_MARK,
3600 SD2_DAT2_MARK, SD2_DAT3_MARK,
3601 SD2_DAT4_MARK, SD2_DAT5_MARK,
3602 SD2_DAT6_MARK, SD2_DAT7_MARK,
3603 };
3604 static const unsigned int sdhi2_ctrl_pins[] = {
3605 /* CLK, CMD */
3606 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3607 };
3608 static const unsigned int sdhi2_ctrl_mux[] = {
3609 SD2_CLK_MARK, SD2_CMD_MARK,
3610 };
3611 static const unsigned int sdhi2_cd_a_pins[] = {
3612 /* CD */
3613 RCAR_GP_PIN(4, 13),
3614 };
3615 static const unsigned int sdhi2_cd_a_mux[] = {
3616 SD2_CD_A_MARK,
3617 };
3618 static const unsigned int sdhi2_cd_b_pins[] = {
3619 /* CD */
3620 RCAR_GP_PIN(5, 10),
3621 };
3622 static const unsigned int sdhi2_cd_b_mux[] = {
3623 SD2_CD_B_MARK,
3624 };
3625 static const unsigned int sdhi2_wp_a_pins[] = {
3626 /* WP */
3627 RCAR_GP_PIN(4, 14),
3628 };
3629 static const unsigned int sdhi2_wp_a_mux[] = {
3630 SD2_WP_A_MARK,
3631 };
3632 static const unsigned int sdhi2_wp_b_pins[] = {
3633 /* WP */
3634 RCAR_GP_PIN(5, 11),
3635 };
3636 static const unsigned int sdhi2_wp_b_mux[] = {
3637 SD2_WP_B_MARK,
3638 };
3639 static const unsigned int sdhi2_ds_pins[] = {
3640 /* DS */
3641 RCAR_GP_PIN(4, 6),
3642 };
3643 static const unsigned int sdhi2_ds_mux[] = {
3644 SD2_DS_MARK,
3645 };
3646 /* - SDHI3 ------------------------------------------------------------------ */
3647 static const unsigned int sdhi3_data_pins[] = {
3648 /* D[0:7] */
3649 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3650 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3651 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3652 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3653 };
3654 static const unsigned int sdhi3_data_mux[] = {
3655 SD3_DAT0_MARK, SD3_DAT1_MARK,
3656 SD3_DAT2_MARK, SD3_DAT3_MARK,
3657 SD3_DAT4_MARK, SD3_DAT5_MARK,
3658 SD3_DAT6_MARK, SD3_DAT7_MARK,
3659 };
3660 static const unsigned int sdhi3_ctrl_pins[] = {
3661 /* CLK, CMD */
3662 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3663 };
3664 static const unsigned int sdhi3_ctrl_mux[] = {
3665 SD3_CLK_MARK, SD3_CMD_MARK,
3666 };
3667 static const unsigned int sdhi3_cd_pins[] = {
3668 /* CD */
3669 RCAR_GP_PIN(4, 15),
3670 };
3671 static const unsigned int sdhi3_cd_mux[] = {
3672 SD3_CD_MARK,
3673 };
3674 static const unsigned int sdhi3_wp_pins[] = {
3675 /* WP */
3676 RCAR_GP_PIN(4, 16),
3677 };
3678 static const unsigned int sdhi3_wp_mux[] = {
3679 SD3_WP_MARK,
3680 };
3681 static const unsigned int sdhi3_ds_pins[] = {
3682 /* DS */
3683 RCAR_GP_PIN(4, 17),
3684 };
3685 static const unsigned int sdhi3_ds_mux[] = {
3686 SD3_DS_MARK,
3687 };
3688
3689 /* - SSI -------------------------------------------------------------------- */
3690 static const unsigned int ssi0_data_pins[] = {
3691 /* SDATA */
3692 RCAR_GP_PIN(6, 2),
3693 };
3694 static const unsigned int ssi0_data_mux[] = {
3695 SSI_SDATA0_MARK,
3696 };
3697 static const unsigned int ssi01239_ctrl_pins[] = {
3698 /* SCK, WS */
3699 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3700 };
3701 static const unsigned int ssi01239_ctrl_mux[] = {
3702 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3703 };
3704 static const unsigned int ssi1_data_a_pins[] = {
3705 /* SDATA */
3706 RCAR_GP_PIN(6, 3),
3707 };
3708 static const unsigned int ssi1_data_a_mux[] = {
3709 SSI_SDATA1_A_MARK,
3710 };
3711 static const unsigned int ssi1_data_b_pins[] = {
3712 /* SDATA */
3713 RCAR_GP_PIN(5, 12),
3714 };
3715 static const unsigned int ssi1_data_b_mux[] = {
3716 SSI_SDATA1_B_MARK,
3717 };
3718 static const unsigned int ssi1_ctrl_a_pins[] = {
3719 /* SCK, WS */
3720 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3721 };
3722 static const unsigned int ssi1_ctrl_a_mux[] = {
3723 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3724 };
3725 static const unsigned int ssi1_ctrl_b_pins[] = {
3726 /* SCK, WS */
3727 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3728 };
3729 static const unsigned int ssi1_ctrl_b_mux[] = {
3730 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3731 };
3732 static const unsigned int ssi2_data_a_pins[] = {
3733 /* SDATA */
3734 RCAR_GP_PIN(6, 4),
3735 };
3736 static const unsigned int ssi2_data_a_mux[] = {
3737 SSI_SDATA2_A_MARK,
3738 };
3739 static const unsigned int ssi2_data_b_pins[] = {
3740 /* SDATA */
3741 RCAR_GP_PIN(5, 13),
3742 };
3743 static const unsigned int ssi2_data_b_mux[] = {
3744 SSI_SDATA2_B_MARK,
3745 };
3746 static const unsigned int ssi2_ctrl_a_pins[] = {
3747 /* SCK, WS */
3748 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3749 };
3750 static const unsigned int ssi2_ctrl_a_mux[] = {
3751 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3752 };
3753 static const unsigned int ssi2_ctrl_b_pins[] = {
3754 /* SCK, WS */
3755 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3756 };
3757 static const unsigned int ssi2_ctrl_b_mux[] = {
3758 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3759 };
3760 static const unsigned int ssi3_data_pins[] = {
3761 /* SDATA */
3762 RCAR_GP_PIN(6, 7),
3763 };
3764 static const unsigned int ssi3_data_mux[] = {
3765 SSI_SDATA3_MARK,
3766 };
3767 static const unsigned int ssi349_ctrl_pins[] = {
3768 /* SCK, WS */
3769 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3770 };
3771 static const unsigned int ssi349_ctrl_mux[] = {
3772 SSI_SCK349_MARK, SSI_WS349_MARK,
3773 };
3774 static const unsigned int ssi4_data_pins[] = {
3775 /* SDATA */
3776 RCAR_GP_PIN(6, 10),
3777 };
3778 static const unsigned int ssi4_data_mux[] = {
3779 SSI_SDATA4_MARK,
3780 };
3781 static const unsigned int ssi4_ctrl_pins[] = {
3782 /* SCK, WS */
3783 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3784 };
3785 static const unsigned int ssi4_ctrl_mux[] = {
3786 SSI_SCK4_MARK, SSI_WS4_MARK,
3787 };
3788 static const unsigned int ssi5_data_pins[] = {
3789 /* SDATA */
3790 RCAR_GP_PIN(6, 13),
3791 };
3792 static const unsigned int ssi5_data_mux[] = {
3793 SSI_SDATA5_MARK,
3794 };
3795 static const unsigned int ssi5_ctrl_pins[] = {
3796 /* SCK, WS */
3797 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3798 };
3799 static const unsigned int ssi5_ctrl_mux[] = {
3800 SSI_SCK5_MARK, SSI_WS5_MARK,
3801 };
3802 static const unsigned int ssi6_data_pins[] = {
3803 /* SDATA */
3804 RCAR_GP_PIN(6, 16),
3805 };
3806 static const unsigned int ssi6_data_mux[] = {
3807 SSI_SDATA6_MARK,
3808 };
3809 static const unsigned int ssi6_ctrl_pins[] = {
3810 /* SCK, WS */
3811 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3812 };
3813 static const unsigned int ssi6_ctrl_mux[] = {
3814 SSI_SCK6_MARK, SSI_WS6_MARK,
3815 };
3816 static const unsigned int ssi7_data_pins[] = {
3817 /* SDATA */
3818 RCAR_GP_PIN(6, 19),
3819 };
3820 static const unsigned int ssi7_data_mux[] = {
3821 SSI_SDATA7_MARK,
3822 };
3823 static const unsigned int ssi78_ctrl_pins[] = {
3824 /* SCK, WS */
3825 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3826 };
3827 static const unsigned int ssi78_ctrl_mux[] = {
3828 SSI_SCK78_MARK, SSI_WS78_MARK,
3829 };
3830 static const unsigned int ssi8_data_pins[] = {
3831 /* SDATA */
3832 RCAR_GP_PIN(6, 20),
3833 };
3834 static const unsigned int ssi8_data_mux[] = {
3835 SSI_SDATA8_MARK,
3836 };
3837 static const unsigned int ssi9_data_a_pins[] = {
3838 /* SDATA */
3839 RCAR_GP_PIN(6, 21),
3840 };
3841 static const unsigned int ssi9_data_a_mux[] = {
3842 SSI_SDATA9_A_MARK,
3843 };
3844 static const unsigned int ssi9_data_b_pins[] = {
3845 /* SDATA */
3846 RCAR_GP_PIN(5, 14),
3847 };
3848 static const unsigned int ssi9_data_b_mux[] = {
3849 SSI_SDATA9_B_MARK,
3850 };
3851 static const unsigned int ssi9_ctrl_a_pins[] = {
3852 /* SCK, WS */
3853 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3854 };
3855 static const unsigned int ssi9_ctrl_a_mux[] = {
3856 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3857 };
3858 static const unsigned int ssi9_ctrl_b_pins[] = {
3859 /* SCK, WS */
3860 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3861 };
3862 static const unsigned int ssi9_ctrl_b_mux[] = {
3863 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3864 };
3865
3866 /* - TMU -------------------------------------------------------------------- */
3867 static const unsigned int tmu_tclk1_a_pins[] = {
3868 /* TCLK */
3869 RCAR_GP_PIN(6, 23),
3870 };
3871 static const unsigned int tmu_tclk1_a_mux[] = {
3872 TCLK1_A_MARK,
3873 };
3874 static const unsigned int tmu_tclk1_b_pins[] = {
3875 /* TCLK */
3876 RCAR_GP_PIN(5, 19),
3877 };
3878 static const unsigned int tmu_tclk1_b_mux[] = {
3879 TCLK1_B_MARK,
3880 };
3881 static const unsigned int tmu_tclk2_a_pins[] = {
3882 /* TCLK */
3883 RCAR_GP_PIN(6, 19),
3884 };
3885 static const unsigned int tmu_tclk2_a_mux[] = {
3886 TCLK2_A_MARK,
3887 };
3888 static const unsigned int tmu_tclk2_b_pins[] = {
3889 /* TCLK */
3890 RCAR_GP_PIN(6, 28),
3891 };
3892 static const unsigned int tmu_tclk2_b_mux[] = {
3893 TCLK2_B_MARK,
3894 };
3895
3896 /* - TPU ------------------------------------------------------------------- */
3897 static const unsigned int tpu_to0_pins[] = {
3898 /* TPU0TO0 */
3899 RCAR_GP_PIN(6, 28),
3900 };
3901 static const unsigned int tpu_to0_mux[] = {
3902 TPU0TO0_MARK,
3903 };
3904 static const unsigned int tpu_to1_pins[] = {
3905 /* TPU0TO1 */
3906 RCAR_GP_PIN(6, 29),
3907 };
3908 static const unsigned int tpu_to1_mux[] = {
3909 TPU0TO1_MARK,
3910 };
3911 static const unsigned int tpu_to2_pins[] = {
3912 /* TPU0TO2 */
3913 RCAR_GP_PIN(6, 30),
3914 };
3915 static const unsigned int tpu_to2_mux[] = {
3916 TPU0TO2_MARK,
3917 };
3918 static const unsigned int tpu_to3_pins[] = {
3919 /* TPU0TO3 */
3920 RCAR_GP_PIN(6, 31),
3921 };
3922 static const unsigned int tpu_to3_mux[] = {
3923 TPU0TO3_MARK,
3924 };
3925
3926 /* - USB0 ------------------------------------------------------------------- */
3927 static const unsigned int usb0_pins[] = {
3928 /* PWEN, OVC */
3929 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3930 };
3931 static const unsigned int usb0_mux[] = {
3932 USB0_PWEN_MARK, USB0_OVC_MARK,
3933 };
3934 /* - USB1 ------------------------------------------------------------------- */
3935 static const unsigned int usb1_pins[] = {
3936 /* PWEN, OVC */
3937 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3938 };
3939 static const unsigned int usb1_mux[] = {
3940 USB1_PWEN_MARK, USB1_OVC_MARK,
3941 };
3942 /* - USB2 ------------------------------------------------------------------- */
3943 static const unsigned int usb2_pins[] = {
3944 /* PWEN, OVC */
3945 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3946 };
3947 static const unsigned int usb2_mux[] = {
3948 USB2_PWEN_MARK, USB2_OVC_MARK,
3949 };
3950 /* - USB2_CH3 --------------------------------------------------------------- */
3951 static const unsigned int usb2_ch3_pins[] = {
3952 /* PWEN, OVC */
3953 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3954 };
3955 static const unsigned int usb2_ch3_mux[] = {
3956 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3957 };
3958
3959 /* - USB30 ------------------------------------------------------------------ */
3960 static const unsigned int usb30_pins[] = {
3961 /* PWEN, OVC */
3962 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3963 };
3964 static const unsigned int usb30_mux[] = {
3965 USB30_PWEN_MARK, USB30_OVC_MARK,
3966 };
3967
3968 /* - VIN4 ------------------------------------------------------------------- */
3969 static const unsigned int vin4_data18_a_pins[] = {
3970 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3971 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3972 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3973 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3974 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3975 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3976 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3977 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3978 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3979 };
3980 static const unsigned int vin4_data18_a_mux[] = {
3981 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3982 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3983 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3984 VI4_DATA10_MARK, VI4_DATA11_MARK,
3985 VI4_DATA12_MARK, VI4_DATA13_MARK,
3986 VI4_DATA14_MARK, VI4_DATA15_MARK,
3987 VI4_DATA18_MARK, VI4_DATA19_MARK,
3988 VI4_DATA20_MARK, VI4_DATA21_MARK,
3989 VI4_DATA22_MARK, VI4_DATA23_MARK,
3990 };
3991 static const unsigned int vin4_data18_b_pins[] = {
3992 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3993 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3994 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3995 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3996 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3997 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3998 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3999 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4000 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4001 };
4002 static const unsigned int vin4_data18_b_mux[] = {
4003 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4004 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4005 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4006 VI4_DATA10_MARK, VI4_DATA11_MARK,
4007 VI4_DATA12_MARK, VI4_DATA13_MARK,
4008 VI4_DATA14_MARK, VI4_DATA15_MARK,
4009 VI4_DATA18_MARK, VI4_DATA19_MARK,
4010 VI4_DATA20_MARK, VI4_DATA21_MARK,
4011 VI4_DATA22_MARK, VI4_DATA23_MARK,
4012 };
4013 static const unsigned int vin4_data_a_pins[] = {
4014 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4015 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4016 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4017 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4018 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4019 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4020 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4021 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4022 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4023 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4024 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4025 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4026 };
4027 static const unsigned int vin4_data_a_mux[] = {
4028 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4029 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4030 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4031 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4032 VI4_DATA8_MARK, VI4_DATA9_MARK,
4033 VI4_DATA10_MARK, VI4_DATA11_MARK,
4034 VI4_DATA12_MARK, VI4_DATA13_MARK,
4035 VI4_DATA14_MARK, VI4_DATA15_MARK,
4036 VI4_DATA16_MARK, VI4_DATA17_MARK,
4037 VI4_DATA18_MARK, VI4_DATA19_MARK,
4038 VI4_DATA20_MARK, VI4_DATA21_MARK,
4039 VI4_DATA22_MARK, VI4_DATA23_MARK,
4040 };
4041 static const unsigned int vin4_data_b_pins[] = {
4042 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4043 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4044 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4045 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4046 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4047 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4048 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4049 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4050 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4051 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4052 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4053 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4054 };
4055 static const unsigned int vin4_data_b_mux[] = {
4056 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4057 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4058 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4059 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4060 VI4_DATA8_MARK, VI4_DATA9_MARK,
4061 VI4_DATA10_MARK, VI4_DATA11_MARK,
4062 VI4_DATA12_MARK, VI4_DATA13_MARK,
4063 VI4_DATA14_MARK, VI4_DATA15_MARK,
4064 VI4_DATA16_MARK, VI4_DATA17_MARK,
4065 VI4_DATA18_MARK, VI4_DATA19_MARK,
4066 VI4_DATA20_MARK, VI4_DATA21_MARK,
4067 VI4_DATA22_MARK, VI4_DATA23_MARK,
4068 };
4069 static const unsigned int vin4_sync_pins[] = {
4070 /* HSYNC#, VSYNC# */
4071 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4072 };
4073 static const unsigned int vin4_sync_mux[] = {
4074 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4075 };
4076 static const unsigned int vin4_field_pins[] = {
4077 /* FIELD */
4078 RCAR_GP_PIN(1, 16),
4079 };
4080 static const unsigned int vin4_field_mux[] = {
4081 VI4_FIELD_MARK,
4082 };
4083 static const unsigned int vin4_clkenb_pins[] = {
4084 /* CLKENB */
4085 RCAR_GP_PIN(1, 19),
4086 };
4087 static const unsigned int vin4_clkenb_mux[] = {
4088 VI4_CLKENB_MARK,
4089 };
4090 static const unsigned int vin4_clk_pins[] = {
4091 /* CLK */
4092 RCAR_GP_PIN(1, 27),
4093 };
4094 static const unsigned int vin4_clk_mux[] = {
4095 VI4_CLK_MARK,
4096 };
4097
4098 /* - VIN5 ------------------------------------------------------------------- */
4099 static const unsigned int vin5_data_pins[] = {
4100 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4101 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4102 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4103 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4104 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4105 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4106 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4107 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4108 };
4109 static const unsigned int vin5_data_mux[] = {
4110 VI5_DATA0_MARK, VI5_DATA1_MARK,
4111 VI5_DATA2_MARK, VI5_DATA3_MARK,
4112 VI5_DATA4_MARK, VI5_DATA5_MARK,
4113 VI5_DATA6_MARK, VI5_DATA7_MARK,
4114 VI5_DATA8_MARK, VI5_DATA9_MARK,
4115 VI5_DATA10_MARK, VI5_DATA11_MARK,
4116 VI5_DATA12_MARK, VI5_DATA13_MARK,
4117 VI5_DATA14_MARK, VI5_DATA15_MARK,
4118 };
4119 static const unsigned int vin5_sync_pins[] = {
4120 /* HSYNC#, VSYNC# */
4121 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4122 };
4123 static const unsigned int vin5_sync_mux[] = {
4124 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4125 };
4126 static const unsigned int vin5_field_pins[] = {
4127 RCAR_GP_PIN(1, 11),
4128 };
4129 static const unsigned int vin5_field_mux[] = {
4130 /* FIELD */
4131 VI5_FIELD_MARK,
4132 };
4133 static const unsigned int vin5_clkenb_pins[] = {
4134 RCAR_GP_PIN(1, 20),
4135 };
4136 static const unsigned int vin5_clkenb_mux[] = {
4137 /* CLKENB */
4138 VI5_CLKENB_MARK,
4139 };
4140 static const unsigned int vin5_clk_pins[] = {
4141 RCAR_GP_PIN(1, 21),
4142 };
4143 static const unsigned int vin5_clk_mux[] = {
4144 /* CLK */
4145 VI5_CLK_MARK,
4146 };
4147
4148 static const struct {
4149 struct sh_pfc_pin_group common[328];
4150 #ifdef CONFIG_PINCTRL_PFC_R8A77951
4151 struct sh_pfc_pin_group automotive[31];
4152 #endif
4153 } pinmux_groups = {
4154 .common = {
4155 SH_PFC_PIN_GROUP(audio_clk_a_a),
4156 SH_PFC_PIN_GROUP(audio_clk_a_b),
4157 SH_PFC_PIN_GROUP(audio_clk_a_c),
4158 SH_PFC_PIN_GROUP(audio_clk_b_a),
4159 SH_PFC_PIN_GROUP(audio_clk_b_b),
4160 SH_PFC_PIN_GROUP(audio_clk_c_a),
4161 SH_PFC_PIN_GROUP(audio_clk_c_b),
4162 SH_PFC_PIN_GROUP(audio_clkout_a),
4163 SH_PFC_PIN_GROUP(audio_clkout_b),
4164 SH_PFC_PIN_GROUP(audio_clkout_c),
4165 SH_PFC_PIN_GROUP(audio_clkout_d),
4166 SH_PFC_PIN_GROUP(audio_clkout1_a),
4167 SH_PFC_PIN_GROUP(audio_clkout1_b),
4168 SH_PFC_PIN_GROUP(audio_clkout2_a),
4169 SH_PFC_PIN_GROUP(audio_clkout2_b),
4170 SH_PFC_PIN_GROUP(audio_clkout3_a),
4171 SH_PFC_PIN_GROUP(audio_clkout3_b),
4172 SH_PFC_PIN_GROUP(avb_link),
4173 SH_PFC_PIN_GROUP(avb_magic),
4174 SH_PFC_PIN_GROUP(avb_phy_int),
4175 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4176 SH_PFC_PIN_GROUP(avb_mdio),
4177 SH_PFC_PIN_GROUP(avb_mii),
4178 SH_PFC_PIN_GROUP(avb_avtp_pps),
4179 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4180 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4181 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4182 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4183 SH_PFC_PIN_GROUP(can0_data_a),
4184 SH_PFC_PIN_GROUP(can0_data_b),
4185 SH_PFC_PIN_GROUP(can1_data),
4186 SH_PFC_PIN_GROUP(can_clk),
4187 SH_PFC_PIN_GROUP(canfd0_data_a),
4188 SH_PFC_PIN_GROUP(canfd0_data_b),
4189 SH_PFC_PIN_GROUP(canfd1_data),
4190 SH_PFC_PIN_GROUP(du_rgb666),
4191 SH_PFC_PIN_GROUP(du_rgb888),
4192 SH_PFC_PIN_GROUP(du_clk_out_0),
4193 SH_PFC_PIN_GROUP(du_clk_out_1),
4194 SH_PFC_PIN_GROUP(du_sync),
4195 SH_PFC_PIN_GROUP(du_oddf),
4196 SH_PFC_PIN_GROUP(du_cde),
4197 SH_PFC_PIN_GROUP(du_disp),
4198 SH_PFC_PIN_GROUP(hscif0_data),
4199 SH_PFC_PIN_GROUP(hscif0_clk),
4200 SH_PFC_PIN_GROUP(hscif0_ctrl),
4201 SH_PFC_PIN_GROUP(hscif1_data_a),
4202 SH_PFC_PIN_GROUP(hscif1_clk_a),
4203 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4204 SH_PFC_PIN_GROUP(hscif1_data_b),
4205 SH_PFC_PIN_GROUP(hscif1_clk_b),
4206 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4207 SH_PFC_PIN_GROUP(hscif2_data_a),
4208 SH_PFC_PIN_GROUP(hscif2_clk_a),
4209 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4210 SH_PFC_PIN_GROUP(hscif2_data_b),
4211 SH_PFC_PIN_GROUP(hscif2_clk_b),
4212 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4213 SH_PFC_PIN_GROUP(hscif2_data_c),
4214 SH_PFC_PIN_GROUP(hscif2_clk_c),
4215 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4216 SH_PFC_PIN_GROUP(hscif3_data_a),
4217 SH_PFC_PIN_GROUP(hscif3_clk),
4218 SH_PFC_PIN_GROUP(hscif3_ctrl),
4219 SH_PFC_PIN_GROUP(hscif3_data_b),
4220 SH_PFC_PIN_GROUP(hscif3_data_c),
4221 SH_PFC_PIN_GROUP(hscif3_data_d),
4222 SH_PFC_PIN_GROUP(hscif4_data_a),
4223 SH_PFC_PIN_GROUP(hscif4_clk),
4224 SH_PFC_PIN_GROUP(hscif4_ctrl),
4225 SH_PFC_PIN_GROUP(hscif4_data_b),
4226 SH_PFC_PIN_GROUP(i2c0),
4227 SH_PFC_PIN_GROUP(i2c1_a),
4228 SH_PFC_PIN_GROUP(i2c1_b),
4229 SH_PFC_PIN_GROUP(i2c2_a),
4230 SH_PFC_PIN_GROUP(i2c2_b),
4231 SH_PFC_PIN_GROUP(i2c3),
4232 SH_PFC_PIN_GROUP(i2c5),
4233 SH_PFC_PIN_GROUP(i2c6_a),
4234 SH_PFC_PIN_GROUP(i2c6_b),
4235 SH_PFC_PIN_GROUP(i2c6_c),
4236 SH_PFC_PIN_GROUP(intc_ex_irq0),
4237 SH_PFC_PIN_GROUP(intc_ex_irq1),
4238 SH_PFC_PIN_GROUP(intc_ex_irq2),
4239 SH_PFC_PIN_GROUP(intc_ex_irq3),
4240 SH_PFC_PIN_GROUP(intc_ex_irq4),
4241 SH_PFC_PIN_GROUP(intc_ex_irq5),
4242 SH_PFC_PIN_GROUP(msiof0_clk),
4243 SH_PFC_PIN_GROUP(msiof0_sync),
4244 SH_PFC_PIN_GROUP(msiof0_ss1),
4245 SH_PFC_PIN_GROUP(msiof0_ss2),
4246 SH_PFC_PIN_GROUP(msiof0_txd),
4247 SH_PFC_PIN_GROUP(msiof0_rxd),
4248 SH_PFC_PIN_GROUP(msiof1_clk_a),
4249 SH_PFC_PIN_GROUP(msiof1_sync_a),
4250 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4251 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4252 SH_PFC_PIN_GROUP(msiof1_txd_a),
4253 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4254 SH_PFC_PIN_GROUP(msiof1_clk_b),
4255 SH_PFC_PIN_GROUP(msiof1_sync_b),
4256 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4257 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4258 SH_PFC_PIN_GROUP(msiof1_txd_b),
4259 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4260 SH_PFC_PIN_GROUP(msiof1_clk_c),
4261 SH_PFC_PIN_GROUP(msiof1_sync_c),
4262 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4263 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4264 SH_PFC_PIN_GROUP(msiof1_txd_c),
4265 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4266 SH_PFC_PIN_GROUP(msiof1_clk_d),
4267 SH_PFC_PIN_GROUP(msiof1_sync_d),
4268 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4269 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4270 SH_PFC_PIN_GROUP(msiof1_txd_d),
4271 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4272 SH_PFC_PIN_GROUP(msiof1_clk_e),
4273 SH_PFC_PIN_GROUP(msiof1_sync_e),
4274 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4275 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4276 SH_PFC_PIN_GROUP(msiof1_txd_e),
4277 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4278 SH_PFC_PIN_GROUP(msiof1_clk_f),
4279 SH_PFC_PIN_GROUP(msiof1_sync_f),
4280 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4281 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4282 SH_PFC_PIN_GROUP(msiof1_txd_f),
4283 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4284 SH_PFC_PIN_GROUP(msiof1_clk_g),
4285 SH_PFC_PIN_GROUP(msiof1_sync_g),
4286 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4287 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4288 SH_PFC_PIN_GROUP(msiof1_txd_g),
4289 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4290 SH_PFC_PIN_GROUP(msiof2_clk_a),
4291 SH_PFC_PIN_GROUP(msiof2_sync_a),
4292 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4293 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4294 SH_PFC_PIN_GROUP(msiof2_txd_a),
4295 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4296 SH_PFC_PIN_GROUP(msiof2_clk_b),
4297 SH_PFC_PIN_GROUP(msiof2_sync_b),
4298 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4299 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4300 SH_PFC_PIN_GROUP(msiof2_txd_b),
4301 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4302 SH_PFC_PIN_GROUP(msiof2_clk_c),
4303 SH_PFC_PIN_GROUP(msiof2_sync_c),
4304 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4305 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4306 SH_PFC_PIN_GROUP(msiof2_txd_c),
4307 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4308 SH_PFC_PIN_GROUP(msiof2_clk_d),
4309 SH_PFC_PIN_GROUP(msiof2_sync_d),
4310 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4311 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4312 SH_PFC_PIN_GROUP(msiof2_txd_d),
4313 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4314 SH_PFC_PIN_GROUP(msiof3_clk_a),
4315 SH_PFC_PIN_GROUP(msiof3_sync_a),
4316 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4317 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4318 SH_PFC_PIN_GROUP(msiof3_txd_a),
4319 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4320 SH_PFC_PIN_GROUP(msiof3_clk_b),
4321 SH_PFC_PIN_GROUP(msiof3_sync_b),
4322 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4323 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4324 SH_PFC_PIN_GROUP(msiof3_txd_b),
4325 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4326 SH_PFC_PIN_GROUP(msiof3_clk_c),
4327 SH_PFC_PIN_GROUP(msiof3_sync_c),
4328 SH_PFC_PIN_GROUP(msiof3_txd_c),
4329 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4330 SH_PFC_PIN_GROUP(msiof3_clk_d),
4331 SH_PFC_PIN_GROUP(msiof3_sync_d),
4332 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4333 SH_PFC_PIN_GROUP(msiof3_txd_d),
4334 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4335 SH_PFC_PIN_GROUP(msiof3_clk_e),
4336 SH_PFC_PIN_GROUP(msiof3_sync_e),
4337 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4338 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4339 SH_PFC_PIN_GROUP(msiof3_txd_e),
4340 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4341 SH_PFC_PIN_GROUP(pwm0),
4342 SH_PFC_PIN_GROUP(pwm1_a),
4343 SH_PFC_PIN_GROUP(pwm1_b),
4344 SH_PFC_PIN_GROUP(pwm2_a),
4345 SH_PFC_PIN_GROUP(pwm2_b),
4346 SH_PFC_PIN_GROUP(pwm3_a),
4347 SH_PFC_PIN_GROUP(pwm3_b),
4348 SH_PFC_PIN_GROUP(pwm4_a),
4349 SH_PFC_PIN_GROUP(pwm4_b),
4350 SH_PFC_PIN_GROUP(pwm5_a),
4351 SH_PFC_PIN_GROUP(pwm5_b),
4352 SH_PFC_PIN_GROUP(pwm6_a),
4353 SH_PFC_PIN_GROUP(pwm6_b),
4354 SH_PFC_PIN_GROUP(qspi0_ctrl),
4355 BUS_DATA_PIN_GROUP(qspi0_data, 2),
4356 BUS_DATA_PIN_GROUP(qspi0_data, 4),
4357 SH_PFC_PIN_GROUP(qspi1_ctrl),
4358 BUS_DATA_PIN_GROUP(qspi1_data, 2),
4359 BUS_DATA_PIN_GROUP(qspi1_data, 4),
4360 SH_PFC_PIN_GROUP(sata0_devslp_a),
4361 SH_PFC_PIN_GROUP(sata0_devslp_b),
4362 SH_PFC_PIN_GROUP(scif0_data),
4363 SH_PFC_PIN_GROUP(scif0_clk),
4364 SH_PFC_PIN_GROUP(scif0_ctrl),
4365 SH_PFC_PIN_GROUP(scif1_data_a),
4366 SH_PFC_PIN_GROUP(scif1_clk),
4367 SH_PFC_PIN_GROUP(scif1_ctrl),
4368 SH_PFC_PIN_GROUP(scif1_data_b),
4369 SH_PFC_PIN_GROUP(scif2_data_a),
4370 SH_PFC_PIN_GROUP(scif2_clk),
4371 SH_PFC_PIN_GROUP(scif2_data_b),
4372 SH_PFC_PIN_GROUP(scif3_data_a),
4373 SH_PFC_PIN_GROUP(scif3_clk),
4374 SH_PFC_PIN_GROUP(scif3_ctrl),
4375 SH_PFC_PIN_GROUP(scif3_data_b),
4376 SH_PFC_PIN_GROUP(scif4_data_a),
4377 SH_PFC_PIN_GROUP(scif4_clk_a),
4378 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4379 SH_PFC_PIN_GROUP(scif4_data_b),
4380 SH_PFC_PIN_GROUP(scif4_clk_b),
4381 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4382 SH_PFC_PIN_GROUP(scif4_data_c),
4383 SH_PFC_PIN_GROUP(scif4_clk_c),
4384 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4385 SH_PFC_PIN_GROUP(scif5_data_a),
4386 SH_PFC_PIN_GROUP(scif5_clk_a),
4387 SH_PFC_PIN_GROUP(scif5_data_b),
4388 SH_PFC_PIN_GROUP(scif5_clk_b),
4389 SH_PFC_PIN_GROUP(scif_clk_a),
4390 SH_PFC_PIN_GROUP(scif_clk_b),
4391 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4392 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
4393 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4394 SH_PFC_PIN_GROUP(sdhi0_cd),
4395 SH_PFC_PIN_GROUP(sdhi0_wp),
4396 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4397 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
4398 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4399 SH_PFC_PIN_GROUP(sdhi1_cd),
4400 SH_PFC_PIN_GROUP(sdhi1_wp),
4401 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4402 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4403 BUS_DATA_PIN_GROUP(sdhi2_data, 8),
4404 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4405 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4406 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4407 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4408 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4409 SH_PFC_PIN_GROUP(sdhi2_ds),
4410 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4411 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4412 BUS_DATA_PIN_GROUP(sdhi3_data, 8),
4413 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4414 SH_PFC_PIN_GROUP(sdhi3_cd),
4415 SH_PFC_PIN_GROUP(sdhi3_wp),
4416 SH_PFC_PIN_GROUP(sdhi3_ds),
4417 SH_PFC_PIN_GROUP(ssi0_data),
4418 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4419 SH_PFC_PIN_GROUP(ssi1_data_a),
4420 SH_PFC_PIN_GROUP(ssi1_data_b),
4421 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4422 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4423 SH_PFC_PIN_GROUP(ssi2_data_a),
4424 SH_PFC_PIN_GROUP(ssi2_data_b),
4425 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4426 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4427 SH_PFC_PIN_GROUP(ssi3_data),
4428 SH_PFC_PIN_GROUP(ssi349_ctrl),
4429 SH_PFC_PIN_GROUP(ssi4_data),
4430 SH_PFC_PIN_GROUP(ssi4_ctrl),
4431 SH_PFC_PIN_GROUP(ssi5_data),
4432 SH_PFC_PIN_GROUP(ssi5_ctrl),
4433 SH_PFC_PIN_GROUP(ssi6_data),
4434 SH_PFC_PIN_GROUP(ssi6_ctrl),
4435 SH_PFC_PIN_GROUP(ssi7_data),
4436 SH_PFC_PIN_GROUP(ssi78_ctrl),
4437 SH_PFC_PIN_GROUP(ssi8_data),
4438 SH_PFC_PIN_GROUP(ssi9_data_a),
4439 SH_PFC_PIN_GROUP(ssi9_data_b),
4440 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4441 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4442 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4443 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4444 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4445 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4446 SH_PFC_PIN_GROUP(tpu_to0),
4447 SH_PFC_PIN_GROUP(tpu_to1),
4448 SH_PFC_PIN_GROUP(tpu_to2),
4449 SH_PFC_PIN_GROUP(tpu_to3),
4450 SH_PFC_PIN_GROUP(usb0),
4451 SH_PFC_PIN_GROUP(usb1),
4452 SH_PFC_PIN_GROUP(usb2),
4453 SH_PFC_PIN_GROUP(usb2_ch3),
4454 SH_PFC_PIN_GROUP(usb30),
4455 BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4456 BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4457 BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4458 BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
4459 SH_PFC_PIN_GROUP(vin4_data18_a),
4460 BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4461 BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4462 BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4463 BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4464 BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4465 BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
4466 SH_PFC_PIN_GROUP(vin4_data18_b),
4467 BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4468 BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4469 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
4470 SH_PFC_PIN_GROUP(vin4_sync),
4471 SH_PFC_PIN_GROUP(vin4_field),
4472 SH_PFC_PIN_GROUP(vin4_clkenb),
4473 SH_PFC_PIN_GROUP(vin4_clk),
4474 BUS_DATA_PIN_GROUP(vin5_data, 8),
4475 BUS_DATA_PIN_GROUP(vin5_data, 10),
4476 BUS_DATA_PIN_GROUP(vin5_data, 12),
4477 BUS_DATA_PIN_GROUP(vin5_data, 16),
4478 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
4479 SH_PFC_PIN_GROUP(vin5_sync),
4480 SH_PFC_PIN_GROUP(vin5_field),
4481 SH_PFC_PIN_GROUP(vin5_clkenb),
4482 SH_PFC_PIN_GROUP(vin5_clk),
4483 },
4484 #ifdef CONFIG_PINCTRL_PFC_R8A77951
4485 .automotive = {
4486 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4487 SH_PFC_PIN_GROUP(drif0_data0_a),
4488 SH_PFC_PIN_GROUP(drif0_data1_a),
4489 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4490 SH_PFC_PIN_GROUP(drif0_data0_b),
4491 SH_PFC_PIN_GROUP(drif0_data1_b),
4492 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4493 SH_PFC_PIN_GROUP(drif0_data0_c),
4494 SH_PFC_PIN_GROUP(drif0_data1_c),
4495 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4496 SH_PFC_PIN_GROUP(drif1_data0_a),
4497 SH_PFC_PIN_GROUP(drif1_data1_a),
4498 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4499 SH_PFC_PIN_GROUP(drif1_data0_b),
4500 SH_PFC_PIN_GROUP(drif1_data1_b),
4501 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4502 SH_PFC_PIN_GROUP(drif1_data0_c),
4503 SH_PFC_PIN_GROUP(drif1_data1_c),
4504 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4505 SH_PFC_PIN_GROUP(drif2_data0_a),
4506 SH_PFC_PIN_GROUP(drif2_data1_a),
4507 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4508 SH_PFC_PIN_GROUP(drif2_data0_b),
4509 SH_PFC_PIN_GROUP(drif2_data1_b),
4510 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4511 SH_PFC_PIN_GROUP(drif3_data0_a),
4512 SH_PFC_PIN_GROUP(drif3_data1_a),
4513 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4514 SH_PFC_PIN_GROUP(drif3_data0_b),
4515 SH_PFC_PIN_GROUP(drif3_data1_b),
4516 SH_PFC_PIN_GROUP(mlb_3pin),
4517 }
4518 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
4519 };
4520
4521 static const char * const audio_clk_groups[] = {
4522 "audio_clk_a_a",
4523 "audio_clk_a_b",
4524 "audio_clk_a_c",
4525 "audio_clk_b_a",
4526 "audio_clk_b_b",
4527 "audio_clk_c_a",
4528 "audio_clk_c_b",
4529 "audio_clkout_a",
4530 "audio_clkout_b",
4531 "audio_clkout_c",
4532 "audio_clkout_d",
4533 "audio_clkout1_a",
4534 "audio_clkout1_b",
4535 "audio_clkout2_a",
4536 "audio_clkout2_b",
4537 "audio_clkout3_a",
4538 "audio_clkout3_b",
4539 };
4540
4541 static const char * const avb_groups[] = {
4542 "avb_link",
4543 "avb_magic",
4544 "avb_phy_int",
4545 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4546 "avb_mdio",
4547 "avb_mii",
4548 "avb_avtp_pps",
4549 "avb_avtp_match_a",
4550 "avb_avtp_capture_a",
4551 "avb_avtp_match_b",
4552 "avb_avtp_capture_b",
4553 };
4554
4555 static const char * const can0_groups[] = {
4556 "can0_data_a",
4557 "can0_data_b",
4558 };
4559
4560 static const char * const can1_groups[] = {
4561 "can1_data",
4562 };
4563
4564 static const char * const can_clk_groups[] = {
4565 "can_clk",
4566 };
4567
4568 static const char * const canfd0_groups[] = {
4569 "canfd0_data_a",
4570 "canfd0_data_b",
4571 };
4572
4573 static const char * const canfd1_groups[] = {
4574 "canfd1_data",
4575 };
4576
4577 #ifdef CONFIG_PINCTRL_PFC_R8A77951
4578 static const char * const drif0_groups[] = {
4579 "drif0_ctrl_a",
4580 "drif0_data0_a",
4581 "drif0_data1_a",
4582 "drif0_ctrl_b",
4583 "drif0_data0_b",
4584 "drif0_data1_b",
4585 "drif0_ctrl_c",
4586 "drif0_data0_c",
4587 "drif0_data1_c",
4588 };
4589
4590 static const char * const drif1_groups[] = {
4591 "drif1_ctrl_a",
4592 "drif1_data0_a",
4593 "drif1_data1_a",
4594 "drif1_ctrl_b",
4595 "drif1_data0_b",
4596 "drif1_data1_b",
4597 "drif1_ctrl_c",
4598 "drif1_data0_c",
4599 "drif1_data1_c",
4600 };
4601
4602 static const char * const drif2_groups[] = {
4603 "drif2_ctrl_a",
4604 "drif2_data0_a",
4605 "drif2_data1_a",
4606 "drif2_ctrl_b",
4607 "drif2_data0_b",
4608 "drif2_data1_b",
4609 };
4610
4611 static const char * const drif3_groups[] = {
4612 "drif3_ctrl_a",
4613 "drif3_data0_a",
4614 "drif3_data1_a",
4615 "drif3_ctrl_b",
4616 "drif3_data0_b",
4617 "drif3_data1_b",
4618 };
4619 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
4620
4621 static const char * const du_groups[] = {
4622 "du_rgb666",
4623 "du_rgb888",
4624 "du_clk_out_0",
4625 "du_clk_out_1",
4626 "du_sync",
4627 "du_oddf",
4628 "du_cde",
4629 "du_disp",
4630 };
4631
4632 static const char * const hscif0_groups[] = {
4633 "hscif0_data",
4634 "hscif0_clk",
4635 "hscif0_ctrl",
4636 };
4637
4638 static const char * const hscif1_groups[] = {
4639 "hscif1_data_a",
4640 "hscif1_clk_a",
4641 "hscif1_ctrl_a",
4642 "hscif1_data_b",
4643 "hscif1_clk_b",
4644 "hscif1_ctrl_b",
4645 };
4646
4647 static const char * const hscif2_groups[] = {
4648 "hscif2_data_a",
4649 "hscif2_clk_a",
4650 "hscif2_ctrl_a",
4651 "hscif2_data_b",
4652 "hscif2_clk_b",
4653 "hscif2_ctrl_b",
4654 "hscif2_data_c",
4655 "hscif2_clk_c",
4656 "hscif2_ctrl_c",
4657 };
4658
4659 static const char * const hscif3_groups[] = {
4660 "hscif3_data_a",
4661 "hscif3_clk",
4662 "hscif3_ctrl",
4663 "hscif3_data_b",
4664 "hscif3_data_c",
4665 "hscif3_data_d",
4666 };
4667
4668 static const char * const hscif4_groups[] = {
4669 "hscif4_data_a",
4670 "hscif4_clk",
4671 "hscif4_ctrl",
4672 "hscif4_data_b",
4673 };
4674
4675 static const char * const i2c0_groups[] = {
4676 "i2c0",
4677 };
4678
4679 static const char * const i2c1_groups[] = {
4680 "i2c1_a",
4681 "i2c1_b",
4682 };
4683
4684 static const char * const i2c2_groups[] = {
4685 "i2c2_a",
4686 "i2c2_b",
4687 };
4688
4689 static const char * const i2c3_groups[] = {
4690 "i2c3",
4691 };
4692
4693 static const char * const i2c5_groups[] = {
4694 "i2c5",
4695 };
4696
4697 static const char * const i2c6_groups[] = {
4698 "i2c6_a",
4699 "i2c6_b",
4700 "i2c6_c",
4701 };
4702
4703 static const char * const intc_ex_groups[] = {
4704 "intc_ex_irq0",
4705 "intc_ex_irq1",
4706 "intc_ex_irq2",
4707 "intc_ex_irq3",
4708 "intc_ex_irq4",
4709 "intc_ex_irq5",
4710 };
4711
4712 #ifdef CONFIG_PINCTRL_PFC_R8A77951
4713 static const char * const mlb_3pin_groups[] = {
4714 "mlb_3pin",
4715 };
4716 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
4717
4718 static const char * const msiof0_groups[] = {
4719 "msiof0_clk",
4720 "msiof0_sync",
4721 "msiof0_ss1",
4722 "msiof0_ss2",
4723 "msiof0_txd",
4724 "msiof0_rxd",
4725 };
4726
4727 static const char * const msiof1_groups[] = {
4728 "msiof1_clk_a",
4729 "msiof1_sync_a",
4730 "msiof1_ss1_a",
4731 "msiof1_ss2_a",
4732 "msiof1_txd_a",
4733 "msiof1_rxd_a",
4734 "msiof1_clk_b",
4735 "msiof1_sync_b",
4736 "msiof1_ss1_b",
4737 "msiof1_ss2_b",
4738 "msiof1_txd_b",
4739 "msiof1_rxd_b",
4740 "msiof1_clk_c",
4741 "msiof1_sync_c",
4742 "msiof1_ss1_c",
4743 "msiof1_ss2_c",
4744 "msiof1_txd_c",
4745 "msiof1_rxd_c",
4746 "msiof1_clk_d",
4747 "msiof1_sync_d",
4748 "msiof1_ss1_d",
4749 "msiof1_ss2_d",
4750 "msiof1_txd_d",
4751 "msiof1_rxd_d",
4752 "msiof1_clk_e",
4753 "msiof1_sync_e",
4754 "msiof1_ss1_e",
4755 "msiof1_ss2_e",
4756 "msiof1_txd_e",
4757 "msiof1_rxd_e",
4758 "msiof1_clk_f",
4759 "msiof1_sync_f",
4760 "msiof1_ss1_f",
4761 "msiof1_ss2_f",
4762 "msiof1_txd_f",
4763 "msiof1_rxd_f",
4764 "msiof1_clk_g",
4765 "msiof1_sync_g",
4766 "msiof1_ss1_g",
4767 "msiof1_ss2_g",
4768 "msiof1_txd_g",
4769 "msiof1_rxd_g",
4770 };
4771
4772 static const char * const msiof2_groups[] = {
4773 "msiof2_clk_a",
4774 "msiof2_sync_a",
4775 "msiof2_ss1_a",
4776 "msiof2_ss2_a",
4777 "msiof2_txd_a",
4778 "msiof2_rxd_a",
4779 "msiof2_clk_b",
4780 "msiof2_sync_b",
4781 "msiof2_ss1_b",
4782 "msiof2_ss2_b",
4783 "msiof2_txd_b",
4784 "msiof2_rxd_b",
4785 "msiof2_clk_c",
4786 "msiof2_sync_c",
4787 "msiof2_ss1_c",
4788 "msiof2_ss2_c",
4789 "msiof2_txd_c",
4790 "msiof2_rxd_c",
4791 "msiof2_clk_d",
4792 "msiof2_sync_d",
4793 "msiof2_ss1_d",
4794 "msiof2_ss2_d",
4795 "msiof2_txd_d",
4796 "msiof2_rxd_d",
4797 };
4798
4799 static const char * const msiof3_groups[] = {
4800 "msiof3_clk_a",
4801 "msiof3_sync_a",
4802 "msiof3_ss1_a",
4803 "msiof3_ss2_a",
4804 "msiof3_txd_a",
4805 "msiof3_rxd_a",
4806 "msiof3_clk_b",
4807 "msiof3_sync_b",
4808 "msiof3_ss1_b",
4809 "msiof3_ss2_b",
4810 "msiof3_txd_b",
4811 "msiof3_rxd_b",
4812 "msiof3_clk_c",
4813 "msiof3_sync_c",
4814 "msiof3_txd_c",
4815 "msiof3_rxd_c",
4816 "msiof3_clk_d",
4817 "msiof3_sync_d",
4818 "msiof3_ss1_d",
4819 "msiof3_txd_d",
4820 "msiof3_rxd_d",
4821 "msiof3_clk_e",
4822 "msiof3_sync_e",
4823 "msiof3_ss1_e",
4824 "msiof3_ss2_e",
4825 "msiof3_txd_e",
4826 "msiof3_rxd_e",
4827 };
4828
4829 static const char * const pwm0_groups[] = {
4830 "pwm0",
4831 };
4832
4833 static const char * const pwm1_groups[] = {
4834 "pwm1_a",
4835 "pwm1_b",
4836 };
4837
4838 static const char * const pwm2_groups[] = {
4839 "pwm2_a",
4840 "pwm2_b",
4841 };
4842
4843 static const char * const pwm3_groups[] = {
4844 "pwm3_a",
4845 "pwm3_b",
4846 };
4847
4848 static const char * const pwm4_groups[] = {
4849 "pwm4_a",
4850 "pwm4_b",
4851 };
4852
4853 static const char * const pwm5_groups[] = {
4854 "pwm5_a",
4855 "pwm5_b",
4856 };
4857
4858 static const char * const pwm6_groups[] = {
4859 "pwm6_a",
4860 "pwm6_b",
4861 };
4862
4863 static const char * const qspi0_groups[] = {
4864 "qspi0_ctrl",
4865 "qspi0_data2",
4866 "qspi0_data4",
4867 };
4868
4869 static const char * const qspi1_groups[] = {
4870 "qspi1_ctrl",
4871 "qspi1_data2",
4872 "qspi1_data4",
4873 };
4874
4875 static const char * const sata0_groups[] = {
4876 "sata0_devslp_a",
4877 "sata0_devslp_b",
4878 };
4879
4880 static const char * const scif0_groups[] = {
4881 "scif0_data",
4882 "scif0_clk",
4883 "scif0_ctrl",
4884 };
4885
4886 static const char * const scif1_groups[] = {
4887 "scif1_data_a",
4888 "scif1_clk",
4889 "scif1_ctrl",
4890 "scif1_data_b",
4891 };
4892
4893 static const char * const scif2_groups[] = {
4894 "scif2_data_a",
4895 "scif2_clk",
4896 "scif2_data_b",
4897 };
4898
4899 static const char * const scif3_groups[] = {
4900 "scif3_data_a",
4901 "scif3_clk",
4902 "scif3_ctrl",
4903 "scif3_data_b",
4904 };
4905
4906 static const char * const scif4_groups[] = {
4907 "scif4_data_a",
4908 "scif4_clk_a",
4909 "scif4_ctrl_a",
4910 "scif4_data_b",
4911 "scif4_clk_b",
4912 "scif4_ctrl_b",
4913 "scif4_data_c",
4914 "scif4_clk_c",
4915 "scif4_ctrl_c",
4916 };
4917
4918 static const char * const scif5_groups[] = {
4919 "scif5_data_a",
4920 "scif5_clk_a",
4921 "scif5_data_b",
4922 "scif5_clk_b",
4923 };
4924
4925 static const char * const scif_clk_groups[] = {
4926 "scif_clk_a",
4927 "scif_clk_b",
4928 };
4929
4930 static const char * const sdhi0_groups[] = {
4931 "sdhi0_data1",
4932 "sdhi0_data4",
4933 "sdhi0_ctrl",
4934 "sdhi0_cd",
4935 "sdhi0_wp",
4936 };
4937
4938 static const char * const sdhi1_groups[] = {
4939 "sdhi1_data1",
4940 "sdhi1_data4",
4941 "sdhi1_ctrl",
4942 "sdhi1_cd",
4943 "sdhi1_wp",
4944 };
4945
4946 static const char * const sdhi2_groups[] = {
4947 "sdhi2_data1",
4948 "sdhi2_data4",
4949 "sdhi2_data8",
4950 "sdhi2_ctrl",
4951 "sdhi2_cd_a",
4952 "sdhi2_wp_a",
4953 "sdhi2_cd_b",
4954 "sdhi2_wp_b",
4955 "sdhi2_ds",
4956 };
4957
4958 static const char * const sdhi3_groups[] = {
4959 "sdhi3_data1",
4960 "sdhi3_data4",
4961 "sdhi3_data8",
4962 "sdhi3_ctrl",
4963 "sdhi3_cd",
4964 "sdhi3_wp",
4965 "sdhi3_ds",
4966 };
4967
4968 static const char * const ssi_groups[] = {
4969 "ssi0_data",
4970 "ssi01239_ctrl",
4971 "ssi1_data_a",
4972 "ssi1_data_b",
4973 "ssi1_ctrl_a",
4974 "ssi1_ctrl_b",
4975 "ssi2_data_a",
4976 "ssi2_data_b",
4977 "ssi2_ctrl_a",
4978 "ssi2_ctrl_b",
4979 "ssi3_data",
4980 "ssi349_ctrl",
4981 "ssi4_data",
4982 "ssi4_ctrl",
4983 "ssi5_data",
4984 "ssi5_ctrl",
4985 "ssi6_data",
4986 "ssi6_ctrl",
4987 "ssi7_data",
4988 "ssi78_ctrl",
4989 "ssi8_data",
4990 "ssi9_data_a",
4991 "ssi9_data_b",
4992 "ssi9_ctrl_a",
4993 "ssi9_ctrl_b",
4994 };
4995
4996 static const char * const tmu_groups[] = {
4997 "tmu_tclk1_a",
4998 "tmu_tclk1_b",
4999 "tmu_tclk2_a",
5000 "tmu_tclk2_b",
5001 };
5002
5003 static const char * const tpu_groups[] = {
5004 "tpu_to0",
5005 "tpu_to1",
5006 "tpu_to2",
5007 "tpu_to3",
5008 };
5009
5010 static const char * const usb0_groups[] = {
5011 "usb0",
5012 };
5013
5014 static const char * const usb1_groups[] = {
5015 "usb1",
5016 };
5017
5018 static const char * const usb2_groups[] = {
5019 "usb2",
5020 };
5021
5022 static const char * const usb2_ch3_groups[] = {
5023 "usb2_ch3",
5024 };
5025
5026 static const char * const usb30_groups[] = {
5027 "usb30",
5028 };
5029
5030 static const char * const vin4_groups[] = {
5031 "vin4_data8_a",
5032 "vin4_data10_a",
5033 "vin4_data12_a",
5034 "vin4_data16_a",
5035 "vin4_data18_a",
5036 "vin4_data20_a",
5037 "vin4_data24_a",
5038 "vin4_data8_b",
5039 "vin4_data10_b",
5040 "vin4_data12_b",
5041 "vin4_data16_b",
5042 "vin4_data18_b",
5043 "vin4_data20_b",
5044 "vin4_data24_b",
5045 "vin4_g8",
5046 "vin4_sync",
5047 "vin4_field",
5048 "vin4_clkenb",
5049 "vin4_clk",
5050 };
5051
5052 static const char * const vin5_groups[] = {
5053 "vin5_data8",
5054 "vin5_data10",
5055 "vin5_data12",
5056 "vin5_data16",
5057 "vin5_high8",
5058 "vin5_sync",
5059 "vin5_field",
5060 "vin5_clkenb",
5061 "vin5_clk",
5062 };
5063
5064 static const struct {
5065 struct sh_pfc_function common[55];
5066 #ifdef CONFIG_PINCTRL_PFC_R8A77951
5067 struct sh_pfc_function automotive[5];
5068 #endif
5069 } pinmux_functions = {
5070 .common = {
5071 SH_PFC_FUNCTION(audio_clk),
5072 SH_PFC_FUNCTION(avb),
5073 SH_PFC_FUNCTION(can0),
5074 SH_PFC_FUNCTION(can1),
5075 SH_PFC_FUNCTION(can_clk),
5076 SH_PFC_FUNCTION(canfd0),
5077 SH_PFC_FUNCTION(canfd1),
5078 SH_PFC_FUNCTION(du),
5079 SH_PFC_FUNCTION(hscif0),
5080 SH_PFC_FUNCTION(hscif1),
5081 SH_PFC_FUNCTION(hscif2),
5082 SH_PFC_FUNCTION(hscif3),
5083 SH_PFC_FUNCTION(hscif4),
5084 SH_PFC_FUNCTION(i2c0),
5085 SH_PFC_FUNCTION(i2c1),
5086 SH_PFC_FUNCTION(i2c2),
5087 SH_PFC_FUNCTION(i2c3),
5088 SH_PFC_FUNCTION(i2c5),
5089 SH_PFC_FUNCTION(i2c6),
5090 SH_PFC_FUNCTION(intc_ex),
5091 SH_PFC_FUNCTION(msiof0),
5092 SH_PFC_FUNCTION(msiof1),
5093 SH_PFC_FUNCTION(msiof2),
5094 SH_PFC_FUNCTION(msiof3),
5095 SH_PFC_FUNCTION(pwm0),
5096 SH_PFC_FUNCTION(pwm1),
5097 SH_PFC_FUNCTION(pwm2),
5098 SH_PFC_FUNCTION(pwm3),
5099 SH_PFC_FUNCTION(pwm4),
5100 SH_PFC_FUNCTION(pwm5),
5101 SH_PFC_FUNCTION(pwm6),
5102 SH_PFC_FUNCTION(qspi0),
5103 SH_PFC_FUNCTION(qspi1),
5104 SH_PFC_FUNCTION(sata0),
5105 SH_PFC_FUNCTION(scif0),
5106 SH_PFC_FUNCTION(scif1),
5107 SH_PFC_FUNCTION(scif2),
5108 SH_PFC_FUNCTION(scif3),
5109 SH_PFC_FUNCTION(scif4),
5110 SH_PFC_FUNCTION(scif5),
5111 SH_PFC_FUNCTION(scif_clk),
5112 SH_PFC_FUNCTION(sdhi0),
5113 SH_PFC_FUNCTION(sdhi1),
5114 SH_PFC_FUNCTION(sdhi2),
5115 SH_PFC_FUNCTION(sdhi3),
5116 SH_PFC_FUNCTION(ssi),
5117 SH_PFC_FUNCTION(tmu),
5118 SH_PFC_FUNCTION(tpu),
5119 SH_PFC_FUNCTION(usb0),
5120 SH_PFC_FUNCTION(usb1),
5121 SH_PFC_FUNCTION(usb2),
5122 SH_PFC_FUNCTION(usb2_ch3),
5123 SH_PFC_FUNCTION(usb30),
5124 SH_PFC_FUNCTION(vin4),
5125 SH_PFC_FUNCTION(vin5),
5126 },
5127 #ifdef CONFIG_PINCTRL_PFC_R8A77951
5128 .automotive = {
5129 SH_PFC_FUNCTION(drif0),
5130 SH_PFC_FUNCTION(drif1),
5131 SH_PFC_FUNCTION(drif2),
5132 SH_PFC_FUNCTION(drif3),
5133 SH_PFC_FUNCTION(mlb_3pin),
5134 }
5135 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
5136 };
5137
5138 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5139 #define F_(x, y) FN_##y
5140 #define FM(x) FN_##x
5141 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5142 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5143 1, 1, 1, 1, 1),
5144 GROUP(
5145 /* GP0_31_16 RESERVED */
5146 GP_0_15_FN, GPSR0_15,
5147 GP_0_14_FN, GPSR0_14,
5148 GP_0_13_FN, GPSR0_13,
5149 GP_0_12_FN, GPSR0_12,
5150 GP_0_11_FN, GPSR0_11,
5151 GP_0_10_FN, GPSR0_10,
5152 GP_0_9_FN, GPSR0_9,
5153 GP_0_8_FN, GPSR0_8,
5154 GP_0_7_FN, GPSR0_7,
5155 GP_0_6_FN, GPSR0_6,
5156 GP_0_5_FN, GPSR0_5,
5157 GP_0_4_FN, GPSR0_4,
5158 GP_0_3_FN, GPSR0_3,
5159 GP_0_2_FN, GPSR0_2,
5160 GP_0_1_FN, GPSR0_1,
5161 GP_0_0_FN, GPSR0_0, ))
5162 },
5163 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5164 0, 0,
5165 0, 0,
5166 0, 0,
5167 GP_1_28_FN, GPSR1_28,
5168 GP_1_27_FN, GPSR1_27,
5169 GP_1_26_FN, GPSR1_26,
5170 GP_1_25_FN, GPSR1_25,
5171 GP_1_24_FN, GPSR1_24,
5172 GP_1_23_FN, GPSR1_23,
5173 GP_1_22_FN, GPSR1_22,
5174 GP_1_21_FN, GPSR1_21,
5175 GP_1_20_FN, GPSR1_20,
5176 GP_1_19_FN, GPSR1_19,
5177 GP_1_18_FN, GPSR1_18,
5178 GP_1_17_FN, GPSR1_17,
5179 GP_1_16_FN, GPSR1_16,
5180 GP_1_15_FN, GPSR1_15,
5181 GP_1_14_FN, GPSR1_14,
5182 GP_1_13_FN, GPSR1_13,
5183 GP_1_12_FN, GPSR1_12,
5184 GP_1_11_FN, GPSR1_11,
5185 GP_1_10_FN, GPSR1_10,
5186 GP_1_9_FN, GPSR1_9,
5187 GP_1_8_FN, GPSR1_8,
5188 GP_1_7_FN, GPSR1_7,
5189 GP_1_6_FN, GPSR1_6,
5190 GP_1_5_FN, GPSR1_5,
5191 GP_1_4_FN, GPSR1_4,
5192 GP_1_3_FN, GPSR1_3,
5193 GP_1_2_FN, GPSR1_2,
5194 GP_1_1_FN, GPSR1_1,
5195 GP_1_0_FN, GPSR1_0, ))
5196 },
5197 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5198 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5199 1, 1, 1, 1),
5200 GROUP(
5201 /* GP2_31_15 RESERVED */
5202 GP_2_14_FN, GPSR2_14,
5203 GP_2_13_FN, GPSR2_13,
5204 GP_2_12_FN, GPSR2_12,
5205 GP_2_11_FN, GPSR2_11,
5206 GP_2_10_FN, GPSR2_10,
5207 GP_2_9_FN, GPSR2_9,
5208 GP_2_8_FN, GPSR2_8,
5209 GP_2_7_FN, GPSR2_7,
5210 GP_2_6_FN, GPSR2_6,
5211 GP_2_5_FN, GPSR2_5,
5212 GP_2_4_FN, GPSR2_4,
5213 GP_2_3_FN, GPSR2_3,
5214 GP_2_2_FN, GPSR2_2,
5215 GP_2_1_FN, GPSR2_1,
5216 GP_2_0_FN, GPSR2_0, ))
5217 },
5218 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5219 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5220 1, 1, 1, 1, 1),
5221 GROUP(
5222 /* GP3_31_16 RESERVED */
5223 GP_3_15_FN, GPSR3_15,
5224 GP_3_14_FN, GPSR3_14,
5225 GP_3_13_FN, GPSR3_13,
5226 GP_3_12_FN, GPSR3_12,
5227 GP_3_11_FN, GPSR3_11,
5228 GP_3_10_FN, GPSR3_10,
5229 GP_3_9_FN, GPSR3_9,
5230 GP_3_8_FN, GPSR3_8,
5231 GP_3_7_FN, GPSR3_7,
5232 GP_3_6_FN, GPSR3_6,
5233 GP_3_5_FN, GPSR3_5,
5234 GP_3_4_FN, GPSR3_4,
5235 GP_3_3_FN, GPSR3_3,
5236 GP_3_2_FN, GPSR3_2,
5237 GP_3_1_FN, GPSR3_1,
5238 GP_3_0_FN, GPSR3_0, ))
5239 },
5240 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5241 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5242 1, 1, 1, 1, 1, 1, 1),
5243 GROUP(
5244 /* GP4_31_18 RESERVED */
5245 GP_4_17_FN, GPSR4_17,
5246 GP_4_16_FN, GPSR4_16,
5247 GP_4_15_FN, GPSR4_15,
5248 GP_4_14_FN, GPSR4_14,
5249 GP_4_13_FN, GPSR4_13,
5250 GP_4_12_FN, GPSR4_12,
5251 GP_4_11_FN, GPSR4_11,
5252 GP_4_10_FN, GPSR4_10,
5253 GP_4_9_FN, GPSR4_9,
5254 GP_4_8_FN, GPSR4_8,
5255 GP_4_7_FN, GPSR4_7,
5256 GP_4_6_FN, GPSR4_6,
5257 GP_4_5_FN, GPSR4_5,
5258 GP_4_4_FN, GPSR4_4,
5259 GP_4_3_FN, GPSR4_3,
5260 GP_4_2_FN, GPSR4_2,
5261 GP_4_1_FN, GPSR4_1,
5262 GP_4_0_FN, GPSR4_0, ))
5263 },
5264 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5265 0, 0,
5266 0, 0,
5267 0, 0,
5268 0, 0,
5269 0, 0,
5270 0, 0,
5271 GP_5_25_FN, GPSR5_25,
5272 GP_5_24_FN, GPSR5_24,
5273 GP_5_23_FN, GPSR5_23,
5274 GP_5_22_FN, GPSR5_22,
5275 GP_5_21_FN, GPSR5_21,
5276 GP_5_20_FN, GPSR5_20,
5277 GP_5_19_FN, GPSR5_19,
5278 GP_5_18_FN, GPSR5_18,
5279 GP_5_17_FN, GPSR5_17,
5280 GP_5_16_FN, GPSR5_16,
5281 GP_5_15_FN, GPSR5_15,
5282 GP_5_14_FN, GPSR5_14,
5283 GP_5_13_FN, GPSR5_13,
5284 GP_5_12_FN, GPSR5_12,
5285 GP_5_11_FN, GPSR5_11,
5286 GP_5_10_FN, GPSR5_10,
5287 GP_5_9_FN, GPSR5_9,
5288 GP_5_8_FN, GPSR5_8,
5289 GP_5_7_FN, GPSR5_7,
5290 GP_5_6_FN, GPSR5_6,
5291 GP_5_5_FN, GPSR5_5,
5292 GP_5_4_FN, GPSR5_4,
5293 GP_5_3_FN, GPSR5_3,
5294 GP_5_2_FN, GPSR5_2,
5295 GP_5_1_FN, GPSR5_1,
5296 GP_5_0_FN, GPSR5_0, ))
5297 },
5298 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5299 GP_6_31_FN, GPSR6_31,
5300 GP_6_30_FN, GPSR6_30,
5301 GP_6_29_FN, GPSR6_29,
5302 GP_6_28_FN, GPSR6_28,
5303 GP_6_27_FN, GPSR6_27,
5304 GP_6_26_FN, GPSR6_26,
5305 GP_6_25_FN, GPSR6_25,
5306 GP_6_24_FN, GPSR6_24,
5307 GP_6_23_FN, GPSR6_23,
5308 GP_6_22_FN, GPSR6_22,
5309 GP_6_21_FN, GPSR6_21,
5310 GP_6_20_FN, GPSR6_20,
5311 GP_6_19_FN, GPSR6_19,
5312 GP_6_18_FN, GPSR6_18,
5313 GP_6_17_FN, GPSR6_17,
5314 GP_6_16_FN, GPSR6_16,
5315 GP_6_15_FN, GPSR6_15,
5316 GP_6_14_FN, GPSR6_14,
5317 GP_6_13_FN, GPSR6_13,
5318 GP_6_12_FN, GPSR6_12,
5319 GP_6_11_FN, GPSR6_11,
5320 GP_6_10_FN, GPSR6_10,
5321 GP_6_9_FN, GPSR6_9,
5322 GP_6_8_FN, GPSR6_8,
5323 GP_6_7_FN, GPSR6_7,
5324 GP_6_6_FN, GPSR6_6,
5325 GP_6_5_FN, GPSR6_5,
5326 GP_6_4_FN, GPSR6_4,
5327 GP_6_3_FN, GPSR6_3,
5328 GP_6_2_FN, GPSR6_2,
5329 GP_6_1_FN, GPSR6_1,
5330 GP_6_0_FN, GPSR6_0, ))
5331 },
5332 { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5333 GROUP(-28, 1, 1, 1, 1),
5334 GROUP(
5335 /* GP7_31_4 RESERVED */
5336 GP_7_3_FN, GPSR7_3,
5337 GP_7_2_FN, GPSR7_2,
5338 GP_7_1_FN, GPSR7_1,
5339 GP_7_0_FN, GPSR7_0, ))
5340 },
5341 #undef F_
5342 #undef FM
5343
5344 #define F_(x, y) x,
5345 #define FM(x) FN_##x,
5346 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5347 IP0_31_28
5348 IP0_27_24
5349 IP0_23_20
5350 IP0_19_16
5351 IP0_15_12
5352 IP0_11_8
5353 IP0_7_4
5354 IP0_3_0 ))
5355 },
5356 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5357 IP1_31_28
5358 IP1_27_24
5359 IP1_23_20
5360 IP1_19_16
5361 IP1_15_12
5362 IP1_11_8
5363 IP1_7_4
5364 IP1_3_0 ))
5365 },
5366 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5367 IP2_31_28
5368 IP2_27_24
5369 IP2_23_20
5370 IP2_19_16
5371 IP2_15_12
5372 IP2_11_8
5373 IP2_7_4
5374 IP2_3_0 ))
5375 },
5376 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5377 IP3_31_28
5378 IP3_27_24
5379 IP3_23_20
5380 IP3_19_16
5381 IP3_15_12
5382 IP3_11_8
5383 IP3_7_4
5384 IP3_3_0 ))
5385 },
5386 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5387 IP4_31_28
5388 IP4_27_24
5389 IP4_23_20
5390 IP4_19_16
5391 IP4_15_12
5392 IP4_11_8
5393 IP4_7_4
5394 IP4_3_0 ))
5395 },
5396 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5397 IP5_31_28
5398 IP5_27_24
5399 IP5_23_20
5400 IP5_19_16
5401 IP5_15_12
5402 IP5_11_8
5403 IP5_7_4
5404 IP5_3_0 ))
5405 },
5406 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5407 IP6_31_28
5408 IP6_27_24
5409 IP6_23_20
5410 IP6_19_16
5411 IP6_15_12
5412 IP6_11_8
5413 IP6_7_4
5414 IP6_3_0 ))
5415 },
5416 { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5417 GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5418 GROUP(
5419 IP7_31_28
5420 IP7_27_24
5421 IP7_23_20
5422 IP7_19_16
5423 /* IP7_15_12 RESERVED */
5424 IP7_11_8
5425 IP7_7_4
5426 IP7_3_0 ))
5427 },
5428 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5429 IP8_31_28
5430 IP8_27_24
5431 IP8_23_20
5432 IP8_19_16
5433 IP8_15_12
5434 IP8_11_8
5435 IP8_7_4
5436 IP8_3_0 ))
5437 },
5438 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5439 IP9_31_28
5440 IP9_27_24
5441 IP9_23_20
5442 IP9_19_16
5443 IP9_15_12
5444 IP9_11_8
5445 IP9_7_4
5446 IP9_3_0 ))
5447 },
5448 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5449 IP10_31_28
5450 IP10_27_24
5451 IP10_23_20
5452 IP10_19_16
5453 IP10_15_12
5454 IP10_11_8
5455 IP10_7_4
5456 IP10_3_0 ))
5457 },
5458 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5459 IP11_31_28
5460 IP11_27_24
5461 IP11_23_20
5462 IP11_19_16
5463 IP11_15_12
5464 IP11_11_8
5465 IP11_7_4
5466 IP11_3_0 ))
5467 },
5468 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5469 IP12_31_28
5470 IP12_27_24
5471 IP12_23_20
5472 IP12_19_16
5473 IP12_15_12
5474 IP12_11_8
5475 IP12_7_4
5476 IP12_3_0 ))
5477 },
5478 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5479 IP13_31_28
5480 IP13_27_24
5481 IP13_23_20
5482 IP13_19_16
5483 IP13_15_12
5484 IP13_11_8
5485 IP13_7_4
5486 IP13_3_0 ))
5487 },
5488 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5489 IP14_31_28
5490 IP14_27_24
5491 IP14_23_20
5492 IP14_19_16
5493 IP14_15_12
5494 IP14_11_8
5495 IP14_7_4
5496 IP14_3_0 ))
5497 },
5498 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5499 IP15_31_28
5500 IP15_27_24
5501 IP15_23_20
5502 IP15_19_16
5503 IP15_15_12
5504 IP15_11_8
5505 IP15_7_4
5506 IP15_3_0 ))
5507 },
5508 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5509 IP16_31_28
5510 IP16_27_24
5511 IP16_23_20
5512 IP16_19_16
5513 IP16_15_12
5514 IP16_11_8
5515 IP16_7_4
5516 IP16_3_0 ))
5517 },
5518 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5519 IP17_31_28
5520 IP17_27_24
5521 IP17_23_20
5522 IP17_19_16
5523 IP17_15_12
5524 IP17_11_8
5525 IP17_7_4
5526 IP17_3_0 ))
5527 },
5528 { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5529 GROUP(-24, 4, 4),
5530 GROUP(
5531 /* IP18_31_8 RESERVED */
5532 IP18_7_4
5533 IP18_3_0 ))
5534 },
5535 #undef F_
5536 #undef FM
5537
5538 #define F_(x, y) x,
5539 #define FM(x) FN_##x,
5540 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5541 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5542 1, 1, 1, 2, 2, 1, 2, -3),
5543 GROUP(
5544 MOD_SEL0_31_30_29
5545 MOD_SEL0_28_27
5546 MOD_SEL0_26_25_24
5547 MOD_SEL0_23
5548 MOD_SEL0_22
5549 MOD_SEL0_21
5550 MOD_SEL0_20
5551 MOD_SEL0_19
5552 MOD_SEL0_18_17
5553 MOD_SEL0_16
5554 /* RESERVED 15 */
5555 MOD_SEL0_14_13
5556 MOD_SEL0_12
5557 MOD_SEL0_11
5558 MOD_SEL0_10
5559 MOD_SEL0_9_8
5560 MOD_SEL0_7_6
5561 MOD_SEL0_5
5562 MOD_SEL0_4_3
5563 /* RESERVED 2, 1, 0 */ ))
5564 },
5565 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5566 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5567 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
5568 GROUP(
5569 MOD_SEL1_31_30
5570 MOD_SEL1_29_28_27
5571 MOD_SEL1_26
5572 MOD_SEL1_25_24
5573 MOD_SEL1_23_22_21
5574 MOD_SEL1_20
5575 MOD_SEL1_19
5576 MOD_SEL1_18_17
5577 MOD_SEL1_16
5578 MOD_SEL1_15_14
5579 MOD_SEL1_13
5580 MOD_SEL1_12
5581 MOD_SEL1_11
5582 MOD_SEL1_10
5583 MOD_SEL1_9
5584 /* RESERVED 8, 7 */
5585 MOD_SEL1_6
5586 MOD_SEL1_5
5587 MOD_SEL1_4
5588 MOD_SEL1_3
5589 MOD_SEL1_2
5590 MOD_SEL1_1
5591 MOD_SEL1_0 ))
5592 },
5593 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5594 GROUP(1, 1, 1, 2, 1, 3, -1, 1, 1, 1, 1, 1,
5595 -16, 1),
5596 GROUP(
5597 MOD_SEL2_31
5598 MOD_SEL2_30
5599 MOD_SEL2_29
5600 MOD_SEL2_28_27
5601 MOD_SEL2_26
5602 MOD_SEL2_25_24_23
5603 /* RESERVED 22 */
5604 MOD_SEL2_21
5605 MOD_SEL2_20
5606 MOD_SEL2_19
5607 MOD_SEL2_18
5608 MOD_SEL2_17
5609 /* RESERVED 16-1 */
5610 MOD_SEL2_0 ))
5611 },
5612 { /* sentinel */ }
5613 };
5614
5615 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5616 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5617 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5618 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5619 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5620 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5621 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5622 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5623 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5624 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
5625 } },
5626 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5627 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5628 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5629 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5630 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5631 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5632 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5633 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5634 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
5635 } },
5636 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5637 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5638 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5639 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5640 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5641 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5642 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5643 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5644 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
5645 } },
5646 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5647 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5648 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5649 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5650 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5651 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5652 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5653 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5654 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5655 } },
5656 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5657 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5658 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5659 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5660 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5661 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5662 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5663 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5664 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5665 } },
5666 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5667 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5668 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5669 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5670 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5671 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5672 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5673 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5674 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5675 } },
5676 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5677 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5678 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5679 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5680 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5681 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5682 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5683 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5684 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5685 } },
5686 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5687 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5688 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5689 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5690 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5691 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5692 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5693 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5694 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5695 } },
5696 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5697 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5698 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5699 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5700 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5701 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5702 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5703 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5704 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5705 } },
5706 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5707 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5708 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
5709 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5710 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5711 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5712 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5713 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5714 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5715 } },
5716 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5717 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5718 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5719 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5720 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5721 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5722 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5723 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5724 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5725 } },
5726 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5727 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5728 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5729 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5730 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5731 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5732 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5733 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5734 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
5735 } },
5736 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5737 #ifdef CONFIG_PINCTRL_PFC_R8A77951
5738 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5739 #endif
5740 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5741 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
5742 { PIN_TMS, 4, 2 }, /* TMS */
5743 } },
5744 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5745 { PIN_TDO, 28, 2 }, /* TDO */
5746 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5747 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5748 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5749 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5750 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5751 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5752 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5753 } },
5754 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5755 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5756 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5757 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5758 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5759 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5760 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5761 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5762 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5763 } },
5764 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5765 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5766 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5767 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5768 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5769 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5770 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5771 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5772 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5773 } },
5774 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5775 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5776 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5777 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5778 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5779 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5780 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5781 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5782 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5783 } },
5784 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5785 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5786 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5787 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5788 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5789 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5790 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5791 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5792 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5793 } },
5794 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5795 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5796 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5797 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5798 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5799 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5800 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5801 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5802 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5803 } },
5804 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5805 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5806 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5807 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5808 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5809 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5810 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5811 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5812 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5813 } },
5814 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5815 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5816 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5817 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5818 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5819 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5820 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5821 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
5822 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5823 } },
5824 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5825 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5826 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5827 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5828 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5829 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5830 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5831 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5832 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5833 } },
5834 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5835 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5836 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5837 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5838 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5839 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5840 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5841 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5842 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5843 } },
5844 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5845 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5846 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5847 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5848 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5849 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5850 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5851 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5852 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5853 } },
5854 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5855 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5856 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5857 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5858 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5859 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5860 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
5861 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
5862 } },
5863 { /* sentinel */ }
5864 };
5865
5866 enum ioctrl_regs {
5867 POCCTRL,
5868 TDSELCTRL,
5869 };
5870
5871 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5872 [POCCTRL] = { 0xe6060380, },
5873 [TDSELCTRL] = { 0xe60603c0, },
5874 { /* sentinel */ }
5875 };
5876
r8a77951_pin_to_pocctrl(unsigned int pin,u32 * pocctrl)5877 static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
5878 {
5879 int bit = -EINVAL;
5880
5881 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5882
5883 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5884 bit = pin & 0x1f;
5885
5886 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5887 bit = (pin & 0x1f) + 12;
5888
5889 return bit;
5890 }
5891
5892 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5893 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5894 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5895 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5896 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5897 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5898 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5899 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5900 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5901 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5902 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5903 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5904 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5905 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5906 [12] = PIN_RPC_INT_N, /* RPC_INT# */
5907 [13] = PIN_RPC_WP_N, /* RPC_WP# */
5908 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5909 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5910 [16] = PIN_AVB_RXC, /* AVB_RXC */
5911 [17] = PIN_AVB_RD0, /* AVB_RD0 */
5912 [18] = PIN_AVB_RD1, /* AVB_RD1 */
5913 [19] = PIN_AVB_RD2, /* AVB_RD2 */
5914 [20] = PIN_AVB_RD3, /* AVB_RD3 */
5915 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5916 [22] = PIN_AVB_TXC, /* AVB_TXC */
5917 [23] = PIN_AVB_TD0, /* AVB_TD0 */
5918 [24] = PIN_AVB_TD1, /* AVB_TD1 */
5919 [25] = PIN_AVB_TD2, /* AVB_TD2 */
5920 [26] = PIN_AVB_TD3, /* AVB_TD3 */
5921 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5922 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
5923 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5924 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5925 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5926 } },
5927 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5928 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5929 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5930 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5931 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5932 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5933 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5934 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5935 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5936 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5937 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5938 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5939 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5940 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5941 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5942 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5943 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5944 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5945 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5946 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5947 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5948 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5949 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5950 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5951 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5952 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5953 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5954 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5955 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5956 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5957 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5958 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5959 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5960 } },
5961 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5962 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5963 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5964 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5965 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5966 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5967 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5968 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5969 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5970 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5971 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
5972 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5973 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5974 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5975 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5976 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5977 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5978 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5979 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5980 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5981 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5982 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5983 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5984 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5985 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5986 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5987 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5988 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5989 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5990 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
5991 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5992 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
5993 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
5994 } },
5995 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5996 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
5997 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
5998 [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
5999 [ 3] = PIN_EXTALR, /* EXTALR*/
6000 [ 4] = PIN_TRST_N, /* TRST# */
6001 [ 5] = PIN_TCK, /* TCK */
6002 [ 6] = PIN_TMS, /* TMS */
6003 [ 7] = PIN_TDI, /* TDI */
6004 [ 8] = SH_PFC_PIN_NONE,
6005 [ 9] = PIN_ASEBRK, /* ASEBRK */
6006 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6007 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6008 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6009 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6010 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6011 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6012 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6013 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6014 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6015 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6016 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6017 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6018 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6019 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6020 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6021 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6022 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6023 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6024 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6025 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6026 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6027 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6028 } },
6029 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6030 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6031 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6032 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6033 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6034 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6035 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6036 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6037 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6038 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6039 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6040 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6041 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6042 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6043 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6044 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6045 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6046 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6047 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6048 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6049 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6050 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6051 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6052 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6053 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6054 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6055 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6056 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6057 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6058 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6059 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6060 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6061 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6062 } },
6063 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6064 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6065 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6066 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6067 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6068 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6069 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6070 [ 6] = PIN_MLB_REF, /* MLB_REF */
6071 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6072 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6073 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6074 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6075 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6076 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6077 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6078 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6079 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6080 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6081 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6082 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6083 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6084 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6085 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6086 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6087 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6088 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6089 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6090 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6091 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6092 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6093 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6094 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6095 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6096 } },
6097 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6098 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6099 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6100 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6101 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6102 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6103 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6104 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
6105 [ 7] = SH_PFC_PIN_NONE,
6106 [ 8] = SH_PFC_PIN_NONE,
6107 [ 9] = SH_PFC_PIN_NONE,
6108 [10] = SH_PFC_PIN_NONE,
6109 [11] = SH_PFC_PIN_NONE,
6110 [12] = SH_PFC_PIN_NONE,
6111 [13] = SH_PFC_PIN_NONE,
6112 [14] = SH_PFC_PIN_NONE,
6113 [15] = SH_PFC_PIN_NONE,
6114 [16] = SH_PFC_PIN_NONE,
6115 [17] = SH_PFC_PIN_NONE,
6116 [18] = SH_PFC_PIN_NONE,
6117 [19] = SH_PFC_PIN_NONE,
6118 [20] = SH_PFC_PIN_NONE,
6119 [21] = SH_PFC_PIN_NONE,
6120 [22] = SH_PFC_PIN_NONE,
6121 [23] = SH_PFC_PIN_NONE,
6122 [24] = SH_PFC_PIN_NONE,
6123 [25] = SH_PFC_PIN_NONE,
6124 [26] = SH_PFC_PIN_NONE,
6125 [27] = SH_PFC_PIN_NONE,
6126 [28] = SH_PFC_PIN_NONE,
6127 [29] = SH_PFC_PIN_NONE,
6128 [30] = SH_PFC_PIN_NONE,
6129 [31] = SH_PFC_PIN_NONE,
6130 } },
6131 { /* sentinel */ }
6132 };
6133
6134 static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
6135 .pin_to_pocctrl = r8a77951_pin_to_pocctrl,
6136 .get_bias = rcar_pinmux_get_bias,
6137 .set_bias = rcar_pinmux_set_bias,
6138 };
6139
6140 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
6141 const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
6142 .name = "r8a774e1_pfc",
6143 .ops = &r8a77951_pfc_ops,
6144 .unlock_reg = 0xe6060000, /* PMMR */
6145
6146 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6147
6148 .pins = pinmux_pins,
6149 .nr_pins = ARRAY_SIZE(pinmux_pins),
6150 .groups = pinmux_groups.common,
6151 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6152 .functions = pinmux_functions.common,
6153 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6154
6155 .cfg_regs = pinmux_config_regs,
6156 .drive_regs = pinmux_drive_regs,
6157 .bias_regs = pinmux_bias_regs,
6158 .ioctrl_regs = pinmux_ioctrl_regs,
6159
6160 .pinmux_data = pinmux_data,
6161 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6162 };
6163 #endif
6164
6165 #ifdef CONFIG_PINCTRL_PFC_R8A77951
6166 const struct sh_pfc_soc_info r8a77951_pinmux_info = {
6167 .name = "r8a77951_pfc",
6168 .ops = &r8a77951_pfc_ops,
6169 .unlock_reg = 0xe6060000, /* PMMR */
6170
6171 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6172
6173 .pins = pinmux_pins,
6174 .nr_pins = ARRAY_SIZE(pinmux_pins),
6175 .groups = pinmux_groups.common,
6176 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6177 ARRAY_SIZE(pinmux_groups.automotive),
6178 .functions = pinmux_functions.common,
6179 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6180 ARRAY_SIZE(pinmux_functions.automotive),
6181
6182 .cfg_regs = pinmux_config_regs,
6183 .drive_regs = pinmux_drive_regs,
6184 .bias_regs = pinmux_bias_regs,
6185 .ioctrl_regs = pinmux_ioctrl_regs,
6186
6187 .pinmux_data = pinmux_data,
6188 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6189 };
6190 #endif
6191