1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "basics/conversion.h"
35 #include "dcn31_resource.h"
36
37 #include "dcn20/dcn20_resource.h"
38 #include "dcn30/dcn30_resource.h"
39
40 #include "dml/dcn30/dcn30_fpu.h"
41
42 #include "dcn10/dcn10_ipp.h"
43 #include "dcn30/dcn30_hubbub.h"
44 #include "dcn31/dcn31_hubbub.h"
45 #include "dcn30/dcn30_mpc.h"
46 #include "dcn31/dcn31_hubp.h"
47 #include "irq/dcn31/irq_service_dcn31.h"
48 #include "dcn30/dcn30_dpp.h"
49 #include "dcn31/dcn31_optc.h"
50 #include "dcn20/dcn20_hwseq.h"
51 #include "dcn30/dcn30_hwseq.h"
52 #include "dce110/dce110_hwseq.h"
53 #include "dcn30/dcn30_opp.h"
54 #include "dcn20/dcn20_dsc.h"
55 #include "dcn30/dcn30_vpg.h"
56 #include "dcn30/dcn30_afmt.h"
57 #include "dcn30/dcn30_dio_stream_encoder.h"
58 #include "dcn30/dcn30_hpo_frl_stream_encoder.h"
59 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
62 #include "dcn31/dcn31_apg.h"
63 #include "dcn31/dcn31_dio_link_encoder.h"
64 #include "dcn31/dcn31_vpg.h"
65 #include "dcn31/dcn31_afmt.h"
66 #include "dce/dce_clock_source.h"
67 #include "dce/dce_audio.h"
68 #include "dce/dce_hwseq.h"
69 #include "clk_mgr.h"
70 #include "dio/dcn10/dcn10_dio.h"
71 #include "dio/virtual/virtual_stream_encoder.h"
72 #include "dce110/dce110_resource.h"
73 #include "dml/display_mode_vba.h"
74 #include "dml/dcn31/dcn31_fpu.h"
75 #include "dcn31/dcn31_dccg.h"
76 #include "dcn10/dcn10_resource.h"
77 #include "dcn31/dcn31_panel_cntl.h"
78
79 #include "dcn30/dcn30_dwb.h"
80 #include "dcn30/dcn30_mmhubbub.h"
81
82 #include "yellow_carp_offset.h"
83 #include "dcn/dcn_3_1_2_offset.h"
84 #include "dcn/dcn_3_1_2_sh_mask.h"
85 #include "nbio/nbio_7_2_0_offset.h"
86 #include "dpcs/dpcs_4_2_0_offset.h"
87 #include "dpcs/dpcs_4_2_0_sh_mask.h"
88 #include "mmhub/mmhub_2_3_0_offset.h"
89 #include "mmhub/mmhub_2_3_0_sh_mask.h"
90
91
92 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
93 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
94 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
95 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
96
97 #include "reg_helper.h"
98 #include "dce/dmub_abm.h"
99 #include "dce/dmub_psr.h"
100 #include "dce/dce_aux.h"
101 #include "dce/dce_i2c.h"
102 #include "dce/dmub_replay.h"
103
104 #include "dml/dcn30/display_mode_vba_30.h"
105 #include "vm_helper.h"
106 #include "dcn20/dcn20_vmid.h"
107
108 #include "link_enc_cfg.h"
109
110 #define DC_LOGGER \
111 dc->ctx->logger
112 #define DC_LOGGER_INIT(logger)
113
114 enum dcn31_clk_src_array_id {
115 DCN31_CLK_SRC_PLL0,
116 DCN31_CLK_SRC_PLL1,
117 DCN31_CLK_SRC_PLL2,
118 DCN31_CLK_SRC_PLL3,
119 DCN31_CLK_SRC_PLL4,
120 DCN30_CLK_SRC_TOTAL
121 };
122
123 /* begin *********************
124 * macros to expend register list macro defined in HW object header file
125 */
126
127 /* DCN */
128 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
129
130 #define BASE(seg) BASE_INNER(seg)
131
132 #define SR(reg_name)\
133 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
134 reg ## reg_name
135
136 #define SRI(reg_name, block, id)\
137 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138 reg ## block ## id ## _ ## reg_name
139
140 #define SRI2(reg_name, block, id)\
141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
142 reg ## reg_name
143
144 #define SRIR(var_name, reg_name, block, id)\
145 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 reg ## block ## id ## _ ## reg_name
147
148 #define SRII(reg_name, block, id)\
149 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 reg ## block ## id ## _ ## reg_name
151
152 #define SRII_MPC_RMU(reg_name, block, id)\
153 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
155
156 #define SRII_DWB(reg_name, temp_name, block, id)\
157 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## temp_name
159
160 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
161 .field_name = reg_name ## __ ## field_name ## post_fix
162
163 #define DCCG_SRII(reg_name, block, id)\
164 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 reg ## block ## id ## _ ## reg_name
166
167 #define VUPDATE_SRII(reg_name, block, id)\
168 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
169 reg ## reg_name ## _ ## block ## id
170
171 /* NBIO */
172 #define NBIO_BASE_INNER(seg) \
173 NBIO_BASE__INST0_SEG ## seg
174
175 #define NBIO_BASE(seg) \
176 NBIO_BASE_INNER(seg)
177
178 #define NBIO_SR(reg_name)\
179 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
180 regBIF_BX1_ ## reg_name
181
182 /* MMHUB */
183 #define MMHUB_BASE_INNER(seg) \
184 MMHUB_BASE__INST0_SEG ## seg
185
186 #define MMHUB_BASE(seg) \
187 MMHUB_BASE_INNER(seg)
188
189 #define MMHUB_SR(reg_name)\
190 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
191 mm ## reg_name
192
193 /* CLOCK */
194 #define CLK_BASE_INNER(seg) \
195 CLK_BASE__INST0_SEG ## seg
196
197 #define CLK_BASE(seg) \
198 CLK_BASE_INNER(seg)
199
200 #define CLK_SRI(reg_name, block, inst)\
201 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
202 reg ## block ## _ ## inst ## _ ## reg_name
203
204
205 static const struct bios_registers bios_regs = {
206 NBIO_SR(BIOS_SCRATCH_3),
207 NBIO_SR(BIOS_SCRATCH_6)
208 };
209
210 #define clk_src_regs(index, pllid)\
211 [index] = {\
212 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
213 }
214
215 static const struct dce110_clk_src_regs clk_src_regs[] = {
216 clk_src_regs(0, A),
217 clk_src_regs(1, B),
218 clk_src_regs(2, C),
219 clk_src_regs(3, D),
220 clk_src_regs(4, E)
221 };
222 /*pll_id being rempped in dmub, in driver it is logical instance*/
223 static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
224 clk_src_regs(0, A),
225 clk_src_regs(1, B),
226 clk_src_regs(2, F),
227 clk_src_regs(3, G),
228 clk_src_regs(4, E)
229 };
230
231 static const struct dce110_clk_src_shift cs_shift = {
232 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
233 };
234
235 static const struct dce110_clk_src_mask cs_mask = {
236 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
237 };
238
239 #define abm_regs(id)\
240 [id] = {\
241 ABM_DCN302_REG_LIST(id)\
242 }
243
244 static const struct dce_abm_registers abm_regs[] = {
245 abm_regs(0),
246 abm_regs(1),
247 abm_regs(2),
248 abm_regs(3),
249 };
250
251 static const struct dce_abm_shift abm_shift = {
252 ABM_MASK_SH_LIST_DCN30(__SHIFT)
253 };
254
255 static const struct dce_abm_mask abm_mask = {
256 ABM_MASK_SH_LIST_DCN30(_MASK)
257 };
258
259 #define audio_regs(id)\
260 [id] = {\
261 AUD_COMMON_REG_LIST(id)\
262 }
263
264 static const struct dce_audio_registers audio_regs[] = {
265 audio_regs(0),
266 audio_regs(1),
267 audio_regs(2),
268 audio_regs(3),
269 audio_regs(4),
270 audio_regs(5),
271 audio_regs(6)
272 };
273
274 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
275 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
276 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
277 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
278
279 static const struct dce_audio_shift audio_shift = {
280 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
281 };
282
283 static const struct dce_audio_mask audio_mask = {
284 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
285 };
286
287 #define vpg_regs(id)\
288 [id] = {\
289 VPG_DCN31_REG_LIST(id)\
290 }
291
292 static const struct dcn31_vpg_registers vpg_regs[] = {
293 vpg_regs(0),
294 vpg_regs(1),
295 vpg_regs(2),
296 vpg_regs(3),
297 vpg_regs(4),
298 vpg_regs(5),
299 vpg_regs(6),
300 vpg_regs(7),
301 vpg_regs(8),
302 vpg_regs(9),
303 };
304
305 static const struct dcn31_vpg_shift vpg_shift = {
306 DCN31_VPG_MASK_SH_LIST(__SHIFT)
307 };
308
309 static const struct dcn31_vpg_mask vpg_mask = {
310 DCN31_VPG_MASK_SH_LIST(_MASK)
311 };
312
313 #define afmt_regs(id)\
314 [id] = {\
315 AFMT_DCN31_REG_LIST(id)\
316 }
317
318 static const struct dcn31_afmt_registers afmt_regs[] = {
319 afmt_regs(0),
320 afmt_regs(1),
321 afmt_regs(2),
322 afmt_regs(3),
323 afmt_regs(4),
324 afmt_regs(5)
325 };
326
327 static const struct dcn31_afmt_shift afmt_shift = {
328 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
329 };
330
331 static const struct dcn31_afmt_mask afmt_mask = {
332 DCN31_AFMT_MASK_SH_LIST(_MASK)
333 };
334
335 #define apg_regs(id)\
336 [id] = {\
337 APG_DCN31_REG_LIST(id)\
338 }
339
340 static const struct dcn31_apg_registers apg_regs[] = {
341 apg_regs(0),
342 apg_regs(1),
343 apg_regs(2),
344 apg_regs(3)
345 };
346
347 static const struct dcn31_apg_shift apg_shift = {
348 DCN31_APG_MASK_SH_LIST(__SHIFT)
349 };
350
351 static const struct dcn31_apg_mask apg_mask = {
352 DCN31_APG_MASK_SH_LIST(_MASK)
353 };
354
355 #define stream_enc_regs(id)\
356 [id] = {\
357 SE_DCN3_REG_LIST(id)\
358 }
359
360 /* Some encoders won't be initialized here - but they're logical, not physical. */
361 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
362 stream_enc_regs(0),
363 stream_enc_regs(1),
364 stream_enc_regs(2),
365 stream_enc_regs(3),
366 stream_enc_regs(4)
367 };
368
369 static const struct dcn10_stream_encoder_shift se_shift = {
370 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
371 };
372
373 static const struct dcn10_stream_encoder_mask se_mask = {
374 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
375 };
376
377
378 #define aux_regs(id)\
379 [id] = {\
380 DCN2_AUX_REG_LIST(id)\
381 }
382
383 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
384 aux_regs(0),
385 aux_regs(1),
386 aux_regs(2),
387 aux_regs(3),
388 aux_regs(4)
389 };
390
391 #define hpd_regs(id)\
392 [id] = {\
393 HPD_REG_LIST(id)\
394 }
395
396 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
397 hpd_regs(0),
398 hpd_regs(1),
399 hpd_regs(2),
400 hpd_regs(3),
401 hpd_regs(4)
402 };
403
404 #define link_regs(id, phyid)\
405 [id] = {\
406 LE_DCN31_REG_LIST(id), \
407 UNIPHY_DCN2_REG_LIST(phyid), \
408 DPCS_DCN31_REG_LIST(id), \
409 }
410
411 static const struct dce110_aux_registers_shift aux_shift = {
412 DCN_AUX_MASK_SH_LIST(__SHIFT)
413 };
414
415 static const struct dce110_aux_registers_mask aux_mask = {
416 DCN_AUX_MASK_SH_LIST(_MASK)
417 };
418
419 static const struct dcn10_link_enc_registers link_enc_regs[] = {
420 link_regs(0, A),
421 link_regs(1, B),
422 link_regs(2, C),
423 link_regs(3, D),
424 link_regs(4, E)
425 };
426
427 static const struct dcn10_link_enc_shift le_shift = {
428 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
429 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
430 };
431
432 static const struct dcn10_link_enc_mask le_mask = {
433 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
434 DPCS_DCN31_MASK_SH_LIST(_MASK)
435 };
436
437 #define hpo_frl_stream_encoder_reg_list(id)\
438 [id] = {\
439 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST(id)\
440 }
441
442 #define hpo_frl_stream_encoder_dme_reg_list(id)\
443 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST(id, 6)
444
445
446 static const struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[] = {
447 hpo_frl_stream_encoder_reg_list(0),
448 hpo_frl_stream_encoder_dme_reg_list(6),
449 };
450
451 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = {
452 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
453 };
454
455 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = {
456 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
457 };
458
459 #define hpo_frl_link_encoder_reg_list(id)\
460 [id] = {\
461 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST(id)\
462 }
463
464 static const struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[] = {
465 hpo_frl_link_encoder_reg_list(0),
466 };
467
468 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
469 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
470 };
471
472 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
473 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
474 };
475
476 #define hpo_dp_stream_encoder_reg_list(id)\
477 [id] = {\
478 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
479 }
480
481 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
482 hpo_dp_stream_encoder_reg_list(0),
483 hpo_dp_stream_encoder_reg_list(1),
484 hpo_dp_stream_encoder_reg_list(2),
485 hpo_dp_stream_encoder_reg_list(3),
486 };
487
488 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
489 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
490 };
491
492 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
493 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
494 };
495
496 #define hpo_dp_link_encoder_reg_list(id)\
497 [id] = {\
498 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
499 DCN3_1_RDPCSTX_REG_LIST(0),\
500 DCN3_1_RDPCSTX_REG_LIST(1),\
501 DCN3_1_RDPCSTX_REG_LIST(2),\
502 DCN3_1_RDPCSTX_REG_LIST(3),\
503 DCN3_1_RDPCSTX_REG_LIST(4)\
504 }
505
506 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
507 hpo_dp_link_encoder_reg_list(0),
508 hpo_dp_link_encoder_reg_list(1),
509 };
510
511 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
512 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
513 };
514
515 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
516 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
517 };
518
519 #define dpp_regs(id)\
520 [id] = {\
521 DPP_REG_LIST_DCN30(id),\
522 }
523
524 static const struct dcn3_dpp_registers dpp_regs[] = {
525 dpp_regs(0),
526 dpp_regs(1),
527 dpp_regs(2),
528 dpp_regs(3)
529 };
530
531 static const struct dcn3_dpp_shift tf_shift = {
532 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
533 };
534
535 static const struct dcn3_dpp_mask tf_mask = {
536 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
537 };
538
539 #define opp_regs(id)\
540 [id] = {\
541 OPP_REG_LIST_DCN30(id),\
542 }
543
544 static const struct dcn20_opp_registers opp_regs[] = {
545 opp_regs(0),
546 opp_regs(1),
547 opp_regs(2),
548 opp_regs(3)
549 };
550
551 static const struct dcn20_opp_shift opp_shift = {
552 OPP_MASK_SH_LIST_DCN20(__SHIFT)
553 };
554
555 static const struct dcn20_opp_mask opp_mask = {
556 OPP_MASK_SH_LIST_DCN20(_MASK)
557 };
558
559 #define aux_engine_regs(id)\
560 [id] = {\
561 AUX_COMMON_REG_LIST0(id), \
562 .AUXN_IMPCAL = 0, \
563 .AUXP_IMPCAL = 0, \
564 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
565 }
566
567 static const struct dce110_aux_registers aux_engine_regs[] = {
568 aux_engine_regs(0),
569 aux_engine_regs(1),
570 aux_engine_regs(2),
571 aux_engine_regs(3),
572 aux_engine_regs(4)
573 };
574
575 #define dwbc_regs_dcn3(id)\
576 [id] = {\
577 DWBC_COMMON_REG_LIST_DCN30(id),\
578 }
579
580 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
581 dwbc_regs_dcn3(0),
582 };
583
584 static const struct dcn30_dwbc_shift dwbc30_shift = {
585 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
586 };
587
588 static const struct dcn30_dwbc_mask dwbc30_mask = {
589 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
590 };
591
592 #define mcif_wb_regs_dcn3(id)\
593 [id] = {\
594 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
595 }
596
597 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
598 mcif_wb_regs_dcn3(0)
599 };
600
601 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
602 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
603 };
604
605 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
606 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
607 };
608
609 #define dsc_regsDCN20(id)\
610 [id] = {\
611 DSC_REG_LIST_DCN20(id)\
612 }
613
614 static const struct dcn20_dsc_registers dsc_regs[] = {
615 dsc_regsDCN20(0),
616 dsc_regsDCN20(1),
617 dsc_regsDCN20(2)
618 };
619
620 static const struct dcn20_dsc_shift dsc_shift = {
621 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
622 };
623
624 static const struct dcn20_dsc_mask dsc_mask = {
625 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
626 };
627
628 static const struct dcn30_mpc_registers mpc_regs = {
629 MPC_REG_LIST_DCN3_0(0),
630 MPC_REG_LIST_DCN3_0(1),
631 MPC_REG_LIST_DCN3_0(2),
632 MPC_REG_LIST_DCN3_0(3),
633 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
634 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
635 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
636 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
637 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
638 MPC_RMU_REG_LIST_DCN3AG(0),
639 MPC_RMU_REG_LIST_DCN3AG(1),
640 //MPC_RMU_REG_LIST_DCN3AG(2),
641 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
642 };
643
644 static const struct dcn30_mpc_shift mpc_shift = {
645 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
646 };
647
648 static const struct dcn30_mpc_mask mpc_mask = {
649 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
650 };
651
652 #define optc_regs(id)\
653 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
654
655 static const struct dcn_optc_registers optc_regs[] = {
656 optc_regs(0),
657 optc_regs(1),
658 optc_regs(2),
659 optc_regs(3)
660 };
661
662 static const struct dcn_optc_shift optc_shift = {
663 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
664 };
665
666 static const struct dcn_optc_mask optc_mask = {
667 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
668 };
669
670 #define hubp_regs(id)\
671 [id] = {\
672 HUBP_REG_LIST_DCN30(id)\
673 }
674
675 static const struct dcn_hubp2_registers hubp_regs[] = {
676 hubp_regs(0),
677 hubp_regs(1),
678 hubp_regs(2),
679 hubp_regs(3)
680 };
681
682
683 static const struct dcn_hubp2_shift hubp_shift = {
684 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
685 };
686
687 static const struct dcn_hubp2_mask hubp_mask = {
688 HUBP_MASK_SH_LIST_DCN31(_MASK)
689 };
690 static const struct dcn_hubbub_registers hubbub_reg = {
691 HUBBUB_REG_LIST_DCN31(0)
692 };
693
694 static const struct dcn_hubbub_shift hubbub_shift = {
695 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
696 };
697
698 static const struct dcn_hubbub_mask hubbub_mask = {
699 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
700 };
701
702 static const struct dccg_registers dccg_regs = {
703 DCCG_REG_LIST_DCN31()
704 };
705
706 static const struct dccg_shift dccg_shift = {
707 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
708 };
709
710 static const struct dccg_mask dccg_mask = {
711 DCCG_MASK_SH_LIST_DCN31(_MASK)
712 };
713
714
715 #define SRII2(reg_name_pre, reg_name_post, id)\
716 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
717 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
718 reg ## reg_name_pre ## id ## _ ## reg_name_post
719
720
721 #define HWSEQ_DCN31_REG_LIST()\
722 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
723 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
724 SR(DIO_MEM_PWR_CTRL), \
725 SR(ODM_MEM_PWR_CTRL3), \
726 SR(DMU_MEM_PWR_CNTL), \
727 SR(MMHUBBUB_MEM_PWR_CNTL), \
728 SR(DCCG_GATE_DISABLE_CNTL), \
729 SR(DCCG_GATE_DISABLE_CNTL2), \
730 SR(DCFCLK_CNTL),\
731 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
732 SRII(PIXEL_RATE_CNTL, OTG, 0), \
733 SRII(PIXEL_RATE_CNTL, OTG, 1),\
734 SRII(PIXEL_RATE_CNTL, OTG, 2),\
735 SRII(PIXEL_RATE_CNTL, OTG, 3),\
736 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
737 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
738 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
739 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
740 SR(MICROSECOND_TIME_BASE_DIV), \
741 SR(MILLISECOND_TIME_BASE_DIV), \
742 SR(DISPCLK_FREQ_CHANGE_CNTL), \
743 SR(RBBMIF_TIMEOUT_DIS), \
744 SR(RBBMIF_TIMEOUT_DIS_2), \
745 SR(DCHUBBUB_CRC_CTRL), \
746 SR(DPP_TOP0_DPP_CRC_CTRL), \
747 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
748 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
749 SR(MPC_CRC_CTRL), \
750 SR(MPC_CRC_RESULT_GB), \
751 SR(MPC_CRC_RESULT_C), \
752 SR(MPC_CRC_RESULT_AR), \
753 SR(DOMAIN0_PG_CONFIG), \
754 SR(DOMAIN1_PG_CONFIG), \
755 SR(DOMAIN2_PG_CONFIG), \
756 SR(DOMAIN3_PG_CONFIG), \
757 SR(DOMAIN16_PG_CONFIG), \
758 SR(DOMAIN17_PG_CONFIG), \
759 SR(DOMAIN18_PG_CONFIG), \
760 SR(DOMAIN0_PG_STATUS), \
761 SR(DOMAIN1_PG_STATUS), \
762 SR(DOMAIN2_PG_STATUS), \
763 SR(DOMAIN3_PG_STATUS), \
764 SR(DOMAIN16_PG_STATUS), \
765 SR(DOMAIN17_PG_STATUS), \
766 SR(DOMAIN18_PG_STATUS), \
767 SR(D1VGA_CONTROL), \
768 SR(D2VGA_CONTROL), \
769 SR(D3VGA_CONTROL), \
770 SR(D4VGA_CONTROL), \
771 SR(D5VGA_CONTROL), \
772 SR(D6VGA_CONTROL), \
773 SR(DC_IP_REQUEST_CNTL), \
774 SR(AZALIA_AUDIO_DTO), \
775 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
776 SR(HPO_TOP_HW_CONTROL)
777
778 static const struct dce_hwseq_registers hwseq_reg = {
779 HWSEQ_DCN31_REG_LIST()
780 };
781
782 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
783 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
784 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
785 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
786 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
787 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
788 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
789 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
790 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
791 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
792 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
793 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
794 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
795 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
796 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
797 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
798 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
799 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
800 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
801 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
802 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
803 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
804 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
805 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
806 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
807 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
808 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
809 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
810 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
811 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
812 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
813 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
814 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
815 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
816
817 static const struct dce_hwseq_shift hwseq_shift = {
818 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
819 };
820
821 static const struct dce_hwseq_mask hwseq_mask = {
822 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
823 };
824 #define vmid_regs(id)\
825 [id] = {\
826 DCN20_VMID_REG_LIST(id)\
827 }
828
829 static const struct dcn_vmid_registers vmid_regs[] = {
830 vmid_regs(0),
831 vmid_regs(1),
832 vmid_regs(2),
833 vmid_regs(3),
834 vmid_regs(4),
835 vmid_regs(5),
836 vmid_regs(6),
837 vmid_regs(7),
838 vmid_regs(8),
839 vmid_regs(9),
840 vmid_regs(10),
841 vmid_regs(11),
842 vmid_regs(12),
843 vmid_regs(13),
844 vmid_regs(14),
845 vmid_regs(15)
846 };
847
848 static const struct dcn20_vmid_shift vmid_shifts = {
849 DCN20_VMID_MASK_SH_LIST(__SHIFT)
850 };
851
852 static const struct dcn20_vmid_mask vmid_masks = {
853 DCN20_VMID_MASK_SH_LIST(_MASK)
854 };
855
856 static const struct dcn_dio_registers dio_regs = {
857 DIO_REG_LIST_DCN10()
858 };
859
860 #define DIO_MASK_SH_LIST(mask_sh)\
861 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
862
863 static const struct dcn_dio_shift dio_shift = {
864 DIO_MASK_SH_LIST(__SHIFT)
865 };
866
867 static const struct dcn_dio_mask dio_mask = {
868 DIO_MASK_SH_LIST(_MASK)
869 };
870
871 static const struct resource_caps res_cap_dcn31 = {
872 .num_timing_generator = 4,
873 .num_opp = 4,
874 .num_video_plane = 4,
875 .num_audio = 5,
876 .num_stream_encoder = 5,
877 .num_dig_link_enc = 5,
878 .num_hpo_frl = 1,
879 .num_hpo_dp_stream_encoder = 4,
880 .num_hpo_dp_link_encoder = 2,
881 .num_pll = 5,
882 .num_dwb = 1,
883 .num_ddc = 5,
884 .num_vmid = 16,
885 .num_mpc_3dlut = 2,
886 .num_dsc = 3,
887 };
888
889 static const struct dc_plane_cap plane_cap = {
890 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
891 .per_pixel_alpha = true,
892
893 .pixel_format_support = {
894 .argb8888 = true,
895 .nv12 = true,
896 .fp16 = true,
897 .p010 = true,
898 .ayuv = false,
899 },
900
901 .max_upscale_factor = {
902 .argb8888 = 16000,
903 .nv12 = 16000,
904 .fp16 = 16000
905 },
906
907 // 6:1 downscaling ratio: 1000/6 = 166.666
908 .max_downscale_factor = {
909 .argb8888 = 167,
910 .nv12 = 167,
911 .fp16 = 167
912 },
913 64,
914 64
915 };
916
917 static const struct dc_debug_options debug_defaults_drv = {
918 .limit_ffe = 3,
919 .disable_dmcu = true,
920 .force_abm_enable = false,
921 .clock_trace = true,
922 .disable_pplib_clock_request = false,
923 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
924 .force_single_disp_pipe_split = false,
925 .disable_dcc = DCC_ENABLE,
926 .vsr_support = true,
927 .performance_trace = false,
928 .max_downscale_src_width = 4096,/*upto true 4K*/
929 .disable_pplib_wm_range = false,
930 .scl_reset_length10 = true,
931 .sanity_checks = false,
932 .underflow_assert_delay_us = 0xFFFFFFFF,
933 .dwb_fi_phase = -1, // -1 = disable,
934 .dmub_command_table = true,
935 .pstate_enabled = true,
936 .use_max_lb = true,
937 .enable_mem_low_power = {
938 .bits = {
939 .vga = true,
940 .i2c = true,
941 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
942 .dscl = true,
943 .cm = true,
944 .mpc = true,
945 .optc = true,
946 .vpg = true,
947 .afmt = true,
948 }
949 },
950 .disable_z10 = true,
951 .max_frl_rate = HDMI_FRL_LINK_RATE_10GBPS,
952 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
953 .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
954 .using_dml2 = false,
955 };
956
957 static const struct dc_check_config config_defaults = {
958 .enable_legacy_fast_update = true,
959 };
960
961 static const struct dc_panel_config panel_config_defaults = {
962 .psr = {
963 .disable_psr = false,
964 .disallow_psrsu = false,
965 .disallow_replay = false,
966 },
967 .ilr = {
968 .optimize_edp_link_rate = true,
969 },
970 };
971
dcn31_dpp_destroy(struct dpp ** dpp)972 static void dcn31_dpp_destroy(struct dpp **dpp)
973 {
974 kfree(TO_DCN20_DPP(*dpp));
975 *dpp = NULL;
976 }
977
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)978 static struct dpp *dcn31_dpp_create(
979 struct dc_context *ctx,
980 uint32_t inst)
981 {
982 struct dcn3_dpp *dpp =
983 kzalloc_obj(struct dcn3_dpp);
984
985 if (!dpp)
986 return NULL;
987
988 if (dpp3_construct(dpp, ctx, inst,
989 &dpp_regs[inst], &tf_shift, &tf_mask))
990 return &dpp->base;
991
992 BREAK_TO_DEBUGGER();
993 kfree(dpp);
994 return NULL;
995 }
996
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)997 static struct output_pixel_processor *dcn31_opp_create(
998 struct dc_context *ctx, uint32_t inst)
999 {
1000 struct dcn20_opp *opp =
1001 kzalloc_obj(struct dcn20_opp);
1002
1003 if (!opp) {
1004 BREAK_TO_DEBUGGER();
1005 return NULL;
1006 }
1007
1008 dcn20_opp_construct(opp, ctx, inst,
1009 &opp_regs[inst], &opp_shift, &opp_mask);
1010 return &opp->base;
1011 }
1012
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)1013 static struct dce_aux *dcn31_aux_engine_create(
1014 struct dc_context *ctx,
1015 uint32_t inst)
1016 {
1017 struct aux_engine_dce110 *aux_engine =
1018 kzalloc_obj(struct aux_engine_dce110);
1019
1020 if (!aux_engine)
1021 return NULL;
1022
1023 dce110_aux_engine_construct(aux_engine, ctx, inst,
1024 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1025 &aux_engine_regs[inst],
1026 &aux_mask,
1027 &aux_shift,
1028 ctx->dc->caps.extended_aux_timeout_support);
1029
1030 return &aux_engine->base;
1031 }
1032 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1033
1034 static const struct dce_i2c_registers i2c_hw_regs[] = {
1035 i2c_inst_regs(1),
1036 i2c_inst_regs(2),
1037 i2c_inst_regs(3),
1038 i2c_inst_regs(4),
1039 i2c_inst_regs(5),
1040 };
1041
1042 static const struct dce_i2c_shift i2c_shifts = {
1043 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1044 };
1045
1046 static const struct dce_i2c_mask i2c_masks = {
1047 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1048 };
1049
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)1050 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1051 struct dc_context *ctx,
1052 uint32_t inst)
1053 {
1054 struct dce_i2c_hw *dce_i2c_hw =
1055 kzalloc_obj(struct dce_i2c_hw);
1056
1057 if (!dce_i2c_hw)
1058 return NULL;
1059
1060 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1061 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1062
1063 return dce_i2c_hw;
1064 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1065 static struct mpc *dcn31_mpc_create(
1066 struct dc_context *ctx,
1067 int num_mpcc,
1068 int num_rmu)
1069 {
1070 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
1071
1072 if (!mpc30)
1073 return NULL;
1074
1075 dcn30_mpc_construct(mpc30, ctx,
1076 &mpc_regs,
1077 &mpc_shift,
1078 &mpc_mask,
1079 num_mpcc,
1080 num_rmu);
1081
1082 return &mpc30->base;
1083 }
1084
dcn31_dio_create(struct dc_context * ctx)1085 static struct dio *dcn31_dio_create(struct dc_context *ctx)
1086 {
1087 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
1088
1089 if (!dio10)
1090 return NULL;
1091
1092 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
1093
1094 return &dio10->base;
1095 }
1096
dcn31_hubbub_create(struct dc_context * ctx)1097 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1098 {
1099 int i;
1100
1101 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
1102
1103 if (!hubbub3)
1104 return NULL;
1105
1106 hubbub31_construct(hubbub3, ctx,
1107 &hubbub_reg,
1108 &hubbub_shift,
1109 &hubbub_mask,
1110 dcn3_1_ip.det_buffer_size_kbytes,
1111 dcn3_1_ip.pixel_chunk_size_kbytes,
1112 dcn3_1_ip.config_return_buffer_size_in_kbytes);
1113
1114
1115 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1116 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1117
1118 vmid->ctx = ctx;
1119
1120 vmid->regs = &vmid_regs[i];
1121 vmid->shifts = &vmid_shifts;
1122 vmid->masks = &vmid_masks;
1123 }
1124
1125 return &hubbub3->base;
1126 }
1127
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1128 static struct timing_generator *dcn31_timing_generator_create(
1129 struct dc_context *ctx,
1130 uint32_t instance)
1131 {
1132 struct optc *tgn10 =
1133 kzalloc_obj(struct optc);
1134
1135 if (!tgn10)
1136 return NULL;
1137
1138 tgn10->base.inst = instance;
1139 tgn10->base.ctx = ctx;
1140
1141 tgn10->tg_regs = &optc_regs[instance];
1142 tgn10->tg_shift = &optc_shift;
1143 tgn10->tg_mask = &optc_mask;
1144
1145 dcn31_timing_generator_init(tgn10);
1146
1147 return &tgn10->base;
1148 }
1149
1150 static const struct encoder_feature_support link_enc_feature = {
1151 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1152 .max_hdmi_pixel_clock = 600000,
1153 .hdmi_ycbcr420_supported = true,
1154 .dp_ycbcr420_supported = true,
1155 .fec_supported = true,
1156 .flags.bits.IS_HBR2_CAPABLE = true,
1157 .flags.bits.IS_HBR3_CAPABLE = true,
1158 .flags.bits.IS_TPS3_CAPABLE = true,
1159 .flags.bits.IS_TPS4_CAPABLE = true
1160 };
1161
dcn31_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1162 static struct link_encoder *dcn31_link_encoder_create(
1163 struct dc_context *ctx,
1164 const struct encoder_init_data *enc_init_data)
1165 {
1166 (void)ctx;
1167 struct dcn20_link_encoder *enc20 =
1168 kzalloc_obj(struct dcn20_link_encoder);
1169
1170 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1171 return NULL;
1172
1173 dcn31_link_encoder_construct(enc20,
1174 enc_init_data,
1175 &link_enc_feature,
1176 &link_enc_regs[enc_init_data->transmitter],
1177 &link_enc_aux_regs[enc_init_data->channel - 1],
1178 &link_enc_hpd_regs[enc_init_data->hpd_source],
1179 &le_shift,
1180 &le_mask);
1181
1182 return &enc20->enc10.base;
1183 }
1184
1185 /* Create a minimal link encoder object not associated with a particular
1186 * physical connector.
1187 * resource_funcs.link_enc_create_minimal
1188 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1189 static struct link_encoder *dcn31_link_enc_create_minimal(
1190 struct dc_context *ctx, enum engine_id eng_id)
1191 {
1192 struct dcn20_link_encoder *enc20;
1193
1194 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc)
1195 return NULL;
1196
1197 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1198 if (!enc20)
1199 return NULL;
1200
1201 dcn31_link_encoder_construct_minimal(
1202 enc20,
1203 ctx,
1204 &link_enc_feature,
1205 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1206 &le_shift,
1207 &le_mask,
1208 eng_id);
1209
1210 return &enc20->enc10.base;
1211 }
1212
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1213 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1214 {
1215 struct dcn31_panel_cntl *panel_cntl =
1216 kzalloc_obj(struct dcn31_panel_cntl);
1217
1218 if (!panel_cntl)
1219 return NULL;
1220
1221 dcn31_panel_cntl_construct(panel_cntl, init_data);
1222
1223 return &panel_cntl->base;
1224 }
1225
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1226 static void read_dce_straps(
1227 struct dc_context *ctx,
1228 struct resource_straps *straps)
1229 {
1230 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1231 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1232
1233 }
1234
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1235 static struct audio *dcn31_create_audio(
1236 struct dc_context *ctx, unsigned int inst)
1237 {
1238 return dce_audio_create(ctx, inst,
1239 &audio_regs[inst], &audio_shift, &audio_mask);
1240 }
1241
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1242 static struct vpg *dcn31_vpg_create(
1243 struct dc_context *ctx,
1244 uint32_t inst)
1245 {
1246 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1247
1248 if (!vpg31)
1249 return NULL;
1250
1251 vpg31_construct(vpg31, ctx, inst,
1252 &vpg_regs[inst],
1253 &vpg_shift,
1254 &vpg_mask);
1255
1256 return &vpg31->base;
1257 }
1258
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1259 static struct afmt *dcn31_afmt_create(
1260 struct dc_context *ctx,
1261 uint32_t inst)
1262 {
1263 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1264
1265 if (!afmt31)
1266 return NULL;
1267
1268 afmt31_construct(afmt31, ctx, inst,
1269 &afmt_regs[inst],
1270 &afmt_shift,
1271 &afmt_mask);
1272
1273 // Light sleep by default, no need to power down here
1274
1275 return &afmt31->base;
1276 }
1277
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1278 static struct apg *dcn31_apg_create(
1279 struct dc_context *ctx,
1280 uint32_t inst)
1281 {
1282 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1283
1284 if (!apg31)
1285 return NULL;
1286
1287 apg31_construct(apg31, ctx, inst,
1288 &apg_regs[inst],
1289 &apg_shift,
1290 &apg_mask);
1291
1292 return &apg31->base;
1293 }
1294
dcn31_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1295 static struct stream_encoder *dcn31_stream_encoder_create(
1296 enum engine_id eng_id,
1297 struct dc_context *ctx)
1298 {
1299 struct dcn10_stream_encoder *enc1;
1300 struct vpg *vpg;
1301 struct afmt *afmt;
1302 int vpg_inst;
1303 int afmt_inst;
1304
1305 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1306 if (eng_id <= ENGINE_ID_DIGF) {
1307 vpg_inst = eng_id;
1308 afmt_inst = eng_id;
1309 } else
1310 return NULL;
1311
1312 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1313 vpg = dcn31_vpg_create(ctx, vpg_inst);
1314 afmt = dcn31_afmt_create(ctx, afmt_inst);
1315
1316 if (!enc1 || !vpg || !afmt) {
1317 kfree(enc1);
1318 kfree(vpg);
1319 kfree(afmt);
1320 return NULL;
1321 }
1322
1323 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1324 eng_id, vpg, afmt,
1325 &stream_enc_regs[eng_id],
1326 &se_shift, &se_mask);
1327
1328 return &enc1->base;
1329 }
1330
dcn31_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1331 static struct hpo_frl_stream_encoder *dcn31_hpo_frl_stream_encoder_create(enum engine_id eng_id,
1332 struct dc_context *ctx)
1333 {
1334 struct dcn30_hpo_frl_stream_encoder *hpo_enc3;
1335 struct afmt *afmt;
1336 struct vpg *vpg;
1337 int afmt_inst;
1338 int vpg_inst;
1339
1340 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
1341 if (eng_id == ENGINE_ID_HPO_0) {
1342 vpg_inst = 5;
1343 afmt_inst = 5;
1344 } else {
1345 return NULL;
1346 }
1347
1348 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */
1349 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_stream_encoder);
1350 vpg = dcn31_vpg_create(ctx, vpg_inst);
1351 afmt = dcn31_afmt_create(ctx, afmt_inst);
1352
1353 if (!hpo_enc3 || !vpg || !afmt) {
1354 kfree(hpo_enc3);
1355 kfree(vpg);
1356 kfree(afmt);
1357 return NULL;
1358 }
1359
1360 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3,
1361 ctx,
1362 ctx->dc_bios,
1363 eng_id,
1364 vpg,
1365 afmt,
1366 &hpo_frl_stream_enc_regs[eng_id - ENGINE_ID_HPO_0],
1367 &hpo_se_shift, &hpo_se_mask);
1368
1369 return &hpo_enc3->base;
1370 }
1371
dcn31_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1372 static struct hpo_frl_link_encoder *dcn31_hpo_frl_link_encoder_create(enum engine_id eng_id,
1373 struct dc_context *ctx)
1374 {
1375 struct dcn30_hpo_frl_link_encoder *hpo_enc3;
1376
1377 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1378
1379 /* allocate HPO link encoder */
1380 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1381 if (!hpo_enc3)
1382 return NULL; /* out of memory */
1383
1384 hpo_frl_link_encoder3_construct(hpo_enc3,
1385 ctx,
1386 eng_id - ENGINE_ID_HPO_0,
1387 &hpo_frl_link_enc_regs[eng_id - ENGINE_ID_HPO_0],
1388 &hpo_le_shift,
1389 &hpo_le_mask);
1390
1391 return &hpo_enc3->base;
1392 }
1393
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1394 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1395 enum engine_id eng_id,
1396 struct dc_context *ctx)
1397 {
1398 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1399 struct vpg *vpg;
1400 struct apg *apg;
1401 uint32_t hpo_dp_inst;
1402 uint32_t vpg_inst;
1403 uint32_t apg_inst;
1404
1405 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1406 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1407
1408 /* Mapping of VPG register blocks to HPO DP block instance:
1409 * VPG[6] -> HPO_DP[0]
1410 * VPG[7] -> HPO_DP[1]
1411 * VPG[8] -> HPO_DP[2]
1412 * VPG[9] -> HPO_DP[3]
1413 */
1414 vpg_inst = hpo_dp_inst + 6;
1415
1416 /* Mapping of APG register blocks to HPO DP block instance:
1417 * APG[0] -> HPO_DP[0]
1418 * APG[1] -> HPO_DP[1]
1419 * APG[2] -> HPO_DP[2]
1420 * APG[3] -> HPO_DP[3]
1421 */
1422 apg_inst = hpo_dp_inst;
1423
1424 /* allocate HPO stream encoder and create VPG sub-block */
1425 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1426 vpg = dcn31_vpg_create(ctx, vpg_inst);
1427 apg = dcn31_apg_create(ctx, apg_inst);
1428
1429 if (!hpo_dp_enc31 || !vpg || !apg) {
1430 kfree(hpo_dp_enc31);
1431 kfree(vpg);
1432 kfree(apg);
1433 return NULL;
1434 }
1435
1436 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1437 hpo_dp_inst, eng_id, vpg, apg,
1438 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1439 &hpo_dp_se_shift, &hpo_dp_se_mask);
1440
1441 return &hpo_dp_enc31->base;
1442 }
1443
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1444 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1445 uint8_t inst,
1446 struct dc_context *ctx)
1447 {
1448 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1449
1450 /* allocate HPO link encoder */
1451 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1452 if (!hpo_dp_enc31)
1453 return NULL; /* out of memory */
1454
1455 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1456 &hpo_dp_link_enc_regs[inst],
1457 &hpo_dp_le_shift, &hpo_dp_le_mask);
1458
1459 return &hpo_dp_enc31->base;
1460 }
1461
dcn31_hwseq_create(struct dc_context * ctx)1462 static struct dce_hwseq *dcn31_hwseq_create(
1463 struct dc_context *ctx)
1464 {
1465 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1466
1467 if (hws) {
1468 hws->ctx = ctx;
1469 hws->regs = &hwseq_reg;
1470 hws->shifts = &hwseq_shift;
1471 hws->masks = &hwseq_mask;
1472 }
1473 return hws;
1474 }
1475 static const struct resource_create_funcs res_create_funcs = {
1476 .read_dce_straps = read_dce_straps,
1477 .create_audio = dcn31_create_audio,
1478 .create_stream_encoder = dcn31_stream_encoder_create,
1479 .create_hpo_frl_stream_encoder = dcn31_hpo_frl_stream_encoder_create,
1480 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1481 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1482 .create_hwseq = dcn31_hwseq_create,
1483 };
1484
dcn31_resource_destruct(struct dcn31_resource_pool * pool)1485 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1486 {
1487 unsigned int i;
1488
1489 for (i = 0; i < pool->base.stream_enc_count; i++) {
1490 if (pool->base.stream_enc[i] != NULL) {
1491 if (pool->base.stream_enc[i]->vpg != NULL) {
1492 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1493 pool->base.stream_enc[i]->vpg = NULL;
1494 }
1495 if (pool->base.stream_enc[i]->afmt != NULL) {
1496 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1497 pool->base.stream_enc[i]->afmt = NULL;
1498 }
1499 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1500 pool->base.stream_enc[i] = NULL;
1501 }
1502 }
1503
1504 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1505 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1506 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1507 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1508 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1509 }
1510
1511 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
1512 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
1513 pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
1514 }
1515
1516 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1517 pool->base.hpo_frl_stream_enc[i] = NULL;
1518 }
1519 }
1520
1521 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1522 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1523 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1524 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1525 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1526 }
1527 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1528 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1529 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1530 }
1531 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1532 pool->base.hpo_dp_stream_enc[i] = NULL;
1533 }
1534 }
1535
1536 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1537 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1538 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1539 pool->base.hpo_dp_link_enc[i] = NULL;
1540 }
1541 }
1542
1543 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1544 if (pool->base.dscs[i] != NULL)
1545 dcn20_dsc_destroy(&pool->base.dscs[i]);
1546 }
1547
1548 if (pool->base.mpc != NULL) {
1549 kfree(TO_DCN20_MPC(pool->base.mpc));
1550 pool->base.mpc = NULL;
1551 }
1552 if (pool->base.hubbub != NULL) {
1553 kfree(pool->base.hubbub);
1554 pool->base.hubbub = NULL;
1555 }
1556 if (pool->base.dio != NULL) {
1557 kfree(TO_DCN10_DIO(pool->base.dio));
1558 pool->base.dio = NULL;
1559 }
1560 for (i = 0; i < pool->base.pipe_count; i++) {
1561 if (pool->base.dpps[i] != NULL)
1562 dcn31_dpp_destroy(&pool->base.dpps[i]);
1563
1564 if (pool->base.ipps[i] != NULL)
1565 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1566
1567 if (pool->base.hubps[i] != NULL) {
1568 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1569 pool->base.hubps[i] = NULL;
1570 }
1571
1572 if (pool->base.irqs != NULL) {
1573 dal_irq_service_destroy(&pool->base.irqs);
1574 }
1575 }
1576
1577 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1578 if (pool->base.engines[i] != NULL)
1579 dce110_engine_destroy(&pool->base.engines[i]);
1580 if (pool->base.hw_i2cs[i] != NULL) {
1581 kfree(pool->base.hw_i2cs[i]);
1582 pool->base.hw_i2cs[i] = NULL;
1583 }
1584 if (pool->base.sw_i2cs[i] != NULL) {
1585 kfree(pool->base.sw_i2cs[i]);
1586 pool->base.sw_i2cs[i] = NULL;
1587 }
1588 }
1589
1590 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1591 if (pool->base.opps[i] != NULL)
1592 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1593 }
1594
1595 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1596 if (pool->base.timing_generators[i] != NULL) {
1597 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1598 pool->base.timing_generators[i] = NULL;
1599 }
1600 }
1601
1602 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1603 if (pool->base.dwbc[i] != NULL) {
1604 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1605 pool->base.dwbc[i] = NULL;
1606 }
1607 if (pool->base.mcif_wb[i] != NULL) {
1608 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1609 pool->base.mcif_wb[i] = NULL;
1610 }
1611 }
1612
1613 for (i = 0; i < pool->base.audio_count; i++) {
1614 if (pool->base.audios[i])
1615 dce_aud_destroy(&pool->base.audios[i]);
1616 }
1617
1618 for (i = 0; i < pool->base.clk_src_count; i++) {
1619 if (pool->base.clock_sources[i] != NULL) {
1620 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1621 pool->base.clock_sources[i] = NULL;
1622 }
1623 }
1624
1625 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1626 if (pool->base.mpc_lut[i] != NULL) {
1627 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1628 pool->base.mpc_lut[i] = NULL;
1629 }
1630 if (pool->base.mpc_shaper[i] != NULL) {
1631 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1632 pool->base.mpc_shaper[i] = NULL;
1633 }
1634 }
1635
1636 if (pool->base.dp_clock_source != NULL) {
1637 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1638 pool->base.dp_clock_source = NULL;
1639 }
1640
1641 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1642 if (pool->base.multiple_abms[i] != NULL)
1643 dce_abm_destroy(&pool->base.multiple_abms[i]);
1644 }
1645
1646 if (pool->base.psr != NULL)
1647 dmub_psr_destroy(&pool->base.psr);
1648
1649 if (pool->base.replay != NULL)
1650 dmub_replay_destroy(&pool->base.replay);
1651
1652 if (pool->base.dccg != NULL)
1653 dcn_dccg_destroy(&pool->base.dccg);
1654 }
1655
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1656 static struct hubp *dcn31_hubp_create(
1657 struct dc_context *ctx,
1658 uint32_t inst)
1659 {
1660 struct dcn20_hubp *hubp2 =
1661 kzalloc_obj(struct dcn20_hubp);
1662
1663 if (!hubp2)
1664 return NULL;
1665
1666 if (hubp31_construct(hubp2, ctx, inst,
1667 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1668 return &hubp2->base;
1669
1670 BREAK_TO_DEBUGGER();
1671 kfree(hubp2);
1672 return NULL;
1673 }
1674
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1675 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1676 {
1677 unsigned int i;
1678 uint32_t pipe_count = pool->res_cap->num_dwb;
1679
1680 for (i = 0; i < pipe_count; i++) {
1681 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1682
1683 if (!dwbc30) {
1684 dm_error("DC: failed to create dwbc30!\n");
1685 return false;
1686 }
1687
1688 dcn30_dwbc_construct(dwbc30, ctx,
1689 &dwbc30_regs[i],
1690 &dwbc30_shift,
1691 &dwbc30_mask,
1692 i);
1693
1694 pool->dwbc[i] = &dwbc30->base;
1695 }
1696 return true;
1697 }
1698
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1699 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1700 {
1701 unsigned int i;
1702 uint32_t pipe_count = pool->res_cap->num_dwb;
1703
1704 for (i = 0; i < pipe_count; i++) {
1705 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1706
1707 if (!mcif_wb30) {
1708 dm_error("DC: failed to create mcif_wb30!\n");
1709 return false;
1710 }
1711
1712 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1713 &mcif_wb30_regs[i],
1714 &mcif_wb30_shift,
1715 &mcif_wb30_mask,
1716 i);
1717
1718 pool->mcif_wb[i] = &mcif_wb30->base;
1719 }
1720 return true;
1721 }
1722
dcn31_dsc_create(struct dc_context * ctx,uint32_t inst)1723 static struct display_stream_compressor *dcn31_dsc_create(
1724 struct dc_context *ctx, uint32_t inst)
1725 {
1726 struct dcn20_dsc *dsc =
1727 kzalloc_obj(struct dcn20_dsc);
1728
1729 if (!dsc) {
1730 BREAK_TO_DEBUGGER();
1731 return NULL;
1732 }
1733
1734 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1735 return &dsc->base;
1736 }
1737
dcn31_destroy_resource_pool(struct resource_pool ** pool)1738 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1739 {
1740 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1741
1742 dcn31_resource_destruct(dcn31_pool);
1743 kfree(dcn31_pool);
1744 *pool = NULL;
1745 }
1746
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1747 static struct clock_source *dcn31_clock_source_create(
1748 struct dc_context *ctx,
1749 struct dc_bios *bios,
1750 enum clock_source_id id,
1751 const struct dce110_clk_src_regs *regs,
1752 bool dp_clk_src)
1753 {
1754 struct dce110_clk_src *clk_src =
1755 kzalloc_obj(struct dce110_clk_src);
1756
1757 if (!clk_src)
1758 return NULL;
1759
1760 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1761 regs, &cs_shift, &cs_mask)) {
1762 clk_src->base.dp_clk_src = dp_clk_src;
1763 return &clk_src->base;
1764 }
1765
1766 kfree(clk_src);
1767 BREAK_TO_DEBUGGER();
1768 return NULL;
1769 }
1770
is_dual_plane(enum surface_pixel_format format)1771 static bool is_dual_plane(enum surface_pixel_format format)
1772 {
1773 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1774 }
1775
dcn31x_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1776 int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
1777 struct dc_state *context,
1778 display_e2e_pipe_params_st *pipes,
1779 enum dc_validate_mode validate_mode)
1780 {
1781 uint32_t pipe_cnt;
1782 unsigned int i;
1783
1784 dc_assert_fp_enabled();
1785
1786 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1787
1788 for (i = 0; i < pipe_cnt; i++) {
1789 pipes[i].pipe.src.gpuvm = 1;
1790 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) {
1791 //pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1792 pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled;
1793 } else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
1794 pipes[i].pipe.src.hostvm = false;
1795 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
1796 pipes[i].pipe.src.hostvm = true;
1797 }
1798 return pipe_cnt;
1799 }
1800
dcn31_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1801 int dcn31_populate_dml_pipes_from_context(
1802 struct dc *dc, struct dc_state *context,
1803 display_e2e_pipe_params_st *pipes,
1804 enum dc_validate_mode validate_mode)
1805 {
1806 unsigned int i, pipe_cnt;
1807 struct resource_context *res_ctx = &context->res_ctx;
1808 struct pipe_ctx *pipe = 0;
1809 bool upscaled = false;
1810
1811 DC_FP_START();
1812 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1813 DC_FP_END();
1814
1815 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1816 struct dc_crtc_timing *timing;
1817
1818 if (!res_ctx->pipe_ctx[i].stream)
1819 continue;
1820 pipe = &res_ctx->pipe_ctx[i];
1821 timing = &pipe->stream->timing;
1822 if (pipe->plane_state &&
1823 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
1824 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
1825 upscaled = true;
1826
1827 /*
1828 * Immediate flip can be set dynamically after enabling the plane.
1829 * We need to require support for immediate flip or underflow can be
1830 * intermittently experienced depending on peak b/w requirements.
1831 */
1832 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1833 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1834 pipes[pipe_cnt].pipe.src.gpuvm = true;
1835 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1836 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1837 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1838 DC_FP_START();
1839 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1840 DC_FP_END();
1841
1842
1843 if (pipes[pipe_cnt].dout.dsc_enable) {
1844 switch (timing->display_color_depth) {
1845 case COLOR_DEPTH_888:
1846 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1847 break;
1848 case COLOR_DEPTH_101010:
1849 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1850 break;
1851 case COLOR_DEPTH_121212:
1852 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1853 break;
1854 default:
1855 ASSERT(0);
1856 break;
1857 }
1858 }
1859
1860 pipe_cnt++;
1861 }
1862 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1863
1864 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1865 if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
1866 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1867 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1868 pipes[0].pipe.src.unbounded_req_mode = true;
1869 }
1870 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
1871 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
1872 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
1873 } else if (context->stream_count >= 3 && upscaled) {
1874 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1875 }
1876
1877 return pipe_cnt;
1878 }
1879
dcn31_get_det_buffer_size(const struct dc_state * context)1880 unsigned int dcn31_get_det_buffer_size(
1881 const struct dc_state *context)
1882 {
1883 return context->bw_ctx.dml.ip.det_buffer_size_kbytes;
1884 }
1885
dcn31_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1886 void dcn31_calculate_wm_and_dlg(
1887 struct dc *dc, struct dc_state *context,
1888 display_e2e_pipe_params_st *pipes,
1889 int pipe_cnt,
1890 int vlevel)
1891 {
1892 DC_FP_START();
1893 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1894 DC_FP_END();
1895 }
1896
1897 void
dcn31_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)1898 dcn31_populate_dml_writeback_from_context(struct dc *dc,
1899 struct resource_context *res_ctx,
1900 display_e2e_pipe_params_st *pipes)
1901 {
1902 DC_FP_START();
1903 dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1904 DC_FP_END();
1905 }
1906
1907 void
dcn31_set_mcif_arb_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)1908 dcn31_set_mcif_arb_params(struct dc *dc,
1909 struct dc_state *context,
1910 display_e2e_pipe_params_st *pipes,
1911 int pipe_cnt)
1912 {
1913 DC_FP_START();
1914 dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1915 DC_FP_END();
1916 }
1917
dcn31_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1918 enum dc_status dcn31_validate_bandwidth(struct dc *dc,
1919 struct dc_state *context,
1920 enum dc_validate_mode validate_mode)
1921 {
1922 bool out = false;
1923
1924 BW_VAL_TRACE_SETUP();
1925
1926 int vlevel = 0;
1927 int pipe_cnt = 0;
1928 display_e2e_pipe_params_st *pipes = kzalloc_objs(display_e2e_pipe_params_st,
1929 dc->res_pool->pipe_count);
1930 DC_LOGGER_INIT(dc->ctx->logger);
1931
1932 BW_VAL_TRACE_COUNT();
1933
1934 if (!pipes)
1935 goto validate_fail;
1936
1937 DC_FP_START();
1938 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);
1939 DC_FP_END();
1940
1941 // Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calculate_wm_and_dlg
1942 if (pipe_cnt == 0)
1943 validate_mode = DC_VALIDATE_MODE_AND_PROGRAMMING;
1944
1945 if (!out)
1946 goto validate_fail;
1947
1948 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1949
1950 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
1951 BW_VAL_TRACE_SKIP(fast);
1952 goto validate_out;
1953 }
1954 if (dc->res_pool->funcs->calculate_wm_and_dlg)
1955 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1956
1957 BW_VAL_TRACE_END_WATERMARKS();
1958
1959 goto validate_out;
1960
1961 validate_fail:
1962 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1963 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1964
1965 BW_VAL_TRACE_SKIP(fail);
1966 out = false;
1967
1968 validate_out:
1969 kfree(pipes);
1970
1971 BW_VAL_TRACE_FINISH();
1972
1973 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1974 }
1975
dcn31_get_panel_config_defaults(struct dc_panel_config * panel_config)1976 static void dcn31_get_panel_config_defaults(struct dc_panel_config *panel_config)
1977 {
1978 *panel_config = panel_config_defaults;
1979 }
1980
1981 static struct dc_cap_funcs cap_funcs = {
1982 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1983 };
1984
dcn31_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1985 static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1986 {
1987 DC_FP_START();
1988 dcn31_update_bw_bounding_box_fpu(dc, bw_params);
1989 DC_FP_END();
1990 }
1991
1992 static struct resource_funcs dcn31_res_pool_funcs = {
1993 .destroy = dcn31_destroy_resource_pool,
1994 .link_enc_create = dcn31_link_encoder_create,
1995 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1996 .link_encs_assign = link_enc_cfg_link_encs_assign,
1997 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1998 .hpo_frl_link_enc_create = dcn31_hpo_frl_link_encoder_create,
1999 .panel_cntl_create = dcn31_panel_cntl_create,
2000 .validate_bandwidth = dcn31_validate_bandwidth,
2001 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
2002 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
2003 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
2004 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
2005 .release_pipe = dcn20_release_pipe,
2006 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2007 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2008 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2009 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
2010 .set_mcif_arb_params = dcn31_set_mcif_arb_params,
2011 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2012 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2013 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2014 .update_bw_bounding_box = dcn31_update_bw_bounding_box,
2015 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2016 .get_panel_config_defaults = dcn31_get_panel_config_defaults,
2017 .get_det_buffer_size = dcn31_get_det_buffer_size,
2018 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
2019 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
2020 .get_default_tiling_info = dcn10_get_default_tiling_info,
2021 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
2022 };
2023
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)2024 static struct clock_source *dcn30_clock_source_create(
2025 struct dc_context *ctx,
2026 struct dc_bios *bios,
2027 enum clock_source_id id,
2028 const struct dce110_clk_src_regs *regs,
2029 bool dp_clk_src)
2030 {
2031 struct dce110_clk_src *clk_src =
2032 kzalloc_obj(struct dce110_clk_src);
2033
2034 if (!clk_src)
2035 return NULL;
2036
2037 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
2038 regs, &cs_shift, &cs_mask)) {
2039 clk_src->base.dp_clk_src = dp_clk_src;
2040 return &clk_src->base;
2041 }
2042
2043 kfree(clk_src);
2044 BREAK_TO_DEBUGGER();
2045 return NULL;
2046 }
2047
dcn31_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn31_resource_pool * pool)2048 static bool dcn31_resource_construct(
2049 uint8_t num_virtual_links,
2050 struct dc *dc,
2051 struct dcn31_resource_pool *pool)
2052 {
2053 int i;
2054 struct dc_context *ctx = dc->ctx;
2055 struct irq_service_init_data init_data;
2056
2057 ctx->dc_bios->regs = &bios_regs;
2058
2059 pool->base.res_cap = &res_cap_dcn31;
2060
2061 pool->base.funcs = &dcn31_res_pool_funcs;
2062
2063 /*************************************************
2064 * Resource + asic cap harcoding *
2065 *************************************************/
2066 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
2067 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2068 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2069 dc->caps.max_downscale_ratio = 600;
2070 dc->caps.i2c_speed_in_khz = 100;
2071 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
2072 dc->caps.max_cursor_size = 256;
2073 dc->caps.min_horizontal_blanking_period = 80;
2074 dc->caps.dmdata_alloc_size = 2048;
2075
2076 dc->caps.max_slave_planes = 2;
2077 dc->caps.max_slave_yuv_planes = 2;
2078 dc->caps.max_slave_rgb_planes = 2;
2079 dc->caps.post_blend_color_processing = true;
2080 dc->caps.force_dp_tps4_for_cp2520 = true;
2081 if (dc->config.forceHBR2CP2520)
2082 dc->caps.force_dp_tps4_for_cp2520 = false;
2083 dc->caps.hdmi_hpo = true;
2084 dc->caps.dp_hpo = true;
2085 dc->caps.dp_hdmi21_pcon_support = true;
2086 dc->caps.edp_dsc_support = true;
2087 dc->caps.extended_aux_timeout_support = true;
2088 dc->caps.dmcub_support = true;
2089 dc->caps.is_apu = true;
2090 dc->caps.zstate_support = true;
2091
2092 /* Enable 4to1MPC by default */
2093 dc->config.allow_4to1MPC = true;
2094
2095 /* Color pipeline capabilities */
2096 dc->caps.color.dpp.dcn_arch = 1;
2097 dc->caps.color.dpp.input_lut_shared = 0;
2098 dc->caps.color.dpp.icsc = 1;
2099 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2100 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2101 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2102 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2103 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2104 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2105 dc->caps.color.dpp.post_csc = 1;
2106 dc->caps.color.dpp.gamma_corr = 1;
2107 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2108
2109 dc->caps.color.dpp.hw_3d_lut = 1;
2110 dc->caps.color.dpp.ogam_ram = 1;
2111 // no OGAM ROM on DCN301
2112 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2113 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2114 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2115 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2116 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2117 dc->caps.color.dpp.ocsc = 0;
2118
2119 dc->caps.color.mpc.gamut_remap = 1;
2120 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
2121 dc->caps.color.mpc.ogam_ram = 1;
2122 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2123 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2124 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2125 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2126 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2127 dc->caps.color.mpc.ocsc = 1;
2128 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
2129
2130 dc->caps.num_of_host_routers = 2;
2131 dc->caps.num_of_dpias_per_host_router = 2;
2132
2133 /* Use pipe context based otg sync logic */
2134 dc->config.use_pipe_ctx_sync_logic = true;
2135 dc->config.disable_hbr_audio_dp2 = true;
2136
2137 dc->config.no_native422_support = true;
2138
2139 /* read VBIOS LTTPR caps */
2140 {
2141 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2142 enum bp_result bp_query_result;
2143 uint8_t is_vbios_lttpr_enable = 0;
2144
2145 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2146 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2147 }
2148
2149 /* interop bit is implicit */
2150 {
2151 dc->caps.vbios_lttpr_aware = true;
2152 }
2153 }
2154 dc->check_config = config_defaults;
2155
2156 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2157 dc->debug = debug_defaults_drv;
2158
2159 // Init the vm_helper
2160 if (dc->vm_helper)
2161 vm_helper_init(dc->vm_helper, 16);
2162
2163 /*************************************************
2164 * Create resources *
2165 *************************************************/
2166
2167 /* Clock Sources for Pixel Clock*/
2168 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
2169 dcn30_clock_source_create(ctx, ctx->dc_bios,
2170 CLOCK_SOURCE_COMBO_PHY_PLL0,
2171 &clk_src_regs[0], false);
2172 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
2173 dcn30_clock_source_create(ctx, ctx->dc_bios,
2174 CLOCK_SOURCE_COMBO_PHY_PLL1,
2175 &clk_src_regs[1], false);
2176 /*move phypllx_pixclk_resync to dmub next*/
2177 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
2178 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2179 dcn30_clock_source_create(ctx, ctx->dc_bios,
2180 CLOCK_SOURCE_COMBO_PHY_PLL2,
2181 &clk_src_regs_b0[2], false);
2182 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2183 dcn30_clock_source_create(ctx, ctx->dc_bios,
2184 CLOCK_SOURCE_COMBO_PHY_PLL3,
2185 &clk_src_regs_b0[3], false);
2186 } else {
2187 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2188 dcn30_clock_source_create(ctx, ctx->dc_bios,
2189 CLOCK_SOURCE_COMBO_PHY_PLL2,
2190 &clk_src_regs[2], false);
2191 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2192 dcn30_clock_source_create(ctx, ctx->dc_bios,
2193 CLOCK_SOURCE_COMBO_PHY_PLL3,
2194 &clk_src_regs[3], false);
2195 }
2196
2197 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2198 dcn30_clock_source_create(ctx, ctx->dc_bios,
2199 CLOCK_SOURCE_COMBO_PHY_PLL4,
2200 &clk_src_regs[4], false);
2201
2202 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2203
2204 /* todo: not reuse phy_pll registers */
2205 pool->base.dp_clock_source =
2206 dcn31_clock_source_create(ctx, ctx->dc_bios,
2207 CLOCK_SOURCE_ID_DP_DTO,
2208 &clk_src_regs[0], true);
2209
2210 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2211 if (pool->base.clock_sources[i] == NULL) {
2212 dm_error("DC: failed to create clock sources!\n");
2213 BREAK_TO_DEBUGGER();
2214 goto create_fail;
2215 }
2216 }
2217
2218 /* TODO: DCCG */
2219 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2220 if (pool->base.dccg == NULL) {
2221 dm_error("DC: failed to create dccg!\n");
2222 BREAK_TO_DEBUGGER();
2223 goto create_fail;
2224 }
2225
2226 /* TODO: IRQ */
2227 init_data.ctx = dc->ctx;
2228 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2229 if (!pool->base.irqs)
2230 goto create_fail;
2231
2232 /* HUBBUB */
2233 pool->base.hubbub = dcn31_hubbub_create(ctx);
2234 if (pool->base.hubbub == NULL) {
2235 BREAK_TO_DEBUGGER();
2236 dm_error("DC: failed to create hubbub!\n");
2237 goto create_fail;
2238 }
2239
2240 /* DIO */
2241 pool->base.dio = dcn31_dio_create(ctx);
2242 if (pool->base.dio == NULL) {
2243 BREAK_TO_DEBUGGER();
2244 dm_error("DC: failed to create dio!\n");
2245 goto create_fail;
2246 }
2247
2248 /* HUBPs, DPPs, OPPs and TGs */
2249 for (i = 0; i < (int)pool->base.pipe_count; i++) {
2250 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2251 if (pool->base.hubps[i] == NULL) {
2252 BREAK_TO_DEBUGGER();
2253 dm_error(
2254 "DC: failed to create hubps!\n");
2255 goto create_fail;
2256 }
2257
2258 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2259 if (pool->base.dpps[i] == NULL) {
2260 BREAK_TO_DEBUGGER();
2261 dm_error(
2262 "DC: failed to create dpps!\n");
2263 goto create_fail;
2264 }
2265 }
2266
2267 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2268 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2269 if (pool->base.opps[i] == NULL) {
2270 BREAK_TO_DEBUGGER();
2271 dm_error(
2272 "DC: failed to create output pixel processor!\n");
2273 goto create_fail;
2274 }
2275 }
2276
2277 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2278 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2279 ctx, i);
2280 if (pool->base.timing_generators[i] == NULL) {
2281 BREAK_TO_DEBUGGER();
2282 dm_error("DC: failed to create tg!\n");
2283 goto create_fail;
2284 }
2285 }
2286 pool->base.timing_generator_count = i;
2287
2288 /* PSR */
2289 pool->base.psr = dmub_psr_create(ctx);
2290 if (pool->base.psr == NULL) {
2291 dm_error("DC: failed to create psr obj!\n");
2292 BREAK_TO_DEBUGGER();
2293 goto create_fail;
2294 }
2295
2296 /* Replay */
2297 pool->base.replay = dmub_replay_create(ctx);
2298 if (pool->base.replay == NULL) {
2299 dm_error("DC: failed to create replay obj!\n");
2300 BREAK_TO_DEBUGGER();
2301 goto create_fail;
2302 }
2303
2304 /* ABM */
2305 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2306 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2307 &abm_regs[i],
2308 &abm_shift,
2309 &abm_mask);
2310 if (pool->base.multiple_abms[i] == NULL) {
2311 dm_error("DC: failed to create abm for pipe %d!\n", i);
2312 BREAK_TO_DEBUGGER();
2313 goto create_fail;
2314 }
2315 }
2316
2317 /* MPC and DSC */
2318 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2319 if (pool->base.mpc == NULL) {
2320 BREAK_TO_DEBUGGER();
2321 dm_error("DC: failed to create mpc!\n");
2322 goto create_fail;
2323 }
2324
2325 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2326 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2327 if (pool->base.dscs[i] == NULL) {
2328 BREAK_TO_DEBUGGER();
2329 dm_error("DC: failed to create display stream compressor %d!\n", i);
2330 goto create_fail;
2331 }
2332 }
2333
2334 /* DWB and MMHUBBUB */
2335 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2336 BREAK_TO_DEBUGGER();
2337 dm_error("DC: failed to create dwbc!\n");
2338 goto create_fail;
2339 }
2340
2341 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2342 BREAK_TO_DEBUGGER();
2343 dm_error("DC: failed to create mcif_wb!\n");
2344 goto create_fail;
2345 }
2346
2347 /* AUX and I2C */
2348 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2349 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2350 if (pool->base.engines[i] == NULL) {
2351 BREAK_TO_DEBUGGER();
2352 dm_error(
2353 "DC:failed to create aux engine!!\n");
2354 goto create_fail;
2355 }
2356 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2357 if (pool->base.hw_i2cs[i] == NULL) {
2358 BREAK_TO_DEBUGGER();
2359 dm_error(
2360 "DC:failed to create hw i2c!!\n");
2361 goto create_fail;
2362 }
2363 pool->base.sw_i2cs[i] = NULL;
2364 }
2365
2366 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
2367 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
2368 !dc->debug.dpia_debug.bits.disable_dpia) {
2369 /* YELLOW CARP B0 has 4 DPIA's */
2370 pool->base.usb4_dpia_count = 4;
2371 }
2372
2373 if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1)
2374 pool->base.usb4_dpia_count = 4;
2375
2376 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2377 if (!resource_construct(num_virtual_links, dc, &pool->base,
2378 &res_create_funcs))
2379 goto create_fail;
2380
2381 /* HW Sequencer and Plane caps */
2382 dcn31_hw_sequencer_construct(dc);
2383
2384 dc->caps.max_planes = pool->base.pipe_count;
2385
2386 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2387 dc->caps.planes[i] = plane_cap;
2388
2389 dc->caps.max_odm_combine_factor = 4;
2390
2391 dc->cap_funcs = cap_funcs;
2392
2393 dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
2394
2395 return true;
2396
2397 create_fail:
2398 dcn31_resource_destruct(pool);
2399
2400 return false;
2401 }
2402
dcn31_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2403 struct resource_pool *dcn31_create_resource_pool(
2404 const struct dc_init_data *init_data,
2405 struct dc *dc)
2406 {
2407 struct dcn31_resource_pool *pool =
2408 kzalloc_obj(struct dcn31_resource_pool);
2409
2410 if (!pool)
2411 return NULL;
2412
2413 if (dcn31_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2414 return &pool->base;
2415
2416 BREAK_TO_DEBUGGER();
2417 kfree(pool);
2418 return NULL;
2419 }
2420
dcn31_update_dc_state_for_encoder_switch(struct dc_link * link,struct dc_link_settings * link_setting,uint8_t pipe_count,struct pipe_ctx * pipes,struct audio_output * audio_output)2421 enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link,
2422 struct dc_link_settings *link_setting,
2423 uint8_t pipe_count,
2424 struct pipe_ctx *pipes,
2425 struct audio_output *audio_output)
2426 {
2427 (void)link_setting;
2428 struct dc_state *state = link->dc->current_state;
2429 int i;
2430
2431 #if defined(CONFIG_DRM_AMD_DC_FP)
2432 if (link->dc->hwss.calculate_pix_rate_divider) {
2433 for (i = 0; i < state->stream_count; i++)
2434 if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link)
2435 link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]);
2436 }
2437
2438 for (i = 0; i < pipe_count; i++) {
2439 if (link->dc->res_pool->funcs->build_pipe_pix_clk_params)
2440 link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]);
2441
2442 // Setup audio
2443 if (pipes[i].stream_res.audio != NULL)
2444 build_audio_output(state, &pipes[i], &audio_output[i]);
2445 }
2446 #else
2447 /* This DCN requires rate divider updates and audio reprogramming to allow DP1<-->DP2 link rate switching,
2448 * but the above will not compile on architectures without an FPU.
2449 */
2450 DC_LOG_WARNING("%s: DP1<-->DP2 link retraining will not work on this DCN on non-FPU platforms", __func__);
2451 ASSERT(0);
2452 #endif
2453
2454 return DC_OK;
2455 }
2456