1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7
8 #include <linux/bitfield.h>
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <linux/refcount.h>
17 #include <linux/crash_dump.h>
18 #include <linux/trace_events.h>
19 #include <linux/trace.h>
20 #include <linux/irq.h>
21
22 #include <scsi/scsi_tcq.h>
23 #include <scsi/scsicam.h>
24 #include <scsi/scsi_transport.h>
25 #include <scsi/scsi_transport_fc.h>
26
27 #include "qla_target.h"
28
29 /*
30 * Driver version
31 */
32 char qla2x00_version_str[40];
33
34 static int apidev_major;
35
36 /*
37 * SRB allocation cache
38 */
39 struct kmem_cache *srb_cachep;
40
41 static struct trace_array *qla_trc_array;
42
43 int ql2xfulldump_on_mpifail;
44 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
46 "Set this to take full dump on MPI hang.");
47
48 int ql2xenforce_iocb_limit = 2;
49 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
50 MODULE_PARM_DESC(ql2xenforce_iocb_limit,
51 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) "
52 "1: track usage per queue, 2: track usage per adapter");
53
54 /*
55 * CT6 CTX allocation cache
56 */
57 static struct kmem_cache *ctx_cachep;
58 /*
59 * error level for logging
60 */
61 uint ql_errlev = 0x8001;
62
63 int ql2xsecenable;
64 module_param(ql2xsecenable, int, S_IRUGO);
65 MODULE_PARM_DESC(ql2xsecenable,
66 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
67
68 static int ql2xenableclass2;
69 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
70 MODULE_PARM_DESC(ql2xenableclass2,
71 "Specify if Class 2 operations are supported from the very "
72 "beginning. Default is 0 - class 2 not supported.");
73
74
75 int ql2xlogintimeout = 20;
76 module_param(ql2xlogintimeout, int, S_IRUGO);
77 MODULE_PARM_DESC(ql2xlogintimeout,
78 "Login timeout value in seconds.");
79
80 int qlport_down_retry;
81 module_param(qlport_down_retry, int, S_IRUGO);
82 MODULE_PARM_DESC(qlport_down_retry,
83 "Maximum number of command retries to a port that returns "
84 "a PORT-DOWN status.");
85
86 int ql2xplogiabsentdevice;
87 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
88 MODULE_PARM_DESC(ql2xplogiabsentdevice,
89 "Option to enable PLOGI to devices that are not present after "
90 "a Fabric scan. This is needed for several broken switches. "
91 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
92
93 int ql2xloginretrycount;
94 module_param(ql2xloginretrycount, int, S_IRUGO);
95 MODULE_PARM_DESC(ql2xloginretrycount,
96 "Specify an alternate value for the NVRAM login retry count.");
97
98 int ql2xallocfwdump = 1;
99 module_param(ql2xallocfwdump, int, S_IRUGO);
100 MODULE_PARM_DESC(ql2xallocfwdump,
101 "Option to enable allocation of memory for a firmware dump "
102 "during HBA initialization. Memory allocation requirements "
103 "vary by ISP type. Default is 1 - allocate memory.");
104
105 int ql2xextended_error_logging;
106 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
107 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
108 MODULE_PARM_DESC(ql2xextended_error_logging,
109 "Option to enable extended error logging,\n"
110 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
111 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
112 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
113 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
114 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
115 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
116 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
117 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
118 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
119 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
120 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
121 "\t\t0x1e400000 - Preferred value for capturing essential "
122 "debug information (equivalent to old "
123 "ql2xextended_error_logging=1).\n"
124 "\t\tDo LOGICAL OR of the value to enable more than one level");
125
126 int ql2xextended_error_logging_ktrace = 1;
127 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR);
128 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace,
129 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n");
130
131 int ql2xshiftctondsd = 6;
132 module_param(ql2xshiftctondsd, int, S_IRUGO);
133 MODULE_PARM_DESC(ql2xshiftctondsd,
134 "Set to control shifting of command type processing "
135 "based on total number of SG elements.");
136
137 int ql2xfdmienable = 1;
138 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
139 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
140 MODULE_PARM_DESC(ql2xfdmienable,
141 "Enables FDMI registrations. "
142 "0 - no FDMI registrations. "
143 "1 - provide FDMI registrations (default).");
144
145 #define MAX_Q_DEPTH 64
146 static int ql2xmaxqdepth = MAX_Q_DEPTH;
147 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
148 MODULE_PARM_DESC(ql2xmaxqdepth,
149 "Maximum queue depth to set for each LUN. "
150 "Default is 64.");
151
152 int ql2xenabledif = 2;
153 module_param(ql2xenabledif, int, S_IRUGO);
154 MODULE_PARM_DESC(ql2xenabledif,
155 " Enable T10-CRC-DIF:\n"
156 " Default is 2.\n"
157 " 0 -- No DIF Support\n"
158 " 1 -- Enable DIF for all types\n"
159 " 2 -- Enable DIF for all types, except Type 0.\n");
160
161 #if (IS_ENABLED(CONFIG_NVME_FC))
162 int ql2xnvmeenable = 1;
163 #else
164 int ql2xnvmeenable;
165 #endif
166 module_param(ql2xnvmeenable, int, 0644);
167 MODULE_PARM_DESC(ql2xnvmeenable,
168 "Enables NVME support. "
169 "0 - no NVMe. Default is Y");
170
171 int ql2xenablehba_err_chk = 2;
172 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
173 MODULE_PARM_DESC(ql2xenablehba_err_chk,
174 " Enable T10-CRC-DIF Error isolation by HBA:\n"
175 " Default is 2.\n"
176 " 0 -- Error isolation disabled\n"
177 " 1 -- Error isolation enabled only for DIX Type 0\n"
178 " 2 -- Error isolation enabled for all Types\n");
179
180 int ql2xmqsupport = 1;
181 module_param(ql2xmqsupport, int, S_IRUGO);
182 MODULE_PARM_DESC(ql2xmqsupport,
183 "Enable on demand multiple queue pairs support "
184 "Default is 1 for supported. "
185 "Set it to 0 to turn off mq qpair support.");
186
187 int ql2xfwloadbin;
188 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
189 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
190 MODULE_PARM_DESC(ql2xfwloadbin,
191 "Option to specify location from which to load ISP firmware:.\n"
192 " 2 -- load firmware via the request_firmware() (hotplug).\n"
193 " interface.\n"
194 " 1 -- load firmware from flash.\n"
195 " 0 -- use default semantics.\n");
196
197 int ql2xdbwr = 1;
198 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
199 MODULE_PARM_DESC(ql2xdbwr,
200 "Option to specify scheme for request queue posting.\n"
201 " 0 -- Regular doorbell.\n"
202 " 1 -- CAMRAM doorbell (faster).\n");
203
204 int ql2xgffidenable;
205 module_param(ql2xgffidenable, int, S_IRUGO);
206 MODULE_PARM_DESC(ql2xgffidenable,
207 "Enables GFF_ID checks of port type. "
208 "Default is 0 - Do not use GFF_ID information.");
209
210 int ql2xasynctmfenable = 1;
211 module_param(ql2xasynctmfenable, int, S_IRUGO);
212 MODULE_PARM_DESC(ql2xasynctmfenable,
213 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
214 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
215
216 int ql2xdontresethba;
217 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
218 MODULE_PARM_DESC(ql2xdontresethba,
219 "Option to specify reset behaviour.\n"
220 " 0 (Default) -- Reset on failure.\n"
221 " 1 -- Do not reset on failure.\n");
222
223 uint64_t ql2xmaxlun = MAX_LUNS;
224 module_param(ql2xmaxlun, ullong, S_IRUGO);
225 MODULE_PARM_DESC(ql2xmaxlun,
226 "Defines the maximum LU number to register with the SCSI "
227 "midlayer. Default is 65535.");
228
229 int ql2xmdcapmask = 0x1F;
230 module_param(ql2xmdcapmask, int, S_IRUGO);
231 MODULE_PARM_DESC(ql2xmdcapmask,
232 "Set the Minidump driver capture mask level. "
233 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
234
235 int ql2xmdenable = 1;
236 module_param(ql2xmdenable, int, S_IRUGO);
237 MODULE_PARM_DESC(ql2xmdenable,
238 "Enable/disable MiniDump. "
239 "0 - MiniDump disabled. "
240 "1 (Default) - MiniDump enabled.");
241
242 int ql2xexlogins;
243 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
244 MODULE_PARM_DESC(ql2xexlogins,
245 "Number of extended Logins. "
246 "0 (Default)- Disabled.");
247
248 int ql2xexchoffld = 1024;
249 module_param(ql2xexchoffld, uint, 0644);
250 MODULE_PARM_DESC(ql2xexchoffld,
251 "Number of target exchanges.");
252
253 int ql2xiniexchg = 1024;
254 module_param(ql2xiniexchg, uint, 0644);
255 MODULE_PARM_DESC(ql2xiniexchg,
256 "Number of initiator exchanges.");
257
258 int ql2xfwholdabts;
259 module_param(ql2xfwholdabts, int, S_IRUGO);
260 MODULE_PARM_DESC(ql2xfwholdabts,
261 "Allow FW to hold status IOCB until ABTS rsp received. "
262 "0 (Default) Do not set fw option. "
263 "1 - Set fw option to hold ABTS.");
264
265 int ql2xmvasynctoatio = 1;
266 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
267 MODULE_PARM_DESC(ql2xmvasynctoatio,
268 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
269 "0 (Default). Do not move IOCBs"
270 "1 - Move IOCBs.");
271
272 int ql2xautodetectsfp = 1;
273 module_param(ql2xautodetectsfp, int, 0444);
274 MODULE_PARM_DESC(ql2xautodetectsfp,
275 "Detect SFP range and set appropriate distance.\n"
276 "1 (Default): Enable\n");
277
278 int ql2xenablemsix = 1;
279 module_param(ql2xenablemsix, int, 0444);
280 MODULE_PARM_DESC(ql2xenablemsix,
281 "Set to enable MSI or MSI-X interrupt mechanism.\n"
282 " Default is 1, enable MSI-X interrupt mechanism.\n"
283 " 0 -- enable traditional pin-based mechanism.\n"
284 " 1 -- enable MSI-X interrupt mechanism.\n"
285 " 2 -- enable MSI interrupt mechanism.\n");
286
287 int qla2xuseresexchforels;
288 module_param(qla2xuseresexchforels, int, 0444);
289 MODULE_PARM_DESC(qla2xuseresexchforels,
290 "Reserve 1/2 of emergency exchanges for ELS.\n"
291 " 0 (default): disabled");
292
293 static int ql2xprotmask;
294 module_param(ql2xprotmask, int, 0644);
295 MODULE_PARM_DESC(ql2xprotmask,
296 "Override DIF/DIX protection capabilities mask\n"
297 "Default is 0 which sets protection mask based on "
298 "capabilities reported by HBA firmware.\n");
299
300 static int ql2xprotguard;
301 module_param(ql2xprotguard, int, 0644);
302 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
303 " 0 -- Let HBA firmware decide\n"
304 " 1 -- Force T10 CRC\n"
305 " 2 -- Force IP checksum\n");
306
307 int ql2xdifbundlinginternalbuffers;
308 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
309 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
310 "Force using internal buffers for DIF information\n"
311 "0 (Default). Based on check.\n"
312 "1 Force using internal buffers\n");
313
314 int ql2xsmartsan;
315 module_param(ql2xsmartsan, int, 0444);
316 module_param_named(smartsan, ql2xsmartsan, int, 0444);
317 MODULE_PARM_DESC(ql2xsmartsan,
318 "Send SmartSAN Management Attributes for FDMI Registration."
319 " Default is 0 - No SmartSAN registration,"
320 " 1 - Register SmartSAN Management Attributes.");
321
322 int ql2xrdpenable;
323 module_param(ql2xrdpenable, int, 0444);
324 module_param_named(rdpenable, ql2xrdpenable, int, 0444);
325 MODULE_PARM_DESC(ql2xrdpenable,
326 "Enables RDP responses. "
327 "0 - no RDP responses (default). "
328 "1 - provide RDP responses.");
329 int ql2xabts_wait_nvme = 1;
330 module_param(ql2xabts_wait_nvme, int, 0444);
331 MODULE_PARM_DESC(ql2xabts_wait_nvme,
332 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)");
333
334
335 static u32 ql2xdelay_before_pci_error_handling = 5;
336 module_param(ql2xdelay_before_pci_error_handling, uint, 0644);
337 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling,
338 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");
339
340 static void qla2x00_clear_drv_active(struct qla_hw_data *);
341 static void qla2x00_free_device(scsi_qla_host_t *);
342 static void qla2xxx_map_queues(struct Scsi_Host *shost);
343 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
344
345 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES;
346 module_param(ql2xnvme_queues, uint, S_IRUGO);
347 MODULE_PARM_DESC(ql2xnvme_queues,
348 "Number of NVMe Queues that can be configured.\n"
349 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n"
350 "1 - Minimum number of queues supported\n"
351 "8 - Default value");
352
353 int ql2xfc2target = 1;
354 module_param(ql2xfc2target, int, 0444);
355 MODULE_PARM_DESC(qla2xfc2target,
356 "Enables FC2 Target support. "
357 "0 - FC2 Target support is disabled. "
358 "1 - FC2 Target support is enabled (default).");
359
360 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
361 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
362
363 /* TODO Convert to inlines
364 *
365 * Timer routines
366 */
367
368 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,unsigned long interval)369 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
370 {
371 timer_setup(&vha->timer, qla2x00_timer, 0);
372 vha->timer.expires = jiffies + interval * HZ;
373 add_timer(&vha->timer);
374 vha->timer_active = 1;
375 }
376
377 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)378 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
379 {
380 /* Currently used for 82XX only. */
381 if (vha->device_flags & DFLG_DEV_FAILED) {
382 ql_dbg(ql_dbg_timer, vha, 0x600d,
383 "Device in a failed state, returning.\n");
384 return;
385 }
386
387 mod_timer(&vha->timer, jiffies + interval * HZ);
388 }
389
390 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)391 qla2x00_stop_timer(scsi_qla_host_t *vha)
392 {
393 timer_delete_sync(&vha->timer);
394 vha->timer_active = 0;
395 }
396
397 static int qla2x00_do_dpc(void *data);
398
399 static void qla2x00_rst_aen(scsi_qla_host_t *);
400
401 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
402 struct req_que **, struct rsp_que **);
403 static void qla2x00_free_fw_dump(struct qla_hw_data *);
404 static void qla2x00_mem_free(struct qla_hw_data *);
405 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
406 struct qla_qpair *qpair);
407
408 /* -------------------------------------------------------------------------- */
qla_init_base_qpair(struct scsi_qla_host * vha,struct req_que * req,struct rsp_que * rsp)409 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
410 struct rsp_que *rsp)
411 {
412 struct qla_hw_data *ha = vha->hw;
413
414 rsp->qpair = ha->base_qpair;
415 rsp->req = req;
416 ha->base_qpair->hw = ha;
417 ha->base_qpair->req = req;
418 ha->base_qpair->rsp = rsp;
419 ha->base_qpair->vha = vha;
420 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
421 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
422 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
423 ha->base_qpair->srb_mempool = ha->srb_mempool;
424 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
425 INIT_LIST_HEAD(&ha->base_qpair->dsd_list);
426 ha->base_qpair->enable_class_2 = ql2xenableclass2;
427 /* init qpair to this cpu. Will adjust at run time. */
428 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
429 ha->base_qpair->pdev = ha->pdev;
430
431 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
432 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
433 }
434
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)435 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
436 struct rsp_que *rsp)
437 {
438 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
439
440 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
441 GFP_KERNEL);
442 if (!ha->req_q_map) {
443 ql_log(ql_log_fatal, vha, 0x003b,
444 "Unable to allocate memory for request queue ptrs.\n");
445 goto fail_req_map;
446 }
447
448 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
449 GFP_KERNEL);
450 if (!ha->rsp_q_map) {
451 ql_log(ql_log_fatal, vha, 0x003c,
452 "Unable to allocate memory for response queue ptrs.\n");
453 goto fail_rsp_map;
454 }
455
456 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
457 if (ha->base_qpair == NULL) {
458 ql_log(ql_log_warn, vha, 0x00e0,
459 "Failed to allocate base queue pair memory.\n");
460 goto fail_base_qpair;
461 }
462
463 qla_init_base_qpair(vha, req, rsp);
464
465 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
466 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
467 GFP_KERNEL);
468 if (!ha->queue_pair_map) {
469 ql_log(ql_log_fatal, vha, 0x0180,
470 "Unable to allocate memory for queue pair ptrs.\n");
471 goto fail_qpair_map;
472 }
473 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) {
474 kfree(ha->queue_pair_map);
475 ha->queue_pair_map = NULL;
476 goto fail_qpair_map;
477 }
478 }
479
480 /*
481 * Make sure we record at least the request and response queue zero in
482 * case we need to free them if part of the probe fails.
483 */
484 ha->rsp_q_map[0] = rsp;
485 ha->req_q_map[0] = req;
486 set_bit(0, ha->rsp_qid_map);
487 set_bit(0, ha->req_qid_map);
488 return 0;
489
490 fail_qpair_map:
491 kfree(ha->base_qpair);
492 ha->base_qpair = NULL;
493 fail_base_qpair:
494 kfree(ha->rsp_q_map);
495 ha->rsp_q_map = NULL;
496 fail_rsp_map:
497 kfree(ha->req_q_map);
498 ha->req_q_map = NULL;
499 fail_req_map:
500 return -ENOMEM;
501 }
502
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)503 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
504 {
505 if (IS_QLAFX00(ha)) {
506 if (req && req->ring_fx00)
507 dma_free_coherent(&ha->pdev->dev,
508 (req->length_fx00 + 1) * sizeof(request_t),
509 req->ring_fx00, req->dma_fx00);
510 } else if (req && req->ring)
511 dma_free_coherent(&ha->pdev->dev,
512 (req->length + 1) * sizeof(request_t),
513 req->ring, req->dma);
514
515 if (req)
516 kfree(req->outstanding_cmds);
517
518 kfree(req);
519 }
520
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)521 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
522 {
523 if (IS_QLAFX00(ha)) {
524 if (rsp && rsp->ring_fx00)
525 dma_free_coherent(&ha->pdev->dev,
526 (rsp->length_fx00 + 1) * sizeof(request_t),
527 rsp->ring_fx00, rsp->dma_fx00);
528 } else if (rsp && rsp->ring) {
529 dma_free_coherent(&ha->pdev->dev,
530 (rsp->length + 1) * sizeof(response_t),
531 rsp->ring, rsp->dma);
532 }
533 kfree(rsp);
534 }
535
qla2x00_free_queues(struct qla_hw_data * ha)536 static void qla2x00_free_queues(struct qla_hw_data *ha)
537 {
538 struct req_que *req;
539 struct rsp_que *rsp;
540 int cnt;
541 unsigned long flags;
542
543 if (ha->queue_pair_map) {
544 kfree(ha->queue_pair_map);
545 ha->queue_pair_map = NULL;
546 }
547 if (ha->base_qpair) {
548 kfree(ha->base_qpair);
549 ha->base_qpair = NULL;
550 }
551
552 qla_mapq_free_qp_cpu_map(ha);
553 spin_lock_irqsave(&ha->hardware_lock, flags);
554 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
555 if (!test_bit(cnt, ha->req_qid_map))
556 continue;
557
558 req = ha->req_q_map[cnt];
559 clear_bit(cnt, ha->req_qid_map);
560 ha->req_q_map[cnt] = NULL;
561
562 spin_unlock_irqrestore(&ha->hardware_lock, flags);
563 qla2x00_free_req_que(ha, req);
564 spin_lock_irqsave(&ha->hardware_lock, flags);
565 }
566 spin_unlock_irqrestore(&ha->hardware_lock, flags);
567
568 kfree(ha->req_q_map);
569 ha->req_q_map = NULL;
570
571
572 spin_lock_irqsave(&ha->hardware_lock, flags);
573 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
574 if (!test_bit(cnt, ha->rsp_qid_map))
575 continue;
576
577 rsp = ha->rsp_q_map[cnt];
578 clear_bit(cnt, ha->rsp_qid_map);
579 ha->rsp_q_map[cnt] = NULL;
580 spin_unlock_irqrestore(&ha->hardware_lock, flags);
581 qla2x00_free_rsp_que(ha, rsp);
582 spin_lock_irqsave(&ha->hardware_lock, flags);
583 }
584 spin_unlock_irqrestore(&ha->hardware_lock, flags);
585
586 kfree(ha->rsp_q_map);
587 ha->rsp_q_map = NULL;
588 }
589
590 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)591 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
592 {
593 struct qla_hw_data *ha = vha->hw;
594 static const char *const pci_bus_modes[] = {
595 "33", "66", "100", "133",
596 };
597 uint16_t pci_bus;
598
599 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
600 if (pci_bus) {
601 snprintf(str, str_len, "PCI-X (%s MHz)",
602 pci_bus_modes[pci_bus]);
603 } else {
604 pci_bus = (ha->pci_attr & BIT_8) >> 8;
605 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
606 }
607
608 return str;
609 }
610
611 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)612 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
613 {
614 static const char *const pci_bus_modes[] = {
615 "33", "66", "100", "133",
616 };
617 struct qla_hw_data *ha = vha->hw;
618 uint32_t pci_bus;
619
620 if (pci_is_pcie(ha->pdev)) {
621 uint32_t lstat, lspeed, lwidth;
622 const char *speed_str;
623
624 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
625 lspeed = FIELD_GET(PCI_EXP_LNKCAP_SLS, lstat);
626 lwidth = FIELD_GET(PCI_EXP_LNKCAP_MLW, lstat);
627
628 switch (lspeed) {
629 case 1:
630 speed_str = "2.5GT/s";
631 break;
632 case 2:
633 speed_str = "5.0GT/s";
634 break;
635 case 3:
636 speed_str = "8.0GT/s";
637 break;
638 case 4:
639 speed_str = "16.0GT/s";
640 break;
641 default:
642 speed_str = "<unknown>";
643 break;
644 }
645 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
646
647 return str;
648 }
649
650 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
651 if (pci_bus == 0 || pci_bus == 8)
652 snprintf(str, str_len, "PCI (%s MHz)",
653 pci_bus_modes[pci_bus >> 3]);
654 else
655 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
656 pci_bus & 4 ? 2 : 1,
657 pci_bus_modes[pci_bus & 3]);
658
659 return str;
660 }
661
662 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)663 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
664 {
665 char un_str[10];
666 struct qla_hw_data *ha = vha->hw;
667
668 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
669 ha->fw_minor_version, ha->fw_subminor_version);
670
671 if (ha->fw_attributes & BIT_9) {
672 strcat(str, "FLX");
673 return (str);
674 }
675
676 switch (ha->fw_attributes & 0xFF) {
677 case 0x7:
678 strcat(str, "EF");
679 break;
680 case 0x17:
681 strcat(str, "TP");
682 break;
683 case 0x37:
684 strcat(str, "IP");
685 break;
686 case 0x77:
687 strcat(str, "VI");
688 break;
689 default:
690 sprintf(un_str, "(%x)", ha->fw_attributes);
691 strcat(str, un_str);
692 break;
693 }
694 if (ha->fw_attributes & 0x100)
695 strcat(str, "X");
696
697 return (str);
698 }
699
700 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)701 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
702 {
703 struct qla_hw_data *ha = vha->hw;
704
705 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
706 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
707 return str;
708 }
709
qla2x00_sp_free_dma(srb_t * sp)710 void qla2x00_sp_free_dma(srb_t *sp)
711 {
712 struct qla_hw_data *ha = sp->vha->hw;
713 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
714
715 if (sp->flags & SRB_DMA_VALID) {
716 scsi_dma_unmap(cmd);
717 sp->flags &= ~SRB_DMA_VALID;
718 }
719
720 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
721 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
722 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
723 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
724 }
725
726 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
727 /* List assured to be having elements */
728 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
729 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
730 }
731
732 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
733 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
734
735 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
736 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
737 }
738
739 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
740 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
741
742 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
743 ctx1->fcp_cmnd_dma);
744 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
745 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
746 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
747 }
748
749 if (sp->flags & SRB_GOT_BUF)
750 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
751 }
752
qla2x00_sp_compl(srb_t * sp,int res)753 void qla2x00_sp_compl(srb_t *sp, int res)
754 {
755 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
756 struct completion *comp = sp->comp;
757
758 /* kref: INIT */
759 kref_put(&sp->cmd_kref, qla2x00_sp_release);
760 cmd->result = res;
761 sp->type = 0;
762 scsi_done(cmd);
763 if (comp)
764 complete(comp);
765 }
766
qla2xxx_qpair_sp_free_dma(srb_t * sp)767 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
768 {
769 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
770 struct qla_hw_data *ha = sp->fcport->vha->hw;
771
772 if (sp->flags & SRB_DMA_VALID) {
773 scsi_dma_unmap(cmd);
774 sp->flags &= ~SRB_DMA_VALID;
775 }
776
777 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
778 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
779 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
780 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
781 }
782
783 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
784 /* List assured to be having elements */
785 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
786 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
787 }
788
789 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
790 struct crc_context *difctx = sp->u.scmd.crc_ctx;
791 struct dsd_dma *dif_dsd, *nxt_dsd;
792
793 list_for_each_entry_safe(dif_dsd, nxt_dsd,
794 &difctx->ldif_dma_hndl_list, list) {
795 list_del(&dif_dsd->list);
796 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
797 dif_dsd->dsd_list_dma);
798 kfree(dif_dsd);
799 difctx->no_dif_bundl--;
800 }
801
802 list_for_each_entry_safe(dif_dsd, nxt_dsd,
803 &difctx->ldif_dsd_list, list) {
804 list_del(&dif_dsd->list);
805 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
806 dif_dsd->dsd_list_dma);
807 kfree(dif_dsd);
808 difctx->no_ldif_dsd--;
809 }
810
811 if (difctx->no_ldif_dsd) {
812 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
813 "%s: difctx->no_ldif_dsd=%x\n",
814 __func__, difctx->no_ldif_dsd);
815 }
816
817 if (difctx->no_dif_bundl) {
818 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
819 "%s: difctx->no_dif_bundl=%x\n",
820 __func__, difctx->no_dif_bundl);
821 }
822 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
823 }
824
825 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
826 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
827
828 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
829 ctx1->fcp_cmnd_dma);
830 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
831 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
832 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
833 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
834 }
835
836 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
837 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
838
839 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
840 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
841 }
842
843 if (sp->flags & SRB_GOT_BUF)
844 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
845 }
846
qla2xxx_qpair_sp_compl(srb_t * sp,int res)847 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
848 {
849 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
850 struct completion *comp = sp->comp;
851
852 /* ref: INIT */
853 kref_put(&sp->cmd_kref, qla2x00_sp_release);
854 cmd->result = res;
855 sp->type = 0;
856 scsi_done(cmd);
857 if (comp)
858 complete(comp);
859 }
860
861 static int
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)862 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
863 {
864 scsi_qla_host_t *vha = shost_priv(host);
865 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
866 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
867 struct qla_hw_data *ha = vha->hw;
868 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
869 srb_t *sp;
870 int rval;
871
872 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
873 WARN_ON_ONCE(!rport)) {
874 cmd->result = DID_NO_CONNECT << 16;
875 goto qc24_fail_command;
876 }
877
878 if (ha->mqenable) {
879 uint32_t tag;
880 uint16_t hwq;
881 struct qla_qpair *qpair = NULL;
882
883 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
884 hwq = blk_mq_unique_tag_to_hwq(tag);
885 qpair = ha->queue_pair_map[hwq];
886
887 if (qpair)
888 return qla2xxx_mqueuecommand(host, cmd, qpair);
889 }
890
891 if (ha->flags.eeh_busy) {
892 if (ha->flags.pci_channel_io_perm_failure) {
893 ql_dbg(ql_dbg_aer, vha, 0x9010,
894 "PCI Channel IO permanent failure, exiting "
895 "cmd=%p.\n", cmd);
896 cmd->result = DID_NO_CONNECT << 16;
897 } else {
898 ql_dbg(ql_dbg_aer, vha, 0x9011,
899 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
900 cmd->result = DID_REQUEUE << 16;
901 }
902 goto qc24_fail_command;
903 }
904
905 rval = fc_remote_port_chkready(rport);
906 if (rval) {
907 cmd->result = rval;
908 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
909 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
910 cmd, rval);
911 goto qc24_fail_command;
912 }
913
914 if (!vha->flags.difdix_supported &&
915 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
916 ql_dbg(ql_dbg_io, vha, 0x3004,
917 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
918 cmd);
919 cmd->result = DID_NO_CONNECT << 16;
920 goto qc24_fail_command;
921 }
922
923 if (!fcport || fcport->deleted) {
924 cmd->result = DID_IMM_RETRY << 16;
925 goto qc24_fail_command;
926 }
927
928 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
929 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
930 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
931 ql_dbg(ql_dbg_io, vha, 0x3005,
932 "Returning DNC, fcport_state=%d loop_state=%d.\n",
933 atomic_read(&fcport->state),
934 atomic_read(&base_vha->loop_state));
935 cmd->result = DID_NO_CONNECT << 16;
936 goto qc24_fail_command;
937 }
938 goto qc24_target_busy;
939 }
940
941 /*
942 * Return target busy if we've received a non-zero retry_delay_timer
943 * in a FCP_RSP.
944 */
945 if (fcport->retry_delay_timestamp == 0) {
946 /* retry delay not set */
947 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
948 fcport->retry_delay_timestamp = 0;
949 else
950 goto qc24_target_busy;
951
952 sp = scsi_cmd_priv(cmd);
953 /* ref: INIT */
954 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
955
956 sp->u.scmd.cmd = cmd;
957 sp->type = SRB_SCSI_CMD;
958 sp->free = qla2x00_sp_free_dma;
959 sp->done = qla2x00_sp_compl;
960
961 rval = ha->isp_ops->start_scsi(sp);
962 if (rval != QLA_SUCCESS) {
963 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
964 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
965 goto qc24_host_busy_free_sp;
966 }
967
968 return 0;
969
970 qc24_host_busy_free_sp:
971 /* ref: INIT */
972 kref_put(&sp->cmd_kref, qla2x00_sp_release);
973
974 qc24_target_busy:
975 return SCSI_MLQUEUE_TARGET_BUSY;
976
977 qc24_fail_command:
978 scsi_done(cmd);
979
980 return 0;
981 }
982
983 /* For MQ supported I/O */
984 int
qla2xxx_mqueuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd,struct qla_qpair * qpair)985 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
986 struct qla_qpair *qpair)
987 {
988 scsi_qla_host_t *vha = shost_priv(host);
989 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
990 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
991 struct qla_hw_data *ha = vha->hw;
992 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
993 srb_t *sp;
994 int rval;
995
996 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16);
997 if (rval) {
998 cmd->result = rval;
999 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
1000 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
1001 cmd, rval);
1002 goto qc24_fail_command;
1003 }
1004
1005 if (!qpair->online) {
1006 ql_dbg(ql_dbg_io, vha, 0x3077,
1007 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
1008 cmd->result = DID_NO_CONNECT << 16;
1009 goto qc24_fail_command;
1010 }
1011
1012 if (!fcport || fcport->deleted) {
1013 cmd->result = DID_IMM_RETRY << 16;
1014 goto qc24_fail_command;
1015 }
1016
1017 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
1018 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1019 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1020 ql_dbg(ql_dbg_io, vha, 0x3077,
1021 "Returning DNC, fcport_state=%d loop_state=%d.\n",
1022 atomic_read(&fcport->state),
1023 atomic_read(&base_vha->loop_state));
1024 cmd->result = DID_NO_CONNECT << 16;
1025 goto qc24_fail_command;
1026 }
1027 goto qc24_target_busy;
1028 }
1029
1030 /*
1031 * Return target busy if we've received a non-zero retry_delay_timer
1032 * in a FCP_RSP.
1033 */
1034 if (fcport->retry_delay_timestamp == 0) {
1035 /* retry delay not set */
1036 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1037 fcport->retry_delay_timestamp = 0;
1038 else
1039 goto qc24_target_busy;
1040
1041 sp = scsi_cmd_priv(cmd);
1042 /* ref: INIT */
1043 qla2xxx_init_sp(sp, vha, qpair, fcport);
1044
1045 sp->u.scmd.cmd = cmd;
1046 sp->type = SRB_SCSI_CMD;
1047 sp->free = qla2xxx_qpair_sp_free_dma;
1048 sp->done = qla2xxx_qpair_sp_compl;
1049
1050 rval = ha->isp_ops->start_scsi_mq(sp);
1051 if (rval != QLA_SUCCESS) {
1052 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1053 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1054 goto qc24_host_busy_free_sp;
1055 }
1056
1057 return 0;
1058
1059 qc24_host_busy_free_sp:
1060 /* ref: INIT */
1061 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1062
1063 qc24_target_busy:
1064 return SCSI_MLQUEUE_TARGET_BUSY;
1065
1066 qc24_fail_command:
1067 scsi_done(cmd);
1068
1069 return 0;
1070 }
1071
1072 /*
1073 * qla2x00_wait_for_hba_online
1074 * Wait till the HBA is online after going through
1075 * <= MAX_RETRIES_OF_ISP_ABORT or
1076 * finally HBA is disabled ie marked offline
1077 *
1078 * Input:
1079 * ha - pointer to host adapter structure
1080 *
1081 * Note:
1082 * Does context switching-Release SPIN_LOCK
1083 * (if any) before calling this routine.
1084 *
1085 * Return:
1086 * Success (Adapter is online) : 0
1087 * Failed (Adapter is offline/disabled) : 1
1088 */
1089 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)1090 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1091 {
1092 int return_status;
1093 unsigned long wait_online;
1094 struct qla_hw_data *ha = vha->hw;
1095 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1096
1097 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1098 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1099 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1100 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1101 ha->dpc_active) && time_before(jiffies, wait_online)) {
1102
1103 msleep(1000);
1104 }
1105 if (base_vha->flags.online)
1106 return_status = QLA_SUCCESS;
1107 else
1108 return_status = QLA_FUNCTION_FAILED;
1109
1110 return (return_status);
1111 }
1112
test_fcport_count(scsi_qla_host_t * vha)1113 static inline int test_fcport_count(scsi_qla_host_t *vha)
1114 {
1115 struct qla_hw_data *ha = vha->hw;
1116 unsigned long flags;
1117 int res;
1118 /* Return 0 = sleep, x=wake */
1119
1120 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1121 ql_dbg(ql_dbg_init, vha, 0x00ec,
1122 "tgt %p, fcport_count=%d\n",
1123 vha, vha->fcport_count);
1124 res = (vha->fcport_count == 0);
1125 if (res) {
1126 struct fc_port *fcport;
1127
1128 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1129 if (fcport->deleted != QLA_SESS_DELETED) {
1130 /* session(s) may not be fully logged in
1131 * (ie fcport_count=0), but session
1132 * deletion thread(s) may be inflight.
1133 */
1134
1135 res = 0;
1136 break;
1137 }
1138 }
1139 }
1140 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1141
1142 return res;
1143 }
1144
1145 /*
1146 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1147 * it has dependency on UNLOADING flag to stop device discovery
1148 */
1149 void
qla2x00_wait_for_sess_deletion(scsi_qla_host_t * vha)1150 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1151 {
1152 u8 i;
1153
1154 qla2x00_mark_all_devices_lost(vha);
1155
1156 for (i = 0; i < 10; i++) {
1157 if (wait_event_timeout(vha->fcport_waitQ,
1158 test_fcport_count(vha), HZ) > 0)
1159 break;
1160 }
1161
1162 flush_workqueue(vha->hw->wq);
1163 }
1164
1165 /*
1166 * qla2x00_wait_for_hba_ready
1167 * Wait till the HBA is ready before doing driver unload
1168 *
1169 * Input:
1170 * ha - pointer to host adapter structure
1171 *
1172 * Note:
1173 * Does context switching-Release SPIN_LOCK
1174 * (if any) before calling this routine.
1175 *
1176 */
1177 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)1178 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1179 {
1180 struct qla_hw_data *ha = vha->hw;
1181 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1182
1183 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1184 ha->flags.mbox_busy) ||
1185 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1186 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1187 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1188 break;
1189 msleep(1000);
1190 }
1191 }
1192
1193 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)1194 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1195 {
1196 int return_status;
1197 unsigned long wait_reset;
1198 struct qla_hw_data *ha = vha->hw;
1199 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1200
1201 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1202 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1203 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1204 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1205 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1206
1207 msleep(1000);
1208
1209 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1210 ha->flags.chip_reset_done)
1211 break;
1212 }
1213 if (ha->flags.chip_reset_done)
1214 return_status = QLA_SUCCESS;
1215 else
1216 return_status = QLA_FUNCTION_FAILED;
1217
1218 return return_status;
1219 }
1220
1221 /**************************************************************************
1222 * qla2xxx_eh_abort
1223 *
1224 * Description:
1225 * The abort function will abort the specified command.
1226 *
1227 * Input:
1228 * cmd = Linux SCSI command packet to be aborted.
1229 *
1230 * Returns:
1231 * Either SUCCESS or FAILED.
1232 *
1233 * Note:
1234 * Only return FAILED if command not returned by firmware.
1235 **************************************************************************/
1236 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)1237 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1238 {
1239 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1240 DECLARE_COMPLETION_ONSTACK(comp);
1241 srb_t *sp;
1242 int ret;
1243 unsigned int id;
1244 uint64_t lun;
1245 int rval;
1246 struct qla_hw_data *ha = vha->hw;
1247 uint32_t ratov_j;
1248 struct qla_qpair *qpair;
1249 unsigned long flags;
1250 int fast_fail_status = SUCCESS;
1251
1252 if (qla2x00_isp_reg_stat(ha)) {
1253 ql_log(ql_log_info, vha, 0x8042,
1254 "PCI/Register disconnect, exiting.\n");
1255 qla_pci_set_eeh_busy(vha);
1256 return FAILED;
1257 }
1258
1259 /* Save any FAST_IO_FAIL value to return later if abort succeeds */
1260 ret = fc_block_scsi_eh(cmd);
1261 if (ret != 0)
1262 fast_fail_status = ret;
1263
1264 sp = scsi_cmd_priv(cmd);
1265 qpair = sp->qpair;
1266
1267 vha->cmd_timeout_cnt++;
1268
1269 if ((sp->fcport && sp->fcport->deleted) || !qpair)
1270 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
1271
1272 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1273 sp->comp = ∁
1274 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1275
1276
1277 id = cmd->device->id;
1278 lun = cmd->device->lun;
1279
1280 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1281 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1282 vha->host_no, id, lun, sp, cmd, sp->handle);
1283
1284 /*
1285 * Abort will release the original Command/sp from FW. Let the
1286 * original command call scsi_done. In return, he will wakeup
1287 * this sleeping thread.
1288 */
1289 rval = ha->isp_ops->abort_command(sp);
1290
1291 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1292 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1293
1294 /* Wait for the command completion. */
1295 ratov_j = ha->r_a_tov / 10 * 4;
1296 ratov_j = secs_to_jiffies(ratov_j);
1297 switch (rval) {
1298 case QLA_SUCCESS:
1299 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1300 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1301 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1302 __func__, ha->r_a_tov/10);
1303 ret = FAILED;
1304 } else {
1305 ret = fast_fail_status;
1306 }
1307 break;
1308 default:
1309 ret = FAILED;
1310 break;
1311 }
1312
1313 sp->comp = NULL;
1314
1315 ql_log(ql_log_info, vha, 0x801c,
1316 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1317 vha->host_no, id, lun, ret);
1318
1319 return ret;
1320 }
1321
1322 #define ABORT_POLLING_PERIOD 1000
1323 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1324
1325 /*
1326 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1327 */
1328 static int
__qla2x00_eh_wait_for_pending_commands(struct qla_qpair * qpair,unsigned int t,uint64_t l,enum nexus_wait_type type)1329 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t,
1330 uint64_t l, enum nexus_wait_type type)
1331 {
1332 int cnt, match, status;
1333 unsigned long flags;
1334 scsi_qla_host_t *vha = qpair->vha;
1335 struct req_que *req = qpair->req;
1336 srb_t *sp;
1337 struct scsi_cmnd *cmd;
1338 unsigned long wait_iter = ABORT_WAIT_ITER;
1339 bool found;
1340 struct qla_hw_data *ha = vha->hw;
1341
1342 status = QLA_SUCCESS;
1343
1344 while (wait_iter--) {
1345 found = false;
1346
1347 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1348 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1349 sp = req->outstanding_cmds[cnt];
1350 if (!sp)
1351 continue;
1352 if (sp->type != SRB_SCSI_CMD)
1353 continue;
1354 if (vha->vp_idx != sp->vha->vp_idx)
1355 continue;
1356 match = 0;
1357 cmd = GET_CMD_SP(sp);
1358 switch (type) {
1359 case WAIT_HOST:
1360 match = 1;
1361 break;
1362 case WAIT_TARGET:
1363 if (sp->fcport)
1364 match = sp->fcport->d_id.b24 == t;
1365 else
1366 match = 0;
1367 break;
1368 case WAIT_LUN:
1369 if (sp->fcport)
1370 match = (sp->fcport->d_id.b24 == t &&
1371 cmd->device->lun == l);
1372 else
1373 match = 0;
1374 break;
1375 }
1376 if (!match)
1377 continue;
1378
1379 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1380
1381 if (unlikely(pci_channel_offline(ha->pdev)) ||
1382 ha->flags.eeh_busy) {
1383 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1384 "Return:eh_wait.\n");
1385 return status;
1386 }
1387
1388 /*
1389 * SRB_SCSI_CMD is still in the outstanding_cmds array.
1390 * it means scsi_done has not called. Wait for it to
1391 * clear from outstanding_cmds.
1392 */
1393 msleep(ABORT_POLLING_PERIOD);
1394 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1395 found = true;
1396 }
1397 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1398
1399 if (!found)
1400 break;
1401 }
1402
1403 if (wait_iter == -1)
1404 status = QLA_FUNCTION_FAILED;
1405
1406 return status;
1407 }
1408
1409 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1410 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1411 uint64_t l, enum nexus_wait_type type)
1412 {
1413 struct qla_qpair *qpair;
1414 struct qla_hw_data *ha = vha->hw;
1415 int i, status = QLA_SUCCESS;
1416
1417 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
1418 type);
1419 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
1420 qpair = ha->queue_pair_map[i];
1421 if (!qpair)
1422 continue;
1423 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l,
1424 type);
1425 }
1426 return status;
1427 }
1428
1429 static char *reset_errors[] = {
1430 "HBA not online",
1431 "HBA not ready",
1432 "Task management failed",
1433 "Waiting for command completions",
1434 };
1435
1436 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1437 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1438 {
1439 struct scsi_device *sdev = cmd->device;
1440 scsi_qla_host_t *vha = shost_priv(sdev->host);
1441 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1442 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1443 struct qla_hw_data *ha = vha->hw;
1444 int err;
1445
1446 if (qla2x00_isp_reg_stat(ha)) {
1447 ql_log(ql_log_info, vha, 0x803e,
1448 "PCI/Register disconnect, exiting.\n");
1449 qla_pci_set_eeh_busy(vha);
1450 return FAILED;
1451 }
1452
1453 if (!fcport) {
1454 return FAILED;
1455 }
1456
1457 err = fc_block_rport(rport);
1458 if (err != 0)
1459 return err;
1460
1461 if (fcport->deleted)
1462 return FAILED;
1463
1464 ql_log(ql_log_info, vha, 0x8009,
1465 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
1466 sdev->id, sdev->lun, cmd);
1467
1468 err = 0;
1469 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1470 ql_log(ql_log_warn, vha, 0x800a,
1471 "Wait for hba online failed for cmd=%p.\n", cmd);
1472 goto eh_reset_failed;
1473 }
1474 err = 2;
1475 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
1476 != QLA_SUCCESS) {
1477 ql_log(ql_log_warn, vha, 0x800c,
1478 "do_reset failed for cmd=%p.\n", cmd);
1479 goto eh_reset_failed;
1480 }
1481 err = 3;
1482 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24,
1483 cmd->device->lun,
1484 WAIT_LUN) != QLA_SUCCESS) {
1485 ql_log(ql_log_warn, vha, 0x800d,
1486 "wait for pending cmds failed for cmd=%p.\n", cmd);
1487 goto eh_reset_failed;
1488 }
1489
1490 ql_log(ql_log_info, vha, 0x800e,
1491 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n",
1492 vha->host_no, sdev->id, sdev->lun, cmd);
1493
1494 return SUCCESS;
1495
1496 eh_reset_failed:
1497 ql_log(ql_log_info, vha, 0x800f,
1498 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1499 reset_errors[err], vha->host_no, sdev->id, sdev->lun,
1500 cmd);
1501 vha->reset_cmd_err_cnt++;
1502 return FAILED;
1503 }
1504
1505 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1506 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1507 {
1508 struct scsi_device *sdev = cmd->device;
1509 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1510 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport));
1511 struct qla_hw_data *ha = vha->hw;
1512 fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
1513 int err;
1514
1515 if (qla2x00_isp_reg_stat(ha)) {
1516 ql_log(ql_log_info, vha, 0x803f,
1517 "PCI/Register disconnect, exiting.\n");
1518 qla_pci_set_eeh_busy(vha);
1519 return FAILED;
1520 }
1521
1522 if (!fcport) {
1523 return FAILED;
1524 }
1525
1526 err = fc_block_rport(rport);
1527 if (err != 0)
1528 return err;
1529
1530 if (fcport->deleted)
1531 return FAILED;
1532
1533 ql_log(ql_log_info, vha, 0x8009,
1534 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
1535 sdev->id, cmd);
1536
1537 err = 0;
1538 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1539 ql_log(ql_log_warn, vha, 0x800a,
1540 "Wait for hba online failed for cmd=%p.\n", cmd);
1541 goto eh_reset_failed;
1542 }
1543 err = 2;
1544 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
1545 ql_log(ql_log_warn, vha, 0x800c,
1546 "target_reset failed for cmd=%p.\n", cmd);
1547 goto eh_reset_failed;
1548 }
1549 err = 3;
1550 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0,
1551 WAIT_TARGET) != QLA_SUCCESS) {
1552 ql_log(ql_log_warn, vha, 0x800d,
1553 "wait for pending cmds failed for cmd=%p.\n", cmd);
1554 goto eh_reset_failed;
1555 }
1556
1557 ql_log(ql_log_info, vha, 0x800e,
1558 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n",
1559 vha->host_no, sdev->id, cmd);
1560
1561 return SUCCESS;
1562
1563 eh_reset_failed:
1564 ql_log(ql_log_info, vha, 0x800f,
1565 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1566 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1567 cmd);
1568 vha->reset_cmd_err_cnt++;
1569 return FAILED;
1570 }
1571
1572 /**************************************************************************
1573 * qla2xxx_eh_bus_reset
1574 *
1575 * Description:
1576 * The bus reset function will reset the bus and abort any executing
1577 * commands.
1578 *
1579 * Input:
1580 * cmd = Linux SCSI command packet of the command that cause the
1581 * bus reset.
1582 *
1583 * Returns:
1584 * SUCCESS/FAILURE (defined as macro in scsi.h).
1585 *
1586 **************************************************************************/
1587 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1588 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1589 {
1590 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1591 int ret = FAILED;
1592 unsigned int id;
1593 uint64_t lun;
1594 struct qla_hw_data *ha = vha->hw;
1595
1596 if (qla2x00_isp_reg_stat(ha)) {
1597 ql_log(ql_log_info, vha, 0x8040,
1598 "PCI/Register disconnect, exiting.\n");
1599 qla_pci_set_eeh_busy(vha);
1600 return FAILED;
1601 }
1602
1603 id = cmd->device->id;
1604 lun = cmd->device->lun;
1605
1606 if (qla2x00_chip_is_down(vha))
1607 return ret;
1608
1609 ql_log(ql_log_info, vha, 0x8012,
1610 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1611
1612 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1613 ql_log(ql_log_fatal, vha, 0x8013,
1614 "Wait for hba online failed board disabled.\n");
1615 goto eh_bus_reset_done;
1616 }
1617
1618 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1619 ret = SUCCESS;
1620
1621 if (ret == FAILED)
1622 goto eh_bus_reset_done;
1623
1624 /* Flush outstanding commands. */
1625 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1626 QLA_SUCCESS) {
1627 ql_log(ql_log_warn, vha, 0x8014,
1628 "Wait for pending commands failed.\n");
1629 ret = FAILED;
1630 }
1631
1632 eh_bus_reset_done:
1633 ql_log(ql_log_warn, vha, 0x802b,
1634 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1635 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1636
1637 return ret;
1638 }
1639
1640 /**************************************************************************
1641 * qla2xxx_eh_host_reset
1642 *
1643 * Description:
1644 * The reset function will reset the Adapter.
1645 *
1646 * Input:
1647 * cmd = Linux SCSI command packet of the command that cause the
1648 * adapter reset.
1649 *
1650 * Returns:
1651 * Either SUCCESS or FAILED.
1652 *
1653 * Note:
1654 **************************************************************************/
1655 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1656 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1657 {
1658 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1659 struct qla_hw_data *ha = vha->hw;
1660 int ret = FAILED;
1661 unsigned int id;
1662 uint64_t lun;
1663 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1664
1665 if (qla2x00_isp_reg_stat(ha)) {
1666 ql_log(ql_log_info, vha, 0x8041,
1667 "PCI/Register disconnect, exiting.\n");
1668 qla_pci_set_eeh_busy(vha);
1669 return SUCCESS;
1670 }
1671
1672 id = cmd->device->id;
1673 lun = cmd->device->lun;
1674
1675 ql_log(ql_log_info, vha, 0x8018,
1676 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1677
1678 /*
1679 * No point in issuing another reset if one is active. Also do not
1680 * attempt a reset if we are updating flash.
1681 */
1682 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1683 goto eh_host_reset_lock;
1684
1685 if (vha != base_vha) {
1686 if (qla2x00_vp_abort_isp(vha))
1687 goto eh_host_reset_lock;
1688 } else {
1689 if (IS_P3P_TYPE(vha->hw)) {
1690 if (!qla82xx_fcoe_ctx_reset(vha)) {
1691 /* Ctx reset success */
1692 ret = SUCCESS;
1693 goto eh_host_reset_lock;
1694 }
1695 /* fall thru if ctx reset failed */
1696 }
1697 if (ha->wq)
1698 flush_workqueue(ha->wq);
1699
1700 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1701 if (ha->isp_ops->abort_isp(base_vha)) {
1702 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1703 /* failed. schedule dpc to try */
1704 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1705
1706 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1707 ql_log(ql_log_warn, vha, 0x802a,
1708 "wait for hba online failed.\n");
1709 goto eh_host_reset_lock;
1710 }
1711 }
1712 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1713 }
1714
1715 /* Waiting for command to be returned to OS.*/
1716 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1717 QLA_SUCCESS)
1718 ret = SUCCESS;
1719
1720 eh_host_reset_lock:
1721 ql_log(ql_log_info, vha, 0x8017,
1722 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1723 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1724
1725 return ret;
1726 }
1727
1728 /*
1729 * qla2x00_loop_reset
1730 * Issue loop reset.
1731 *
1732 * Input:
1733 * ha = adapter block pointer.
1734 *
1735 * Returns:
1736 * 0 = success
1737 */
1738 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1739 qla2x00_loop_reset(scsi_qla_host_t *vha)
1740 {
1741 int ret;
1742 struct qla_hw_data *ha = vha->hw;
1743
1744 if (IS_QLAFX00(ha))
1745 return QLA_SUCCESS;
1746
1747 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1748 atomic_set(&vha->loop_state, LOOP_DOWN);
1749 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1750 qla2x00_mark_all_devices_lost(vha);
1751 ret = qla2x00_full_login_lip(vha);
1752 if (ret != QLA_SUCCESS) {
1753 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1754 "full_login_lip=%d.\n", ret);
1755 }
1756 }
1757
1758 if (ha->flags.enable_lip_reset) {
1759 ret = qla2x00_lip_reset(vha);
1760 if (ret != QLA_SUCCESS)
1761 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1762 "lip_reset failed (%d).\n", ret);
1763 }
1764
1765 /* Issue marker command only when we are going to start the I/O */
1766 vha->marker_needed = 1;
1767
1768 return QLA_SUCCESS;
1769 }
1770
1771 /*
1772 * The caller must ensure that no completion interrupts will happen
1773 * while this function is in progress.
1774 */
qla2x00_abort_srb(struct qla_qpair * qp,srb_t * sp,const int res,unsigned long * flags)1775 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1776 unsigned long *flags)
1777 __releases(qp->qp_lock_ptr)
1778 __acquires(qp->qp_lock_ptr)
1779 {
1780 DECLARE_COMPLETION_ONSTACK(comp);
1781 scsi_qla_host_t *vha = qp->vha;
1782 struct qla_hw_data *ha = vha->hw;
1783 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1784 int rval;
1785 bool ret_cmd;
1786 uint32_t ratov_j;
1787
1788 lockdep_assert_held(qp->qp_lock_ptr);
1789
1790 if (qla2x00_chip_is_down(vha)) {
1791 sp->done(sp, res);
1792 return;
1793 }
1794
1795 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1796 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1797 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1798 !qla2x00_isp_reg_stat(ha))) {
1799 if (sp->comp) {
1800 sp->done(sp, res);
1801 return;
1802 }
1803
1804 sp->comp = ∁
1805 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1806
1807 rval = ha->isp_ops->abort_command(sp);
1808 /* Wait for command completion. */
1809 ret_cmd = false;
1810 ratov_j = ha->r_a_tov / 10 * 4;
1811 ratov_j = secs_to_jiffies(ratov_j);
1812 switch (rval) {
1813 case QLA_SUCCESS:
1814 if (wait_for_completion_timeout(&comp, ratov_j)) {
1815 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1816 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1817 __func__, ha->r_a_tov/10);
1818 ret_cmd = true;
1819 }
1820 /* else FW return SP to driver */
1821 break;
1822 default:
1823 ret_cmd = true;
1824 break;
1825 }
1826
1827 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1828 switch (sp->type) {
1829 case SRB_SCSI_CMD:
1830 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd)))
1831 sp->done(sp, res);
1832 break;
1833 default:
1834 if (ret_cmd)
1835 sp->done(sp, res);
1836 break;
1837 }
1838 } else {
1839 sp->done(sp, res);
1840 }
1841 }
1842
1843 /*
1844 * The caller must ensure that no completion interrupts will happen
1845 * while this function is in progress.
1846 */
1847 static void
__qla2x00_abort_all_cmds(struct qla_qpair * qp,int res)1848 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1849 {
1850 int cnt;
1851 unsigned long flags;
1852 srb_t *sp;
1853 scsi_qla_host_t *vha = qp->vha;
1854 struct qla_hw_data *ha = vha->hw;
1855 struct req_que *req;
1856 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1857 struct qla_tgt_cmd *cmd;
1858
1859 if (!ha->req_q_map)
1860 return;
1861 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1862 req = qp->req;
1863 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1864 sp = req->outstanding_cmds[cnt];
1865 if (sp) {
1866 switch (sp->cmd_type) {
1867 case TYPE_SRB:
1868 qla2x00_abort_srb(qp, sp, res, &flags);
1869 break;
1870 case TYPE_TGT_CMD:
1871 if (!vha->hw->tgt.tgt_ops || !tgt ||
1872 qla_ini_mode_enabled(vha)) {
1873 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1874 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1875 vha->dpc_flags);
1876 continue;
1877 }
1878 cmd = (struct qla_tgt_cmd *)sp;
1879
1880 if (cmd->sg_mapped)
1881 qlt_unmap_sg(vha, cmd);
1882
1883 if (cmd->state == QLA_TGT_STATE_NEED_DATA) {
1884 cmd->aborted = 1;
1885 cmd->write_data_transferred = 0;
1886 cmd->state = QLA_TGT_STATE_DATA_IN;
1887 ha->tgt.tgt_ops->handle_data(cmd);
1888 } else {
1889 ha->tgt.tgt_ops->free_cmd(cmd);
1890 }
1891 break;
1892 case TYPE_TGT_TMCMD:
1893 /*
1894 * Currently, only ABTS response gets on the
1895 * outstanding_cmds[]
1896 */
1897 qlt_free_ul_mcmd(ha,
1898 (struct qla_tgt_mgmt_cmd *) sp);
1899 break;
1900 default:
1901 break;
1902 }
1903 req->outstanding_cmds[cnt] = NULL;
1904 }
1905 }
1906 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1907 }
1908
1909 /*
1910 * The caller must ensure that no completion interrupts will happen
1911 * while this function is in progress.
1912 */
1913 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1914 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1915 {
1916 int que;
1917 struct qla_hw_data *ha = vha->hw;
1918
1919 /* Continue only if initialization complete. */
1920 if (!ha->base_qpair)
1921 return;
1922 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1923
1924 if (!ha->queue_pair_map)
1925 return;
1926 for (que = 0; que < ha->max_qpairs; que++) {
1927 if (!ha->queue_pair_map[que])
1928 continue;
1929
1930 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1931 }
1932 }
1933
1934 static int
qla2xxx_sdev_init(struct scsi_device * sdev)1935 qla2xxx_sdev_init(struct scsi_device *sdev)
1936 {
1937 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1938
1939 if (!rport || fc_remote_port_chkready(rport))
1940 return -ENXIO;
1941
1942 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1943
1944 return 0;
1945 }
1946
1947 static int
qla2xxx_sdev_configure(struct scsi_device * sdev,struct queue_limits * lim)1948 qla2xxx_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim)
1949 {
1950 scsi_qla_host_t *vha = shost_priv(sdev->host);
1951 struct req_que *req = vha->req;
1952
1953 scsi_change_queue_depth(sdev, req->max_q_depth);
1954 return 0;
1955 }
1956
1957 static void
qla2xxx_sdev_destroy(struct scsi_device * sdev)1958 qla2xxx_sdev_destroy(struct scsi_device *sdev)
1959 {
1960 sdev->hostdata = NULL;
1961 }
1962
1963 /**
1964 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1965 * @ha: HA context
1966 *
1967 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1968 * supported addressing method.
1969 */
1970 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1971 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1972 {
1973 /* Assume a 32bit DMA mask. */
1974 ha->flags.enable_64bit_addressing = 0;
1975
1976 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1977 /* Any upper-dword bits set? */
1978 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1979 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1980 /* Ok, a 64bit DMA mask is applicable. */
1981 ha->flags.enable_64bit_addressing = 1;
1982 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1983 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1984 return;
1985 }
1986 }
1987
1988 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1989 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1990 }
1991
1992 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)1993 qla2x00_enable_intrs(struct qla_hw_data *ha)
1994 {
1995 unsigned long flags = 0;
1996 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1997
1998 spin_lock_irqsave(&ha->hardware_lock, flags);
1999 ha->interrupts_on = 1;
2000 /* enable risc and host interrupts */
2001 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
2002 rd_reg_word(®->ictrl);
2003 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2004
2005 }
2006
2007 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)2008 qla2x00_disable_intrs(struct qla_hw_data *ha)
2009 {
2010 unsigned long flags = 0;
2011 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2012
2013 spin_lock_irqsave(&ha->hardware_lock, flags);
2014 ha->interrupts_on = 0;
2015 /* disable risc and host interrupts */
2016 wrt_reg_word(®->ictrl, 0);
2017 rd_reg_word(®->ictrl);
2018 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2019 }
2020
2021 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)2022 qla24xx_enable_intrs(struct qla_hw_data *ha)
2023 {
2024 unsigned long flags = 0;
2025 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2026
2027 spin_lock_irqsave(&ha->hardware_lock, flags);
2028 ha->interrupts_on = 1;
2029 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT);
2030 rd_reg_dword(®->ictrl);
2031 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2032 }
2033
2034 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)2035 qla24xx_disable_intrs(struct qla_hw_data *ha)
2036 {
2037 unsigned long flags = 0;
2038 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2039
2040 if (IS_NOPOLLING_TYPE(ha))
2041 return;
2042 spin_lock_irqsave(&ha->hardware_lock, flags);
2043 ha->interrupts_on = 0;
2044 wrt_reg_dword(®->ictrl, 0);
2045 rd_reg_dword(®->ictrl);
2046 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2047 }
2048
2049 static int
qla2x00_iospace_config(struct qla_hw_data * ha)2050 qla2x00_iospace_config(struct qla_hw_data *ha)
2051 {
2052 resource_size_t pio;
2053 uint16_t msix;
2054
2055 if (pci_request_selected_regions(ha->pdev, ha->bars,
2056 QLA2XXX_DRIVER_NAME)) {
2057 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2058 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2059 pci_name(ha->pdev));
2060 goto iospace_error_exit;
2061 }
2062 if (!(ha->bars & 1))
2063 goto skip_pio;
2064
2065 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
2066 pio = pci_resource_start(ha->pdev, 0);
2067 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2068 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2069 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2070 "Invalid pci I/O region size (%s).\n",
2071 pci_name(ha->pdev));
2072 pio = 0;
2073 }
2074 } else {
2075 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2076 "Region #0 no a PIO resource (%s).\n",
2077 pci_name(ha->pdev));
2078 pio = 0;
2079 }
2080 ha->pio_address = pio;
2081 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2082 "PIO address=%llu.\n",
2083 (unsigned long long)ha->pio_address);
2084
2085 skip_pio:
2086 /* Use MMIO operations for all accesses. */
2087 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2088 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2089 "Region #1 not an MMIO resource (%s), aborting.\n",
2090 pci_name(ha->pdev));
2091 goto iospace_error_exit;
2092 }
2093 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2094 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2095 "Invalid PCI mem region size (%s), aborting.\n",
2096 pci_name(ha->pdev));
2097 goto iospace_error_exit;
2098 }
2099
2100 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2101 if (!ha->iobase) {
2102 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2103 "Cannot remap MMIO (%s), aborting.\n",
2104 pci_name(ha->pdev));
2105 goto iospace_error_exit;
2106 }
2107
2108 /* Determine queue resources */
2109 ha->max_req_queues = ha->max_rsp_queues = 1;
2110 ha->msix_count = QLA_BASE_VECTORS;
2111
2112 /* Check if FW supports MQ or not */
2113 if (!(ha->fw_attributes & BIT_6))
2114 goto mqiobase_exit;
2115
2116 if (!ql2xmqsupport || !ql2xnvmeenable ||
2117 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2118 goto mqiobase_exit;
2119
2120 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2121 pci_resource_len(ha->pdev, 3));
2122 if (ha->mqiobase) {
2123 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2124 "MQIO Base=%p.\n", ha->mqiobase);
2125 /* Read MSIX vector size of the board */
2126 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2127 ha->msix_count = msix + 1;
2128 /* Max queues are bounded by available msix vectors */
2129 /* MB interrupt uses 1 vector */
2130 ha->max_req_queues = ha->msix_count - 1;
2131 ha->max_rsp_queues = ha->max_req_queues;
2132 /* Queue pairs is the max value minus the base queue pair */
2133 ha->max_qpairs = ha->max_rsp_queues - 1;
2134 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2135 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2136
2137 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2138 "MSI-X vector count: %d.\n", ha->msix_count);
2139 } else
2140 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2141 "BAR 3 not enabled.\n");
2142
2143 mqiobase_exit:
2144 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2145 "MSIX Count: %d.\n", ha->msix_count);
2146 return (0);
2147
2148 iospace_error_exit:
2149 return (-ENOMEM);
2150 }
2151
2152
2153 static int
qla83xx_iospace_config(struct qla_hw_data * ha)2154 qla83xx_iospace_config(struct qla_hw_data *ha)
2155 {
2156 uint16_t msix;
2157
2158 if (pci_request_selected_regions(ha->pdev, ha->bars,
2159 QLA2XXX_DRIVER_NAME)) {
2160 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2161 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2162 pci_name(ha->pdev));
2163
2164 goto iospace_error_exit;
2165 }
2166
2167 /* Use MMIO operations for all accesses. */
2168 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2169 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2170 "Invalid pci I/O region size (%s).\n",
2171 pci_name(ha->pdev));
2172 goto iospace_error_exit;
2173 }
2174 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2175 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2176 "Invalid PCI mem region size (%s), aborting\n",
2177 pci_name(ha->pdev));
2178 goto iospace_error_exit;
2179 }
2180
2181 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2182 if (!ha->iobase) {
2183 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2184 "Cannot remap MMIO (%s), aborting.\n",
2185 pci_name(ha->pdev));
2186 goto iospace_error_exit;
2187 }
2188
2189 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2190 /* 83XX 26XX always use MQ type access for queues
2191 * - mbar 2, a.k.a region 4 */
2192 ha->max_req_queues = ha->max_rsp_queues = 1;
2193 ha->msix_count = QLA_BASE_VECTORS;
2194 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2195 pci_resource_len(ha->pdev, 4));
2196
2197 if (!ha->mqiobase) {
2198 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2199 "BAR2/region4 not enabled\n");
2200 goto mqiobase_exit;
2201 }
2202
2203 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2204 pci_resource_len(ha->pdev, 2));
2205 if (ha->msixbase) {
2206 /* Read MSIX vector size of the board */
2207 pci_read_config_word(ha->pdev,
2208 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2209 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2210 /*
2211 * By default, driver uses at least two msix vectors
2212 * (default & rspq)
2213 */
2214 if (ql2xmqsupport || ql2xnvmeenable) {
2215 /* MB interrupt uses 1 vector */
2216 ha->max_req_queues = ha->msix_count - 1;
2217
2218 /* ATIOQ needs 1 vector. That's 1 less QPair */
2219 if (QLA_TGT_MODE_ENABLED())
2220 ha->max_req_queues--;
2221
2222 ha->max_rsp_queues = ha->max_req_queues;
2223
2224 /* Queue pairs is the max value minus
2225 * the base queue pair */
2226 ha->max_qpairs = ha->max_req_queues - 1;
2227 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2228 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2229 }
2230 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2231 "MSI-X vector count: %d.\n", ha->msix_count);
2232 } else
2233 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2234 "BAR 1 not enabled.\n");
2235
2236 mqiobase_exit:
2237 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2238 "MSIX Count: %d.\n", ha->msix_count);
2239 return 0;
2240
2241 iospace_error_exit:
2242 return -ENOMEM;
2243 }
2244
2245 static struct isp_operations qla2100_isp_ops = {
2246 .pci_config = qla2100_pci_config,
2247 .reset_chip = qla2x00_reset_chip,
2248 .chip_diag = qla2x00_chip_diag,
2249 .config_rings = qla2x00_config_rings,
2250 .reset_adapter = qla2x00_reset_adapter,
2251 .nvram_config = qla2x00_nvram_config,
2252 .update_fw_options = qla2x00_update_fw_options,
2253 .load_risc = qla2x00_load_risc,
2254 .pci_info_str = qla2x00_pci_info_str,
2255 .fw_version_str = qla2x00_fw_version_str,
2256 .intr_handler = qla2100_intr_handler,
2257 .enable_intrs = qla2x00_enable_intrs,
2258 .disable_intrs = qla2x00_disable_intrs,
2259 .abort_command = qla2x00_abort_command,
2260 .target_reset = qla2x00_abort_target,
2261 .lun_reset = qla2x00_lun_reset,
2262 .fabric_login = qla2x00_login_fabric,
2263 .fabric_logout = qla2x00_fabric_logout,
2264 .calc_req_entries = qla2x00_calc_iocbs_32,
2265 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2266 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2267 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2268 .read_nvram = qla2x00_read_nvram_data,
2269 .write_nvram = qla2x00_write_nvram_data,
2270 .fw_dump = qla2100_fw_dump,
2271 .beacon_on = NULL,
2272 .beacon_off = NULL,
2273 .beacon_blink = NULL,
2274 .read_optrom = qla2x00_read_optrom_data,
2275 .write_optrom = qla2x00_write_optrom_data,
2276 .get_flash_version = qla2x00_get_flash_version,
2277 .start_scsi = qla2x00_start_scsi,
2278 .start_scsi_mq = NULL,
2279 .abort_isp = qla2x00_abort_isp,
2280 .iospace_config = qla2x00_iospace_config,
2281 .initialize_adapter = qla2x00_initialize_adapter,
2282 };
2283
2284 static struct isp_operations qla2300_isp_ops = {
2285 .pci_config = qla2300_pci_config,
2286 .reset_chip = qla2x00_reset_chip,
2287 .chip_diag = qla2x00_chip_diag,
2288 .config_rings = qla2x00_config_rings,
2289 .reset_adapter = qla2x00_reset_adapter,
2290 .nvram_config = qla2x00_nvram_config,
2291 .update_fw_options = qla2x00_update_fw_options,
2292 .load_risc = qla2x00_load_risc,
2293 .pci_info_str = qla2x00_pci_info_str,
2294 .fw_version_str = qla2x00_fw_version_str,
2295 .intr_handler = qla2300_intr_handler,
2296 .enable_intrs = qla2x00_enable_intrs,
2297 .disable_intrs = qla2x00_disable_intrs,
2298 .abort_command = qla2x00_abort_command,
2299 .target_reset = qla2x00_abort_target,
2300 .lun_reset = qla2x00_lun_reset,
2301 .fabric_login = qla2x00_login_fabric,
2302 .fabric_logout = qla2x00_fabric_logout,
2303 .calc_req_entries = qla2x00_calc_iocbs_32,
2304 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2305 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2306 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2307 .read_nvram = qla2x00_read_nvram_data,
2308 .write_nvram = qla2x00_write_nvram_data,
2309 .fw_dump = qla2300_fw_dump,
2310 .beacon_on = qla2x00_beacon_on,
2311 .beacon_off = qla2x00_beacon_off,
2312 .beacon_blink = qla2x00_beacon_blink,
2313 .read_optrom = qla2x00_read_optrom_data,
2314 .write_optrom = qla2x00_write_optrom_data,
2315 .get_flash_version = qla2x00_get_flash_version,
2316 .start_scsi = qla2x00_start_scsi,
2317 .start_scsi_mq = NULL,
2318 .abort_isp = qla2x00_abort_isp,
2319 .iospace_config = qla2x00_iospace_config,
2320 .initialize_adapter = qla2x00_initialize_adapter,
2321 };
2322
2323 static struct isp_operations qla24xx_isp_ops = {
2324 .pci_config = qla24xx_pci_config,
2325 .reset_chip = qla24xx_reset_chip,
2326 .chip_diag = qla24xx_chip_diag,
2327 .config_rings = qla24xx_config_rings,
2328 .reset_adapter = qla24xx_reset_adapter,
2329 .nvram_config = qla24xx_nvram_config,
2330 .update_fw_options = qla24xx_update_fw_options,
2331 .load_risc = qla24xx_load_risc,
2332 .pci_info_str = qla24xx_pci_info_str,
2333 .fw_version_str = qla24xx_fw_version_str,
2334 .intr_handler = qla24xx_intr_handler,
2335 .enable_intrs = qla24xx_enable_intrs,
2336 .disable_intrs = qla24xx_disable_intrs,
2337 .abort_command = qla24xx_abort_command,
2338 .target_reset = qla24xx_abort_target,
2339 .lun_reset = qla24xx_lun_reset,
2340 .fabric_login = qla24xx_login_fabric,
2341 .fabric_logout = qla24xx_fabric_logout,
2342 .calc_req_entries = NULL,
2343 .build_iocbs = NULL,
2344 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2345 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2346 .read_nvram = qla24xx_read_nvram_data,
2347 .write_nvram = qla24xx_write_nvram_data,
2348 .fw_dump = qla24xx_fw_dump,
2349 .beacon_on = qla24xx_beacon_on,
2350 .beacon_off = qla24xx_beacon_off,
2351 .beacon_blink = qla24xx_beacon_blink,
2352 .read_optrom = qla24xx_read_optrom_data,
2353 .write_optrom = qla24xx_write_optrom_data,
2354 .get_flash_version = qla24xx_get_flash_version,
2355 .start_scsi = qla24xx_start_scsi,
2356 .start_scsi_mq = NULL,
2357 .abort_isp = qla2x00_abort_isp,
2358 .iospace_config = qla2x00_iospace_config,
2359 .initialize_adapter = qla2x00_initialize_adapter,
2360 };
2361
2362 static struct isp_operations qla25xx_isp_ops = {
2363 .pci_config = qla25xx_pci_config,
2364 .reset_chip = qla24xx_reset_chip,
2365 .chip_diag = qla24xx_chip_diag,
2366 .config_rings = qla24xx_config_rings,
2367 .reset_adapter = qla24xx_reset_adapter,
2368 .nvram_config = qla24xx_nvram_config,
2369 .update_fw_options = qla24xx_update_fw_options,
2370 .load_risc = qla24xx_load_risc,
2371 .pci_info_str = qla24xx_pci_info_str,
2372 .fw_version_str = qla24xx_fw_version_str,
2373 .intr_handler = qla24xx_intr_handler,
2374 .enable_intrs = qla24xx_enable_intrs,
2375 .disable_intrs = qla24xx_disable_intrs,
2376 .abort_command = qla24xx_abort_command,
2377 .target_reset = qla24xx_abort_target,
2378 .lun_reset = qla24xx_lun_reset,
2379 .fabric_login = qla24xx_login_fabric,
2380 .fabric_logout = qla24xx_fabric_logout,
2381 .calc_req_entries = NULL,
2382 .build_iocbs = NULL,
2383 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2384 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2385 .read_nvram = qla25xx_read_nvram_data,
2386 .write_nvram = qla25xx_write_nvram_data,
2387 .fw_dump = qla25xx_fw_dump,
2388 .beacon_on = qla24xx_beacon_on,
2389 .beacon_off = qla24xx_beacon_off,
2390 .beacon_blink = qla24xx_beacon_blink,
2391 .read_optrom = qla25xx_read_optrom_data,
2392 .write_optrom = qla24xx_write_optrom_data,
2393 .get_flash_version = qla24xx_get_flash_version,
2394 .start_scsi = qla24xx_dif_start_scsi,
2395 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2396 .abort_isp = qla2x00_abort_isp,
2397 .iospace_config = qla2x00_iospace_config,
2398 .initialize_adapter = qla2x00_initialize_adapter,
2399 };
2400
2401 static struct isp_operations qla81xx_isp_ops = {
2402 .pci_config = qla25xx_pci_config,
2403 .reset_chip = qla24xx_reset_chip,
2404 .chip_diag = qla24xx_chip_diag,
2405 .config_rings = qla24xx_config_rings,
2406 .reset_adapter = qla24xx_reset_adapter,
2407 .nvram_config = qla81xx_nvram_config,
2408 .update_fw_options = qla24xx_update_fw_options,
2409 .load_risc = qla81xx_load_risc,
2410 .pci_info_str = qla24xx_pci_info_str,
2411 .fw_version_str = qla24xx_fw_version_str,
2412 .intr_handler = qla24xx_intr_handler,
2413 .enable_intrs = qla24xx_enable_intrs,
2414 .disable_intrs = qla24xx_disable_intrs,
2415 .abort_command = qla24xx_abort_command,
2416 .target_reset = qla24xx_abort_target,
2417 .lun_reset = qla24xx_lun_reset,
2418 .fabric_login = qla24xx_login_fabric,
2419 .fabric_logout = qla24xx_fabric_logout,
2420 .calc_req_entries = NULL,
2421 .build_iocbs = NULL,
2422 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2423 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2424 .read_nvram = NULL,
2425 .write_nvram = NULL,
2426 .fw_dump = qla81xx_fw_dump,
2427 .beacon_on = qla24xx_beacon_on,
2428 .beacon_off = qla24xx_beacon_off,
2429 .beacon_blink = qla83xx_beacon_blink,
2430 .read_optrom = qla25xx_read_optrom_data,
2431 .write_optrom = qla24xx_write_optrom_data,
2432 .get_flash_version = qla24xx_get_flash_version,
2433 .start_scsi = qla24xx_dif_start_scsi,
2434 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2435 .abort_isp = qla2x00_abort_isp,
2436 .iospace_config = qla2x00_iospace_config,
2437 .initialize_adapter = qla2x00_initialize_adapter,
2438 };
2439
2440 static struct isp_operations qla82xx_isp_ops = {
2441 .pci_config = qla82xx_pci_config,
2442 .reset_chip = qla82xx_reset_chip,
2443 .chip_diag = qla24xx_chip_diag,
2444 .config_rings = qla82xx_config_rings,
2445 .reset_adapter = qla24xx_reset_adapter,
2446 .nvram_config = qla81xx_nvram_config,
2447 .update_fw_options = qla24xx_update_fw_options,
2448 .load_risc = qla82xx_load_risc,
2449 .pci_info_str = qla24xx_pci_info_str,
2450 .fw_version_str = qla24xx_fw_version_str,
2451 .intr_handler = qla82xx_intr_handler,
2452 .enable_intrs = qla82xx_enable_intrs,
2453 .disable_intrs = qla82xx_disable_intrs,
2454 .abort_command = qla24xx_abort_command,
2455 .target_reset = qla24xx_abort_target,
2456 .lun_reset = qla24xx_lun_reset,
2457 .fabric_login = qla24xx_login_fabric,
2458 .fabric_logout = qla24xx_fabric_logout,
2459 .calc_req_entries = NULL,
2460 .build_iocbs = NULL,
2461 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2462 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2463 .read_nvram = qla24xx_read_nvram_data,
2464 .write_nvram = qla24xx_write_nvram_data,
2465 .fw_dump = qla82xx_fw_dump,
2466 .beacon_on = qla82xx_beacon_on,
2467 .beacon_off = qla82xx_beacon_off,
2468 .beacon_blink = NULL,
2469 .read_optrom = qla82xx_read_optrom_data,
2470 .write_optrom = qla82xx_write_optrom_data,
2471 .get_flash_version = qla82xx_get_flash_version,
2472 .start_scsi = qla82xx_start_scsi,
2473 .start_scsi_mq = NULL,
2474 .abort_isp = qla82xx_abort_isp,
2475 .iospace_config = qla82xx_iospace_config,
2476 .initialize_adapter = qla2x00_initialize_adapter,
2477 };
2478
2479 static struct isp_operations qla8044_isp_ops = {
2480 .pci_config = qla82xx_pci_config,
2481 .reset_chip = qla82xx_reset_chip,
2482 .chip_diag = qla24xx_chip_diag,
2483 .config_rings = qla82xx_config_rings,
2484 .reset_adapter = qla24xx_reset_adapter,
2485 .nvram_config = qla81xx_nvram_config,
2486 .update_fw_options = qla24xx_update_fw_options,
2487 .load_risc = qla82xx_load_risc,
2488 .pci_info_str = qla24xx_pci_info_str,
2489 .fw_version_str = qla24xx_fw_version_str,
2490 .intr_handler = qla8044_intr_handler,
2491 .enable_intrs = qla82xx_enable_intrs,
2492 .disable_intrs = qla82xx_disable_intrs,
2493 .abort_command = qla24xx_abort_command,
2494 .target_reset = qla24xx_abort_target,
2495 .lun_reset = qla24xx_lun_reset,
2496 .fabric_login = qla24xx_login_fabric,
2497 .fabric_logout = qla24xx_fabric_logout,
2498 .calc_req_entries = NULL,
2499 .build_iocbs = NULL,
2500 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2501 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2502 .read_nvram = NULL,
2503 .write_nvram = NULL,
2504 .fw_dump = qla8044_fw_dump,
2505 .beacon_on = qla82xx_beacon_on,
2506 .beacon_off = qla82xx_beacon_off,
2507 .beacon_blink = NULL,
2508 .read_optrom = qla8044_read_optrom_data,
2509 .write_optrom = qla8044_write_optrom_data,
2510 .get_flash_version = qla82xx_get_flash_version,
2511 .start_scsi = qla82xx_start_scsi,
2512 .start_scsi_mq = NULL,
2513 .abort_isp = qla8044_abort_isp,
2514 .iospace_config = qla82xx_iospace_config,
2515 .initialize_adapter = qla2x00_initialize_adapter,
2516 };
2517
2518 static struct isp_operations qla83xx_isp_ops = {
2519 .pci_config = qla25xx_pci_config,
2520 .reset_chip = qla24xx_reset_chip,
2521 .chip_diag = qla24xx_chip_diag,
2522 .config_rings = qla24xx_config_rings,
2523 .reset_adapter = qla24xx_reset_adapter,
2524 .nvram_config = qla81xx_nvram_config,
2525 .update_fw_options = qla24xx_update_fw_options,
2526 .load_risc = qla81xx_load_risc,
2527 .pci_info_str = qla24xx_pci_info_str,
2528 .fw_version_str = qla24xx_fw_version_str,
2529 .intr_handler = qla24xx_intr_handler,
2530 .enable_intrs = qla24xx_enable_intrs,
2531 .disable_intrs = qla24xx_disable_intrs,
2532 .abort_command = qla24xx_abort_command,
2533 .target_reset = qla24xx_abort_target,
2534 .lun_reset = qla24xx_lun_reset,
2535 .fabric_login = qla24xx_login_fabric,
2536 .fabric_logout = qla24xx_fabric_logout,
2537 .calc_req_entries = NULL,
2538 .build_iocbs = NULL,
2539 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2540 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2541 .read_nvram = NULL,
2542 .write_nvram = NULL,
2543 .fw_dump = qla83xx_fw_dump,
2544 .beacon_on = qla24xx_beacon_on,
2545 .beacon_off = qla24xx_beacon_off,
2546 .beacon_blink = qla83xx_beacon_blink,
2547 .read_optrom = qla25xx_read_optrom_data,
2548 .write_optrom = qla24xx_write_optrom_data,
2549 .get_flash_version = qla24xx_get_flash_version,
2550 .start_scsi = qla24xx_dif_start_scsi,
2551 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2552 .abort_isp = qla2x00_abort_isp,
2553 .iospace_config = qla83xx_iospace_config,
2554 .initialize_adapter = qla2x00_initialize_adapter,
2555 };
2556
2557 static struct isp_operations qlafx00_isp_ops = {
2558 .pci_config = qlafx00_pci_config,
2559 .reset_chip = qlafx00_soft_reset,
2560 .chip_diag = qlafx00_chip_diag,
2561 .config_rings = qlafx00_config_rings,
2562 .reset_adapter = qlafx00_soft_reset,
2563 .nvram_config = NULL,
2564 .update_fw_options = NULL,
2565 .load_risc = NULL,
2566 .pci_info_str = qlafx00_pci_info_str,
2567 .fw_version_str = qlafx00_fw_version_str,
2568 .intr_handler = qlafx00_intr_handler,
2569 .enable_intrs = qlafx00_enable_intrs,
2570 .disable_intrs = qlafx00_disable_intrs,
2571 .abort_command = qla24xx_async_abort_command,
2572 .target_reset = qlafx00_abort_target,
2573 .lun_reset = qlafx00_lun_reset,
2574 .fabric_login = NULL,
2575 .fabric_logout = NULL,
2576 .calc_req_entries = NULL,
2577 .build_iocbs = NULL,
2578 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2579 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2580 .read_nvram = qla24xx_read_nvram_data,
2581 .write_nvram = qla24xx_write_nvram_data,
2582 .fw_dump = NULL,
2583 .beacon_on = qla24xx_beacon_on,
2584 .beacon_off = qla24xx_beacon_off,
2585 .beacon_blink = NULL,
2586 .read_optrom = qla24xx_read_optrom_data,
2587 .write_optrom = qla24xx_write_optrom_data,
2588 .get_flash_version = qla24xx_get_flash_version,
2589 .start_scsi = qlafx00_start_scsi,
2590 .start_scsi_mq = NULL,
2591 .abort_isp = qlafx00_abort_isp,
2592 .iospace_config = qlafx00_iospace_config,
2593 .initialize_adapter = qlafx00_initialize_adapter,
2594 };
2595
2596 static struct isp_operations qla27xx_isp_ops = {
2597 .pci_config = qla25xx_pci_config,
2598 .reset_chip = qla24xx_reset_chip,
2599 .chip_diag = qla24xx_chip_diag,
2600 .config_rings = qla24xx_config_rings,
2601 .reset_adapter = qla24xx_reset_adapter,
2602 .nvram_config = qla81xx_nvram_config,
2603 .update_fw_options = qla24xx_update_fw_options,
2604 .load_risc = qla81xx_load_risc,
2605 .pci_info_str = qla24xx_pci_info_str,
2606 .fw_version_str = qla24xx_fw_version_str,
2607 .intr_handler = qla24xx_intr_handler,
2608 .enable_intrs = qla24xx_enable_intrs,
2609 .disable_intrs = qla24xx_disable_intrs,
2610 .abort_command = qla24xx_abort_command,
2611 .target_reset = qla24xx_abort_target,
2612 .lun_reset = qla24xx_lun_reset,
2613 .fabric_login = qla24xx_login_fabric,
2614 .fabric_logout = qla24xx_fabric_logout,
2615 .calc_req_entries = NULL,
2616 .build_iocbs = NULL,
2617 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2618 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2619 .read_nvram = NULL,
2620 .write_nvram = NULL,
2621 .fw_dump = qla27xx_fwdump,
2622 .mpi_fw_dump = qla27xx_mpi_fwdump,
2623 .beacon_on = qla24xx_beacon_on,
2624 .beacon_off = qla24xx_beacon_off,
2625 .beacon_blink = qla83xx_beacon_blink,
2626 .read_optrom = qla25xx_read_optrom_data,
2627 .write_optrom = qla24xx_write_optrom_data,
2628 .get_flash_version = qla24xx_get_flash_version,
2629 .start_scsi = qla24xx_dif_start_scsi,
2630 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2631 .abort_isp = qla2x00_abort_isp,
2632 .iospace_config = qla83xx_iospace_config,
2633 .initialize_adapter = qla2x00_initialize_adapter,
2634 };
2635
2636 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2637 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2638 {
2639 ha->device_type = DT_EXTENDED_IDS;
2640 switch (ha->pdev->device) {
2641 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2642 ha->isp_type |= DT_ISP2100;
2643 ha->device_type &= ~DT_EXTENDED_IDS;
2644 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2645 break;
2646 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2647 ha->isp_type |= DT_ISP2200;
2648 ha->device_type &= ~DT_EXTENDED_IDS;
2649 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2650 break;
2651 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2652 ha->isp_type |= DT_ISP2300;
2653 ha->device_type |= DT_ZIO_SUPPORTED;
2654 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2655 break;
2656 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2657 ha->isp_type |= DT_ISP2312;
2658 ha->device_type |= DT_ZIO_SUPPORTED;
2659 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2660 break;
2661 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2662 ha->isp_type |= DT_ISP2322;
2663 ha->device_type |= DT_ZIO_SUPPORTED;
2664 if (ha->pdev->subsystem_vendor == 0x1028 &&
2665 ha->pdev->subsystem_device == 0x0170)
2666 ha->device_type |= DT_OEM_001;
2667 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2668 break;
2669 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2670 ha->isp_type |= DT_ISP6312;
2671 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2672 break;
2673 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2674 ha->isp_type |= DT_ISP6322;
2675 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2676 break;
2677 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2678 ha->isp_type |= DT_ISP2422;
2679 ha->device_type |= DT_ZIO_SUPPORTED;
2680 ha->device_type |= DT_FWI2;
2681 ha->device_type |= DT_IIDMA;
2682 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2683 break;
2684 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2685 ha->isp_type |= DT_ISP2432;
2686 ha->device_type |= DT_ZIO_SUPPORTED;
2687 ha->device_type |= DT_FWI2;
2688 ha->device_type |= DT_IIDMA;
2689 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2690 break;
2691 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2692 ha->isp_type |= DT_ISP8432;
2693 ha->device_type |= DT_ZIO_SUPPORTED;
2694 ha->device_type |= DT_FWI2;
2695 ha->device_type |= DT_IIDMA;
2696 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2697 break;
2698 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2699 ha->isp_type |= DT_ISP5422;
2700 ha->device_type |= DT_FWI2;
2701 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2702 break;
2703 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2704 ha->isp_type |= DT_ISP5432;
2705 ha->device_type |= DT_FWI2;
2706 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2707 break;
2708 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2709 ha->isp_type |= DT_ISP2532;
2710 ha->device_type |= DT_ZIO_SUPPORTED;
2711 ha->device_type |= DT_FWI2;
2712 ha->device_type |= DT_IIDMA;
2713 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2714 break;
2715 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2716 ha->isp_type |= DT_ISP8001;
2717 ha->device_type |= DT_ZIO_SUPPORTED;
2718 ha->device_type |= DT_FWI2;
2719 ha->device_type |= DT_IIDMA;
2720 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2721 break;
2722 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2723 ha->isp_type |= DT_ISP8021;
2724 ha->device_type |= DT_ZIO_SUPPORTED;
2725 ha->device_type |= DT_FWI2;
2726 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2727 /* Initialize 82XX ISP flags */
2728 qla82xx_init_flags(ha);
2729 break;
2730 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2731 ha->isp_type |= DT_ISP8044;
2732 ha->device_type |= DT_ZIO_SUPPORTED;
2733 ha->device_type |= DT_FWI2;
2734 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2735 /* Initialize 82XX ISP flags */
2736 qla82xx_init_flags(ha);
2737 break;
2738 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2739 ha->isp_type |= DT_ISP2031;
2740 ha->device_type |= DT_ZIO_SUPPORTED;
2741 ha->device_type |= DT_FWI2;
2742 ha->device_type |= DT_IIDMA;
2743 ha->device_type |= DT_T10_PI;
2744 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2745 break;
2746 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2747 ha->isp_type |= DT_ISP8031;
2748 ha->device_type |= DT_ZIO_SUPPORTED;
2749 ha->device_type |= DT_FWI2;
2750 ha->device_type |= DT_IIDMA;
2751 ha->device_type |= DT_T10_PI;
2752 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2753 break;
2754 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2755 ha->isp_type |= DT_ISPFX00;
2756 break;
2757 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2758 ha->isp_type |= DT_ISP2071;
2759 ha->device_type |= DT_ZIO_SUPPORTED;
2760 ha->device_type |= DT_FWI2;
2761 ha->device_type |= DT_IIDMA;
2762 ha->device_type |= DT_T10_PI;
2763 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2764 break;
2765 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2766 ha->isp_type |= DT_ISP2271;
2767 ha->device_type |= DT_ZIO_SUPPORTED;
2768 ha->device_type |= DT_FWI2;
2769 ha->device_type |= DT_IIDMA;
2770 ha->device_type |= DT_T10_PI;
2771 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2772 break;
2773 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2774 ha->isp_type |= DT_ISP2261;
2775 ha->device_type |= DT_ZIO_SUPPORTED;
2776 ha->device_type |= DT_FWI2;
2777 ha->device_type |= DT_IIDMA;
2778 ha->device_type |= DT_T10_PI;
2779 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2780 break;
2781 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2782 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2783 ha->isp_type |= DT_ISP2081;
2784 ha->device_type |= DT_ZIO_SUPPORTED;
2785 ha->device_type |= DT_FWI2;
2786 ha->device_type |= DT_IIDMA;
2787 ha->device_type |= DT_T10_PI;
2788 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2789 break;
2790 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2791 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2792 ha->isp_type |= DT_ISP2281;
2793 ha->device_type |= DT_ZIO_SUPPORTED;
2794 ha->device_type |= DT_FWI2;
2795 ha->device_type |= DT_IIDMA;
2796 ha->device_type |= DT_T10_PI;
2797 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2798 break;
2799 }
2800
2801 if (IS_QLA82XX(ha))
2802 ha->port_no = ha->portnum & 1;
2803 else {
2804 /* Get adapter physical port no from interrupt pin register. */
2805 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2806 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2807 IS_QLA27XX(ha) || IS_QLA28XX(ha))
2808 ha->port_no--;
2809 else
2810 ha->port_no = !(ha->port_no & 1);
2811 }
2812
2813 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2814 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2815 ha->device_type, ha->port_no, ha->fw_srisc_address);
2816 }
2817
2818 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2819 qla2xxx_scan_start(struct Scsi_Host *shost)
2820 {
2821 scsi_qla_host_t *vha = shost_priv(shost);
2822
2823 if (vha->hw->flags.running_gold_fw)
2824 return;
2825
2826 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2827 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2828 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2829 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2830 }
2831
2832 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2833 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2834 {
2835 scsi_qla_host_t *vha = shost_priv(shost);
2836
2837 if (test_bit(UNLOADING, &vha->dpc_flags))
2838 return 1;
2839 if (!vha->host)
2840 return 1;
2841 if (time > vha->hw->loop_reset_delay * HZ)
2842 return 1;
2843
2844 return atomic_read(&vha->loop_state) == LOOP_READY;
2845 }
2846
qla_heartbeat_work_fn(struct work_struct * work)2847 static void qla_heartbeat_work_fn(struct work_struct *work)
2848 {
2849 struct qla_hw_data *ha = container_of(work,
2850 struct qla_hw_data, heartbeat_work);
2851 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2852
2853 if (!ha->flags.mbox_busy && base_vha->flags.init_done)
2854 qla_no_op_mb(base_vha);
2855 }
2856
qla2x00_iocb_work_fn(struct work_struct * work)2857 static void qla2x00_iocb_work_fn(struct work_struct *work)
2858 {
2859 struct scsi_qla_host *vha = container_of(work,
2860 struct scsi_qla_host, iocb_work);
2861 struct qla_hw_data *ha = vha->hw;
2862 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2863 int i = 2;
2864 unsigned long flags;
2865
2866 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2867 return;
2868
2869 while (!list_empty(&vha->work_list) && i > 0) {
2870 qla2x00_do_work(vha);
2871 i--;
2872 }
2873
2874 spin_lock_irqsave(&vha->work_lock, flags);
2875 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2876 spin_unlock_irqrestore(&vha->work_lock, flags);
2877 }
2878
2879 static void
qla_trace_init(void)2880 qla_trace_init(void)
2881 {
2882 qla_trc_array = trace_array_get_by_name("qla2xxx", NULL);
2883 if (!qla_trc_array) {
2884 ql_log(ql_log_fatal, NULL, 0x0001,
2885 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n");
2886 return;
2887 }
2888
2889 QLA_TRACE_ENABLE(qla_trc_array);
2890 }
2891
2892 static void
qla_trace_uninit(void)2893 qla_trace_uninit(void)
2894 {
2895 if (!qla_trc_array)
2896 return;
2897 trace_array_put(qla_trc_array);
2898 }
2899
2900 /*
2901 * PCI driver interface
2902 */
2903 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2904 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2905 {
2906 int ret = -ENODEV;
2907 struct Scsi_Host *host;
2908 scsi_qla_host_t *base_vha = NULL;
2909 struct qla_hw_data *ha;
2910 char pci_info[30];
2911 char fw_str[30], wq_name[30];
2912 struct scsi_host_template *sht;
2913 int bars, mem_only = 0;
2914 uint16_t req_length = 0, rsp_length = 0;
2915 struct req_que *req = NULL;
2916 struct rsp_que *rsp = NULL;
2917 int i;
2918
2919 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2920 sht = &qla2xxx_driver_template;
2921 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2922 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2923 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2929 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2930 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2931 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2932 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2933 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2934 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2935 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2936 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2937 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2938 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2939 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2940 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2941 mem_only = 1;
2942 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2943 "Mem only adapter.\n");
2944 }
2945 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2946 "Bars=%d.\n", bars);
2947
2948 if (mem_only) {
2949 if (pci_enable_device_mem(pdev))
2950 return ret;
2951 } else {
2952 if (pci_enable_device(pdev))
2953 return ret;
2954 }
2955
2956 if (is_kdump_kernel()) {
2957 ql2xmqsupport = 0;
2958 ql2xallocfwdump = 0;
2959 }
2960
2961 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2962 if (!ha) {
2963 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2964 "Unable to allocate memory for ha.\n");
2965 goto disable_device;
2966 }
2967 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2968 "Memory allocated for ha=%p.\n", ha);
2969 ha->pdev = pdev;
2970 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2971 spin_lock_init(&ha->tgt.q_full_lock);
2972 spin_lock_init(&ha->tgt.sess_lock);
2973 spin_lock_init(&ha->tgt.atio_lock);
2974
2975 spin_lock_init(&ha->sadb_lock);
2976 INIT_LIST_HEAD(&ha->sadb_tx_index_list);
2977 INIT_LIST_HEAD(&ha->sadb_rx_index_list);
2978
2979 spin_lock_init(&ha->sadb_fp_lock);
2980
2981 if (qla_edif_sadb_build_free_pool(ha)) {
2982 kfree(ha);
2983 goto disable_device;
2984 }
2985
2986 atomic_set(&ha->nvme_active_aen_cnt, 0);
2987
2988 /* Clear our data area */
2989 ha->bars = bars;
2990 ha->mem_only = mem_only;
2991 spin_lock_init(&ha->hardware_lock);
2992 spin_lock_init(&ha->vport_slock);
2993 mutex_init(&ha->selflogin_lock);
2994 mutex_init(&ha->optrom_mutex);
2995
2996 /* Set ISP-type information. */
2997 qla2x00_set_isp_flags(ha);
2998
2999 /* Set EEH reset type to fundamental if required by hba */
3000 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
3001 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3002 pdev->needs_freset = 1;
3003
3004 ha->prev_topology = 0;
3005 ha->init_cb_size = sizeof(init_cb_t);
3006 ha->link_data_rate = PORT_SPEED_UNKNOWN;
3007 ha->optrom_size = OPTROM_SIZE_2300;
3008 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
3009 atomic_set(&ha->num_pend_mbx_stage1, 0);
3010 atomic_set(&ha->num_pend_mbx_stage2, 0);
3011 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
3012 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
3013 INIT_LIST_HEAD(&ha->tmf_pending);
3014 INIT_LIST_HEAD(&ha->tmf_active);
3015
3016 /* Assign ISP specific operations. */
3017 if (IS_QLA2100(ha)) {
3018 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3019 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
3020 req_length = REQUEST_ENTRY_CNT_2100;
3021 rsp_length = RESPONSE_ENTRY_CNT_2100;
3022 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3023 ha->gid_list_info_size = 4;
3024 ha->flash_conf_off = ~0;
3025 ha->flash_data_off = ~0;
3026 ha->nvram_conf_off = ~0;
3027 ha->nvram_data_off = ~0;
3028 ha->isp_ops = &qla2100_isp_ops;
3029 } else if (IS_QLA2200(ha)) {
3030 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3031 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
3032 req_length = REQUEST_ENTRY_CNT_2200;
3033 rsp_length = RESPONSE_ENTRY_CNT_2100;
3034 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3035 ha->gid_list_info_size = 4;
3036 ha->flash_conf_off = ~0;
3037 ha->flash_data_off = ~0;
3038 ha->nvram_conf_off = ~0;
3039 ha->nvram_data_off = ~0;
3040 ha->isp_ops = &qla2100_isp_ops;
3041 } else if (IS_QLA23XX(ha)) {
3042 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3043 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3044 req_length = REQUEST_ENTRY_CNT_2200;
3045 rsp_length = RESPONSE_ENTRY_CNT_2300;
3046 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3047 ha->gid_list_info_size = 6;
3048 if (IS_QLA2322(ha) || IS_QLA6322(ha))
3049 ha->optrom_size = OPTROM_SIZE_2322;
3050 ha->flash_conf_off = ~0;
3051 ha->flash_data_off = ~0;
3052 ha->nvram_conf_off = ~0;
3053 ha->nvram_data_off = ~0;
3054 ha->isp_ops = &qla2300_isp_ops;
3055 } else if (IS_QLA24XX_TYPE(ha)) {
3056 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3057 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3058 req_length = REQUEST_ENTRY_CNT_24XX;
3059 rsp_length = RESPONSE_ENTRY_CNT_2300;
3060 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3061 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3062 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3063 ha->gid_list_info_size = 8;
3064 ha->optrom_size = OPTROM_SIZE_24XX;
3065 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
3066 ha->isp_ops = &qla24xx_isp_ops;
3067 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3068 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3069 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3070 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3071 } else if (IS_QLA25XX(ha)) {
3072 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3073 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3074 req_length = REQUEST_ENTRY_CNT_24XX;
3075 rsp_length = RESPONSE_ENTRY_CNT_2300;
3076 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3077 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3078 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3079 ha->gid_list_info_size = 8;
3080 ha->optrom_size = OPTROM_SIZE_25XX;
3081 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3082 ha->isp_ops = &qla25xx_isp_ops;
3083 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3084 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3085 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3086 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3087 } else if (IS_QLA81XX(ha)) {
3088 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3089 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3090 req_length = REQUEST_ENTRY_CNT_24XX;
3091 rsp_length = RESPONSE_ENTRY_CNT_2300;
3092 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3093 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3094 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3095 ha->gid_list_info_size = 8;
3096 ha->optrom_size = OPTROM_SIZE_81XX;
3097 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3098 ha->isp_ops = &qla81xx_isp_ops;
3099 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3100 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3101 ha->nvram_conf_off = ~0;
3102 ha->nvram_data_off = ~0;
3103 } else if (IS_QLA82XX(ha)) {
3104 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3105 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3106 req_length = REQUEST_ENTRY_CNT_82XX;
3107 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3108 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3109 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3110 ha->gid_list_info_size = 8;
3111 ha->optrom_size = OPTROM_SIZE_82XX;
3112 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3113 ha->isp_ops = &qla82xx_isp_ops;
3114 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3115 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3116 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3117 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3118 } else if (IS_QLA8044(ha)) {
3119 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3120 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3121 req_length = REQUEST_ENTRY_CNT_82XX;
3122 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3123 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3124 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3125 ha->gid_list_info_size = 8;
3126 ha->optrom_size = OPTROM_SIZE_83XX;
3127 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3128 ha->isp_ops = &qla8044_isp_ops;
3129 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3130 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3131 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3132 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3133 } else if (IS_QLA83XX(ha)) {
3134 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3135 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3136 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3137 req_length = REQUEST_ENTRY_CNT_83XX;
3138 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3139 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3140 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3141 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3142 ha->gid_list_info_size = 8;
3143 ha->optrom_size = OPTROM_SIZE_83XX;
3144 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3145 ha->isp_ops = &qla83xx_isp_ops;
3146 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3147 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3148 ha->nvram_conf_off = ~0;
3149 ha->nvram_data_off = ~0;
3150 } else if (IS_QLAFX00(ha)) {
3151 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3152 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3153 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3154 req_length = REQUEST_ENTRY_CNT_FX00;
3155 rsp_length = RESPONSE_ENTRY_CNT_FX00;
3156 ha->isp_ops = &qlafx00_isp_ops;
3157 ha->port_down_retry_count = 30; /* default value */
3158 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3159 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3160 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3161 ha->mr.fw_hbt_en = 1;
3162 ha->mr.host_info_resend = false;
3163 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3164 } else if (IS_QLA27XX(ha)) {
3165 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3166 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3167 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3168 req_length = REQUEST_ENTRY_CNT_83XX;
3169 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3170 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3171 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3172 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3173 ha->gid_list_info_size = 8;
3174 ha->optrom_size = OPTROM_SIZE_83XX;
3175 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3176 ha->isp_ops = &qla27xx_isp_ops;
3177 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3178 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3179 ha->nvram_conf_off = ~0;
3180 ha->nvram_data_off = ~0;
3181 } else if (IS_QLA28XX(ha)) {
3182 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3183 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3184 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3185 req_length = REQUEST_ENTRY_CNT_83XX;
3186 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3187 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3188 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3189 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3190 ha->gid_list_info_size = 8;
3191 ha->optrom_size = OPTROM_SIZE_28XX;
3192 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3193 ha->isp_ops = &qla27xx_isp_ops;
3194 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3195 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3196 ha->nvram_conf_off = ~0;
3197 ha->nvram_data_off = ~0;
3198 }
3199
3200 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3201 "mbx_count=%d, req_length=%d, "
3202 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3203 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3204 "max_fibre_devices=%d.\n",
3205 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3206 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3207 ha->nvram_npiv_size, ha->max_fibre_devices);
3208 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3209 "isp_ops=%p, flash_conf_off=%d, "
3210 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3211 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3212 ha->nvram_conf_off, ha->nvram_data_off);
3213
3214 /* Configure PCI I/O space */
3215 ret = ha->isp_ops->iospace_config(ha);
3216 if (ret)
3217 goto iospace_config_failed;
3218
3219 ql_log_pci(ql_log_info, pdev, 0x001d,
3220 "Found an ISP%04X irq %d iobase 0x%p.\n",
3221 pdev->device, pdev->irq, ha->iobase);
3222 mutex_init(&ha->vport_lock);
3223 mutex_init(&ha->mq_lock);
3224 init_completion(&ha->mbx_cmd_comp);
3225 complete(&ha->mbx_cmd_comp);
3226 init_completion(&ha->mbx_intr_comp);
3227 init_completion(&ha->dcbx_comp);
3228 init_completion(&ha->lb_portup_comp);
3229
3230 set_bit(0, (unsigned long *) ha->vp_idx_map);
3231
3232 qla2x00_config_dma_addressing(ha);
3233 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3234 "64 Bit addressing is %s.\n",
3235 ha->flags.enable_64bit_addressing ? "enable" :
3236 "disable");
3237 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3238 if (ret) {
3239 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3240 "Failed to allocate memory for adapter, aborting.\n");
3241
3242 goto probe_hw_failed;
3243 }
3244
3245 req->max_q_depth = MAX_Q_DEPTH;
3246 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3247 req->max_q_depth = ql2xmaxqdepth;
3248
3249
3250 base_vha = qla2x00_create_host(sht, ha);
3251 if (!base_vha) {
3252 ret = -ENOMEM;
3253 goto probe_hw_failed;
3254 }
3255
3256 pci_set_drvdata(pdev, base_vha);
3257 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3258
3259 host = base_vha->host;
3260 base_vha->req = req;
3261 if (IS_QLA2XXX_MIDTYPE(ha))
3262 base_vha->mgmt_svr_loop_id =
3263 qla2x00_reserve_mgmt_server_loop_id(base_vha);
3264 else
3265 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3266 base_vha->vp_idx;
3267
3268 /* Setup fcport template structure. */
3269 ha->mr.fcport.vha = base_vha;
3270 ha->mr.fcport.port_type = FCT_UNKNOWN;
3271 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3272 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3273 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3274 ha->mr.fcport.scan_state = 1;
3275
3276 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN |
3277 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT |
3278 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN);
3279
3280 /* Set the SG table size based on ISP type */
3281 if (!IS_FWI2_CAPABLE(ha)) {
3282 if (IS_QLA2100(ha))
3283 host->sg_tablesize = 32;
3284 } else {
3285 if (!IS_QLA82XX(ha))
3286 host->sg_tablesize = QLA_SG_ALL;
3287 }
3288 host->max_id = ha->max_fibre_devices;
3289 host->cmd_per_lun = 3;
3290 host->unique_id = host->host_no;
3291
3292 if (ql2xenabledif && ql2xenabledif != 2) {
3293 ql_log(ql_log_warn, base_vha, 0x302d,
3294 "Invalid value for ql2xenabledif, resetting it to default (2)\n");
3295 ql2xenabledif = 2;
3296 }
3297
3298 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3299 host->max_cmd_len = 32;
3300 else
3301 host->max_cmd_len = MAX_CMDSZ;
3302 host->max_channel = MAX_BUSES - 1;
3303 /* Older HBAs support only 16-bit LUNs */
3304 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3305 ql2xmaxlun > 0xffff)
3306 host->max_lun = 0xffff;
3307 else
3308 host->max_lun = ql2xmaxlun;
3309 host->transportt = qla2xxx_transport_template;
3310 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3311
3312 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3313 "max_id=%d this_id=%d "
3314 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3315 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3316 host->this_id, host->cmd_per_lun, host->unique_id,
3317 host->max_cmd_len, host->max_channel, host->max_lun,
3318 host->transportt, sht->vendor_id);
3319
3320 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
3321
3322 /* Set up the irqs */
3323 ret = qla2x00_request_irqs(ha, rsp);
3324 if (ret)
3325 goto probe_failed;
3326
3327 /* Alloc arrays of request and response ring ptrs */
3328 ret = qla2x00_alloc_queues(ha, req, rsp);
3329 if (ret) {
3330 ql_log(ql_log_fatal, base_vha, 0x003d,
3331 "Failed to allocate memory for queue pointers..."
3332 "aborting.\n");
3333 ret = -ENODEV;
3334 goto probe_failed;
3335 }
3336
3337 if (ha->mqenable) {
3338 /* number of hardware queues supported by blk/scsi-mq*/
3339 host->nr_hw_queues = ha->max_qpairs;
3340
3341 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3342 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3343 } else {
3344 if (ql2xnvmeenable) {
3345 host->nr_hw_queues = ha->max_qpairs;
3346 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3347 "FC-NVMe support is enabled, HW queues=%d\n",
3348 host->nr_hw_queues);
3349 } else {
3350 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3351 "blk/scsi-mq disabled.\n");
3352 }
3353 }
3354
3355 qlt_probe_one_stage1(base_vha, ha);
3356
3357 pci_save_state(pdev);
3358
3359 /* Assign back pointers */
3360 rsp->req = req;
3361 req->rsp = rsp;
3362
3363 if (IS_QLAFX00(ha)) {
3364 ha->rsp_q_map[0] = rsp;
3365 ha->req_q_map[0] = req;
3366 set_bit(0, ha->req_qid_map);
3367 set_bit(0, ha->rsp_qid_map);
3368 }
3369
3370 /* FWI2-capable only. */
3371 req->req_q_in = &ha->iobase->isp24.req_q_in;
3372 req->req_q_out = &ha->iobase->isp24.req_q_out;
3373 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3374 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3375 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3376 IS_QLA28XX(ha)) {
3377 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3378 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3379 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3380 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3381 }
3382
3383 if (IS_QLAFX00(ha)) {
3384 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3385 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3386 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3387 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3388 }
3389
3390 if (IS_P3P_TYPE(ha)) {
3391 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3392 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3393 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3394 }
3395
3396 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3397 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3398 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3399 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3400 "req->req_q_in=%p req->req_q_out=%p "
3401 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3402 req->req_q_in, req->req_q_out,
3403 rsp->rsp_q_in, rsp->rsp_q_out);
3404 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3405 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3406 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3407 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3408 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3409 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3410
3411 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM | WQ_PERCPU, 0);
3412 if (unlikely(!ha->wq)) {
3413 ret = -ENOMEM;
3414 goto probe_failed;
3415 }
3416
3417 if (ha->isp_ops->initialize_adapter(base_vha)) {
3418 ql_log(ql_log_fatal, base_vha, 0x00d6,
3419 "Failed to initialize adapter - Adapter flags %x.\n",
3420 base_vha->device_flags);
3421
3422 if (IS_QLA82XX(ha)) {
3423 qla82xx_idc_lock(ha);
3424 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3425 QLA8XXX_DEV_FAILED);
3426 qla82xx_idc_unlock(ha);
3427 ql_log(ql_log_fatal, base_vha, 0x00d7,
3428 "HW State: FAILED.\n");
3429 } else if (IS_QLA8044(ha)) {
3430 qla8044_idc_lock(ha);
3431 qla8044_wr_direct(base_vha,
3432 QLA8044_CRB_DEV_STATE_INDEX,
3433 QLA8XXX_DEV_FAILED);
3434 qla8044_idc_unlock(ha);
3435 ql_log(ql_log_fatal, base_vha, 0x0150,
3436 "HW State: FAILED.\n");
3437 }
3438
3439 ret = -ENODEV;
3440 goto probe_failed;
3441 }
3442
3443 if (IS_QLAFX00(ha))
3444 host->can_queue = QLAFX00_MAX_CANQUEUE;
3445 else
3446 host->can_queue = req->num_outstanding_cmds - 10;
3447
3448 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3449 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3450 host->can_queue, base_vha->req,
3451 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3452
3453 /* Check if FW supports MQ or not for ISP25xx */
3454 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
3455 ha->mqenable = 0;
3456
3457 if (ha->mqenable) {
3458 bool startit = !!(host->active_mode & MODE_INITIATOR);
3459
3460 /* Create start of day qpairs for Block MQ */
3461 for (i = 0; i < ha->max_qpairs; i++)
3462 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3463 }
3464 qla_init_iocb_limit(base_vha);
3465
3466 if (ha->flags.running_gold_fw)
3467 goto skip_dpc;
3468
3469 /*
3470 * Startup the kernel thread for this host adapter
3471 */
3472 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3473 "%s_dpc", base_vha->host_str);
3474 if (IS_ERR(ha->dpc_thread)) {
3475 ql_log(ql_log_fatal, base_vha, 0x00ed,
3476 "Failed to start DPC thread.\n");
3477 ret = PTR_ERR(ha->dpc_thread);
3478 ha->dpc_thread = NULL;
3479 goto probe_failed;
3480 }
3481 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3482 "DPC thread started successfully.\n");
3483
3484 /*
3485 * If we're not coming up in initiator mode, we might sit for
3486 * a while without waking up the dpc thread, which leads to a
3487 * stuck process warning. So just kick the dpc once here and
3488 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3489 */
3490 qla2xxx_wake_dpc(base_vha);
3491
3492 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3493
3494 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3495 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3496 ha->dpc_lp_wq =
3497 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
3498 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3499
3500 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3501 ha->dpc_hp_wq =
3502 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
3503 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3504 INIT_WORK(&ha->idc_state_handler,
3505 qla83xx_idc_state_handler_work);
3506 INIT_WORK(&ha->nic_core_unrecoverable,
3507 qla83xx_nic_core_unrecoverable_work);
3508 }
3509
3510 skip_dpc:
3511 list_add_tail(&base_vha->list, &ha->vp_list);
3512 base_vha->host->irq = ha->pdev->irq;
3513
3514 /* Initialized the timer */
3515 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3516 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3517 "Started qla2x00_timer with "
3518 "interval=%d.\n", WATCH_INTERVAL);
3519 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3520 "Detected hba at address=%p.\n",
3521 ha);
3522
3523 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3524 if (ha->fw_attributes & BIT_4) {
3525 int prot = 0, guard;
3526
3527 base_vha->flags.difdix_supported = 1;
3528 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3529 "Registering for DIF/DIX type 1 and 3 protection.\n");
3530 if (ql2xprotmask)
3531 scsi_host_set_prot(host, ql2xprotmask);
3532 else
3533 scsi_host_set_prot(host,
3534 prot | SHOST_DIF_TYPE1_PROTECTION
3535 | SHOST_DIF_TYPE2_PROTECTION
3536 | SHOST_DIF_TYPE3_PROTECTION
3537 | SHOST_DIX_TYPE1_PROTECTION
3538 | SHOST_DIX_TYPE2_PROTECTION
3539 | SHOST_DIX_TYPE3_PROTECTION);
3540
3541 guard = SHOST_DIX_GUARD_CRC;
3542
3543 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3544 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3545 guard |= SHOST_DIX_GUARD_IP;
3546
3547 if (ql2xprotguard)
3548 scsi_host_set_guard(host, ql2xprotguard);
3549 else
3550 scsi_host_set_guard(host, guard);
3551 } else
3552 base_vha->flags.difdix_supported = 0;
3553 }
3554
3555 ha->isp_ops->enable_intrs(ha);
3556
3557 if (IS_QLAFX00(ha)) {
3558 ret = qlafx00_fx_disc(base_vha,
3559 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3560 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3561 QLA_SG_ALL : 128;
3562 }
3563
3564 if (IS_T10_PI_CAPABLE(base_vha->hw))
3565 host->dma_alignment = 0x7;
3566
3567 ret = scsi_add_host(host, &pdev->dev);
3568 if (ret)
3569 goto probe_failed;
3570
3571 base_vha->flags.init_done = 1;
3572 base_vha->flags.online = 1;
3573 ha->prev_minidump_failed = 0;
3574
3575 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3576 "Init done and hba is online.\n");
3577
3578 if (qla_ini_mode_enabled(base_vha) ||
3579 qla_dual_mode_enabled(base_vha))
3580 scsi_scan_host(host);
3581 else
3582 ql_log(ql_log_info, base_vha, 0x0122,
3583 "skipping scsi_scan_host() for non-initiator port\n");
3584
3585 qla2x00_alloc_sysfs_attr(base_vha);
3586
3587 if (IS_QLAFX00(ha)) {
3588 ret = qlafx00_fx_disc(base_vha,
3589 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3590
3591 /* Register system information */
3592 ret = qlafx00_fx_disc(base_vha,
3593 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3594 }
3595
3596 qla2x00_init_host_attr(base_vha);
3597
3598 qla2x00_dfs_setup(base_vha);
3599
3600 ql_log(ql_log_info, base_vha, 0x00fb,
3601 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3602 ql_log(ql_log_info, base_vha, 0x00fc,
3603 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3604 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3605 sizeof(pci_info)),
3606 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3607 base_vha->host_no,
3608 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3609
3610 qlt_add_target(ha, base_vha);
3611
3612 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3613
3614 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3615 return -ENODEV;
3616
3617 return 0;
3618
3619 probe_failed:
3620 qla_enode_stop(base_vha);
3621 qla_edb_stop(base_vha);
3622 vfree(base_vha->scan.l);
3623 if (base_vha->gnl.l) {
3624 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3625 base_vha->gnl.l, base_vha->gnl.ldma);
3626 base_vha->gnl.l = NULL;
3627 }
3628
3629 if (base_vha->timer_active)
3630 qla2x00_stop_timer(base_vha);
3631 base_vha->flags.online = 0;
3632 if (ha->dpc_thread) {
3633 struct task_struct *t = ha->dpc_thread;
3634
3635 ha->dpc_thread = NULL;
3636 kthread_stop(t);
3637 }
3638
3639 qla2x00_free_device(base_vha);
3640 scsi_host_put(base_vha->host);
3641 /*
3642 * Need to NULL out local req/rsp after
3643 * qla2x00_free_device => qla2x00_free_queues frees
3644 * what these are pointing to. Or else we'll
3645 * fall over below in qla2x00_free_req/rsp_que.
3646 */
3647 req = NULL;
3648 rsp = NULL;
3649
3650 probe_hw_failed:
3651 qla2x00_mem_free(ha);
3652 qla2x00_free_req_que(ha, req);
3653 qla2x00_free_rsp_que(ha, rsp);
3654 qla2x00_clear_drv_active(ha);
3655
3656 iospace_config_failed:
3657 if (IS_P3P_TYPE(ha)) {
3658 if (!ha->nx_pcibase)
3659 iounmap((device_reg_t *)ha->nx_pcibase);
3660 if (!ql2xdbwr)
3661 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3662 } else {
3663 if (ha->iobase)
3664 iounmap(ha->iobase);
3665 if (ha->cregbase)
3666 iounmap(ha->cregbase);
3667 }
3668 pci_release_selected_regions(ha->pdev, ha->bars);
3669 kfree(ha);
3670
3671 disable_device:
3672 pci_disable_device(pdev);
3673 return ret;
3674 }
3675
__qla_set_remove_flag(scsi_qla_host_t * base_vha)3676 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3677 {
3678 scsi_qla_host_t *vp;
3679 unsigned long flags;
3680 struct qla_hw_data *ha;
3681
3682 if (!base_vha)
3683 return;
3684
3685 ha = base_vha->hw;
3686
3687 spin_lock_irqsave(&ha->vport_slock, flags);
3688 list_for_each_entry(vp, &ha->vp_list, list)
3689 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3690
3691 /*
3692 * Indicate device removal to prevent future board_disable
3693 * and wait until any pending board_disable has completed.
3694 */
3695 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3696 spin_unlock_irqrestore(&ha->vport_slock, flags);
3697 }
3698
3699 static void
qla2x00_shutdown(struct pci_dev * pdev)3700 qla2x00_shutdown(struct pci_dev *pdev)
3701 {
3702 scsi_qla_host_t *vha;
3703 struct qla_hw_data *ha;
3704
3705 vha = pci_get_drvdata(pdev);
3706 ha = vha->hw;
3707
3708 ql_log(ql_log_info, vha, 0xfffa,
3709 "Adapter shutdown\n");
3710
3711 /*
3712 * Prevent future board_disable and wait
3713 * until any pending board_disable has completed.
3714 */
3715 __qla_set_remove_flag(vha);
3716 cancel_work_sync(&ha->board_disable);
3717
3718 if (!atomic_read(&pdev->enable_cnt))
3719 return;
3720
3721 /* Notify ISPFX00 firmware */
3722 if (IS_QLAFX00(ha))
3723 qlafx00_driver_shutdown(vha, 20);
3724
3725 /* Turn-off FCE trace */
3726 if (ha->flags.fce_enabled) {
3727 qla2x00_disable_fce_trace(vha, NULL, NULL);
3728 ha->flags.fce_enabled = 0;
3729 }
3730
3731 /* Turn-off EFT trace */
3732 if (ha->eft)
3733 qla2x00_disable_eft_trace(vha);
3734
3735 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3736 IS_QLA28XX(ha)) {
3737 if (ha->flags.fw_started)
3738 qla2x00_abort_isp_cleanup(vha);
3739 } else {
3740 /* Stop currently executing firmware. */
3741 qla2x00_try_to_stop_firmware(vha);
3742 }
3743
3744 /* Disable timer */
3745 if (vha->timer_active)
3746 qla2x00_stop_timer(vha);
3747
3748 /* Turn adapter off line */
3749 vha->flags.online = 0;
3750
3751 /* turn-off interrupts on the card */
3752 if (ha->interrupts_on) {
3753 vha->flags.init_done = 0;
3754 ha->isp_ops->disable_intrs(ha);
3755 }
3756
3757 qla2x00_free_irqs(vha);
3758
3759 qla2x00_free_fw_dump(ha);
3760
3761 pci_disable_device(pdev);
3762 ql_log(ql_log_info, vha, 0xfffe,
3763 "Adapter shutdown successfully.\n");
3764 }
3765
3766 /* Deletes all the virtual ports for a given ha */
3767 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)3768 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3769 {
3770 scsi_qla_host_t *vha;
3771 unsigned long flags;
3772
3773 mutex_lock(&ha->vport_lock);
3774 while (ha->cur_vport_count) {
3775 spin_lock_irqsave(&ha->vport_slock, flags);
3776
3777 BUG_ON(base_vha->list.next == &ha->vp_list);
3778 /* This assumes first entry in ha->vp_list is always base vha */
3779 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3780 scsi_host_get(vha->host);
3781
3782 spin_unlock_irqrestore(&ha->vport_slock, flags);
3783 mutex_unlock(&ha->vport_lock);
3784
3785 qla_nvme_delete(vha);
3786
3787 fc_vport_terminate(vha->fc_vport);
3788 scsi_host_put(vha->host);
3789
3790 mutex_lock(&ha->vport_lock);
3791 }
3792 mutex_unlock(&ha->vport_lock);
3793 }
3794
3795 /* Stops all deferred work threads */
3796 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3797 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3798 {
3799 /* Cancel all work and destroy DPC workqueues */
3800 if (ha->dpc_lp_wq) {
3801 cancel_work_sync(&ha->idc_aen);
3802 destroy_workqueue(ha->dpc_lp_wq);
3803 ha->dpc_lp_wq = NULL;
3804 }
3805
3806 if (ha->dpc_hp_wq) {
3807 cancel_work_sync(&ha->nic_core_reset);
3808 cancel_work_sync(&ha->idc_state_handler);
3809 cancel_work_sync(&ha->nic_core_unrecoverable);
3810 destroy_workqueue(ha->dpc_hp_wq);
3811 ha->dpc_hp_wq = NULL;
3812 }
3813
3814 /* Kill the kernel thread for this host */
3815 if (ha->dpc_thread) {
3816 struct task_struct *t = ha->dpc_thread;
3817
3818 /*
3819 * qla2xxx_wake_dpc checks for ->dpc_thread
3820 * so we need to zero it out.
3821 */
3822 ha->dpc_thread = NULL;
3823 kthread_stop(t);
3824 }
3825 }
3826
3827 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3828 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3829 {
3830 if (IS_QLA82XX(ha)) {
3831
3832 iounmap((device_reg_t *)ha->nx_pcibase);
3833 if (!ql2xdbwr)
3834 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3835 } else {
3836 if (ha->iobase)
3837 iounmap(ha->iobase);
3838
3839 if (ha->cregbase)
3840 iounmap(ha->cregbase);
3841
3842 if (ha->mqiobase)
3843 iounmap(ha->mqiobase);
3844
3845 if (ha->msixbase)
3846 iounmap(ha->msixbase);
3847 }
3848 }
3849
3850 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3851 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3852 {
3853 if (IS_QLA8044(ha)) {
3854 qla8044_idc_lock(ha);
3855 qla8044_clear_drv_active(ha);
3856 qla8044_idc_unlock(ha);
3857 } else if (IS_QLA82XX(ha)) {
3858 qla82xx_idc_lock(ha);
3859 qla82xx_clear_drv_active(ha);
3860 qla82xx_idc_unlock(ha);
3861 }
3862 }
3863
3864 static void
qla2x00_remove_one(struct pci_dev * pdev)3865 qla2x00_remove_one(struct pci_dev *pdev)
3866 {
3867 scsi_qla_host_t *base_vha;
3868 struct qla_hw_data *ha;
3869
3870 base_vha = pci_get_drvdata(pdev);
3871 ha = base_vha->hw;
3872 ql_log(ql_log_info, base_vha, 0xb079,
3873 "Removing driver\n");
3874 __qla_set_remove_flag(base_vha);
3875 cancel_work_sync(&ha->board_disable);
3876
3877 /*
3878 * If the PCI device is disabled then there was a PCI-disconnect and
3879 * qla2x00_disable_board_on_pci_error has taken care of most of the
3880 * resources.
3881 */
3882 if (!atomic_read(&pdev->enable_cnt)) {
3883 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3884 base_vha->gnl.l, base_vha->gnl.ldma);
3885 base_vha->gnl.l = NULL;
3886 scsi_host_put(base_vha->host);
3887 kfree(ha);
3888 pci_set_drvdata(pdev, NULL);
3889 return;
3890 }
3891 qla2x00_wait_for_hba_ready(base_vha);
3892
3893 /*
3894 * if UNLOADING flag is already set, then continue unload,
3895 * where it was set first.
3896 */
3897 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3898 return;
3899
3900 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3901 IS_QLA28XX(ha)) {
3902 if (ha->flags.fw_started)
3903 qla2x00_abort_isp_cleanup(base_vha);
3904 } else if (!IS_QLAFX00(ha)) {
3905 if (IS_QLA8031(ha)) {
3906 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3907 "Clearing fcoe driver presence.\n");
3908 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3909 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3910 "Error while clearing DRV-Presence.\n");
3911 }
3912
3913 qla2x00_try_to_stop_firmware(base_vha);
3914 }
3915
3916 qla2x00_wait_for_sess_deletion(base_vha);
3917
3918 qla_nvme_delete(base_vha);
3919
3920 dma_free_coherent(&ha->pdev->dev,
3921 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3922
3923 base_vha->gnl.l = NULL;
3924 qla_enode_stop(base_vha);
3925 qla_edb_stop(base_vha);
3926
3927 vfree(base_vha->scan.l);
3928
3929 if (IS_QLAFX00(ha))
3930 qlafx00_driver_shutdown(base_vha, 20);
3931
3932 qla2x00_delete_all_vps(ha, base_vha);
3933
3934 qla2x00_dfs_remove(base_vha);
3935
3936 qla84xx_put_chip(base_vha);
3937
3938 /* Disable timer */
3939 if (base_vha->timer_active)
3940 qla2x00_stop_timer(base_vha);
3941
3942 base_vha->flags.online = 0;
3943
3944 /* free DMA memory */
3945 if (ha->exlogin_buf)
3946 qla2x00_free_exlogin_buffer(ha);
3947
3948 /* free DMA memory */
3949 if (ha->exchoffld_buf)
3950 qla2x00_free_exchoffld_buffer(ha);
3951
3952 qla2x00_destroy_deferred_work(ha);
3953
3954 qlt_remove_target(ha, base_vha);
3955
3956 qla2x00_free_sysfs_attr(base_vha, true);
3957
3958 fc_remove_host(base_vha->host);
3959
3960 scsi_remove_host(base_vha->host);
3961
3962 qla2x00_free_device(base_vha);
3963
3964 qla2x00_clear_drv_active(ha);
3965
3966 scsi_host_put(base_vha->host);
3967
3968 qla2x00_unmap_iobases(ha);
3969
3970 pci_release_selected_regions(ha->pdev, ha->bars);
3971 kfree(ha);
3972
3973 pci_disable_device(pdev);
3974 }
3975
3976 static inline void
qla24xx_free_purex_list(struct purex_list * list)3977 qla24xx_free_purex_list(struct purex_list *list)
3978 {
3979 struct purex_item *item, *next;
3980 ulong flags;
3981
3982 spin_lock_irqsave(&list->lock, flags);
3983 list_for_each_entry_safe(item, next, &list->head, list) {
3984 list_del(&item->list);
3985 if (item == &item->vha->default_item)
3986 continue;
3987 kfree(item);
3988 }
3989 spin_unlock_irqrestore(&list->lock, flags);
3990 }
3991
3992 static void
qla2x00_free_device(scsi_qla_host_t * vha)3993 qla2x00_free_device(scsi_qla_host_t *vha)
3994 {
3995 struct qla_hw_data *ha = vha->hw;
3996
3997 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3998
3999 /* Disable timer */
4000 if (vha->timer_active)
4001 qla2x00_stop_timer(vha);
4002
4003 qla25xx_delete_queues(vha);
4004 vha->flags.online = 0;
4005
4006 /* turn-off interrupts on the card */
4007 if (ha->interrupts_on) {
4008 vha->flags.init_done = 0;
4009 ha->isp_ops->disable_intrs(ha);
4010 }
4011
4012 qla2x00_free_fcports(vha);
4013
4014 qla2x00_free_irqs(vha);
4015
4016 /* Flush the work queue and remove it */
4017 if (ha->wq) {
4018 destroy_workqueue(ha->wq);
4019 ha->wq = NULL;
4020 }
4021
4022
4023 qla24xx_free_purex_list(&vha->purex_list);
4024
4025 qla2x00_mem_free(ha);
4026
4027 qla82xx_md_free(vha);
4028
4029 qla_edif_sadb_release_free_pool(ha);
4030 qla_edif_sadb_release(ha);
4031
4032 qla2x00_free_queues(ha);
4033 }
4034
qla2x00_free_fcports(struct scsi_qla_host * vha)4035 void qla2x00_free_fcports(struct scsi_qla_host *vha)
4036 {
4037 fc_port_t *fcport, *tfcport;
4038
4039 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
4040 qla2x00_free_fcport(fcport);
4041 }
4042
4043 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport)4044 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
4045 {
4046 int now;
4047
4048 if (!fcport->rport)
4049 return;
4050
4051 if (fcport->rport) {
4052 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
4053 "%s %8phN. rport %p roles %x\n",
4054 __func__, fcport->port_name, fcport->rport,
4055 fcport->rport->roles);
4056 fc_remote_port_delete(fcport->rport);
4057 }
4058 qlt_do_generation_tick(vha, &now);
4059 }
4060
4061 /*
4062 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
4063 *
4064 * Input: ha = adapter block pointer. fcport = port structure pointer.
4065 *
4066 * Return: None.
4067 *
4068 * Context:
4069 */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login)4070 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
4071 int do_login)
4072 {
4073 if (IS_QLAFX00(vha->hw)) {
4074 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4075 qla2x00_schedule_rport_del(vha, fcport);
4076 return;
4077 }
4078
4079 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4080 vha->vp_idx == fcport->vha->vp_idx) {
4081 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4082 qla2x00_schedule_rport_del(vha, fcport);
4083 }
4084
4085 /*
4086 * We may need to retry the login, so don't change the state of the
4087 * port but do the retries.
4088 */
4089 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
4090 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4091
4092 if (!do_login)
4093 return;
4094
4095 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4096 }
4097
4098 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha)4099 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
4100 {
4101 fc_port_t *fcport;
4102
4103 ql_dbg(ql_dbg_disc, vha, 0x20f1,
4104 "Mark all dev lost\n");
4105
4106 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4107 if (ql2xfc2target &&
4108 fcport->loop_id != FC_NO_LOOP_ID &&
4109 (fcport->flags & FCF_FCP2_DEVICE) &&
4110 fcport->port_type == FCT_TARGET &&
4111 !qla2x00_reset_active(vha)) {
4112 ql_dbg(ql_dbg_disc, vha, 0x211a,
4113 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
4114 fcport->flags, fcport->port_type,
4115 fcport->d_id.b24, fcport->port_name);
4116 continue;
4117 }
4118 fcport->scan_state = 0;
4119 qlt_schedule_sess_for_deletion(fcport);
4120 }
4121 }
4122
qla2x00_set_reserved_loop_ids(struct qla_hw_data * ha)4123 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
4124 {
4125 int i;
4126
4127 if (IS_FWI2_CAPABLE(ha))
4128 return;
4129
4130 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
4131 set_bit(i, ha->loop_id_map);
4132 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
4133 set_bit(BROADCAST, ha->loop_id_map);
4134 }
4135
4136 /*
4137 * qla2x00_mem_alloc
4138 * Allocates adapter memory.
4139 *
4140 * Returns:
4141 * 0 = success.
4142 * !0 = failure.
4143 */
4144 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)4145 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
4146 struct req_que **req, struct rsp_que **rsp)
4147 {
4148 char name[16];
4149 int rc;
4150
4151 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) {
4152 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL);
4153 if (!ha->vp_map)
4154 goto fail;
4155 }
4156
4157 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
4158 &ha->init_cb_dma, GFP_KERNEL);
4159 if (!ha->init_cb)
4160 goto fail_free_vp_map;
4161
4162 rc = btree_init32(&ha->host_map);
4163 if (rc)
4164 goto fail_free_init_cb;
4165
4166 if (qlt_mem_alloc(ha) < 0)
4167 goto fail_free_btree;
4168
4169 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4170 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
4171 if (!ha->gid_list)
4172 goto fail_free_tgt_mem;
4173
4174 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4175 if (!ha->srb_mempool)
4176 goto fail_free_gid_list;
4177
4178 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) {
4179 /* Allocate cache for CT6 Ctx. */
4180 if (!ctx_cachep) {
4181 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4182 sizeof(struct ct6_dsd), 0,
4183 SLAB_HWCACHE_ALIGN, NULL);
4184 if (!ctx_cachep)
4185 goto fail_free_srb_mempool;
4186 }
4187 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4188 ctx_cachep);
4189 if (!ha->ctx_mempool)
4190 goto fail_free_srb_mempool;
4191 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4192 "ctx_cachep=%p ctx_mempool=%p.\n",
4193 ctx_cachep, ha->ctx_mempool);
4194 }
4195
4196 /* Get memory for cached NVRAM */
4197 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4198 if (!ha->nvram)
4199 goto fail_free_ctx_mempool;
4200
4201 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4202 ha->pdev->device);
4203 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4204 DMA_POOL_SIZE, 8, 0);
4205 if (!ha->s_dma_pool)
4206 goto fail_free_nvram;
4207
4208 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4209 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4210 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4211
4212 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) {
4213 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4214 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4215 if (!ha->dl_dma_pool) {
4216 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4217 "Failed to allocate memory for dl_dma_pool.\n");
4218 goto fail_s_dma_pool;
4219 }
4220
4221 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4222 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4223 if (!ha->fcp_cmnd_dma_pool) {
4224 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4225 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4226 goto fail_dl_dma_pool;
4227 }
4228
4229 if (ql2xenabledif) {
4230 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4231 struct dsd_dma *dsd, *nxt;
4232 uint i;
4233 /* Creata a DMA pool of buffers for DIF bundling */
4234 ha->dif_bundl_pool = dma_pool_create(name,
4235 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4236 if (!ha->dif_bundl_pool) {
4237 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4238 "%s: failed create dif_bundl_pool\n",
4239 __func__);
4240 goto fail_dif_bundl_dma_pool;
4241 }
4242
4243 INIT_LIST_HEAD(&ha->pool.good.head);
4244 INIT_LIST_HEAD(&ha->pool.unusable.head);
4245 ha->pool.good.count = 0;
4246 ha->pool.unusable.count = 0;
4247 for (i = 0; i < 128; i++) {
4248 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4249 if (!dsd) {
4250 ql_dbg_pci(ql_dbg_init, ha->pdev,
4251 0xe0ee, "%s: failed alloc dsd\n",
4252 __func__);
4253 return -ENOMEM;
4254 }
4255 ha->dif_bundle_kallocs++;
4256
4257 dsd->dsd_addr = dma_pool_alloc(
4258 ha->dif_bundl_pool, GFP_ATOMIC,
4259 &dsd->dsd_list_dma);
4260 if (!dsd->dsd_addr) {
4261 ql_dbg_pci(ql_dbg_init, ha->pdev,
4262 0xe0ee,
4263 "%s: failed alloc ->dsd_addr\n",
4264 __func__);
4265 kfree(dsd);
4266 ha->dif_bundle_kallocs--;
4267 continue;
4268 }
4269 ha->dif_bundle_dma_allocs++;
4270
4271 /*
4272 * if DMA buffer crosses 4G boundary,
4273 * put it on bad list
4274 */
4275 if (MSD(dsd->dsd_list_dma) ^
4276 MSD(dsd->dsd_list_dma + bufsize)) {
4277 list_add_tail(&dsd->list,
4278 &ha->pool.unusable.head);
4279 ha->pool.unusable.count++;
4280 } else {
4281 list_add_tail(&dsd->list,
4282 &ha->pool.good.head);
4283 ha->pool.good.count++;
4284 }
4285 }
4286
4287 /* return the good ones back to the pool */
4288 list_for_each_entry_safe(dsd, nxt,
4289 &ha->pool.good.head, list) {
4290 list_del(&dsd->list);
4291 dma_pool_free(ha->dif_bundl_pool,
4292 dsd->dsd_addr, dsd->dsd_list_dma);
4293 ha->dif_bundle_dma_allocs--;
4294 kfree(dsd);
4295 ha->dif_bundle_kallocs--;
4296 }
4297
4298 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4299 "%s: dif dma pool (good=%u unusable=%u)\n",
4300 __func__, ha->pool.good.count,
4301 ha->pool.unusable.count);
4302 }
4303
4304 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4305 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4306 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4307 ha->dif_bundl_pool);
4308 }
4309
4310 /* Allocate memory for SNS commands */
4311 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4312 /* Get consistent memory allocated for SNS commands */
4313 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4314 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4315 if (!ha->sns_cmd)
4316 goto fail_dma_pool;
4317 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4318 "sns_cmd: %p.\n", ha->sns_cmd);
4319 } else {
4320 /* Get consistent memory allocated for MS IOCB */
4321 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4322 &ha->ms_iocb_dma);
4323 if (!ha->ms_iocb)
4324 goto fail_dma_pool;
4325 /* Get consistent memory allocated for CT SNS commands */
4326 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4327 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4328 if (!ha->ct_sns)
4329 goto fail_free_ms_iocb;
4330 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4331 "ms_iocb=%p ct_sns=%p.\n",
4332 ha->ms_iocb, ha->ct_sns);
4333 }
4334
4335 /* Allocate memory for request ring */
4336 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4337 if (!*req) {
4338 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4339 "Failed to allocate memory for req.\n");
4340 goto fail_req;
4341 }
4342 (*req)->length = req_len;
4343 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4344 ((*req)->length + 1) * sizeof(request_t),
4345 &(*req)->dma, GFP_KERNEL);
4346 if (!(*req)->ring) {
4347 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4348 "Failed to allocate memory for req_ring.\n");
4349 goto fail_req_ring;
4350 }
4351 /* Allocate memory for response ring */
4352 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4353 if (!*rsp) {
4354 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4355 "Failed to allocate memory for rsp.\n");
4356 goto fail_rsp;
4357 }
4358 (*rsp)->hw = ha;
4359 (*rsp)->length = rsp_len;
4360 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4361 ((*rsp)->length + 1) * sizeof(response_t),
4362 &(*rsp)->dma, GFP_KERNEL);
4363 if (!(*rsp)->ring) {
4364 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4365 "Failed to allocate memory for rsp_ring.\n");
4366 goto fail_rsp_ring;
4367 }
4368 (*req)->rsp = *rsp;
4369 (*rsp)->req = *req;
4370 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4371 "req=%p req->length=%d req->ring=%p rsp=%p "
4372 "rsp->length=%d rsp->ring=%p.\n",
4373 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4374 (*rsp)->ring);
4375 /* Allocate memory for NVRAM data for vports */
4376 if (ha->nvram_npiv_size) {
4377 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4378 sizeof(struct qla_npiv_entry),
4379 GFP_KERNEL);
4380 if (!ha->npiv_info) {
4381 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4382 "Failed to allocate memory for npiv_info.\n");
4383 goto fail_npiv_info;
4384 }
4385 } else
4386 ha->npiv_info = NULL;
4387
4388 /* Get consistent memory allocated for EX-INIT-CB. */
4389 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4390 IS_QLA28XX(ha)) {
4391 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4392 &ha->ex_init_cb_dma);
4393 if (!ha->ex_init_cb)
4394 goto fail_ex_init_cb;
4395 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4396 "ex_init_cb=%p.\n", ha->ex_init_cb);
4397 }
4398
4399 /* Get consistent memory allocated for Special Features-CB. */
4400 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4401 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
4402 &ha->sf_init_cb_dma);
4403 if (!ha->sf_init_cb)
4404 goto fail_sf_init_cb;
4405 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4406 "sf_init_cb=%p.\n", ha->sf_init_cb);
4407 }
4408
4409
4410 /* Get consistent memory allocated for Async Port-Database. */
4411 if (!IS_FWI2_CAPABLE(ha)) {
4412 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4413 &ha->async_pd_dma);
4414 if (!ha->async_pd)
4415 goto fail_async_pd;
4416 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4417 "async_pd=%p.\n", ha->async_pd);
4418 }
4419
4420 INIT_LIST_HEAD(&ha->vp_list);
4421
4422 /* Allocate memory for our loop_id bitmap */
4423 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4424 sizeof(long),
4425 GFP_KERNEL);
4426 if (!ha->loop_id_map)
4427 goto fail_loop_id_map;
4428 else {
4429 qla2x00_set_reserved_loop_ids(ha);
4430 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4431 "loop_id_map=%p.\n", ha->loop_id_map);
4432 }
4433
4434 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4435 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4436 if (!ha->sfp_data) {
4437 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4438 "Unable to allocate memory for SFP read-data.\n");
4439 goto fail_sfp_data;
4440 }
4441
4442 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4443 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4444 GFP_KERNEL);
4445 if (!ha->flt) {
4446 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4447 "Unable to allocate memory for FLT.\n");
4448 goto fail_flt_buffer;
4449 }
4450
4451 /* allocate the purex dma pool */
4452 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4453 ELS_MAX_PAYLOAD, 8, 0);
4454
4455 if (!ha->purex_dma_pool) {
4456 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4457 "Unable to allocate purex_dma_pool.\n");
4458 goto fail_flt;
4459 }
4460
4461 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
4462 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
4463 ha->elsrej.size,
4464 &ha->elsrej.cdma,
4465 GFP_KERNEL);
4466 if (!ha->elsrej.c) {
4467 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4468 "Alloc failed for els reject cmd.\n");
4469 goto fail_elsrej;
4470 }
4471 ha->elsrej.c->er_cmd = ELS_LS_RJT;
4472 ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
4473 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
4474
4475 ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt);
4476 ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size,
4477 &ha->lsrjt.cdma, GFP_KERNEL);
4478 if (!ha->lsrjt.c) {
4479 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4480 "Alloc failed for nvme fc reject cmd.\n");
4481 goto fail_lsrjt;
4482 }
4483
4484 return 0;
4485
4486 fail_lsrjt:
4487 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
4488 ha->elsrej.c, ha->elsrej.cdma);
4489 fail_elsrej:
4490 dma_pool_destroy(ha->purex_dma_pool);
4491 fail_flt:
4492 dma_free_coherent(&ha->pdev->dev, sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4493 ha->flt, ha->flt_dma);
4494
4495 fail_flt_buffer:
4496 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4497 ha->sfp_data, ha->sfp_data_dma);
4498 fail_sfp_data:
4499 kfree(ha->loop_id_map);
4500 fail_loop_id_map:
4501 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4502 fail_async_pd:
4503 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4504 fail_sf_init_cb:
4505 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4506 fail_ex_init_cb:
4507 kfree(ha->npiv_info);
4508 fail_npiv_info:
4509 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4510 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4511 (*rsp)->ring = NULL;
4512 (*rsp)->dma = 0;
4513 fail_rsp_ring:
4514 kfree(*rsp);
4515 *rsp = NULL;
4516 fail_rsp:
4517 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4518 sizeof(request_t), (*req)->ring, (*req)->dma);
4519 (*req)->ring = NULL;
4520 (*req)->dma = 0;
4521 fail_req_ring:
4522 kfree(*req);
4523 *req = NULL;
4524 fail_req:
4525 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4526 ha->ct_sns, ha->ct_sns_dma);
4527 ha->ct_sns = NULL;
4528 ha->ct_sns_dma = 0;
4529 fail_free_ms_iocb:
4530 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4531 ha->ms_iocb = NULL;
4532 ha->ms_iocb_dma = 0;
4533
4534 if (ha->sns_cmd)
4535 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4536 ha->sns_cmd, ha->sns_cmd_dma);
4537 fail_dma_pool:
4538 if (ql2xenabledif) {
4539 struct dsd_dma *dsd, *nxt;
4540
4541 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4542 list) {
4543 list_del(&dsd->list);
4544 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4545 dsd->dsd_list_dma);
4546 ha->dif_bundle_dma_allocs--;
4547 kfree(dsd);
4548 ha->dif_bundle_kallocs--;
4549 ha->pool.unusable.count--;
4550 }
4551 dma_pool_destroy(ha->dif_bundl_pool);
4552 ha->dif_bundl_pool = NULL;
4553 }
4554
4555 fail_dif_bundl_dma_pool:
4556 if (IS_QLA82XX(ha) || ql2xenabledif) {
4557 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4558 ha->fcp_cmnd_dma_pool = NULL;
4559 }
4560 fail_dl_dma_pool:
4561 if (IS_QLA82XX(ha) || ql2xenabledif) {
4562 dma_pool_destroy(ha->dl_dma_pool);
4563 ha->dl_dma_pool = NULL;
4564 }
4565 fail_s_dma_pool:
4566 dma_pool_destroy(ha->s_dma_pool);
4567 ha->s_dma_pool = NULL;
4568 fail_free_nvram:
4569 kfree(ha->nvram);
4570 ha->nvram = NULL;
4571 fail_free_ctx_mempool:
4572 mempool_destroy(ha->ctx_mempool);
4573 ha->ctx_mempool = NULL;
4574 fail_free_srb_mempool:
4575 mempool_destroy(ha->srb_mempool);
4576 ha->srb_mempool = NULL;
4577 fail_free_gid_list:
4578 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4579 ha->gid_list,
4580 ha->gid_list_dma);
4581 ha->gid_list = NULL;
4582 ha->gid_list_dma = 0;
4583 fail_free_tgt_mem:
4584 qlt_mem_free(ha);
4585 fail_free_btree:
4586 btree_destroy32(&ha->host_map);
4587 fail_free_init_cb:
4588 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4589 ha->init_cb_dma);
4590 ha->init_cb = NULL;
4591 ha->init_cb_dma = 0;
4592 fail_free_vp_map:
4593 kfree(ha->vp_map);
4594 ha->vp_map = NULL;
4595 fail:
4596 ql_log(ql_log_fatal, NULL, 0x0030,
4597 "Memory allocation failure.\n");
4598 return -ENOMEM;
4599 }
4600
4601 int
qla2x00_set_exlogins_buffer(scsi_qla_host_t * vha)4602 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4603 {
4604 int rval;
4605 uint16_t size, max_cnt;
4606 uint32_t temp;
4607 struct qla_hw_data *ha = vha->hw;
4608
4609 /* Return if we don't need to alloacate any extended logins */
4610 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4611 return QLA_SUCCESS;
4612
4613 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4614 return QLA_SUCCESS;
4615
4616 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4617 max_cnt = 0;
4618 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4619 if (rval != QLA_SUCCESS) {
4620 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4621 "Failed to get exlogin status.\n");
4622 return rval;
4623 }
4624
4625 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4626 temp *= size;
4627
4628 if (temp != ha->exlogin_size) {
4629 qla2x00_free_exlogin_buffer(ha);
4630 ha->exlogin_size = temp;
4631
4632 ql_log(ql_log_info, vha, 0xd024,
4633 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4634 max_cnt, size, temp);
4635
4636 ql_log(ql_log_info, vha, 0xd025,
4637 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4638
4639 /* Get consistent memory for extended logins */
4640 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4641 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4642 if (!ha->exlogin_buf) {
4643 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4644 "Failed to allocate memory for exlogin_buf_dma.\n");
4645 return -ENOMEM;
4646 }
4647 }
4648
4649 /* Now configure the dma buffer */
4650 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4651 if (rval) {
4652 ql_log(ql_log_fatal, vha, 0xd033,
4653 "Setup extended login buffer ****FAILED****.\n");
4654 qla2x00_free_exlogin_buffer(ha);
4655 }
4656
4657 return rval;
4658 }
4659
4660 /*
4661 * qla2x00_free_exlogin_buffer
4662 *
4663 * Input:
4664 * ha = adapter block pointer
4665 */
4666 void
qla2x00_free_exlogin_buffer(struct qla_hw_data * ha)4667 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4668 {
4669 if (ha->exlogin_buf) {
4670 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4671 ha->exlogin_buf, ha->exlogin_buf_dma);
4672 ha->exlogin_buf = NULL;
4673 ha->exlogin_size = 0;
4674 }
4675 }
4676
4677 static void
qla2x00_number_of_exch(scsi_qla_host_t * vha,u32 * ret_cnt,u16 max_cnt)4678 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4679 {
4680 u32 temp;
4681 struct init_cb_81xx *icb = (struct init_cb_81xx *)vha->hw->init_cb;
4682 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4683
4684 if (max_cnt > vha->hw->max_exchg)
4685 max_cnt = vha->hw->max_exchg;
4686
4687 if (qla_ini_mode_enabled(vha)) {
4688 if (vha->ql2xiniexchg > max_cnt)
4689 vha->ql2xiniexchg = max_cnt;
4690
4691 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4692 *ret_cnt = vha->ql2xiniexchg;
4693
4694 } else if (qla_tgt_mode_enabled(vha)) {
4695 if (vha->ql2xexchoffld > max_cnt) {
4696 vha->ql2xexchoffld = max_cnt;
4697 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4698 }
4699
4700 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4701 *ret_cnt = vha->ql2xexchoffld;
4702 } else if (qla_dual_mode_enabled(vha)) {
4703 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4704 if (temp > max_cnt) {
4705 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4706 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4707 temp = max_cnt;
4708 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4709 }
4710
4711 if (temp > FW_DEF_EXCHANGES_CNT)
4712 *ret_cnt = temp;
4713 }
4714 }
4715
4716 int
qla2x00_set_exchoffld_buffer(scsi_qla_host_t * vha)4717 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4718 {
4719 int rval;
4720 u16 size, max_cnt;
4721 u32 actual_cnt, totsz;
4722 struct qla_hw_data *ha = vha->hw;
4723
4724 if (!ha->flags.exchoffld_enabled)
4725 return QLA_SUCCESS;
4726
4727 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4728 return QLA_SUCCESS;
4729
4730 max_cnt = 0;
4731 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4732 if (rval != QLA_SUCCESS) {
4733 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4734 "Failed to get exlogin status.\n");
4735 return rval;
4736 }
4737
4738 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4739 ql_log(ql_log_info, vha, 0xd014,
4740 "Actual exchange offload count: %d.\n", actual_cnt);
4741
4742 totsz = actual_cnt * size;
4743
4744 if (totsz != ha->exchoffld_size) {
4745 qla2x00_free_exchoffld_buffer(ha);
4746 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4747 ha->exchoffld_size = 0;
4748 ha->flags.exchoffld_enabled = 0;
4749 return QLA_SUCCESS;
4750 }
4751
4752 ha->exchoffld_size = totsz;
4753
4754 ql_log(ql_log_info, vha, 0xd016,
4755 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4756 max_cnt, actual_cnt, size, totsz);
4757
4758 ql_log(ql_log_info, vha, 0xd017,
4759 "Exchange Buffers requested size = 0x%x\n",
4760 ha->exchoffld_size);
4761
4762 /* Get consistent memory for extended logins */
4763 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4764 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4765 if (!ha->exchoffld_buf) {
4766 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4767 "Failed to allocate memory for Exchange Offload.\n");
4768
4769 if (ha->max_exchg >
4770 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4771 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4772 } else if (ha->max_exchg >
4773 (FW_DEF_EXCHANGES_CNT + 512)) {
4774 ha->max_exchg -= 512;
4775 } else {
4776 ha->flags.exchoffld_enabled = 0;
4777 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4778 "Disabling Exchange offload due to lack of memory\n");
4779 }
4780 ha->exchoffld_size = 0;
4781
4782 return -ENOMEM;
4783 }
4784 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4785 /* pathological case */
4786 qla2x00_free_exchoffld_buffer(ha);
4787 ha->exchoffld_size = 0;
4788 ha->flags.exchoffld_enabled = 0;
4789 ql_log(ql_log_info, vha, 0xd016,
4790 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4791 ha->exchoffld_size, actual_cnt, size, totsz);
4792 return 0;
4793 }
4794
4795 /* Now configure the dma buffer */
4796 rval = qla_set_exchoffld_mem_cfg(vha);
4797 if (rval) {
4798 ql_log(ql_log_fatal, vha, 0xd02e,
4799 "Setup exchange offload buffer ****FAILED****.\n");
4800 qla2x00_free_exchoffld_buffer(ha);
4801 } else {
4802 /* re-adjust number of target exchange */
4803 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4804
4805 if (qla_ini_mode_enabled(vha))
4806 icb->exchange_count = 0;
4807 else
4808 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4809 }
4810
4811 return rval;
4812 }
4813
4814 /*
4815 * qla2x00_free_exchoffld_buffer
4816 *
4817 * Input:
4818 * ha = adapter block pointer
4819 */
4820 void
qla2x00_free_exchoffld_buffer(struct qla_hw_data * ha)4821 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4822 {
4823 if (ha->exchoffld_buf) {
4824 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4825 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4826 ha->exchoffld_buf = NULL;
4827 ha->exchoffld_size = 0;
4828 }
4829 }
4830
4831 /*
4832 * qla2x00_free_fw_dump
4833 * Frees fw dump stuff.
4834 *
4835 * Input:
4836 * ha = adapter block pointer
4837 */
4838 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)4839 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4840 {
4841 struct fwdt *fwdt = ha->fwdt;
4842 uint j;
4843
4844 if (ha->fce)
4845 dma_free_coherent(&ha->pdev->dev,
4846 FCE_SIZE, ha->fce, ha->fce_dma);
4847
4848 if (ha->eft)
4849 dma_free_coherent(&ha->pdev->dev,
4850 EFT_SIZE, ha->eft, ha->eft_dma);
4851
4852 vfree(ha->fw_dump);
4853
4854 ha->fce = NULL;
4855 ha->fce_dma = 0;
4856 ha->flags.fce_enabled = 0;
4857 ha->eft = NULL;
4858 ha->eft_dma = 0;
4859 ha->fw_dumped = false;
4860 ha->fw_dump_cap_flags = 0;
4861 ha->fw_dump_reading = 0;
4862 ha->fw_dump = NULL;
4863 ha->fw_dump_len = 0;
4864
4865 for (j = 0; j < 2; j++, fwdt++) {
4866 vfree(fwdt->template);
4867 fwdt->template = NULL;
4868 fwdt->length = 0;
4869 }
4870 }
4871
4872 /*
4873 * qla2x00_mem_free
4874 * Frees all adapter allocated memory.
4875 *
4876 * Input:
4877 * ha = adapter block pointer.
4878 */
4879 static void
qla2x00_mem_free(struct qla_hw_data * ha)4880 qla2x00_mem_free(struct qla_hw_data *ha)
4881 {
4882 qla2x00_free_fw_dump(ha);
4883
4884 if (ha->mctp_dump)
4885 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4886 ha->mctp_dump_dma);
4887 ha->mctp_dump = NULL;
4888
4889 mempool_destroy(ha->srb_mempool);
4890 ha->srb_mempool = NULL;
4891
4892 if (ha->dcbx_tlv)
4893 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4894 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4895 ha->dcbx_tlv = NULL;
4896
4897 if (ha->xgmac_data)
4898 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4899 ha->xgmac_data, ha->xgmac_data_dma);
4900 ha->xgmac_data = NULL;
4901
4902 if (ha->sns_cmd)
4903 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4904 ha->sns_cmd, ha->sns_cmd_dma);
4905 ha->sns_cmd = NULL;
4906 ha->sns_cmd_dma = 0;
4907
4908 if (ha->ct_sns)
4909 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4910 ha->ct_sns, ha->ct_sns_dma);
4911 ha->ct_sns = NULL;
4912 ha->ct_sns_dma = 0;
4913
4914 if (ha->sfp_data)
4915 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4916 ha->sfp_data_dma);
4917 ha->sfp_data = NULL;
4918
4919 if (ha->flt)
4920 dma_free_coherent(&ha->pdev->dev,
4921 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4922 ha->flt, ha->flt_dma);
4923 ha->flt = NULL;
4924 ha->flt_dma = 0;
4925
4926 if (ha->ms_iocb)
4927 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4928 ha->ms_iocb = NULL;
4929 ha->ms_iocb_dma = 0;
4930
4931 if (ha->sf_init_cb)
4932 dma_pool_free(ha->s_dma_pool,
4933 ha->sf_init_cb, ha->sf_init_cb_dma);
4934
4935 if (ha->ex_init_cb)
4936 dma_pool_free(ha->s_dma_pool,
4937 ha->ex_init_cb, ha->ex_init_cb_dma);
4938 ha->ex_init_cb = NULL;
4939 ha->ex_init_cb_dma = 0;
4940
4941 if (ha->async_pd)
4942 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4943 ha->async_pd = NULL;
4944 ha->async_pd_dma = 0;
4945
4946 dma_pool_destroy(ha->s_dma_pool);
4947 ha->s_dma_pool = NULL;
4948
4949 if (ha->gid_list)
4950 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4951 ha->gid_list, ha->gid_list_dma);
4952 ha->gid_list = NULL;
4953 ha->gid_list_dma = 0;
4954
4955 if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) {
4956 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4957
4958 /* clean up allocated prev pool */
4959 list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
4960 &ha->base_qpair->dsd_list, list) {
4961 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
4962 dsd_ptr->dsd_list_dma);
4963 list_del(&dsd_ptr->list);
4964 kfree(dsd_ptr);
4965 }
4966 }
4967
4968 dma_pool_destroy(ha->dl_dma_pool);
4969 ha->dl_dma_pool = NULL;
4970
4971 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4972 ha->fcp_cmnd_dma_pool = NULL;
4973
4974 mempool_destroy(ha->ctx_mempool);
4975 ha->ctx_mempool = NULL;
4976
4977 if (ql2xenabledif && ha->dif_bundl_pool) {
4978 struct dsd_dma *dsd, *nxt;
4979
4980 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4981 list) {
4982 list_del(&dsd->list);
4983 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4984 dsd->dsd_list_dma);
4985 ha->dif_bundle_dma_allocs--;
4986 kfree(dsd);
4987 ha->dif_bundle_kallocs--;
4988 ha->pool.unusable.count--;
4989 }
4990 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4991 list_del(&dsd->list);
4992 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4993 dsd->dsd_list_dma);
4994 ha->dif_bundle_dma_allocs--;
4995 kfree(dsd);
4996 ha->dif_bundle_kallocs--;
4997 }
4998 }
4999
5000 dma_pool_destroy(ha->dif_bundl_pool);
5001 ha->dif_bundl_pool = NULL;
5002
5003 qlt_mem_free(ha);
5004 qla_remove_hostmap(ha);
5005
5006 if (ha->init_cb)
5007 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
5008 ha->init_cb, ha->init_cb_dma);
5009
5010 dma_pool_destroy(ha->purex_dma_pool);
5011 ha->purex_dma_pool = NULL;
5012
5013 if (ha->elsrej.c) {
5014 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
5015 ha->elsrej.c, ha->elsrej.cdma);
5016 ha->elsrej.c = NULL;
5017 }
5018
5019 if (ha->lsrjt.c) {
5020 dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c,
5021 ha->lsrjt.cdma);
5022 ha->lsrjt.c = NULL;
5023 }
5024
5025 ha->init_cb = NULL;
5026 ha->init_cb_dma = 0;
5027
5028 vfree(ha->optrom_buffer);
5029 ha->optrom_buffer = NULL;
5030 kfree(ha->nvram);
5031 ha->nvram = NULL;
5032 kfree(ha->npiv_info);
5033 ha->npiv_info = NULL;
5034 kfree(ha->swl);
5035 ha->swl = NULL;
5036 kfree(ha->loop_id_map);
5037 ha->sf_init_cb = NULL;
5038 ha->sf_init_cb_dma = 0;
5039 ha->loop_id_map = NULL;
5040
5041 kfree(ha->vp_map);
5042 ha->vp_map = NULL;
5043 }
5044
qla2x00_create_host(const struct scsi_host_template * sht,struct qla_hw_data * ha)5045 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht,
5046 struct qla_hw_data *ha)
5047 {
5048 struct Scsi_Host *host;
5049 struct scsi_qla_host *vha = NULL;
5050
5051 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
5052 if (!host) {
5053 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
5054 "Failed to allocate host from the scsi layer, aborting.\n");
5055 return NULL;
5056 }
5057
5058 /* Clear our data area */
5059 vha = shost_priv(host);
5060 memset(vha, 0, sizeof(scsi_qla_host_t));
5061
5062 vha->host = host;
5063 vha->host_no = host->host_no;
5064 vha->hw = ha;
5065
5066 vha->qlini_mode = ql2x_ini_mode;
5067 vha->ql2xexchoffld = ql2xexchoffld;
5068 vha->ql2xiniexchg = ql2xiniexchg;
5069
5070 INIT_LIST_HEAD(&vha->vp_fcports);
5071 INIT_LIST_HEAD(&vha->work_list);
5072 INIT_LIST_HEAD(&vha->list);
5073 INIT_LIST_HEAD(&vha->qla_cmd_list);
5074 INIT_LIST_HEAD(&vha->logo_list);
5075 INIT_LIST_HEAD(&vha->plogi_ack_list);
5076 INIT_LIST_HEAD(&vha->qp_list);
5077 INIT_LIST_HEAD(&vha->gnl.fcports);
5078 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
5079
5080 INIT_LIST_HEAD(&vha->purex_list.head);
5081 spin_lock_init(&vha->purex_list.lock);
5082
5083 spin_lock_init(&vha->work_lock);
5084 spin_lock_init(&vha->cmd_list_lock);
5085 init_waitqueue_head(&vha->fcport_waitQ);
5086 init_waitqueue_head(&vha->vref_waitq);
5087 qla_enode_init(vha);
5088 qla_edb_init(vha);
5089
5090
5091 vha->gnl.size = sizeof(struct get_name_list_extended) *
5092 (ha->max_loop_id + 1);
5093 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
5094 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
5095 if (!vha->gnl.l) {
5096 ql_log(ql_log_fatal, vha, 0xd04a,
5097 "Alloc failed for name list.\n");
5098 scsi_host_put(vha->host);
5099 return NULL;
5100 }
5101
5102 /* todo: what about ext login? */
5103 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
5104 vha->scan.l = vmalloc(vha->scan.size);
5105 if (!vha->scan.l) {
5106 ql_log(ql_log_fatal, vha, 0xd04a,
5107 "Alloc failed for scan database.\n");
5108 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
5109 vha->gnl.l, vha->gnl.ldma);
5110 vha->gnl.l = NULL;
5111 scsi_host_put(vha->host);
5112 return NULL;
5113 }
5114 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
5115
5116 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu",
5117 QLA2XXX_DRIVER_NAME, vha->host_no);
5118 ql_dbg(ql_dbg_init, vha, 0x0041,
5119 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
5120 vha->host, vha->hw, vha,
5121 dev_name(&(ha->pdev->dev)));
5122
5123 return vha;
5124 }
5125
5126 struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)5127 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
5128 {
5129 struct qla_work_evt *e;
5130
5131 if (test_bit(UNLOADING, &vha->dpc_flags))
5132 return NULL;
5133
5134 if (qla_vha_mark_busy(vha))
5135 return NULL;
5136
5137 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
5138 if (!e) {
5139 QLA_VHA_MARK_NOT_BUSY(vha);
5140 return NULL;
5141 }
5142
5143 INIT_LIST_HEAD(&e->list);
5144 e->type = type;
5145 e->flags = QLA_EVT_FLAG_FREE;
5146 return e;
5147 }
5148
5149 int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)5150 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
5151 {
5152 unsigned long flags;
5153 bool q = false;
5154
5155 spin_lock_irqsave(&vha->work_lock, flags);
5156 list_add_tail(&e->list, &vha->work_list);
5157
5158 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
5159 q = true;
5160
5161 spin_unlock_irqrestore(&vha->work_lock, flags);
5162
5163 if (q)
5164 queue_work(vha->hw->wq, &vha->iocb_work);
5165
5166 return QLA_SUCCESS;
5167 }
5168
5169 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)5170 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
5171 u32 data)
5172 {
5173 struct qla_work_evt *e;
5174
5175 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
5176 if (!e)
5177 return QLA_FUNCTION_FAILED;
5178
5179 e->u.aen.code = code;
5180 e->u.aen.data = data;
5181 return qla2x00_post_work(vha, e);
5182 }
5183
5184 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)5185 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
5186 {
5187 struct qla_work_evt *e;
5188
5189 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
5190 if (!e)
5191 return QLA_FUNCTION_FAILED;
5192
5193 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
5194 return qla2x00_post_work(vha, e);
5195 }
5196
5197 #define qla2x00_post_async_work(name, type) \
5198 int qla2x00_post_async_##name##_work( \
5199 struct scsi_qla_host *vha, \
5200 fc_port_t *fcport, uint16_t *data) \
5201 { \
5202 struct qla_work_evt *e; \
5203 \
5204 e = qla2x00_alloc_work(vha, type); \
5205 if (!e) \
5206 return QLA_FUNCTION_FAILED; \
5207 \
5208 e->u.logio.fcport = fcport; \
5209 if (data) { \
5210 e->u.logio.data[0] = data[0]; \
5211 e->u.logio.data[1] = data[1]; \
5212 } \
5213 fcport->flags |= FCF_ASYNC_ACTIVE; \
5214 return qla2x00_post_work(vha, e); \
5215 }
5216
5217 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
5218 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5219 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
5220 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
5221 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
5222
5223 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)5224 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
5225 {
5226 struct qla_work_evt *e;
5227
5228 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
5229 if (!e)
5230 return QLA_FUNCTION_FAILED;
5231
5232 e->u.uevent.code = code;
5233 return qla2x00_post_work(vha, e);
5234 }
5235
5236 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)5237 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5238 {
5239 char event_string[40];
5240 char *envp[] = { event_string, NULL };
5241
5242 switch (code) {
5243 case QLA_UEVENT_CODE_FW_DUMP:
5244 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5245 vha->host_no);
5246 break;
5247 default:
5248 /* do nothing */
5249 break;
5250 }
5251 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5252 }
5253
5254 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)5255 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5256 uint32_t *data, int cnt)
5257 {
5258 struct qla_work_evt *e;
5259
5260 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5261 if (!e)
5262 return QLA_FUNCTION_FAILED;
5263
5264 e->u.aenfx.evtcode = evtcode;
5265 e->u.aenfx.count = cnt;
5266 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5267 return qla2x00_post_work(vha, e);
5268 }
5269
qla24xx_sched_upd_fcport(fc_port_t * fcport)5270 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5271 {
5272 unsigned long flags;
5273
5274 if (IS_SW_RESV_ADDR(fcport->d_id))
5275 return;
5276
5277 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5278 if (fcport->disc_state == DSC_UPD_FCPORT) {
5279 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5280 return;
5281 }
5282 fcport->jiffies_at_registration = jiffies;
5283 fcport->sec_since_registration = 0;
5284 fcport->next_disc_state = DSC_DELETED;
5285 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5286 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5287
5288 queue_work(system_dfl_wq, &fcport->reg_work);
5289 }
5290
5291 static
qla24xx_create_new_sess(struct scsi_qla_host * vha,struct qla_work_evt * e)5292 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5293 {
5294 unsigned long flags;
5295 fc_port_t *fcport = NULL, *tfcp;
5296 struct qlt_plogi_ack_t *pla =
5297 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5298 uint8_t free_fcport = 0;
5299
5300 ql_dbg(ql_dbg_disc, vha, 0xffff,
5301 "%s %d %8phC enter\n",
5302 __func__, __LINE__, e->u.new_sess.port_name);
5303
5304 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5305 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5306 if (fcport) {
5307 fcport->d_id = e->u.new_sess.id;
5308 if (pla) {
5309 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5310 memcpy(fcport->node_name,
5311 pla->iocb.u.isp24.u.plogi.node_name,
5312 WWN_SIZE);
5313 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5314 /* we took an extra ref_count to prevent PLOGI ACK when
5315 * fcport/sess has not been created.
5316 */
5317 pla->ref_count--;
5318 }
5319 } else {
5320 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5321 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5322 if (fcport) {
5323 fcport->d_id = e->u.new_sess.id;
5324 fcport->flags |= FCF_FABRIC_DEVICE;
5325 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5326 fcport->tgt_short_link_down_cnt = 0;
5327
5328 memcpy(fcport->port_name, e->u.new_sess.port_name,
5329 WWN_SIZE);
5330
5331 fcport->fc4_type = e->u.new_sess.fc4_type;
5332 if (NVME_PRIORITY(vha->hw, fcport))
5333 fcport->do_prli_nvme = 1;
5334 else
5335 fcport->do_prli_nvme = 0;
5336
5337 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5338 fcport->dm_login_expire = jiffies +
5339 QLA_N2N_WAIT_TIME * HZ;
5340 fcport->fc4_type = FS_FC4TYPE_FCP;
5341 fcport->n2n_flag = 1;
5342 if (vha->flags.nvme_enabled)
5343 fcport->fc4_type |= FS_FC4TYPE_NVME;
5344 }
5345
5346 } else {
5347 ql_dbg(ql_dbg_disc, vha, 0xffff,
5348 "%s %8phC mem alloc fail.\n",
5349 __func__, e->u.new_sess.port_name);
5350
5351 if (pla) {
5352 list_del(&pla->list);
5353 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5354 }
5355 return;
5356 }
5357
5358 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5359 /* search again to make sure no one else got ahead */
5360 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5361 e->u.new_sess.port_name, 1);
5362 if (tfcp) {
5363 /* should rarily happen */
5364 ql_dbg(ql_dbg_disc, vha, 0xffff,
5365 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5366 __func__, tfcp->port_name, tfcp->disc_state,
5367 tfcp->fw_login_state);
5368
5369 free_fcport = 1;
5370 } else {
5371 list_add_tail(&fcport->list, &vha->vp_fcports);
5372
5373 }
5374 if (pla) {
5375 qlt_plogi_ack_link(vha, pla, fcport,
5376 QLT_PLOGI_LINK_SAME_WWN);
5377 pla->ref_count--;
5378 }
5379 }
5380 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5381
5382 if (fcport) {
5383 fcport->id_changed = 1;
5384 fcport->scan_state = QLA_FCPORT_FOUND;
5385 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5386 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5387
5388 if (pla) {
5389 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5390 u16 wd3_lo;
5391
5392 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5393 fcport->local = 0;
5394 fcport->loop_id =
5395 le16_to_cpu(
5396 pla->iocb.u.isp24.nport_handle);
5397 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5398 wd3_lo =
5399 le16_to_cpu(
5400 pla->iocb.u.isp24.u.prli.wd3_lo);
5401
5402 if (wd3_lo & BIT_7)
5403 fcport->conf_compl_supported = 1;
5404
5405 if ((wd3_lo & BIT_4) == 0)
5406 fcport->port_type = FCT_INITIATOR;
5407 else
5408 fcport->port_type = FCT_TARGET;
5409 }
5410 qlt_plogi_ack_unref(vha, pla);
5411 } else {
5412 fc_port_t *dfcp = NULL;
5413
5414 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5415 tfcp = qla2x00_find_fcport_by_nportid(vha,
5416 &e->u.new_sess.id, 1);
5417 if (tfcp && (tfcp != fcport)) {
5418 /*
5419 * We have a conflict fcport with same NportID.
5420 */
5421 ql_dbg(ql_dbg_disc, vha, 0xffff,
5422 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5423 __func__, tfcp->port_name, tfcp->disc_state,
5424 tfcp->fw_login_state);
5425
5426 switch (tfcp->disc_state) {
5427 case DSC_DELETED:
5428 break;
5429 case DSC_DELETE_PEND:
5430 fcport->login_pause = 1;
5431 tfcp->conflict = fcport;
5432 break;
5433 default:
5434 fcport->login_pause = 1;
5435 tfcp->conflict = fcport;
5436 dfcp = tfcp;
5437 break;
5438 }
5439 }
5440 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5441 if (dfcp)
5442 qlt_schedule_sess_for_deletion(tfcp);
5443
5444 if (N2N_TOPO(vha->hw)) {
5445 fcport->flags &= ~FCF_FABRIC_DEVICE;
5446 fcport->keep_nport_handle = 1;
5447 if (vha->flags.nvme_enabled) {
5448 fcport->fc4_type =
5449 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5450 fcport->n2n_flag = 1;
5451 }
5452 fcport->fw_login_state = 0;
5453
5454 schedule_delayed_work(&vha->scan.scan_work, 5);
5455 } else {
5456 qla24xx_fcport_handle_login(vha, fcport);
5457 }
5458 }
5459 }
5460
5461 if (free_fcport) {
5462 qla2x00_free_fcport(fcport);
5463 if (pla) {
5464 list_del(&pla->list);
5465 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5466 }
5467 }
5468 }
5469
qla_sp_retry(struct scsi_qla_host * vha,struct qla_work_evt * e)5470 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5471 {
5472 struct srb *sp = e->u.iosb.sp;
5473 int rval;
5474
5475 rval = qla2x00_start_sp(sp);
5476 if (rval != QLA_SUCCESS) {
5477 ql_dbg(ql_dbg_disc, vha, 0x2043,
5478 "%s: %s: Re-issue IOCB failed (%d).\n",
5479 __func__, sp->name, rval);
5480 qla24xx_sp_unmap(vha, sp);
5481 }
5482 }
5483
5484 void
qla2x00_do_work(struct scsi_qla_host * vha)5485 qla2x00_do_work(struct scsi_qla_host *vha)
5486 {
5487 struct qla_work_evt *e, *tmp;
5488 unsigned long flags;
5489 LIST_HEAD(work);
5490 int rc;
5491
5492 spin_lock_irqsave(&vha->work_lock, flags);
5493 list_splice_init(&vha->work_list, &work);
5494 spin_unlock_irqrestore(&vha->work_lock, flags);
5495
5496 list_for_each_entry_safe(e, tmp, &work, list) {
5497 rc = QLA_SUCCESS;
5498 switch (e->type) {
5499 case QLA_EVT_AEN:
5500 fc_host_post_event(vha->host, fc_get_event_number(),
5501 e->u.aen.code, e->u.aen.data);
5502 break;
5503 case QLA_EVT_IDC_ACK:
5504 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5505 break;
5506 case QLA_EVT_ASYNC_LOGIN:
5507 qla2x00_async_login(vha, e->u.logio.fcport,
5508 e->u.logio.data);
5509 break;
5510 case QLA_EVT_ASYNC_LOGOUT:
5511 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5512 break;
5513 case QLA_EVT_ASYNC_ADISC:
5514 qla2x00_async_adisc(vha, e->u.logio.fcport,
5515 e->u.logio.data);
5516 break;
5517 case QLA_EVT_UEVENT:
5518 qla2x00_uevent_emit(vha, e->u.uevent.code);
5519 break;
5520 case QLA_EVT_AENFX:
5521 qlafx00_process_aen(vha, e);
5522 break;
5523 case QLA_EVT_UNMAP:
5524 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5525 break;
5526 case QLA_EVT_RELOGIN:
5527 qla2x00_relogin(vha);
5528 break;
5529 case QLA_EVT_NEW_SESS:
5530 qla24xx_create_new_sess(vha, e);
5531 break;
5532 case QLA_EVT_GPDB:
5533 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5534 e->u.fcport.opt);
5535 break;
5536 case QLA_EVT_PRLI:
5537 qla24xx_async_prli(vha, e->u.fcport.fcport);
5538 break;
5539 case QLA_EVT_GPSC:
5540 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5541 break;
5542 case QLA_EVT_GNL:
5543 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5544 break;
5545 case QLA_EVT_NACK:
5546 qla24xx_do_nack_work(vha, e);
5547 break;
5548 case QLA_EVT_ASYNC_PRLO:
5549 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5550 break;
5551 case QLA_EVT_ASYNC_PRLO_DONE:
5552 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5553 e->u.logio.data);
5554 break;
5555 case QLA_EVT_SCAN_CMD:
5556 qla_fab_async_scan(vha, e->u.iosb.sp);
5557 break;
5558 case QLA_EVT_SCAN_FINISH:
5559 qla_fab_scan_finish(vha, e->u.iosb.sp);
5560 break;
5561 case QLA_EVT_GFPNID:
5562 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5563 break;
5564 case QLA_EVT_SP_RETRY:
5565 qla_sp_retry(vha, e);
5566 break;
5567 case QLA_EVT_IIDMA:
5568 qla_do_iidma_work(vha, e->u.fcport.fcport);
5569 break;
5570 case QLA_EVT_ELS_PLOGI:
5571 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5572 e->u.fcport.fcport);
5573 break;
5574 case QLA_EVT_SA_REPLACE:
5575 rc = qla24xx_issue_sa_replace_iocb(vha, e);
5576 break;
5577 }
5578
5579 if (rc == EAGAIN) {
5580 /* put 'work' at head of 'vha->work_list' */
5581 spin_lock_irqsave(&vha->work_lock, flags);
5582 list_splice(&work, &vha->work_list);
5583 spin_unlock_irqrestore(&vha->work_lock, flags);
5584 break;
5585 }
5586 list_del_init(&e->list);
5587 if (e->flags & QLA_EVT_FLAG_FREE)
5588 kfree(e);
5589
5590 /* For each work completed decrement vha ref count */
5591 QLA_VHA_MARK_NOT_BUSY(vha);
5592 }
5593 }
5594
qla24xx_post_relogin_work(struct scsi_qla_host * vha)5595 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5596 {
5597 struct qla_work_evt *e;
5598
5599 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5600
5601 if (!e) {
5602 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5603 return QLA_FUNCTION_FAILED;
5604 }
5605
5606 return qla2x00_post_work(vha, e);
5607 }
5608
5609 /* Relogins all the fcports of a vport
5610 * Context: dpc thread
5611 */
qla2x00_relogin(struct scsi_qla_host * vha)5612 void qla2x00_relogin(struct scsi_qla_host *vha)
5613 {
5614 fc_port_t *fcport;
5615 int status, relogin_needed = 0;
5616 struct event_arg ea;
5617
5618 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5619 /*
5620 * If the port is not ONLINE then try to login
5621 * to it if we haven't run out of retries.
5622 */
5623 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5624 fcport->login_retry) {
5625 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5626 fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
5627 fcport->disc_state == DSC_LOGIN_COMPLETE)
5628 continue;
5629
5630 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5631 fcport->disc_state == DSC_DELETE_PEND) {
5632 relogin_needed = 1;
5633 } else {
5634 if (vha->hw->current_topology != ISP_CFG_NL) {
5635 memset(&ea, 0, sizeof(ea));
5636 ea.fcport = fcport;
5637 qla24xx_handle_relogin_event(vha, &ea);
5638 } else if (vha->hw->current_topology ==
5639 ISP_CFG_NL &&
5640 IS_QLA2XXX_MIDTYPE(vha->hw)) {
5641 (void)qla24xx_fcport_handle_login(vha,
5642 fcport);
5643 } else if (vha->hw->current_topology ==
5644 ISP_CFG_NL) {
5645 fcport->login_retry--;
5646 status =
5647 qla2x00_local_device_login(vha,
5648 fcport);
5649 if (status == QLA_SUCCESS) {
5650 fcport->old_loop_id =
5651 fcport->loop_id;
5652 ql_dbg(ql_dbg_disc, vha, 0x2003,
5653 "Port login OK: logged in ID 0x%x.\n",
5654 fcport->loop_id);
5655 qla2x00_update_fcport
5656 (vha, fcport);
5657 } else if (status == 1) {
5658 set_bit(RELOGIN_NEEDED,
5659 &vha->dpc_flags);
5660 /* retry the login again */
5661 ql_dbg(ql_dbg_disc, vha, 0x2007,
5662 "Retrying %d login again loop_id 0x%x.\n",
5663 fcport->login_retry,
5664 fcport->loop_id);
5665 } else {
5666 fcport->login_retry = 0;
5667 }
5668
5669 if (fcport->login_retry == 0 &&
5670 status != QLA_SUCCESS)
5671 qla2x00_clear_loop_id(fcport);
5672 }
5673 }
5674 }
5675 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5676 break;
5677 }
5678
5679 if (relogin_needed)
5680 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5681
5682 ql_dbg(ql_dbg_disc, vha, 0x400e,
5683 "Relogin end.\n");
5684 }
5685
5686 /* Schedule work on any of the dpc-workqueues */
5687 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)5688 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5689 {
5690 struct qla_hw_data *ha = base_vha->hw;
5691
5692 switch (work_code) {
5693 case MBA_IDC_AEN: /* 0x8200 */
5694 if (ha->dpc_lp_wq)
5695 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5696 break;
5697
5698 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5699 if (!ha->flags.nic_core_reset_hdlr_active) {
5700 if (ha->dpc_hp_wq)
5701 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5702 } else
5703 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5704 "NIC Core reset is already active. Skip "
5705 "scheduling it again.\n");
5706 break;
5707 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5708 if (ha->dpc_hp_wq)
5709 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5710 break;
5711 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5712 if (ha->dpc_hp_wq)
5713 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5714 break;
5715 default:
5716 ql_log(ql_log_warn, base_vha, 0xb05f,
5717 "Unknown work-code=0x%x.\n", work_code);
5718 }
5719
5720 return;
5721 }
5722
5723 /* Work: Perform NIC Core Unrecoverable state handling */
5724 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)5725 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5726 {
5727 struct qla_hw_data *ha =
5728 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5729 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5730 uint32_t dev_state = 0;
5731
5732 qla83xx_idc_lock(base_vha, 0);
5733 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5734 qla83xx_reset_ownership(base_vha);
5735 if (ha->flags.nic_core_reset_owner) {
5736 ha->flags.nic_core_reset_owner = 0;
5737 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5738 QLA8XXX_DEV_FAILED);
5739 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5740 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5741 }
5742 qla83xx_idc_unlock(base_vha, 0);
5743 }
5744
5745 /* Work: Execute IDC state handler */
5746 void
qla83xx_idc_state_handler_work(struct work_struct * work)5747 qla83xx_idc_state_handler_work(struct work_struct *work)
5748 {
5749 struct qla_hw_data *ha =
5750 container_of(work, struct qla_hw_data, idc_state_handler);
5751 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5752 uint32_t dev_state = 0;
5753
5754 qla83xx_idc_lock(base_vha, 0);
5755 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5756 if (dev_state == QLA8XXX_DEV_FAILED ||
5757 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5758 qla83xx_idc_state_handler(base_vha);
5759 qla83xx_idc_unlock(base_vha, 0);
5760 }
5761
5762 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)5763 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5764 {
5765 int rval = QLA_SUCCESS;
5766 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5767 uint32_t heart_beat_counter1, heart_beat_counter2;
5768
5769 do {
5770 if (time_after(jiffies, heart_beat_wait)) {
5771 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5772 "Nic Core f/w is not alive.\n");
5773 rval = QLA_FUNCTION_FAILED;
5774 break;
5775 }
5776
5777 qla83xx_idc_lock(base_vha, 0);
5778 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5779 &heart_beat_counter1);
5780 qla83xx_idc_unlock(base_vha, 0);
5781 msleep(100);
5782 qla83xx_idc_lock(base_vha, 0);
5783 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5784 &heart_beat_counter2);
5785 qla83xx_idc_unlock(base_vha, 0);
5786 } while (heart_beat_counter1 == heart_beat_counter2);
5787
5788 return rval;
5789 }
5790
5791 /* Work: Perform NIC Core Reset handling */
5792 void
qla83xx_nic_core_reset_work(struct work_struct * work)5793 qla83xx_nic_core_reset_work(struct work_struct *work)
5794 {
5795 struct qla_hw_data *ha =
5796 container_of(work, struct qla_hw_data, nic_core_reset);
5797 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5798 uint32_t dev_state = 0;
5799
5800 if (IS_QLA2031(ha)) {
5801 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5802 ql_log(ql_log_warn, base_vha, 0xb081,
5803 "Failed to dump mctp\n");
5804 return;
5805 }
5806
5807 if (!ha->flags.nic_core_reset_hdlr_active) {
5808 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5809 qla83xx_idc_lock(base_vha, 0);
5810 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5811 &dev_state);
5812 qla83xx_idc_unlock(base_vha, 0);
5813 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5814 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5815 "Nic Core f/w is alive.\n");
5816 return;
5817 }
5818 }
5819
5820 ha->flags.nic_core_reset_hdlr_active = 1;
5821 if (qla83xx_nic_core_reset(base_vha)) {
5822 /* NIC Core reset failed. */
5823 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5824 "NIC Core reset failed.\n");
5825 }
5826 ha->flags.nic_core_reset_hdlr_active = 0;
5827 }
5828 }
5829
5830 /* Work: Handle 8200 IDC aens */
5831 void
qla83xx_service_idc_aen(struct work_struct * work)5832 qla83xx_service_idc_aen(struct work_struct *work)
5833 {
5834 struct qla_hw_data *ha =
5835 container_of(work, struct qla_hw_data, idc_aen);
5836 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5837 uint32_t dev_state, idc_control;
5838
5839 qla83xx_idc_lock(base_vha, 0);
5840 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5841 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5842 qla83xx_idc_unlock(base_vha, 0);
5843 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5844 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5845 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5846 "Application requested NIC Core Reset.\n");
5847 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5848 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5849 QLA_SUCCESS) {
5850 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5851 "Other protocol driver requested NIC Core Reset.\n");
5852 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5853 }
5854 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5855 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5856 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5857 }
5858 }
5859
5860 /*
5861 * Control the frequency of IDC lock retries
5862 */
5863 #define QLA83XX_WAIT_LOGIC_MS 100
5864
5865 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)5866 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5867 {
5868 int rval;
5869 uint32_t data;
5870 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5871 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5872 struct qla_hw_data *ha = base_vha->hw;
5873
5874 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5875 "Trying force recovery of the IDC lock.\n");
5876
5877 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5878 if (rval)
5879 return rval;
5880
5881 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5882 return QLA_SUCCESS;
5883 } else {
5884 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5885 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5886 data);
5887 if (rval)
5888 return rval;
5889
5890 msleep(200);
5891
5892 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5893 &data);
5894 if (rval)
5895 return rval;
5896
5897 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5898 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5899 ~(idc_lck_rcvry_stage_mask));
5900 rval = qla83xx_wr_reg(base_vha,
5901 QLA83XX_IDC_LOCK_RECOVERY, data);
5902 if (rval)
5903 return rval;
5904
5905 /* Forcefully perform IDC UnLock */
5906 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5907 &data);
5908 if (rval)
5909 return rval;
5910 /* Clear lock-id by setting 0xff */
5911 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5912 0xff);
5913 if (rval)
5914 return rval;
5915 /* Clear lock-recovery by setting 0x0 */
5916 rval = qla83xx_wr_reg(base_vha,
5917 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5918 if (rval)
5919 return rval;
5920 } else
5921 return QLA_SUCCESS;
5922 }
5923
5924 return rval;
5925 }
5926
5927 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)5928 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5929 {
5930 int rval = QLA_SUCCESS;
5931 uint32_t o_drv_lockid, n_drv_lockid;
5932 unsigned long lock_recovery_timeout;
5933
5934 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5935 retry_lockid:
5936 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5937 if (rval)
5938 goto exit;
5939
5940 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5941 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5942 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5943 return QLA_SUCCESS;
5944 else
5945 return QLA_FUNCTION_FAILED;
5946 }
5947
5948 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5949 if (rval)
5950 goto exit;
5951
5952 if (o_drv_lockid == n_drv_lockid) {
5953 msleep(QLA83XX_WAIT_LOGIC_MS);
5954 goto retry_lockid;
5955 } else
5956 return QLA_SUCCESS;
5957
5958 exit:
5959 return rval;
5960 }
5961
5962 /*
5963 * Context: task, can sleep
5964 */
5965 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)5966 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5967 {
5968 uint32_t data;
5969 uint32_t lock_owner;
5970 struct qla_hw_data *ha = base_vha->hw;
5971
5972 might_sleep();
5973
5974 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5975 retry_lock:
5976 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5977 == QLA_SUCCESS) {
5978 if (data) {
5979 /* Setting lock-id to our function-number */
5980 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5981 ha->portnum);
5982 } else {
5983 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5984 &lock_owner);
5985 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5986 "Failed to acquire IDC lock, acquired by %d, "
5987 "retrying...\n", lock_owner);
5988
5989 /* Retry/Perform IDC-Lock recovery */
5990 if (qla83xx_idc_lock_recovery(base_vha)
5991 == QLA_SUCCESS) {
5992 msleep(QLA83XX_WAIT_LOGIC_MS);
5993 goto retry_lock;
5994 } else
5995 ql_log(ql_log_warn, base_vha, 0xb075,
5996 "IDC Lock recovery FAILED.\n");
5997 }
5998
5999 }
6000
6001 return;
6002 }
6003
6004 static bool
qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host * vha,struct purex_entry_24xx * purex)6005 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
6006 struct purex_entry_24xx *purex)
6007 {
6008 char fwstr[16];
6009 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
6010 struct port_database_24xx *pdb;
6011
6012 /* Domain Controller is always logged-out. */
6013 /* if RDP request is not from Domain Controller: */
6014 if (sid != 0xfffc01)
6015 return false;
6016
6017 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
6018
6019 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
6020 if (!pdb) {
6021 ql_dbg(ql_dbg_init, vha, 0x0181,
6022 "%s: Failed allocate pdb\n", __func__);
6023 } else if (qla24xx_get_port_database(vha,
6024 le16_to_cpu(purex->nport_handle), pdb)) {
6025 ql_dbg(ql_dbg_init, vha, 0x0181,
6026 "%s: Failed get pdb sid=%x\n", __func__, sid);
6027 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
6028 pdb->current_login_state != PDS_PRLI_COMPLETE) {
6029 ql_dbg(ql_dbg_init, vha, 0x0181,
6030 "%s: Port not logged in sid=%#x\n", __func__, sid);
6031 } else {
6032 /* RDP request is from logged in port */
6033 kfree(pdb);
6034 return false;
6035 }
6036 kfree(pdb);
6037
6038 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
6039 fwstr[strcspn(fwstr, " ")] = 0;
6040 /* if FW version allows RDP response length upto 2048 bytes: */
6041 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
6042 return false;
6043
6044 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
6045
6046 /* RDP response length is to be reduced to maximum 256 bytes */
6047 return true;
6048 }
6049
6050 /*
6051 * Function Name: qla24xx_process_purex_iocb
6052 *
6053 * Description:
6054 * Prepare a RDP response and send to Fabric switch
6055 *
6056 * PARAMETERS:
6057 * vha: SCSI qla host
6058 * purex: RDP request received by HBA
6059 */
qla24xx_process_purex_rdp(struct scsi_qla_host * vha,struct purex_item * item)6060 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
6061 struct purex_item *item)
6062 {
6063 struct qla_hw_data *ha = vha->hw;
6064 struct purex_entry_24xx *purex =
6065 (struct purex_entry_24xx *)&item->iocb;
6066 dma_addr_t rsp_els_dma;
6067 dma_addr_t rsp_payload_dma;
6068 dma_addr_t stat_dma;
6069 dma_addr_t sfp_dma;
6070 struct els_entry_24xx *rsp_els = NULL;
6071 struct rdp_rsp_payload *rsp_payload = NULL;
6072 struct link_statistics *stat = NULL;
6073 uint8_t *sfp = NULL;
6074 uint16_t sfp_flags = 0;
6075 uint rsp_payload_length = sizeof(*rsp_payload);
6076 int rval;
6077
6078 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
6079 "%s: Enter\n", __func__);
6080
6081 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
6082 "-------- ELS REQ -------\n");
6083 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
6084 purex, sizeof(*purex));
6085
6086 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
6087 rsp_payload_length =
6088 offsetof(typeof(*rsp_payload), optical_elmt_desc);
6089 ql_dbg(ql_dbg_init, vha, 0x0181,
6090 "Reducing RSP payload length to %u bytes...\n",
6091 rsp_payload_length);
6092 }
6093
6094 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6095 &rsp_els_dma, GFP_KERNEL);
6096 if (!rsp_els) {
6097 ql_log(ql_log_warn, vha, 0x0183,
6098 "Failed allocate dma buffer ELS RSP.\n");
6099 goto dealloc;
6100 }
6101
6102 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6103 &rsp_payload_dma, GFP_KERNEL);
6104 if (!rsp_payload) {
6105 ql_log(ql_log_warn, vha, 0x0184,
6106 "Failed allocate dma buffer ELS RSP payload.\n");
6107 goto dealloc;
6108 }
6109
6110 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6111 &sfp_dma, GFP_KERNEL);
6112
6113 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
6114 &stat_dma, GFP_KERNEL);
6115
6116 /* Prepare Response IOCB */
6117 rsp_els->entry_type = ELS_IOCB_TYPE;
6118 rsp_els->entry_count = 1;
6119 rsp_els->sys_define = 0;
6120 rsp_els->entry_status = 0;
6121 rsp_els->handle = 0;
6122 rsp_els->nport_handle = purex->nport_handle;
6123 rsp_els->tx_dsd_count = cpu_to_le16(1);
6124 rsp_els->vp_index = purex->vp_idx;
6125 rsp_els->sof_type = EST_SOFI3;
6126 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
6127 rsp_els->rx_dsd_count = 0;
6128 rsp_els->opcode = purex->els_frame_payload[0];
6129
6130 rsp_els->d_id[0] = purex->s_id[0];
6131 rsp_els->d_id[1] = purex->s_id[1];
6132 rsp_els->d_id[2] = purex->s_id[2];
6133
6134 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
6135 rsp_els->rx_byte_count = 0;
6136 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
6137
6138 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
6139 rsp_els->tx_len = rsp_els->tx_byte_count;
6140
6141 rsp_els->rx_address = 0;
6142 rsp_els->rx_len = 0;
6143
6144 /* Prepare Response Payload */
6145 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
6146 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6147 sizeof(rsp_payload->hdr));
6148
6149 /* Link service Request Info Descriptor */
6150 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6151 rsp_payload->ls_req_info_desc.desc_len =
6152 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6153 rsp_payload->ls_req_info_desc.req_payload_word_0 =
6154 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6155
6156 /* Link service Request Info Descriptor 2 */
6157 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6158 rsp_payload->ls_req_info_desc2.desc_len =
6159 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6160 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6161 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6162
6163
6164 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6165 rsp_payload->sfp_diag_desc.desc_len =
6166 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6167
6168 if (sfp) {
6169 /* SFP Flags */
6170 memset(sfp, 0, SFP_RTDI_LEN);
6171 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
6172 if (!rval) {
6173 /* SFP Flags bits 3-0: Port Tx Laser Type */
6174 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
6175 sfp_flags |= BIT_0; /* short wave */
6176 else if (sfp[0] & BIT_1)
6177 sfp_flags |= BIT_1; /* long wave 1310nm */
6178 else if (sfp[1] & BIT_4)
6179 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
6180 }
6181
6182 /* SFP Type */
6183 memset(sfp, 0, SFP_RTDI_LEN);
6184 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
6185 if (!rval) {
6186 sfp_flags |= BIT_4; /* optical */
6187 if (sfp[0] == 0x3)
6188 sfp_flags |= BIT_6; /* sfp+ */
6189 }
6190
6191 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6192
6193 /* SFP Diagnostics */
6194 memset(sfp, 0, SFP_RTDI_LEN);
6195 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
6196 if (!rval) {
6197 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6198 rsp_payload->sfp_diag_desc.temperature = trx[0];
6199 rsp_payload->sfp_diag_desc.vcc = trx[1];
6200 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6201 rsp_payload->sfp_diag_desc.tx_power = trx[3];
6202 rsp_payload->sfp_diag_desc.rx_power = trx[4];
6203 }
6204 }
6205
6206 /* Port Speed Descriptor */
6207 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6208 rsp_payload->port_speed_desc.desc_len =
6209 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6210 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6211 qla25xx_fdmi_port_speed_capability(ha));
6212 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6213 qla25xx_fdmi_port_speed_currently(ha));
6214
6215 /* Link Error Status Descriptor */
6216 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6217 rsp_payload->ls_err_desc.desc_len =
6218 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6219
6220 if (stat) {
6221 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
6222 if (!rval) {
6223 rsp_payload->ls_err_desc.link_fail_cnt =
6224 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
6225 rsp_payload->ls_err_desc.loss_sync_cnt =
6226 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
6227 rsp_payload->ls_err_desc.loss_sig_cnt =
6228 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6229 rsp_payload->ls_err_desc.prim_seq_err_cnt =
6230 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6231 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6232 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6233 rsp_payload->ls_err_desc.inval_crc_cnt =
6234 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6235 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6236 }
6237 }
6238
6239 /* Portname Descriptor */
6240 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6241 rsp_payload->port_name_diag_desc.desc_len =
6242 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6243 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6244 vha->node_name,
6245 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6246 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6247 vha->port_name,
6248 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6249
6250 /* F-Port Portname Descriptor */
6251 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6252 rsp_payload->port_name_direct_desc.desc_len =
6253 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6254 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6255 vha->fabric_node_name,
6256 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6257 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6258 vha->fabric_port_name,
6259 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6260
6261 /* Bufer Credit Descriptor */
6262 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6263 rsp_payload->buffer_credit_desc.desc_len =
6264 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6265 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6266 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6267 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6268
6269 if (ha->flags.plogi_template_valid) {
6270 uint32_t tmp =
6271 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6272 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6273 }
6274
6275 if (rsp_payload_length < sizeof(*rsp_payload))
6276 goto send;
6277
6278 /* Optical Element Descriptor, Temperature */
6279 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6280 rsp_payload->optical_elmt_desc[0].desc_len =
6281 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6282 /* Optical Element Descriptor, Voltage */
6283 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6284 rsp_payload->optical_elmt_desc[1].desc_len =
6285 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6286 /* Optical Element Descriptor, Tx Bias Current */
6287 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6288 rsp_payload->optical_elmt_desc[2].desc_len =
6289 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6290 /* Optical Element Descriptor, Tx Power */
6291 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6292 rsp_payload->optical_elmt_desc[3].desc_len =
6293 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6294 /* Optical Element Descriptor, Rx Power */
6295 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6296 rsp_payload->optical_elmt_desc[4].desc_len =
6297 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6298
6299 if (sfp) {
6300 memset(sfp, 0, SFP_RTDI_LEN);
6301 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6302 if (!rval) {
6303 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6304
6305 /* Optical Element Descriptor, Temperature */
6306 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6307 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6308 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6309 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6310 rsp_payload->optical_elmt_desc[0].element_flags =
6311 cpu_to_be32(1 << 28);
6312
6313 /* Optical Element Descriptor, Voltage */
6314 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6315 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6316 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6317 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6318 rsp_payload->optical_elmt_desc[1].element_flags =
6319 cpu_to_be32(2 << 28);
6320
6321 /* Optical Element Descriptor, Tx Bias Current */
6322 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6323 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6324 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6325 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6326 rsp_payload->optical_elmt_desc[2].element_flags =
6327 cpu_to_be32(3 << 28);
6328
6329 /* Optical Element Descriptor, Tx Power */
6330 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6331 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6332 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6333 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6334 rsp_payload->optical_elmt_desc[3].element_flags =
6335 cpu_to_be32(4 << 28);
6336
6337 /* Optical Element Descriptor, Rx Power */
6338 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6339 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6340 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6341 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6342 rsp_payload->optical_elmt_desc[4].element_flags =
6343 cpu_to_be32(5 << 28);
6344 }
6345
6346 memset(sfp, 0, SFP_RTDI_LEN);
6347 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6348 if (!rval) {
6349 /* Temperature high/low alarm/warning */
6350 rsp_payload->optical_elmt_desc[0].element_flags |=
6351 cpu_to_be32(
6352 (sfp[0] >> 7 & 1) << 3 |
6353 (sfp[0] >> 6 & 1) << 2 |
6354 (sfp[4] >> 7 & 1) << 1 |
6355 (sfp[4] >> 6 & 1) << 0);
6356
6357 /* Voltage high/low alarm/warning */
6358 rsp_payload->optical_elmt_desc[1].element_flags |=
6359 cpu_to_be32(
6360 (sfp[0] >> 5 & 1) << 3 |
6361 (sfp[0] >> 4 & 1) << 2 |
6362 (sfp[4] >> 5 & 1) << 1 |
6363 (sfp[4] >> 4 & 1) << 0);
6364
6365 /* Tx Bias Current high/low alarm/warning */
6366 rsp_payload->optical_elmt_desc[2].element_flags |=
6367 cpu_to_be32(
6368 (sfp[0] >> 3 & 1) << 3 |
6369 (sfp[0] >> 2 & 1) << 2 |
6370 (sfp[4] >> 3 & 1) << 1 |
6371 (sfp[4] >> 2 & 1) << 0);
6372
6373 /* Tx Power high/low alarm/warning */
6374 rsp_payload->optical_elmt_desc[3].element_flags |=
6375 cpu_to_be32(
6376 (sfp[0] >> 1 & 1) << 3 |
6377 (sfp[0] >> 0 & 1) << 2 |
6378 (sfp[4] >> 1 & 1) << 1 |
6379 (sfp[4] >> 0 & 1) << 0);
6380
6381 /* Rx Power high/low alarm/warning */
6382 rsp_payload->optical_elmt_desc[4].element_flags |=
6383 cpu_to_be32(
6384 (sfp[1] >> 7 & 1) << 3 |
6385 (sfp[1] >> 6 & 1) << 2 |
6386 (sfp[5] >> 7 & 1) << 1 |
6387 (sfp[5] >> 6 & 1) << 0);
6388 }
6389 }
6390
6391 /* Optical Product Data Descriptor */
6392 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6393 rsp_payload->optical_prod_desc.desc_len =
6394 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6395
6396 if (sfp) {
6397 memset(sfp, 0, SFP_RTDI_LEN);
6398 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6399 if (!rval) {
6400 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6401 sfp + 0,
6402 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6403 memcpy(rsp_payload->optical_prod_desc.part_number,
6404 sfp + 20,
6405 sizeof(rsp_payload->optical_prod_desc.part_number));
6406 memcpy(rsp_payload->optical_prod_desc.revision,
6407 sfp + 36,
6408 sizeof(rsp_payload->optical_prod_desc.revision));
6409 memcpy(rsp_payload->optical_prod_desc.serial_number,
6410 sfp + 48,
6411 sizeof(rsp_payload->optical_prod_desc.serial_number));
6412 }
6413
6414 memset(sfp, 0, SFP_RTDI_LEN);
6415 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6416 if (!rval) {
6417 memcpy(rsp_payload->optical_prod_desc.date,
6418 sfp + 0,
6419 sizeof(rsp_payload->optical_prod_desc.date));
6420 }
6421 }
6422
6423 send:
6424 ql_dbg(ql_dbg_init, vha, 0x0183,
6425 "Sending ELS Response to RDP Request...\n");
6426 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6427 "-------- ELS RSP -------\n");
6428 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6429 rsp_els, sizeof(*rsp_els));
6430 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6431 "-------- ELS RSP PAYLOAD -------\n");
6432 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6433 rsp_payload, rsp_payload_length);
6434
6435 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6436
6437 if (rval) {
6438 ql_log(ql_log_warn, vha, 0x0188,
6439 "%s: iocb failed to execute -> %x\n", __func__, rval);
6440 } else if (rsp_els->comp_status) {
6441 ql_log(ql_log_warn, vha, 0x0189,
6442 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6443 __func__, rsp_els->comp_status,
6444 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6445 } else {
6446 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6447 }
6448
6449 dealloc:
6450 if (stat)
6451 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6452 stat, stat_dma);
6453 if (sfp)
6454 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6455 sfp, sfp_dma);
6456 if (rsp_payload)
6457 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6458 rsp_payload, rsp_payload_dma);
6459 if (rsp_els)
6460 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6461 rsp_els, rsp_els_dma);
6462 }
6463
6464 void
qla24xx_free_purex_item(struct purex_item * item)6465 qla24xx_free_purex_item(struct purex_item *item)
6466 {
6467 if (item == &item->vha->default_item)
6468 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6469 else
6470 kfree(item);
6471 }
6472
qla24xx_process_purex_list(struct purex_list * list)6473 void qla24xx_process_purex_list(struct purex_list *list)
6474 {
6475 struct list_head head = LIST_HEAD_INIT(head);
6476 struct purex_item *item, *next;
6477 ulong flags;
6478
6479 spin_lock_irqsave(&list->lock, flags);
6480 list_splice_init(&list->head, &head);
6481 spin_unlock_irqrestore(&list->lock, flags);
6482
6483 list_for_each_entry_safe(item, next, &head, list) {
6484 list_del(&item->list);
6485 item->process_item(item->vha, item);
6486 qla24xx_free_purex_item(item);
6487 }
6488 }
6489
6490 /*
6491 * Context: task, can sleep
6492 */
6493 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)6494 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6495 {
6496 #if 0
6497 uint16_t options = (requester_id << 15) | BIT_7;
6498 #endif
6499 uint16_t retry;
6500 uint32_t data;
6501 struct qla_hw_data *ha = base_vha->hw;
6502
6503 might_sleep();
6504
6505 /* IDC-unlock implementation using driver-unlock/lock-id
6506 * remote registers
6507 */
6508 retry = 0;
6509 retry_unlock:
6510 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6511 == QLA_SUCCESS) {
6512 if (data == ha->portnum) {
6513 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6514 /* Clearing lock-id by setting 0xff */
6515 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6516 } else if (retry < 10) {
6517 /* SV: XXX: IDC unlock retrying needed here? */
6518
6519 /* Retry for IDC-unlock */
6520 msleep(QLA83XX_WAIT_LOGIC_MS);
6521 retry++;
6522 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6523 "Failed to release IDC lock, retrying=%d\n", retry);
6524 goto retry_unlock;
6525 }
6526 } else if (retry < 10) {
6527 /* Retry for IDC-unlock */
6528 msleep(QLA83XX_WAIT_LOGIC_MS);
6529 retry++;
6530 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6531 "Failed to read drv-lockid, retrying=%d\n", retry);
6532 goto retry_unlock;
6533 }
6534
6535 return;
6536
6537 #if 0
6538 /* XXX: IDC-unlock implementation using access-control mbx */
6539 retry = 0;
6540 retry_unlock2:
6541 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6542 if (retry < 10) {
6543 /* Retry for IDC-unlock */
6544 msleep(QLA83XX_WAIT_LOGIC_MS);
6545 retry++;
6546 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6547 "Failed to release IDC lock, retrying=%d\n", retry);
6548 goto retry_unlock2;
6549 }
6550 }
6551
6552 return;
6553 #endif
6554 }
6555
6556 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)6557 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6558 {
6559 int rval = QLA_SUCCESS;
6560 struct qla_hw_data *ha = vha->hw;
6561 uint32_t drv_presence;
6562
6563 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6564 if (rval == QLA_SUCCESS) {
6565 drv_presence |= (1 << ha->portnum);
6566 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6567 drv_presence);
6568 }
6569
6570 return rval;
6571 }
6572
6573 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)6574 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6575 {
6576 int rval = QLA_SUCCESS;
6577
6578 qla83xx_idc_lock(vha, 0);
6579 rval = __qla83xx_set_drv_presence(vha);
6580 qla83xx_idc_unlock(vha, 0);
6581
6582 return rval;
6583 }
6584
6585 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6586 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6587 {
6588 int rval = QLA_SUCCESS;
6589 struct qla_hw_data *ha = vha->hw;
6590 uint32_t drv_presence;
6591
6592 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6593 if (rval == QLA_SUCCESS) {
6594 drv_presence &= ~(1 << ha->portnum);
6595 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6596 drv_presence);
6597 }
6598
6599 return rval;
6600 }
6601
6602 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6603 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6604 {
6605 int rval = QLA_SUCCESS;
6606
6607 qla83xx_idc_lock(vha, 0);
6608 rval = __qla83xx_clear_drv_presence(vha);
6609 qla83xx_idc_unlock(vha, 0);
6610
6611 return rval;
6612 }
6613
6614 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)6615 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6616 {
6617 struct qla_hw_data *ha = vha->hw;
6618 uint32_t drv_ack, drv_presence;
6619 unsigned long ack_timeout;
6620
6621 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6622 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6623 while (1) {
6624 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6625 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6626 if ((drv_ack & drv_presence) == drv_presence)
6627 break;
6628
6629 if (time_after_eq(jiffies, ack_timeout)) {
6630 ql_log(ql_log_warn, vha, 0xb067,
6631 "RESET ACK TIMEOUT! drv_presence=0x%x "
6632 "drv_ack=0x%x\n", drv_presence, drv_ack);
6633 /*
6634 * The function(s) which did not ack in time are forced
6635 * to withdraw any further participation in the IDC
6636 * reset.
6637 */
6638 if (drv_ack != drv_presence)
6639 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6640 drv_ack);
6641 break;
6642 }
6643
6644 qla83xx_idc_unlock(vha, 0);
6645 msleep(1000);
6646 qla83xx_idc_lock(vha, 0);
6647 }
6648
6649 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6650 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6651 }
6652
6653 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)6654 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6655 {
6656 int rval = QLA_SUCCESS;
6657 uint32_t idc_control;
6658
6659 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6660 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6661
6662 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6663 __qla83xx_get_idc_control(vha, &idc_control);
6664 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6665 __qla83xx_set_idc_control(vha, 0);
6666
6667 qla83xx_idc_unlock(vha, 0);
6668 rval = qla83xx_restart_nic_firmware(vha);
6669 qla83xx_idc_lock(vha, 0);
6670
6671 if (rval != QLA_SUCCESS) {
6672 ql_log(ql_log_fatal, vha, 0xb06a,
6673 "Failed to restart NIC f/w.\n");
6674 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6675 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6676 } else {
6677 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6678 "Success in restarting nic f/w.\n");
6679 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6680 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6681 }
6682
6683 return rval;
6684 }
6685
6686 /* Assumes idc_lock always held on entry */
6687 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)6688 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6689 {
6690 struct qla_hw_data *ha = base_vha->hw;
6691 int rval = QLA_SUCCESS;
6692 unsigned long dev_init_timeout;
6693 uint32_t dev_state;
6694
6695 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6696 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6697
6698 while (1) {
6699
6700 if (time_after_eq(jiffies, dev_init_timeout)) {
6701 ql_log(ql_log_warn, base_vha, 0xb06e,
6702 "Initialization TIMEOUT!\n");
6703 /* Init timeout. Disable further NIC Core
6704 * communication.
6705 */
6706 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6707 QLA8XXX_DEV_FAILED);
6708 ql_log(ql_log_info, base_vha, 0xb06f,
6709 "HW State: FAILED.\n");
6710 }
6711
6712 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6713 switch (dev_state) {
6714 case QLA8XXX_DEV_READY:
6715 if (ha->flags.nic_core_reset_owner)
6716 qla83xx_idc_audit(base_vha,
6717 IDC_AUDIT_COMPLETION);
6718 ha->flags.nic_core_reset_owner = 0;
6719 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6720 "Reset_owner reset by 0x%x.\n",
6721 ha->portnum);
6722 goto exit;
6723 case QLA8XXX_DEV_COLD:
6724 if (ha->flags.nic_core_reset_owner)
6725 rval = qla83xx_device_bootstrap(base_vha);
6726 else {
6727 /* Wait for AEN to change device-state */
6728 qla83xx_idc_unlock(base_vha, 0);
6729 msleep(1000);
6730 qla83xx_idc_lock(base_vha, 0);
6731 }
6732 break;
6733 case QLA8XXX_DEV_INITIALIZING:
6734 /* Wait for AEN to change device-state */
6735 qla83xx_idc_unlock(base_vha, 0);
6736 msleep(1000);
6737 qla83xx_idc_lock(base_vha, 0);
6738 break;
6739 case QLA8XXX_DEV_NEED_RESET:
6740 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6741 qla83xx_need_reset_handler(base_vha);
6742 else {
6743 /* Wait for AEN to change device-state */
6744 qla83xx_idc_unlock(base_vha, 0);
6745 msleep(1000);
6746 qla83xx_idc_lock(base_vha, 0);
6747 }
6748 /* reset timeout value after need reset handler */
6749 dev_init_timeout = jiffies +
6750 (ha->fcoe_dev_init_timeout * HZ);
6751 break;
6752 case QLA8XXX_DEV_NEED_QUIESCENT:
6753 /* XXX: DEBUG for now */
6754 qla83xx_idc_unlock(base_vha, 0);
6755 msleep(1000);
6756 qla83xx_idc_lock(base_vha, 0);
6757 break;
6758 case QLA8XXX_DEV_QUIESCENT:
6759 /* XXX: DEBUG for now */
6760 if (ha->flags.quiesce_owner)
6761 goto exit;
6762
6763 qla83xx_idc_unlock(base_vha, 0);
6764 msleep(1000);
6765 qla83xx_idc_lock(base_vha, 0);
6766 dev_init_timeout = jiffies +
6767 (ha->fcoe_dev_init_timeout * HZ);
6768 break;
6769 case QLA8XXX_DEV_FAILED:
6770 if (ha->flags.nic_core_reset_owner)
6771 qla83xx_idc_audit(base_vha,
6772 IDC_AUDIT_COMPLETION);
6773 ha->flags.nic_core_reset_owner = 0;
6774 __qla83xx_clear_drv_presence(base_vha);
6775 qla83xx_idc_unlock(base_vha, 0);
6776 qla8xxx_dev_failed_handler(base_vha);
6777 rval = QLA_FUNCTION_FAILED;
6778 qla83xx_idc_lock(base_vha, 0);
6779 goto exit;
6780 case QLA8XXX_BAD_VALUE:
6781 qla83xx_idc_unlock(base_vha, 0);
6782 msleep(1000);
6783 qla83xx_idc_lock(base_vha, 0);
6784 break;
6785 default:
6786 ql_log(ql_log_warn, base_vha, 0xb071,
6787 "Unknown Device State: %x.\n", dev_state);
6788 qla83xx_idc_unlock(base_vha, 0);
6789 qla8xxx_dev_failed_handler(base_vha);
6790 rval = QLA_FUNCTION_FAILED;
6791 qla83xx_idc_lock(base_vha, 0);
6792 goto exit;
6793 }
6794 }
6795
6796 exit:
6797 return rval;
6798 }
6799
6800 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)6801 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6802 {
6803 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6804 board_disable);
6805 struct pci_dev *pdev = ha->pdev;
6806 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6807
6808 ql_log(ql_log_warn, base_vha, 0x015b,
6809 "Disabling adapter.\n");
6810
6811 if (!atomic_read(&pdev->enable_cnt)) {
6812 ql_log(ql_log_info, base_vha, 0xfffc,
6813 "PCI device disabled, no action req for PCI error=%lx\n",
6814 base_vha->pci_flags);
6815 return;
6816 }
6817
6818 /*
6819 * if UNLOADING flag is already set, then continue unload,
6820 * where it was set first.
6821 */
6822 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6823 return;
6824
6825 qla2x00_wait_for_sess_deletion(base_vha);
6826
6827 qla2x00_delete_all_vps(ha, base_vha);
6828
6829 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6830
6831 qla2x00_dfs_remove(base_vha);
6832
6833 qla84xx_put_chip(base_vha);
6834
6835 if (base_vha->timer_active)
6836 qla2x00_stop_timer(base_vha);
6837
6838 base_vha->flags.online = 0;
6839
6840 qla2x00_destroy_deferred_work(ha);
6841
6842 /*
6843 * Do not try to stop beacon blink as it will issue a mailbox
6844 * command.
6845 */
6846 qla2x00_free_sysfs_attr(base_vha, false);
6847
6848 fc_remove_host(base_vha->host);
6849
6850 scsi_remove_host(base_vha->host);
6851
6852 base_vha->flags.init_done = 0;
6853 qla25xx_delete_queues(base_vha);
6854 qla2x00_free_fcports(base_vha);
6855 qla2x00_free_irqs(base_vha);
6856 qla2x00_mem_free(ha);
6857 qla82xx_md_free(base_vha);
6858 qla2x00_free_queues(ha);
6859
6860 qla2x00_unmap_iobases(ha);
6861
6862 pci_release_selected_regions(ha->pdev, ha->bars);
6863 pci_disable_device(pdev);
6864
6865 /*
6866 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6867 */
6868 }
6869
6870 /**************************************************************************
6871 * qla2x00_do_dpc
6872 * This kernel thread is a task that is schedule by the interrupt handler
6873 * to perform the background processing for interrupts.
6874 *
6875 * Notes:
6876 * This task always run in the context of a kernel thread. It
6877 * is kick-off by the driver's detect code and starts up
6878 * up one per adapter. It immediately goes to sleep and waits for
6879 * some fibre event. When either the interrupt handler or
6880 * the timer routine detects a event it will one of the task
6881 * bits then wake us up.
6882 **************************************************************************/
6883 static int
qla2x00_do_dpc(void * data)6884 qla2x00_do_dpc(void *data)
6885 {
6886 scsi_qla_host_t *base_vha;
6887 struct qla_hw_data *ha;
6888 uint32_t online;
6889 struct qla_qpair *qpair;
6890
6891 ha = (struct qla_hw_data *)data;
6892 base_vha = pci_get_drvdata(ha->pdev);
6893
6894 set_user_nice(current, MIN_NICE);
6895
6896 set_current_state(TASK_INTERRUPTIBLE);
6897 while (1) {
6898 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6899 "DPC handler sleeping.\n");
6900
6901 schedule();
6902
6903 if (kthread_should_stop())
6904 break;
6905
6906 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
6907 qla_pci_set_eeh_busy(base_vha);
6908
6909 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6910 goto end_loop;
6911
6912 if (ha->flags.eeh_busy) {
6913 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6914 "eeh_busy=%d.\n", ha->flags.eeh_busy);
6915 goto end_loop;
6916 }
6917
6918 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6919 /* don't do any work. Wait to be terminated by kthread_stop */
6920 goto end_loop;
6921
6922 ha->dpc_active = 1;
6923
6924 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6925 "DPC handler waking up, dpc_flags=0x%lx.\n",
6926 base_vha->dpc_flags);
6927
6928 if (IS_P3P_TYPE(ha)) {
6929 if (IS_QLA8044(ha)) {
6930 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6931 &base_vha->dpc_flags)) {
6932 qla8044_idc_lock(ha);
6933 qla8044_wr_direct(base_vha,
6934 QLA8044_CRB_DEV_STATE_INDEX,
6935 QLA8XXX_DEV_FAILED);
6936 qla8044_idc_unlock(ha);
6937 ql_log(ql_log_info, base_vha, 0x4004,
6938 "HW State: FAILED.\n");
6939 qla8044_device_state_handler(base_vha);
6940 continue;
6941 }
6942
6943 } else {
6944 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6945 &base_vha->dpc_flags)) {
6946 qla82xx_idc_lock(ha);
6947 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6948 QLA8XXX_DEV_FAILED);
6949 qla82xx_idc_unlock(ha);
6950 ql_log(ql_log_info, base_vha, 0x0151,
6951 "HW State: FAILED.\n");
6952 qla82xx_device_state_handler(base_vha);
6953 continue;
6954 }
6955 }
6956
6957 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6958 &base_vha->dpc_flags)) {
6959
6960 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6961 "FCoE context reset scheduled.\n");
6962 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6963 &base_vha->dpc_flags))) {
6964 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6965 /* FCoE-ctx reset failed.
6966 * Escalate to chip-reset
6967 */
6968 set_bit(ISP_ABORT_NEEDED,
6969 &base_vha->dpc_flags);
6970 }
6971 clear_bit(ABORT_ISP_ACTIVE,
6972 &base_vha->dpc_flags);
6973 }
6974
6975 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6976 "FCoE context reset end.\n");
6977 }
6978 } else if (IS_QLAFX00(ha)) {
6979 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6980 &base_vha->dpc_flags)) {
6981 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6982 "Firmware Reset Recovery\n");
6983 if (qlafx00_reset_initialize(base_vha)) {
6984 /* Failed. Abort isp later. */
6985 if (!test_bit(UNLOADING,
6986 &base_vha->dpc_flags)) {
6987 set_bit(ISP_UNRECOVERABLE,
6988 &base_vha->dpc_flags);
6989 ql_dbg(ql_dbg_dpc, base_vha,
6990 0x4021,
6991 "Reset Recovery Failed\n");
6992 }
6993 }
6994 }
6995
6996 if (test_and_clear_bit(FX00_TARGET_SCAN,
6997 &base_vha->dpc_flags)) {
6998 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6999 "ISPFx00 Target Scan scheduled\n");
7000 if (qlafx00_rescan_isp(base_vha)) {
7001 if (!test_bit(UNLOADING,
7002 &base_vha->dpc_flags))
7003 set_bit(ISP_UNRECOVERABLE,
7004 &base_vha->dpc_flags);
7005 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
7006 "ISPFx00 Target Scan Failed\n");
7007 }
7008 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
7009 "ISPFx00 Target Scan End\n");
7010 }
7011 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
7012 &base_vha->dpc_flags)) {
7013 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
7014 "ISPFx00 Host Info resend scheduled\n");
7015 qlafx00_fx_disc(base_vha,
7016 &base_vha->hw->mr.fcport,
7017 FXDISC_REG_HOST_INFO);
7018 }
7019 }
7020
7021 if (test_and_clear_bit(DETECT_SFP_CHANGE,
7022 &base_vha->dpc_flags)) {
7023 /* Semantic:
7024 * - NO-OP -- await next ISP-ABORT. Preferred method
7025 * to minimize disruptions that will occur
7026 * when a forced chip-reset occurs.
7027 * - Force -- ISP-ABORT scheduled.
7028 */
7029 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
7030 }
7031
7032 if (test_and_clear_bit
7033 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
7034 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
7035 bool do_reset = true;
7036
7037 switch (base_vha->qlini_mode) {
7038 case QLA2XXX_INI_MODE_ENABLED:
7039 break;
7040 case QLA2XXX_INI_MODE_DISABLED:
7041 if (!qla_tgt_mode_enabled(base_vha) &&
7042 !ha->flags.fw_started)
7043 do_reset = false;
7044 break;
7045 case QLA2XXX_INI_MODE_DUAL:
7046 if (!qla_dual_mode_enabled(base_vha) &&
7047 !ha->flags.fw_started)
7048 do_reset = false;
7049 break;
7050 default:
7051 break;
7052 }
7053
7054 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
7055 &base_vha->dpc_flags))) {
7056 base_vha->flags.online = 1;
7057 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
7058 "ISP abort scheduled.\n");
7059 if (ha->isp_ops->abort_isp(base_vha)) {
7060 /* failed. retry later */
7061 set_bit(ISP_ABORT_NEEDED,
7062 &base_vha->dpc_flags);
7063 }
7064 clear_bit(ABORT_ISP_ACTIVE,
7065 &base_vha->dpc_flags);
7066 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
7067 "ISP abort end.\n");
7068 }
7069 }
7070
7071 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
7072 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
7073 qla24xx_process_purex_list
7074 (&base_vha->purex_list);
7075 clear_bit(PROCESS_PUREX_IOCB,
7076 &base_vha->dpc_flags);
7077 }
7078 }
7079
7080 if (IS_QLAFX00(ha))
7081 goto loop_resync_check;
7082
7083 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7084 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
7085 "Quiescence mode scheduled.\n");
7086 if (IS_P3P_TYPE(ha)) {
7087 if (IS_QLA82XX(ha))
7088 qla82xx_device_state_handler(base_vha);
7089 if (IS_QLA8044(ha))
7090 qla8044_device_state_handler(base_vha);
7091 clear_bit(ISP_QUIESCE_NEEDED,
7092 &base_vha->dpc_flags);
7093 if (!ha->flags.quiesce_owner) {
7094 qla2x00_perform_loop_resync(base_vha);
7095 if (IS_QLA82XX(ha)) {
7096 qla82xx_idc_lock(ha);
7097 qla82xx_clear_qsnt_ready(
7098 base_vha);
7099 qla82xx_idc_unlock(ha);
7100 } else if (IS_QLA8044(ha)) {
7101 qla8044_idc_lock(ha);
7102 qla8044_clear_qsnt_ready(
7103 base_vha);
7104 qla8044_idc_unlock(ha);
7105 }
7106 }
7107 } else {
7108 clear_bit(ISP_QUIESCE_NEEDED,
7109 &base_vha->dpc_flags);
7110 qla2x00_quiesce_io(base_vha);
7111 }
7112 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
7113 "Quiescence mode end.\n");
7114 }
7115
7116 if (test_and_clear_bit(RESET_MARKER_NEEDED,
7117 &base_vha->dpc_flags) &&
7118 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
7119
7120 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
7121 "Reset marker scheduled.\n");
7122 qla2x00_rst_aen(base_vha);
7123 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7124 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
7125 "Reset marker end.\n");
7126 }
7127
7128 /* Retry each device up to login retry count */
7129 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
7130 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
7131 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
7132
7133 if (!base_vha->relogin_jif ||
7134 time_after_eq(jiffies, base_vha->relogin_jif)) {
7135 base_vha->relogin_jif = jiffies + HZ;
7136 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
7137
7138 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
7139 "Relogin scheduled.\n");
7140 qla24xx_post_relogin_work(base_vha);
7141 }
7142 }
7143 loop_resync_check:
7144 if (!qla2x00_reset_active(base_vha) &&
7145 test_and_clear_bit(LOOP_RESYNC_NEEDED,
7146 &base_vha->dpc_flags)) {
7147 /*
7148 * Allow abort_isp to complete before moving on to scanning.
7149 */
7150 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
7151 "Loop resync scheduled.\n");
7152
7153 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
7154 &base_vha->dpc_flags))) {
7155
7156 qla2x00_loop_resync(base_vha);
7157
7158 clear_bit(LOOP_RESYNC_ACTIVE,
7159 &base_vha->dpc_flags);
7160 }
7161
7162 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
7163 "Loop resync end.\n");
7164 }
7165
7166 if (IS_QLAFX00(ha))
7167 goto intr_on_check;
7168
7169 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7170 atomic_read(&base_vha->loop_state) == LOOP_READY) {
7171 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7172 qla2xxx_flash_npiv_conf(base_vha);
7173 }
7174
7175 intr_on_check:
7176 if (!ha->interrupts_on)
7177 ha->isp_ops->enable_intrs(ha);
7178
7179 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
7180 &base_vha->dpc_flags)) {
7181 if (ha->beacon_blink_led == 1)
7182 ha->isp_ops->beacon_blink(base_vha);
7183 }
7184
7185 /* qpair online check */
7186 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
7187 &base_vha->dpc_flags)) {
7188 if (ha->flags.eeh_busy ||
7189 ha->flags.pci_channel_io_perm_failure)
7190 online = 0;
7191 else
7192 online = 1;
7193
7194 mutex_lock(&ha->mq_lock);
7195 list_for_each_entry(qpair, &base_vha->qp_list,
7196 qp_list_elem)
7197 qpair->online = online;
7198 mutex_unlock(&ha->mq_lock);
7199 }
7200
7201 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
7202 &base_vha->dpc_flags)) {
7203 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;
7204
7205 if (threshold > ha->orig_fw_xcb_count)
7206 threshold = ha->orig_fw_xcb_count;
7207
7208 ql_log(ql_log_info, base_vha, 0xffffff,
7209 "SET ZIO Activity exchange threshold to %d.\n",
7210 threshold);
7211 if (qla27xx_set_zio_threshold(base_vha, threshold)) {
7212 ql_log(ql_log_info, base_vha, 0xffffff,
7213 "Unable to SET ZIO Activity exchange threshold to %d.\n",
7214 threshold);
7215 }
7216 }
7217
7218 if (!IS_QLAFX00(ha))
7219 qla2x00_do_dpc_all_vps(base_vha);
7220
7221 if (test_and_clear_bit(N2N_LINK_RESET,
7222 &base_vha->dpc_flags)) {
7223 qla2x00_lip_reset(base_vha);
7224 }
7225
7226 ha->dpc_active = 0;
7227 end_loop:
7228 set_current_state(TASK_INTERRUPTIBLE);
7229 } /* End of while(1) */
7230 __set_current_state(TASK_RUNNING);
7231
7232 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7233 "DPC handler exiting.\n");
7234
7235 /*
7236 * Make sure that nobody tries to wake us up again.
7237 */
7238 ha->dpc_active = 0;
7239
7240 return 0;
7241 }
7242
7243 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)7244 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7245 {
7246 struct qla_hw_data *ha = vha->hw;
7247 struct task_struct *t = ha->dpc_thread;
7248
7249 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7250 wake_up_process(t);
7251 }
7252 EXPORT_SYMBOL(qla2xxx_wake_dpc);
7253
7254 /*
7255 * qla2x00_rst_aen
7256 * Processes asynchronous reset.
7257 *
7258 * Input:
7259 * ha = adapter block pointer.
7260 */
7261 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)7262 qla2x00_rst_aen(scsi_qla_host_t *vha)
7263 {
7264 if (vha->flags.online && !vha->flags.reset_active &&
7265 !atomic_read(&vha->loop_down_timer) &&
7266 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7267 do {
7268 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7269
7270 /*
7271 * Issue marker command only when we are going to start
7272 * the I/O.
7273 */
7274 vha->marker_needed = 1;
7275 } while (!atomic_read(&vha->loop_down_timer) &&
7276 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7277 }
7278 }
7279
qla_do_heartbeat(struct scsi_qla_host * vha)7280 static bool qla_do_heartbeat(struct scsi_qla_host *vha)
7281 {
7282 struct qla_hw_data *ha = vha->hw;
7283 u32 cmpl_cnt;
7284 u16 i;
7285 bool do_heartbeat = false;
7286
7287 /*
7288 * Allow do_heartbeat only if we don’t have any active interrupts,
7289 * but there are still IOs outstanding with firmware.
7290 */
7291 cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
7292 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
7293 cmpl_cnt != ha->base_qpair->cmd_cnt) {
7294 do_heartbeat = true;
7295 goto skip;
7296 }
7297 ha->base_qpair->prev_completion_cnt = cmpl_cnt;
7298
7299 for (i = 0; i < ha->max_qpairs; i++) {
7300 if (ha->queue_pair_map[i]) {
7301 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
7302 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
7303 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
7304 do_heartbeat = true;
7305 break;
7306 }
7307 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
7308 }
7309 }
7310
7311 skip:
7312 return do_heartbeat;
7313 }
7314
qla_heart_beat(struct scsi_qla_host * vha,u16 dpc_started)7315 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started)
7316 {
7317 struct qla_hw_data *ha = vha->hw;
7318
7319 if (vha->vp_idx)
7320 return;
7321
7322 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
7323 return;
7324
7325 /*
7326 * dpc thread cannot run if heartbeat is running at the same time.
7327 * We also do not want to starve heartbeat task. Therefore, do
7328 * heartbeat task at least once every 5 seconds.
7329 */
7330 if (dpc_started &&
7331 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
7332 return;
7333
7334 if (qla_do_heartbeat(vha)) {
7335 ha->last_heartbeat_run_jiffies = jiffies;
7336 queue_work(ha->wq, &ha->heartbeat_work);
7337 }
7338 }
7339
qla_wind_down_chip(scsi_qla_host_t * vha)7340 static void qla_wind_down_chip(scsi_qla_host_t *vha)
7341 {
7342 struct qla_hw_data *ha = vha->hw;
7343
7344 if (!ha->flags.eeh_busy)
7345 return;
7346 if (ha->pci_error_state)
7347 /* system is trying to recover */
7348 return;
7349
7350 /*
7351 * Current system is not handling PCIE error. At this point, this is
7352 * best effort to wind down the adapter.
7353 */
7354 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
7355 !ha->flags.eeh_flush) {
7356 ql_log(ql_log_info, vha, 0x9009,
7357 "PCI Error detected, attempting to reset hardware.\n");
7358
7359 ha->isp_ops->reset_chip(vha);
7360 ha->isp_ops->disable_intrs(ha);
7361
7362 ha->flags.eeh_flush = EEH_FLUSH_RDY;
7363 ha->eeh_jif = jiffies;
7364
7365 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
7366 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) {
7367 pci_clear_master(ha->pdev);
7368
7369 /* flush all command */
7370 qla2x00_abort_isp_cleanup(vha);
7371 ha->flags.eeh_flush = EEH_FLUSH_DONE;
7372
7373 ql_log(ql_log_info, vha, 0x900a,
7374 "PCI Error handling complete, all IOs aborted.\n");
7375 }
7376 }
7377
7378 /**************************************************************************
7379 * qla2x00_timer
7380 *
7381 * Description:
7382 * One second timer
7383 *
7384 * Context: Interrupt
7385 ***************************************************************************/
7386 void
qla2x00_timer(struct timer_list * t)7387 qla2x00_timer(struct timer_list *t)
7388 {
7389 scsi_qla_host_t *vha = timer_container_of(vha, t, timer);
7390 unsigned long cpu_flags = 0;
7391 int start_dpc = 0;
7392 int index;
7393 srb_t *sp;
7394 uint16_t w;
7395 struct qla_hw_data *ha = vha->hw;
7396 struct req_que *req;
7397 unsigned long flags;
7398 fc_port_t *fcport = NULL;
7399
7400 if (ha->flags.eeh_busy) {
7401 qla_wind_down_chip(vha);
7402
7403 ql_dbg(ql_dbg_timer, vha, 0x6000,
7404 "EEH = %d, restarting timer.\n",
7405 ha->flags.eeh_busy);
7406 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7407 return;
7408 }
7409
7410 /*
7411 * Hardware read to raise pending EEH errors during mailbox waits. If
7412 * the read returns -1 then disable the board.
7413 */
7414 if (!pci_channel_offline(ha->pdev)) {
7415 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7416 qla2x00_check_reg16_for_disconnect(vha, w);
7417 }
7418
7419 /* Make sure qla82xx_watchdog is run only for physical port */
7420 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7421 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7422 start_dpc++;
7423 if (IS_QLA82XX(ha))
7424 qla82xx_watchdog(vha);
7425 else if (IS_QLA8044(ha))
7426 qla8044_watchdog(vha);
7427 }
7428
7429 if (!vha->vp_idx && IS_QLAFX00(ha))
7430 qlafx00_timer_routine(vha);
7431
7432 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7433 vha->link_down_time++;
7434
7435 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7436 list_for_each_entry(fcport, &vha->vp_fcports, list) {
7437 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7438 fcport->tgt_link_down_time++;
7439 }
7440 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
7441
7442 /* Loop down handler. */
7443 if (atomic_read(&vha->loop_down_timer) > 0 &&
7444 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7445 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7446 && vha->flags.online) {
7447
7448 if (atomic_read(&vha->loop_down_timer) ==
7449 vha->loop_down_abort_time) {
7450
7451 ql_log(ql_log_info, vha, 0x6008,
7452 "Loop down - aborting the queues before time expires.\n");
7453
7454 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7455 atomic_set(&vha->loop_state, LOOP_DEAD);
7456
7457 /*
7458 * Schedule an ISP abort to return any FCP2-device
7459 * commands.
7460 */
7461 /* NPIV - scan physical port only */
7462 if (!vha->vp_idx) {
7463 spin_lock_irqsave(&ha->hardware_lock,
7464 cpu_flags);
7465 req = ha->req_q_map[0];
7466 for (index = 1;
7467 index < req->num_outstanding_cmds;
7468 index++) {
7469 fc_port_t *sfcp;
7470
7471 sp = req->outstanding_cmds[index];
7472 if (!sp)
7473 continue;
7474 if (sp->cmd_type != TYPE_SRB)
7475 continue;
7476 if (sp->type != SRB_SCSI_CMD)
7477 continue;
7478 sfcp = sp->fcport;
7479 if (!(sfcp->flags & FCF_FCP2_DEVICE))
7480 continue;
7481
7482 if (IS_QLA82XX(ha))
7483 set_bit(FCOE_CTX_RESET_NEEDED,
7484 &vha->dpc_flags);
7485 else
7486 set_bit(ISP_ABORT_NEEDED,
7487 &vha->dpc_flags);
7488 break;
7489 }
7490 spin_unlock_irqrestore(&ha->hardware_lock,
7491 cpu_flags);
7492 }
7493 start_dpc++;
7494 }
7495
7496 /* if the loop has been down for 4 minutes, reinit adapter */
7497 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7498 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) {
7499 ql_log(ql_log_warn, vha, 0x6009,
7500 "Loop down - aborting ISP.\n");
7501
7502 if (IS_QLA82XX(ha))
7503 set_bit(FCOE_CTX_RESET_NEEDED,
7504 &vha->dpc_flags);
7505 else
7506 set_bit(ISP_ABORT_NEEDED,
7507 &vha->dpc_flags);
7508 }
7509 }
7510 ql_dbg(ql_dbg_timer, vha, 0x600a,
7511 "Loop down - seconds remaining %d.\n",
7512 atomic_read(&vha->loop_down_timer));
7513 }
7514 /* Check if beacon LED needs to be blinked for physical host only */
7515 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7516 /* There is no beacon_blink function for ISP82xx */
7517 if (!IS_P3P_TYPE(ha)) {
7518 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7519 start_dpc++;
7520 }
7521 }
7522
7523 /* check if edif running */
7524 if (vha->hw->flags.edif_enabled)
7525 qla_edif_timer(vha);
7526
7527 /* Process any deferred work. */
7528 if (!list_empty(&vha->work_list)) {
7529 unsigned long flags;
7530 bool q = false;
7531
7532 spin_lock_irqsave(&vha->work_lock, flags);
7533 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7534 q = true;
7535 spin_unlock_irqrestore(&vha->work_lock, flags);
7536 if (q)
7537 queue_work(vha->hw->wq, &vha->iocb_work);
7538 }
7539
7540 /*
7541 * FC-NVME
7542 * see if the active AEN count has changed from what was last reported.
7543 */
7544 index = atomic_read(&ha->nvme_active_aen_cnt);
7545 if (!vha->vp_idx &&
7546 (index != ha->nvme_last_rptd_aen) &&
7547 ha->zio_mode == QLA_ZIO_MODE_6 &&
7548 !ha->flags.host_shutting_down) {
7549 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7550 ql_log(ql_log_info, vha, 0x3002,
7551 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7552 ha->nvme_last_rptd_aen);
7553 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7554 start_dpc++;
7555 }
7556
7557 if (!vha->vp_idx &&
7558 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7559 IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7560 ql_log(ql_log_info, vha, 0x3002,
7561 "Sched: Set ZIO exchange threshold to %d.\n",
7562 ha->last_zio_threshold);
7563 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7564 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7565 start_dpc++;
7566 }
7567 qla_adjust_buf(vha);
7568
7569 /* borrowing w to signify dpc will run */
7570 w = 0;
7571 /* Schedule the DPC routine if needed */
7572 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7573 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7574 start_dpc ||
7575 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7576 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7577 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7578 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7579 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7580 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7581 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7582 ql_dbg(ql_dbg_timer, vha, 0x600b,
7583 "isp_abort_needed=%d loop_resync_needed=%d "
7584 "start_dpc=%d reset_marker_needed=%d",
7585 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7586 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7587 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7588 ql_dbg(ql_dbg_timer, vha, 0x600c,
7589 "beacon_blink_needed=%d isp_unrecoverable=%d "
7590 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7591 "relogin_needed=%d, Process_purex_iocb=%d.\n",
7592 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7593 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7594 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7595 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7596 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7597 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7598 qla2xxx_wake_dpc(vha);
7599 w = 1;
7600 }
7601
7602 qla_heart_beat(vha, w);
7603
7604 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7605 }
7606
7607 /* Firmware interface routines. */
7608
7609 #define FW_ISP21XX 0
7610 #define FW_ISP22XX 1
7611 #define FW_ISP2300 2
7612 #define FW_ISP2322 3
7613 #define FW_ISP24XX 4
7614 #define FW_ISP25XX 5
7615 #define FW_ISP81XX 6
7616 #define FW_ISP82XX 7
7617 #define FW_ISP2031 8
7618 #define FW_ISP8031 9
7619 #define FW_ISP27XX 10
7620 #define FW_ISP28XX 11
7621
7622 #define FW_FILE_ISP21XX "ql2100_fw.bin"
7623 #define FW_FILE_ISP22XX "ql2200_fw.bin"
7624 #define FW_FILE_ISP2300 "ql2300_fw.bin"
7625 #define FW_FILE_ISP2322 "ql2322_fw.bin"
7626 #define FW_FILE_ISP24XX "ql2400_fw.bin"
7627 #define FW_FILE_ISP25XX "ql2500_fw.bin"
7628 #define FW_FILE_ISP81XX "ql8100_fw.bin"
7629 #define FW_FILE_ISP82XX "ql8200_fw.bin"
7630 #define FW_FILE_ISP2031 "ql2600_fw.bin"
7631 #define FW_FILE_ISP8031 "ql8300_fw.bin"
7632 #define FW_FILE_ISP27XX "ql2700_fw.bin"
7633 #define FW_FILE_ISP28XX "ql2800_fw.bin"
7634
7635
7636 static DEFINE_MUTEX(qla_fw_lock);
7637
7638 static struct fw_blob qla_fw_blobs[] = {
7639 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7640 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7641 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7642 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7643 { .name = FW_FILE_ISP24XX, },
7644 { .name = FW_FILE_ISP25XX, },
7645 { .name = FW_FILE_ISP81XX, },
7646 { .name = FW_FILE_ISP82XX, },
7647 { .name = FW_FILE_ISP2031, },
7648 { .name = FW_FILE_ISP8031, },
7649 { .name = FW_FILE_ISP27XX, },
7650 { .name = FW_FILE_ISP28XX, },
7651 { .name = NULL, },
7652 };
7653
7654 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)7655 qla2x00_request_firmware(scsi_qla_host_t *vha)
7656 {
7657 struct qla_hw_data *ha = vha->hw;
7658 struct fw_blob *blob;
7659
7660 if (IS_QLA2100(ha)) {
7661 blob = &qla_fw_blobs[FW_ISP21XX];
7662 } else if (IS_QLA2200(ha)) {
7663 blob = &qla_fw_blobs[FW_ISP22XX];
7664 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7665 blob = &qla_fw_blobs[FW_ISP2300];
7666 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7667 blob = &qla_fw_blobs[FW_ISP2322];
7668 } else if (IS_QLA24XX_TYPE(ha)) {
7669 blob = &qla_fw_blobs[FW_ISP24XX];
7670 } else if (IS_QLA25XX(ha)) {
7671 blob = &qla_fw_blobs[FW_ISP25XX];
7672 } else if (IS_QLA81XX(ha)) {
7673 blob = &qla_fw_blobs[FW_ISP81XX];
7674 } else if (IS_QLA82XX(ha)) {
7675 blob = &qla_fw_blobs[FW_ISP82XX];
7676 } else if (IS_QLA2031(ha)) {
7677 blob = &qla_fw_blobs[FW_ISP2031];
7678 } else if (IS_QLA8031(ha)) {
7679 blob = &qla_fw_blobs[FW_ISP8031];
7680 } else if (IS_QLA27XX(ha)) {
7681 blob = &qla_fw_blobs[FW_ISP27XX];
7682 } else if (IS_QLA28XX(ha)) {
7683 blob = &qla_fw_blobs[FW_ISP28XX];
7684 } else {
7685 return NULL;
7686 }
7687
7688 if (!blob->name)
7689 return NULL;
7690
7691 mutex_lock(&qla_fw_lock);
7692 if (blob->fw)
7693 goto out;
7694
7695 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7696 ql_log(ql_log_warn, vha, 0x0063,
7697 "Failed to load firmware image (%s).\n", blob->name);
7698 blob->fw = NULL;
7699 blob = NULL;
7700 }
7701
7702 out:
7703 mutex_unlock(&qla_fw_lock);
7704 return blob;
7705 }
7706
7707 static void
qla2x00_release_firmware(void)7708 qla2x00_release_firmware(void)
7709 {
7710 struct fw_blob *blob;
7711
7712 mutex_lock(&qla_fw_lock);
7713 for (blob = qla_fw_blobs; blob->name; blob++)
7714 release_firmware(blob->fw);
7715 mutex_unlock(&qla_fw_lock);
7716 }
7717
qla_pci_error_cleanup(scsi_qla_host_t * vha)7718 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7719 {
7720 struct qla_hw_data *ha = vha->hw;
7721 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7722 struct qla_qpair *qpair = NULL;
7723 struct scsi_qla_host *vp, *tvp;
7724 fc_port_t *fcport;
7725 int i;
7726 unsigned long flags;
7727
7728 ql_dbg(ql_dbg_aer, vha, 0x9000,
7729 "%s\n", __func__);
7730 ha->chip_reset++;
7731
7732 ha->base_qpair->chip_reset = ha->chip_reset;
7733 for (i = 0; i < ha->max_qpairs; i++) {
7734 if (ha->queue_pair_map[i])
7735 ha->queue_pair_map[i]->chip_reset =
7736 ha->base_qpair->chip_reset;
7737 }
7738
7739 /*
7740 * purge mailbox might take a while. Slot Reset/chip reset
7741 * will take care of the purge
7742 */
7743
7744 mutex_lock(&ha->mq_lock);
7745 ha->base_qpair->online = 0;
7746 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7747 qpair->online = 0;
7748 wmb();
7749 mutex_unlock(&ha->mq_lock);
7750
7751 qla2x00_mark_all_devices_lost(vha);
7752
7753 spin_lock_irqsave(&ha->vport_slock, flags);
7754 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7755 atomic_inc(&vp->vref_count);
7756 spin_unlock_irqrestore(&ha->vport_slock, flags);
7757 qla2x00_mark_all_devices_lost(vp);
7758 spin_lock_irqsave(&ha->vport_slock, flags);
7759 atomic_dec(&vp->vref_count);
7760 }
7761 spin_unlock_irqrestore(&ha->vport_slock, flags);
7762
7763 /* Clear all async request states across all VPs. */
7764 list_for_each_entry(fcport, &vha->vp_fcports, list)
7765 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7766
7767 spin_lock_irqsave(&ha->vport_slock, flags);
7768 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7769 atomic_inc(&vp->vref_count);
7770 spin_unlock_irqrestore(&ha->vport_slock, flags);
7771 list_for_each_entry(fcport, &vp->vp_fcports, list)
7772 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7773 spin_lock_irqsave(&ha->vport_slock, flags);
7774 atomic_dec(&vp->vref_count);
7775 }
7776 spin_unlock_irqrestore(&ha->vport_slock, flags);
7777 }
7778
7779
7780 /**
7781 * qla2xxx_set_affinity_nobalance
7782 * @pdev: pci_dev struct for a qla2xxx device
7783 * @flag: bool
7784 * true: enable "IRQ_NO_BALANCING" bit for msix interrupt
7785 * false: disable "IRQ_NO_BALANCING" bit for msix interrupt
7786 * Description: This function will be called to disable/enable
7787 * "IRQ_NO_BALANCING" to avoid irqbalance daemon
7788 * kicking in during adapter reset.
7789 **/
7790
qla2xxx_set_affinity_nobalance(struct pci_dev * pdev,bool flag)7791 static void qla2xxx_set_affinity_nobalance(struct pci_dev *pdev, bool flag)
7792 {
7793 int irq, i;
7794
7795 for (i = 0; i < QLA_BASE_VECTORS; i++) {
7796 irq = pci_irq_vector(pdev, i);
7797
7798 if (flag)
7799 irq_set_status_flags(irq, IRQ_NO_BALANCING);
7800 else
7801 irq_clear_status_flags(irq, IRQ_NO_BALANCING);
7802 }
7803 }
7804
7805 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7806 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7807 {
7808 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7809 struct qla_hw_data *ha = vha->hw;
7810 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET;
7811
7812 ql_log(ql_log_warn, vha, 0x9000,
7813 "PCI error detected, state %x.\n", state);
7814 ha->pci_error_state = QLA_PCI_ERR_DETECTED;
7815
7816 if (!atomic_read(&pdev->enable_cnt)) {
7817 ql_log(ql_log_info, vha, 0xffff,
7818 "PCI device is disabled,state %x\n", state);
7819 ret = PCI_ERS_RESULT_NEED_RESET;
7820 goto out;
7821 }
7822
7823 qla2xxx_set_affinity_nobalance(pdev, false);
7824
7825 switch (state) {
7826 case pci_channel_io_normal:
7827 qla_pci_set_eeh_busy(vha);
7828 if (ql2xmqsupport || ql2xnvmeenable) {
7829 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7830 qla2xxx_wake_dpc(vha);
7831 }
7832 ret = PCI_ERS_RESULT_CAN_RECOVER;
7833 break;
7834 case pci_channel_io_frozen:
7835 qla_pci_set_eeh_busy(vha);
7836 ret = PCI_ERS_RESULT_NEED_RESET;
7837 break;
7838 case pci_channel_io_perm_failure:
7839 ha->flags.pci_channel_io_perm_failure = 1;
7840 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7841 if (ql2xmqsupport || ql2xnvmeenable) {
7842 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7843 qla2xxx_wake_dpc(vha);
7844 }
7845 ret = PCI_ERS_RESULT_DISCONNECT;
7846 }
7847 out:
7848 ql_dbg(ql_dbg_aer, vha, 0x600d,
7849 "PCI error detected returning [%x].\n", ret);
7850 return ret;
7851 }
7852
7853 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)7854 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7855 {
7856 int risc_paused = 0;
7857 uint32_t stat;
7858 unsigned long flags;
7859 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7860 struct qla_hw_data *ha = base_vha->hw;
7861 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7862 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7863
7864 ql_log(ql_log_warn, base_vha, 0x9000,
7865 "mmio enabled\n");
7866
7867 ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
7868
7869 if (IS_QLA82XX(ha))
7870 return PCI_ERS_RESULT_RECOVERED;
7871
7872 if (qla2x00_isp_reg_stat(ha)) {
7873 ql_log(ql_log_info, base_vha, 0x803f,
7874 "During mmio enabled, PCI/Register disconnect still detected.\n");
7875 goto out;
7876 }
7877
7878 spin_lock_irqsave(&ha->hardware_lock, flags);
7879 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7880 stat = rd_reg_word(®->hccr);
7881 if (stat & HCCR_RISC_PAUSE)
7882 risc_paused = 1;
7883 } else if (IS_QLA23XX(ha)) {
7884 stat = rd_reg_dword(®->u.isp2300.host_status);
7885 if (stat & HSR_RISC_PAUSED)
7886 risc_paused = 1;
7887 } else if (IS_FWI2_CAPABLE(ha)) {
7888 stat = rd_reg_dword(®24->host_status);
7889 if (stat & HSRX_RISC_PAUSED)
7890 risc_paused = 1;
7891 }
7892 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7893
7894 if (risc_paused) {
7895 ql_log(ql_log_info, base_vha, 0x9003,
7896 "RISC paused -- mmio_enabled, Dumping firmware.\n");
7897 qla2xxx_dump_fw(base_vha);
7898 }
7899 out:
7900 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */
7901 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7902 "mmio enabled returning.\n");
7903 return PCI_ERS_RESULT_NEED_RESET;
7904 }
7905
7906 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)7907 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7908 {
7909 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7910 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7911 struct qla_hw_data *ha = base_vha->hw;
7912 int rc;
7913 struct qla_qpair *qpair = NULL;
7914
7915 ql_log(ql_log_warn, base_vha, 0x9004,
7916 "Slot Reset.\n");
7917
7918 ha->pci_error_state = QLA_PCI_SLOT_RESET;
7919
7920 pci_restore_state(pdev);
7921
7922 if (ha->mem_only)
7923 rc = pci_enable_device_mem(pdev);
7924 else
7925 rc = pci_enable_device(pdev);
7926
7927 if (rc) {
7928 ql_log(ql_log_warn, base_vha, 0x9005,
7929 "Can't re-enable PCI device after reset.\n");
7930 goto exit_slot_reset;
7931 }
7932
7933
7934 if (ha->isp_ops->pci_config(base_vha))
7935 goto exit_slot_reset;
7936
7937 mutex_lock(&ha->mq_lock);
7938 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7939 qpair->online = 1;
7940 mutex_unlock(&ha->mq_lock);
7941
7942 ha->flags.eeh_busy = 0;
7943 base_vha->flags.online = 1;
7944 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7945 ha->isp_ops->abort_isp(base_vha);
7946 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7947
7948 if (qla2x00_isp_reg_stat(ha)) {
7949 ha->flags.eeh_busy = 1;
7950 qla_pci_error_cleanup(base_vha);
7951 ql_log(ql_log_warn, base_vha, 0x9005,
7952 "Device unable to recover from PCI error.\n");
7953 } else {
7954 ret = PCI_ERS_RESULT_RECOVERED;
7955 }
7956
7957 exit_slot_reset:
7958 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7959 "Slot Reset returning %x.\n", ret);
7960
7961 qla2xxx_set_affinity_nobalance(pdev, true);
7962
7963 return ret;
7964 }
7965
7966 static void
qla2xxx_pci_resume(struct pci_dev * pdev)7967 qla2xxx_pci_resume(struct pci_dev *pdev)
7968 {
7969 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7970 struct qla_hw_data *ha = base_vha->hw;
7971 int ret;
7972
7973 ql_log(ql_log_warn, base_vha, 0x900f,
7974 "Pci Resume.\n");
7975
7976
7977 ret = qla2x00_wait_for_hba_online(base_vha);
7978 if (ret != QLA_SUCCESS) {
7979 ql_log(ql_log_fatal, base_vha, 0x9002,
7980 "The device failed to resume I/O from slot/link_reset.\n");
7981 }
7982 ha->pci_error_state = QLA_PCI_RESUME;
7983 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7984 "Pci Resume returning.\n");
7985 }
7986
qla_pci_set_eeh_busy(struct scsi_qla_host * vha)7987 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha)
7988 {
7989 struct qla_hw_data *ha = vha->hw;
7990 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7991 bool do_cleanup = false;
7992 unsigned long flags;
7993
7994 if (ha->flags.eeh_busy)
7995 return;
7996
7997 spin_lock_irqsave(&base_vha->work_lock, flags);
7998 if (!ha->flags.eeh_busy) {
7999 ha->eeh_jif = jiffies;
8000 ha->flags.eeh_flush = 0;
8001
8002 ha->flags.eeh_busy = 1;
8003 do_cleanup = true;
8004 }
8005 spin_unlock_irqrestore(&base_vha->work_lock, flags);
8006
8007 if (do_cleanup)
8008 qla_pci_error_cleanup(base_vha);
8009 }
8010
8011 /*
8012 * this routine will schedule a task to pause IO from interrupt context
8013 * if caller sees a PCIE error event (register read = 0xf's)
8014 */
qla_schedule_eeh_work(struct scsi_qla_host * vha)8015 void qla_schedule_eeh_work(struct scsi_qla_host *vha)
8016 {
8017 struct qla_hw_data *ha = vha->hw;
8018 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
8019
8020 if (ha->flags.eeh_busy)
8021 return;
8022
8023 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
8024 qla2xxx_wake_dpc(base_vha);
8025 }
8026
8027 static void
qla_pci_reset_prepare(struct pci_dev * pdev)8028 qla_pci_reset_prepare(struct pci_dev *pdev)
8029 {
8030 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8031 struct qla_hw_data *ha = base_vha->hw;
8032 struct qla_qpair *qpair;
8033
8034 ql_log(ql_log_warn, base_vha, 0xffff,
8035 "%s.\n", __func__);
8036
8037 /*
8038 * PCI FLR/function reset is about to reset the
8039 * slot. Stop the chip to stop all DMA access.
8040 * It is assumed that pci_reset_done will be called
8041 * after FLR to resume Chip operation.
8042 */
8043 ha->flags.eeh_busy = 1;
8044 mutex_lock(&ha->mq_lock);
8045 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8046 qpair->online = 0;
8047 mutex_unlock(&ha->mq_lock);
8048
8049 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8050 qla2x00_abort_isp_cleanup(base_vha);
8051 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
8052 }
8053
8054 static void
qla_pci_reset_done(struct pci_dev * pdev)8055 qla_pci_reset_done(struct pci_dev *pdev)
8056 {
8057 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8058 struct qla_hw_data *ha = base_vha->hw;
8059 struct qla_qpair *qpair;
8060
8061 ql_log(ql_log_warn, base_vha, 0xffff,
8062 "%s.\n", __func__);
8063
8064 /*
8065 * FLR just completed by PCI layer. Resume adapter
8066 */
8067 ha->flags.eeh_busy = 0;
8068 mutex_lock(&ha->mq_lock);
8069 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8070 qpair->online = 1;
8071 mutex_unlock(&ha->mq_lock);
8072
8073 base_vha->flags.online = 1;
8074 ha->isp_ops->abort_isp(base_vha);
8075 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8076 }
8077
qla2xxx_map_queues(struct Scsi_Host * shost)8078 static void qla2xxx_map_queues(struct Scsi_Host *shost)
8079 {
8080 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
8081 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
8082
8083 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
8084 blk_mq_map_queues(qmap);
8085 else
8086 blk_mq_map_hw_queues(qmap, &vha->hw->pdev->dev,
8087 vha->irq_offset);
8088 }
8089
8090 struct scsi_host_template qla2xxx_driver_template = {
8091 .module = THIS_MODULE,
8092 .name = QLA2XXX_DRIVER_NAME,
8093 .queuecommand = qla2xxx_queuecommand,
8094
8095 .eh_timed_out = fc_eh_timed_out,
8096 .eh_abort_handler = qla2xxx_eh_abort,
8097 .eh_should_retry_cmd = fc_eh_should_retry_cmd,
8098 .eh_device_reset_handler = qla2xxx_eh_device_reset,
8099 .eh_target_reset_handler = qla2xxx_eh_target_reset,
8100 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
8101 .eh_host_reset_handler = qla2xxx_eh_host_reset,
8102
8103 .sdev_configure = qla2xxx_sdev_configure,
8104
8105 .sdev_init = qla2xxx_sdev_init,
8106 .sdev_destroy = qla2xxx_sdev_destroy,
8107 .scan_finished = qla2xxx_scan_finished,
8108 .scan_start = qla2xxx_scan_start,
8109 .change_queue_depth = scsi_change_queue_depth,
8110 .map_queues = qla2xxx_map_queues,
8111 .this_id = -1,
8112 .cmd_per_lun = 3,
8113 .sg_tablesize = SG_ALL,
8114
8115 .max_sectors = 0xFFFF,
8116 .shost_groups = qla2x00_host_groups,
8117
8118 .supported_mode = MODE_INITIATOR,
8119 .track_queue_depth = 1,
8120 .cmd_size = sizeof(srb_t),
8121 };
8122
8123 static const struct pci_error_handlers qla2xxx_err_handler = {
8124 .error_detected = qla2xxx_pci_error_detected,
8125 .mmio_enabled = qla2xxx_pci_mmio_enabled,
8126 .slot_reset = qla2xxx_pci_slot_reset,
8127 .resume = qla2xxx_pci_resume,
8128 .reset_prepare = qla_pci_reset_prepare,
8129 .reset_done = qla_pci_reset_done,
8130 };
8131
8132 static const struct pci_device_id qla2xxx_pci_tbl[] = {
8133 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
8134 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
8135 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
8136 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
8137 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
8138 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
8139 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
8140 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
8141 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
8142 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
8143 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
8144 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
8145 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
8146 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
8147 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
8148 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
8149 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8150 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
8151 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
8152 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
8153 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
8154 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
8155 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
8156 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
8157 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
8158 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
8159 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
8160 { 0 },
8161 };
8162 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
8163
8164 static struct pci_driver qla2xxx_pci_driver = {
8165 .name = QLA2XXX_DRIVER_NAME,
8166 .id_table = qla2xxx_pci_tbl,
8167 .probe = qla2x00_probe_one,
8168 .remove = qla2x00_remove_one,
8169 .shutdown = qla2x00_shutdown,
8170 .err_handler = &qla2xxx_err_handler,
8171 };
8172
8173 static const struct file_operations apidev_fops = {
8174 .owner = THIS_MODULE,
8175 .llseek = noop_llseek,
8176 };
8177
8178 /**
8179 * qla2x00_module_init - Module initialization.
8180 **/
8181 static int __init
qla2x00_module_init(void)8182 qla2x00_module_init(void)
8183 {
8184 int ret = 0;
8185
8186 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
8187 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
8188 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
8189 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
8190 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8191 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
8192 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
8193 BUILD_BUG_ON(sizeof(request_t) != 64);
8194 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
8195 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
8196 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
8197 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8198 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
8199 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
8200 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
8201 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
8202 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
8203 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
8204 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
8205 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
8206 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604);
8207 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
8208 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
8209 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
8210 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
8211 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
8212 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8213 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
8214 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
8215 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
8216 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
8217 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
8218 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
8219 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
8220 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
8221 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
8222 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
8223 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
8224 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
8225 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
8226 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
8227 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
8228 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
8229 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
8230 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
8231 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
8232 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
8233 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
8234 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
8235 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
8236 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
8237 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
8238 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
8239 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
8240 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
8241 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
8242 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
8243 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
8244 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
8245 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
8246 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
8247 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
8248 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
8249 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
8250 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
8251 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
8252 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
8253 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
8254 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
8255 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
8256 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
8257 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
8258 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8259 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
8260 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
8261 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
8262 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
8263 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
8264 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
8265 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
8266 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
8267 BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
8268 BUILD_BUG_ON(sizeof(sw_info_t) != 32);
8269 BUILD_BUG_ON(sizeof(target_id_t) != 2);
8270
8271 qla_trace_init();
8272
8273 /* Allocate cache for SRBs. */
8274 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
8275 SLAB_HWCACHE_ALIGN, NULL);
8276 if (srb_cachep == NULL) {
8277 ql_log(ql_log_fatal, NULL, 0x0001,
8278 "Unable to allocate SRB cache...Failing load!.\n");
8279 return -ENOMEM;
8280 }
8281
8282 /* Initialize target kmem_cache and mem_pools */
8283 ret = qlt_init();
8284 if (ret < 0) {
8285 goto destroy_cache;
8286 } else if (ret > 0) {
8287 /*
8288 * If initiator mode is explictly disabled by qlt_init(),
8289 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
8290 * performing scsi_scan_target() during LOOP UP event.
8291 */
8292 qla2xxx_transport_functions.disable_target_scan = 1;
8293 qla2xxx_transport_vport_functions.disable_target_scan = 1;
8294 }
8295
8296 /* Derive version string. */
8297 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
8298 if (ql2xextended_error_logging)
8299 strcat(qla2x00_version_str, "-debug");
8300 if (ql2xextended_error_logging == 1)
8301 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
8302
8303 qla2xxx_transport_template =
8304 fc_attach_transport(&qla2xxx_transport_functions);
8305 if (!qla2xxx_transport_template) {
8306 ql_log(ql_log_fatal, NULL, 0x0002,
8307 "fc_attach_transport failed...Failing load!.\n");
8308 ret = -ENODEV;
8309 goto qlt_exit;
8310 }
8311
8312 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
8313 if (apidev_major < 0) {
8314 ql_log(ql_log_fatal, NULL, 0x0003,
8315 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
8316 }
8317
8318 qla2xxx_transport_vport_template =
8319 fc_attach_transport(&qla2xxx_transport_vport_functions);
8320 if (!qla2xxx_transport_vport_template) {
8321 ql_log(ql_log_fatal, NULL, 0x0004,
8322 "fc_attach_transport vport failed...Failing load!.\n");
8323 ret = -ENODEV;
8324 goto unreg_chrdev;
8325 }
8326 ql_log(ql_log_info, NULL, 0x0005,
8327 "QLogic Fibre Channel HBA Driver: %s.\n",
8328 qla2x00_version_str);
8329 ret = pci_register_driver(&qla2xxx_pci_driver);
8330 if (ret) {
8331 ql_log(ql_log_fatal, NULL, 0x0006,
8332 "pci_register_driver failed...ret=%d Failing load!.\n",
8333 ret);
8334 goto release_vport_transport;
8335 }
8336 return ret;
8337
8338 release_vport_transport:
8339 fc_release_transport(qla2xxx_transport_vport_template);
8340
8341 unreg_chrdev:
8342 if (apidev_major >= 0)
8343 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8344 fc_release_transport(qla2xxx_transport_template);
8345
8346 qlt_exit:
8347 qlt_exit();
8348
8349 destroy_cache:
8350 kmem_cache_destroy(srb_cachep);
8351
8352 qla_trace_uninit();
8353 return ret;
8354 }
8355
8356 /**
8357 * qla2x00_module_exit - Module cleanup.
8358 **/
8359 static void __exit
qla2x00_module_exit(void)8360 qla2x00_module_exit(void)
8361 {
8362 pci_unregister_driver(&qla2xxx_pci_driver);
8363 qla2x00_release_firmware();
8364 kmem_cache_destroy(ctx_cachep);
8365 fc_release_transport(qla2xxx_transport_vport_template);
8366 if (apidev_major >= 0)
8367 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8368 fc_release_transport(qla2xxx_transport_template);
8369 qlt_exit();
8370 kmem_cache_destroy(srb_cachep);
8371 qla_trace_uninit();
8372 }
8373
8374 module_init(qla2x00_module_init);
8375 module_exit(qla2x00_module_exit);
8376
8377 MODULE_AUTHOR("QLogic Corporation");
8378 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
8379 MODULE_LICENSE("GPL");
8380 MODULE_FIRMWARE(FW_FILE_ISP21XX);
8381 MODULE_FIRMWARE(FW_FILE_ISP22XX);
8382 MODULE_FIRMWARE(FW_FILE_ISP2300);
8383 MODULE_FIRMWARE(FW_FILE_ISP2322);
8384 MODULE_FIRMWARE(FW_FILE_ISP24XX);
8385 MODULE_FIRMWARE(FW_FILE_ISP25XX);
8386