1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
21
22 #include <ufs/unipro.h>
23
24 #include "phy-qcom-qmp-common.h"
25
26 #include "phy-qcom-qmp.h"
27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
32
33 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
34 #include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
35
36 /* QPHY_PCS_READY_STATUS bit */
37 #define PCS_READY BIT(0)
38
39 #define PHY_INIT_COMPLETE_TIMEOUT 10000
40
41 #define NUM_OVERLAY 2
42
43 /* set of registers with offsets different per-PHY */
44 enum qphy_reg_layout {
45 /* PCS registers */
46 QPHY_SW_RESET,
47 QPHY_START_CTRL,
48 QPHY_PCS_READY_STATUS,
49 QPHY_PCS_POWER_DOWN_CONTROL,
50 /* Keep last to ensure regs_layout arrays are properly initialized */
51 QPHY_LAYOUT_SIZE
52 };
53
54 static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
55 [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
56 [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
57 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
58 };
59
60 static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
61 [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START,
62 [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS,
63 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
64 };
65
66 static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
67 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
68 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
69 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
70 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
71 };
72
73 static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
74 [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START,
75 [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS,
76 [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET,
77 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
78 };
79
80 static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
81 [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START,
82 [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS,
83 [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET,
84 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
85 };
86
87 static const struct qmp_phy_init_tbl milos_ufsphy_serdes[] = {
88 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
89 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
90 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
91 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
92 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
93 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
94 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a),
95 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17),
96 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
97 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
98 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
99 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
100 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14),
101 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
102 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18),
103 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),
104 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c),
105 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98),
106 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14),
107 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
108 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18),
109 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32),
110 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f),
111 };
112
113 static const struct qmp_phy_init_tbl milos_ufsphy_tx[] = {
114 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
115 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
116 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
117 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0xcc),
118 };
119
120 static const struct qmp_phy_init_tbl milos_ufsphy_rx[] = {
121 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
122 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e),
123 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
124 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce),
125 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce),
126 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18),
127 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
128 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f),
129 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
130 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
131 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
132 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
133 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
134 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
135 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
136 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),
137 };
138
139 static const struct qmp_phy_init_tbl milos_ufsphy_pcs[] = {
140 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
141 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
142 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b),
143 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
144 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
145 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
146 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
147 };
148
149 static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
150 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
151 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
152 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
153 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
154 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
155 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
156 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
157 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
158 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
159 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
160 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
161 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
162 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
163 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
164 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
165 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
166 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
167 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
168 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
169 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
170 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
171 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
172 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
173 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
174 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
175 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
176 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
177 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
178 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
179 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
180 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
181 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
182 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
183 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
184 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
185 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
186 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
187 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
188 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
189 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
190 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
191 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
192 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
193 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
194 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
195 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
196 };
197
198 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = {
199 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
200 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
201 };
202
203 static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {
204 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
205 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
206 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
207 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
208 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
209 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
210 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
211 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
212 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
213 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
214 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
215 };
216
217 static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = {
218 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
219 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
220 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
221 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
222 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
223 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
224 };
225
226 static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = {
227 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
228 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
229 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
230 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
231 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
232 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
233 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
234 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
235 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
236 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
237 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
238 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
239 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
240 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
241 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
242 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
243 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
244 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
245 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
246 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d),
247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d),
248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed),
249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c),
251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
262 };
263
264 static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = {
265 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
266 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
267 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
268 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
269 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
270 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
271 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
272 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03),
273 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
274 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
275 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
276 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
277 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
278 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
279 };
280
281 static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = {
282 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
283 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
284 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
285 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
286 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
287 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
288 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
289 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
290 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
291 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
292 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
293 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
294 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
295 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
296 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
297 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
298 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
299 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
300 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
301 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
302 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
303 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
304 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
305 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
306 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
307 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
308 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
309 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
310 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
311 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
312 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
313 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
314 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
315 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
316 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
317 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
318 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
319 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f),
320 };
321
322 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
323 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
324 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
325 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
326 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
327 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
328 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
329 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
330 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
331 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
332 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
333 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
334 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
335 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
336 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
337 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
338 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
339 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
340 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
341 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
342 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
343 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
344 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
345 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
346 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
347 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
348 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
349 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
350 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
351 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
352 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
353 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
354 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
355 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
356 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
357 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
358 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
359 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
360 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
361 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
362 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
363 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
364 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
365 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
366 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
367 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
368 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
369 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
370 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
371 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
372 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
373 };
374
375 static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
376 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
377 };
378
379 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {
380 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
381 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
382 };
383
384 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {
385 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
386 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
387 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
388 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
389 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
390 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
391 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
392 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
393 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
394 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
395 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
396 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
397 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
398 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
399 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
400 };
401
402 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {
403 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15),
404 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
405 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
406 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
407 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
408 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
409 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
410 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
411 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
412 };
413
414 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
438 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
439 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
440 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
443 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
444 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
445 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
446 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
447 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
448 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
449 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
450 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
451 };
452
453 static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
454 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
455 };
456
457 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {
458 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
459 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
460 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
461 };
462
463 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {
464 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
465 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
466 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
467 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
468 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
469 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
470 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
471 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
472 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
473 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
474 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
475 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
476 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
477 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
478 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
479 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
480 };
481
482 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a),
490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
491 };
492
493 static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = {
494 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
495 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
496 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
497 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
498 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
499 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
500 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
501 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
502 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
503 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
504 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
505 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
506 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),
507 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
508 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
509 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
510 };
511
512 static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = {
513 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),
514 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
515 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
516 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
517 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
518 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
519 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
520 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
521 };
522
523 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
524 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
525 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
526 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
527 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
528 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
529 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
530 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
531 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
532 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
533 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
534 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
535 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
536 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
537 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
538 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
539 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
540 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
541 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
542 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
543 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
544 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
545 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
546 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
547 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
548 };
549
550 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
551 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
552 };
553
554 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
555 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
556 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
557 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
558 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
559 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
560 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
561 };
562
563 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
564 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
565 };
566
567 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
568 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
569 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
570 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
571 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
572 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
573 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
574 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
575 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
576 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
579 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
580 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
602 };
603
604 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
615 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
616 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
617 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
618 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
621 };
622
623 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
624 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
625 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
626 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
627 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
628 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
629 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
630 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
631 };
632
633 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
634 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
635 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
636 };
637
638 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
639 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
640 };
641
642 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
664 };
665
666 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
667 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
668 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
669 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
670 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
671 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
672 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
673 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
674 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
675 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
676 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
677 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
678 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
679 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
680 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
681 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
682 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
683 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
684 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
685 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
686 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
687 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
688 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
689 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
690 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
691 };
692
693 static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
694 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
695 };
696
697 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {
698 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
699 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
700 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
701 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
702 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
703 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
704 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
705 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
706 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
707 };
708
709 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {
710 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
711 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
712 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
713 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
714 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
715 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
716 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
717 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
718 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
719 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
720 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
721 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
722 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
723 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
724 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
725 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
726 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
727 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
728 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
729 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
730 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
731 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
732 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
733 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
734 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
735 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
736 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
737 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
738 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
739 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
740 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
741 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
742 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
743 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
744 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
745 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
746 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
747 };
748
749 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
750 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
751 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
752 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
753 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
754 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
755 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
756 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
757 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
758 };
759
760 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = {
761 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),
762 };
763
764 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = {
765 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),
766 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),
767 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
768 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
769 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
770 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),
771 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),
772 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
773 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),
774 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),
775 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
776 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),
777 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),
778 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),
779 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),
780 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),
781 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),
782 };
783
784 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {
785 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
786 };
787
788 static const struct qmp_phy_init_tbl sm8475_ufsphy_serdes[] = {
789 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
790 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
791 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
792 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
793 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
794 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
795 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
796 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
797 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18),
798 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),
799 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c),
800 };
801
802 static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_serdes[] = {
803 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
804 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
805 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14),
806 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98),
807 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14),
808 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
809 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18),
810 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32),
811 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f),
812 };
813
814 static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_pcs[] = {
815 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b),
816 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
817 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
818 };
819
820 static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
822 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
823 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
824 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
825 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
826 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
827 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
828 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
829 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
830 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
831 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
832 };
833
834 static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
835 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
836 };
837
838 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
839 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
840 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
841 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
842 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
843 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
844 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
845 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
846 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
847 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
848 };
849
850 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
851 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
852 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
853 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
854 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
855 };
856
857 static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
858 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
859 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
860 };
861
862 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
863 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
864 };
865
866 static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
867 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
868
869 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
870 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
871 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
872 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
873
874 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
875 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
876
877 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
878 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
879 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
880 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
881 };
882
883 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
884 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
885 };
886
887 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
888 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
889 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
890 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
891 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
892 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
893 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
894 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
895 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
896 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
897 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
898 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
899 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
900 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
901 };
902
903 static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
904 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
905 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
906 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
907 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
908 };
909
910 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
911 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
912 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
913 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
914 };
915
916 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
917 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
918 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
919 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
920 };
921
922 static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = {
923 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
924 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
925 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
926 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
927 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
928 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
929 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f),
930 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a),
931 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17),
932 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
933 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
934 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
935 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
936 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
937 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
938 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
939 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
940 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
941 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
942 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
943 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
944 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
945 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
946 };
947
948 static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = {
949 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x01),
950 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
951 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
952 };
953
954 static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = {
955 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
956 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
957 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
958 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
959 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
960 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
961 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
962 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
963 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
964 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e),
965 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
966 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce),
967 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce),
968 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18),
969 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
970 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f),
971 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
972 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
973 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
974 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
975 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
976 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
977 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
978 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B0, 0x24),
979 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B1, 0x24),
980 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B2, 0x20),
981 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
982 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
983 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f),
984 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),
985 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa),
986 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
987 };
988
989 static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = {
990 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
991 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
992 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1),
993 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
994 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
995 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
996 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e),
997 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
998 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
999 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
1000 };
1001
1002 static const struct qmp_phy_init_tbl sm8650_ufsphy_g4_pcs[] = {
1003 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
1004 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
1005 };
1006
1007 static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
1008 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
1009 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
1010 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),
1011 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
1012 };
1013
1014 static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {
1015 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
1016 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
1017 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
1018 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1019 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
1020 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60),
1021 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
1022 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f),
1023 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07),
1024 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20),
1025 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
1026 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40),
1027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
1028 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1029 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1030 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
1031 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
1032 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
1033 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
1034 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
1035 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
1036 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
1037 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
1038 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1039 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
1040 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1041 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
1042 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
1043 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
1044 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
1045 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
1046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
1047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
1048 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe),
1049 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1050 };
1051
1052 static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {
1053 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00),
1054 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
1055 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
1056 };
1057
1058 static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {
1059 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1060 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0c),
1061 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
1062 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
1063 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
1064 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
1065 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
1066 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
1067 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
1068 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8e),
1069 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1070 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xce),
1071 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xce),
1072 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
1073 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1a),
1074 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0f),
1075 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
1076 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
1077 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9a),
1078 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xe2),
1079 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
1080 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1b),
1081 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1b),
1082 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
1083 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9b),
1084 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2a),
1085 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
1086 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
1087 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
1088 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
1089 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
1090 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
1091 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
1092 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5f),
1093 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
1094 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xe3),
1095 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
1096 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9b),
1097 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9b),
1098 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60),
1099 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
1100 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5f),
1101 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
1102 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xfb),
1103 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
1104 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1f),
1105 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
1106 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xfa),
1107 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
1108 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
1109 };
1110
1111 static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {
1112 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1113 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1114 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),
1115 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
1116 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
1117 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
1118 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e),
1119 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
1120 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
1121 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
1122 };
1123
1124 static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {
1125 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
1126 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
1127 };
1128
1129 static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {
1130 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41),
1131 };
1132
1133 struct qmp_ufs_offsets {
1134 u16 serdes;
1135 u16 pcs;
1136 u16 tx;
1137 u16 rx;
1138 u16 tx2;
1139 u16 rx2;
1140 };
1141
1142 struct qmp_phy_cfg_tbls {
1143 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1144 const struct qmp_phy_init_tbl *serdes;
1145 int serdes_num;
1146 const struct qmp_phy_init_tbl *tx;
1147 int tx_num;
1148 const struct qmp_phy_init_tbl *rx;
1149 int rx_num;
1150 const struct qmp_phy_init_tbl *pcs;
1151 int pcs_num;
1152 /* Maximum supported Gear of this tbls */
1153 u32 max_gear;
1154 };
1155
1156 /* struct qmp_phy_cfg - per-PHY initialization config */
1157 struct qmp_phy_cfg {
1158 int lanes;
1159
1160 const struct qmp_ufs_offsets *offsets;
1161 /* Maximum supported Gear of this config */
1162 u32 max_supported_gear;
1163
1164 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
1165 const struct qmp_phy_cfg_tbls tbls;
1166 /* Additional sequence for HS Series B */
1167 const struct qmp_phy_cfg_tbls tbls_hs_b;
1168 /* Additional sequence for different HS Gears */
1169 const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];
1170
1171 /* regulators to be requested */
1172 const struct regulator_bulk_data *vreg_list;
1173 int num_vregs;
1174
1175 /* array of registers with different offsets */
1176 const unsigned int *regs;
1177
1178 /* true, if PCS block has no separate SW_RESET register */
1179 bool no_pcs_sw_reset;
1180 };
1181
1182 struct qmp_ufs {
1183 struct device *dev;
1184
1185 const struct qmp_phy_cfg *cfg;
1186
1187 void __iomem *serdes;
1188 void __iomem *pcs;
1189 void __iomem *pcs_misc;
1190 void __iomem *tx;
1191 void __iomem *rx;
1192 void __iomem *tx2;
1193 void __iomem *rx2;
1194
1195 struct clk_bulk_data *clks;
1196 int num_clks;
1197 struct regulator_bulk_data *vregs;
1198 struct reset_control *ufs_reset;
1199
1200 struct phy *phy;
1201 u32 mode;
1202 u32 submode;
1203 };
1204
qphy_setbits(void __iomem * base,u32 offset,u32 val)1205 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1206 {
1207 u32 reg;
1208
1209 reg = readl(base + offset);
1210 reg |= val;
1211 writel(reg, base + offset);
1212
1213 /* ensure that above write is through */
1214 readl(base + offset);
1215 }
1216
qphy_clrbits(void __iomem * base,u32 offset,u32 val)1217 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1218 {
1219 u32 reg;
1220
1221 reg = readl(base + offset);
1222 reg &= ~val;
1223 writel(reg, base + offset);
1224
1225 /* ensure that above write is through */
1226 readl(base + offset);
1227 }
1228
1229 /* Regulator bulk data with load values for specific configurations */
1230 static const struct regulator_bulk_data milos_ufsphy_vreg_l[] = {
1231 { .supply = "vdda-phy", .init_load_uA = 140120 },
1232 { .supply = "vdda-pll", .init_load_uA = 18340 },
1233 };
1234
1235 static const struct regulator_bulk_data msm8996_ufsphy_vreg_l[] = {
1236 { .supply = "vdda-phy", .init_load_uA = 51400 },
1237 { .supply = "vdda-pll", .init_load_uA = 14600 },
1238 };
1239
1240 static const struct regulator_bulk_data sa8775p_ufsphy_vreg_l[] = {
1241 { .supply = "vdda-phy", .init_load_uA = 137000 },
1242 { .supply = "vdda-pll", .init_load_uA = 18300 },
1243 };
1244
1245 static const struct regulator_bulk_data sc7280_ufsphy_vreg_l[] = {
1246 { .supply = "vdda-phy", .init_load_uA = 97500 },
1247 { .supply = "vdda-pll", .init_load_uA = 18400 },
1248 };
1249
1250 static const struct regulator_bulk_data sc8280xp_ufsphy_vreg_l[] = {
1251 { .supply = "vdda-phy", .init_load_uA = 85700 },
1252 { .supply = "vdda-pll", .init_load_uA = 18300 },
1253 };
1254
1255 static const struct regulator_bulk_data sdm845_ufsphy_vreg_l[] = {
1256 { .supply = "vdda-phy", .init_load_uA = 51400 },
1257 { .supply = "vdda-pll", .init_load_uA = 14600 },
1258 };
1259
1260 static const struct regulator_bulk_data sm6115_ufsphy_vreg_l[] = {
1261 { .supply = "vdda-phy", .init_load_uA = 51400 },
1262 { .supply = "vdda-pll", .init_load_uA = 14200 },
1263 };
1264
1265 static const struct regulator_bulk_data sm7150_ufsphy_vreg_l[] = {
1266 { .supply = "vdda-phy", .init_load_uA = 62900 },
1267 { .supply = "vdda-pll", .init_load_uA = 18300 },
1268 };
1269
1270 static const struct regulator_bulk_data sm8150_ufsphy_vreg_l[] = {
1271 { .supply = "vdda-phy", .init_load_uA = 90200 },
1272 { .supply = "vdda-pll", .init_load_uA = 19000 },
1273 };
1274
1275 static const struct regulator_bulk_data sm8250_ufsphy_vreg_l[] = {
1276 { .supply = "vdda-phy", .init_load_uA = 89900 },
1277 { .supply = "vdda-pll", .init_load_uA = 18800 },
1278 };
1279
1280 static const struct regulator_bulk_data sm8350_ufsphy_vreg_l[] = {
1281 { .supply = "vdda-phy", .init_load_uA = 91600 },
1282 { .supply = "vdda-pll", .init_load_uA = 19000 },
1283 };
1284
1285 static const struct regulator_bulk_data sm8450_ufsphy_vreg_l[] = {
1286 { .supply = "vdda-phy", .init_load_uA = 173000 },
1287 { .supply = "vdda-pll", .init_load_uA = 24900 },
1288 };
1289
1290 static const struct regulator_bulk_data sm8475_ufsphy_vreg_l[] = {
1291 { .supply = "vdda-phy", .init_load_uA = 213030 },
1292 { .supply = "vdda-pll", .init_load_uA = 18340 },
1293 };
1294
1295 static const struct regulator_bulk_data sm8550_ufsphy_vreg_l[] = {
1296 { .supply = "vdda-phy", .init_load_uA = 188000 },
1297 { .supply = "vdda-pll", .init_load_uA = 18300 },
1298 };
1299
1300 static const struct regulator_bulk_data sm8650_ufsphy_vreg_l[] = {
1301 { .supply = "vdda-phy", .init_load_uA = 205000 },
1302 { .supply = "vdda-pll", .init_load_uA = 17500 },
1303 };
1304
1305 static const struct regulator_bulk_data sm8750_ufsphy_vreg_l[] = {
1306 { .supply = "vdda-phy", .init_load_uA = 213000 },
1307 { .supply = "vdda-pll", .init_load_uA = 18300 },
1308 };
1309
1310 static const struct qmp_ufs_offsets qmp_ufs_offsets = {
1311 .serdes = 0,
1312 .pcs = 0xc00,
1313 .tx = 0x400,
1314 .rx = 0x600,
1315 .tx2 = 0x800,
1316 .rx2 = 0xa00,
1317 };
1318
1319 static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
1320 .serdes = 0,
1321 .pcs = 0x0400,
1322 .tx = 0x1000,
1323 .rx = 0x1200,
1324 .tx2 = 0x1800,
1325 .rx2 = 0x1a00,
1326 };
1327
1328 static const struct qmp_phy_cfg milos_ufsphy_cfg = {
1329 .lanes = 2,
1330
1331 .offsets = &qmp_ufs_offsets_v6,
1332 .max_supported_gear = UFS_HS_G4,
1333
1334 .tbls = {
1335 .serdes = milos_ufsphy_serdes,
1336 .serdes_num = ARRAY_SIZE(milos_ufsphy_serdes),
1337 .tx = milos_ufsphy_tx,
1338 .tx_num = ARRAY_SIZE(milos_ufsphy_tx),
1339 .rx = milos_ufsphy_rx,
1340 .rx_num = ARRAY_SIZE(milos_ufsphy_rx),
1341 .pcs = milos_ufsphy_pcs,
1342 .pcs_num = ARRAY_SIZE(milos_ufsphy_pcs),
1343 },
1344 .tbls_hs_b = {
1345 .serdes = sm8550_ufsphy_hs_b_serdes,
1346 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
1347 },
1348
1349 .vreg_list = milos_ufsphy_vreg_l,
1350 .num_vregs = ARRAY_SIZE(milos_ufsphy_vreg_l),
1351 .regs = ufsphy_v6_regs_layout,
1352 };
1353
1354 static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
1355 .lanes = 1,
1356
1357 .offsets = &qmp_ufs_offsets,
1358 .max_supported_gear = UFS_HS_G3,
1359
1360 .tbls = {
1361 .serdes = msm8996_ufsphy_serdes,
1362 .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
1363 .tx = msm8996_ufsphy_tx,
1364 .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx),
1365 .rx = msm8996_ufsphy_rx,
1366 .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx),
1367 },
1368
1369 .vreg_list = msm8996_ufsphy_vreg_l,
1370 .num_vregs = ARRAY_SIZE(msm8996_ufsphy_vreg_l),
1371
1372 .regs = ufsphy_v2_regs_layout,
1373
1374 .no_pcs_sw_reset = true,
1375 };
1376
1377 static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
1378 .lanes = 2,
1379
1380 .offsets = &qmp_ufs_offsets,
1381 .max_supported_gear = UFS_HS_G4,
1382
1383 .tbls = {
1384 .serdes = sm8350_ufsphy_serdes,
1385 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
1386 .tx = sm8350_ufsphy_tx,
1387 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
1388 .rx = sm8350_ufsphy_rx,
1389 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
1390 .pcs = sm8350_ufsphy_pcs,
1391 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
1392 },
1393 .tbls_hs_b = {
1394 .serdes = sm8350_ufsphy_hs_b_serdes,
1395 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1396 },
1397 .tbls_hs_overlay[0] = {
1398 .tx = sm8350_ufsphy_g4_tx,
1399 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1400 .rx = sm8350_ufsphy_g4_rx,
1401 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1402 .pcs = sm8350_ufsphy_g4_pcs,
1403 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1404 .max_gear = UFS_HS_G4,
1405 },
1406 .vreg_list = sa8775p_ufsphy_vreg_l,
1407 .num_vregs = ARRAY_SIZE(sa8775p_ufsphy_vreg_l),
1408 .regs = ufsphy_v5_regs_layout,
1409 };
1410
1411 static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
1412 .lanes = 2,
1413
1414 .offsets = &qmp_ufs_offsets,
1415 .max_supported_gear = UFS_HS_G4,
1416
1417 .tbls = {
1418 .serdes = sm8150_ufsphy_serdes,
1419 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
1420 .tx = sc7280_ufsphy_tx,
1421 .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx),
1422 .rx = sc7280_ufsphy_rx,
1423 .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx),
1424 .pcs = sc7280_ufsphy_pcs,
1425 .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs),
1426 },
1427 .tbls_hs_b = {
1428 .serdes = sm8150_ufsphy_hs_b_serdes,
1429 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1430 },
1431 .tbls_hs_overlay[0] = {
1432 .tx = sm8250_ufsphy_hs_g4_tx,
1433 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1434 .rx = sc7280_ufsphy_hs_g4_rx,
1435 .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
1436 .pcs = sm8150_ufsphy_hs_g4_pcs,
1437 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1438 .max_gear = UFS_HS_G4,
1439 },
1440 .vreg_list = sc7280_ufsphy_vreg_l,
1441 .num_vregs = ARRAY_SIZE(sc7280_ufsphy_vreg_l),
1442 .regs = ufsphy_v4_regs_layout,
1443 };
1444
1445 static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
1446 .lanes = 2,
1447
1448 .offsets = &qmp_ufs_offsets,
1449 .max_supported_gear = UFS_HS_G4,
1450
1451 .tbls = {
1452 .serdes = sm8350_ufsphy_serdes,
1453 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
1454 .tx = sm8350_ufsphy_tx,
1455 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
1456 .rx = sm8350_ufsphy_rx,
1457 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
1458 .pcs = sm8350_ufsphy_pcs,
1459 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
1460 },
1461 .tbls_hs_b = {
1462 .serdes = sm8350_ufsphy_hs_b_serdes,
1463 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1464 },
1465 .tbls_hs_overlay[0] = {
1466 .tx = sm8350_ufsphy_g4_tx,
1467 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1468 .rx = sm8350_ufsphy_g4_rx,
1469 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1470 .pcs = sm8350_ufsphy_g4_pcs,
1471 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1472 .max_gear = UFS_HS_G4,
1473 },
1474 .vreg_list = sc8280xp_ufsphy_vreg_l,
1475 .num_vregs = ARRAY_SIZE(sc8280xp_ufsphy_vreg_l),
1476 .regs = ufsphy_v5_regs_layout,
1477 };
1478
1479 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1480 .lanes = 2,
1481
1482 .offsets = &qmp_ufs_offsets,
1483 .max_supported_gear = UFS_HS_G3,
1484
1485 .tbls = {
1486 .serdes = sdm845_ufsphy_serdes,
1487 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
1488 .tx = sdm845_ufsphy_tx,
1489 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
1490 .rx = sdm845_ufsphy_rx,
1491 .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx),
1492 .pcs = sdm845_ufsphy_pcs,
1493 .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
1494 },
1495 .tbls_hs_b = {
1496 .serdes = sdm845_ufsphy_hs_b_serdes,
1497 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1498 },
1499 .vreg_list = sdm845_ufsphy_vreg_l,
1500 .num_vregs = ARRAY_SIZE(sdm845_ufsphy_vreg_l),
1501 .regs = ufsphy_v3_regs_layout,
1502
1503 .no_pcs_sw_reset = true,
1504 };
1505
1506 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
1507 .lanes = 1,
1508
1509 .offsets = &qmp_ufs_offsets,
1510 .max_supported_gear = UFS_HS_G3,
1511
1512 .tbls = {
1513 .serdes = sm6115_ufsphy_serdes,
1514 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
1515 .tx = sm6115_ufsphy_tx,
1516 .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx),
1517 .rx = sm6115_ufsphy_rx,
1518 .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx),
1519 .pcs = sm6115_ufsphy_pcs,
1520 .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
1521 },
1522 .tbls_hs_b = {
1523 .serdes = sm6115_ufsphy_hs_b_serdes,
1524 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
1525 },
1526 .vreg_list = sm6115_ufsphy_vreg_l,
1527 .num_vregs = ARRAY_SIZE(sm6115_ufsphy_vreg_l),
1528 .regs = ufsphy_v2_regs_layout,
1529
1530 .no_pcs_sw_reset = true,
1531 };
1532
1533 static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
1534 .lanes = 1,
1535
1536 .offsets = &qmp_ufs_offsets,
1537 .max_supported_gear = UFS_HS_G3,
1538
1539 .tbls = {
1540 .serdes = sdm845_ufsphy_serdes,
1541 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
1542 .tx = sdm845_ufsphy_tx,
1543 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
1544 .rx = sm7150_ufsphy_rx,
1545 .rx_num = ARRAY_SIZE(sm7150_ufsphy_rx),
1546 .pcs = sm7150_ufsphy_pcs,
1547 .pcs_num = ARRAY_SIZE(sm7150_ufsphy_pcs),
1548 },
1549 .tbls_hs_b = {
1550 .serdes = sdm845_ufsphy_hs_b_serdes,
1551 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1552 },
1553 .vreg_list = sm7150_ufsphy_vreg_l,
1554 .num_vregs = ARRAY_SIZE(sm7150_ufsphy_vreg_l),
1555 .regs = ufsphy_v3_regs_layout,
1556
1557 .no_pcs_sw_reset = true,
1558 };
1559
1560 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
1561 .lanes = 2,
1562
1563 .offsets = &qmp_ufs_offsets,
1564 .max_supported_gear = UFS_HS_G4,
1565
1566 .tbls = {
1567 .serdes = sm8150_ufsphy_serdes,
1568 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
1569 .tx = sm8150_ufsphy_tx,
1570 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
1571 .rx = sm8150_ufsphy_rx,
1572 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
1573 .pcs = sm8150_ufsphy_pcs,
1574 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
1575 },
1576 .tbls_hs_b = {
1577 .serdes = sm8150_ufsphy_hs_b_serdes,
1578 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1579 },
1580 .tbls_hs_overlay[0] = {
1581 .tx = sm8150_ufsphy_hs_g4_tx,
1582 .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
1583 .rx = sm8150_ufsphy_hs_g4_rx,
1584 .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
1585 .pcs = sm8150_ufsphy_hs_g4_pcs,
1586 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1587 .max_gear = UFS_HS_G4,
1588 },
1589 .vreg_list = sm8150_ufsphy_vreg_l,
1590 .num_vregs = ARRAY_SIZE(sm8150_ufsphy_vreg_l),
1591 .regs = ufsphy_v4_regs_layout,
1592 };
1593
1594 static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
1595 .lanes = 2,
1596
1597 .offsets = &qmp_ufs_offsets,
1598 .max_supported_gear = UFS_HS_G4,
1599
1600 .tbls = {
1601 .serdes = sm8150_ufsphy_serdes,
1602 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
1603 .tx = sm8150_ufsphy_tx,
1604 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
1605 .rx = sm8150_ufsphy_rx,
1606 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
1607 .pcs = sm8150_ufsphy_pcs,
1608 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
1609 },
1610 .tbls_hs_b = {
1611 .serdes = sm8150_ufsphy_hs_b_serdes,
1612 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1613 },
1614 .tbls_hs_overlay[0] = {
1615 .tx = sm8250_ufsphy_hs_g4_tx,
1616 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1617 .rx = sm8250_ufsphy_hs_g4_rx,
1618 .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
1619 .pcs = sm8150_ufsphy_hs_g4_pcs,
1620 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1621 .max_gear = UFS_HS_G4,
1622 },
1623 .vreg_list = sm8250_ufsphy_vreg_l,
1624 .num_vregs = ARRAY_SIZE(sm8250_ufsphy_vreg_l),
1625 .regs = ufsphy_v4_regs_layout,
1626 };
1627
1628 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
1629 .lanes = 2,
1630
1631 .offsets = &qmp_ufs_offsets,
1632 .max_supported_gear = UFS_HS_G4,
1633
1634 .tbls = {
1635 .serdes = sm8350_ufsphy_serdes,
1636 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
1637 .tx = sm8350_ufsphy_tx,
1638 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
1639 .rx = sm8350_ufsphy_rx,
1640 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
1641 .pcs = sm8350_ufsphy_pcs,
1642 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
1643 },
1644 .tbls_hs_b = {
1645 .serdes = sm8350_ufsphy_hs_b_serdes,
1646 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1647 },
1648 .tbls_hs_overlay[0] = {
1649 .tx = sm8350_ufsphy_g4_tx,
1650 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1651 .rx = sm8350_ufsphy_g4_rx,
1652 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1653 .pcs = sm8350_ufsphy_g4_pcs,
1654 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1655 .max_gear = UFS_HS_G4,
1656 },
1657 .vreg_list = sm8350_ufsphy_vreg_l,
1658 .num_vregs = ARRAY_SIZE(sm8350_ufsphy_vreg_l),
1659 .regs = ufsphy_v5_regs_layout,
1660 };
1661
1662 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
1663 .lanes = 2,
1664
1665 .offsets = &qmp_ufs_offsets,
1666 .max_supported_gear = UFS_HS_G4,
1667
1668 .tbls = {
1669 .serdes = sm8350_ufsphy_serdes,
1670 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
1671 .tx = sm8350_ufsphy_tx,
1672 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
1673 .rx = sm8350_ufsphy_rx,
1674 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
1675 .pcs = sm8350_ufsphy_pcs,
1676 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
1677 },
1678 .tbls_hs_b = {
1679 .serdes = sm8350_ufsphy_hs_b_serdes,
1680 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1681 },
1682 .tbls_hs_overlay[0] = {
1683 .tx = sm8350_ufsphy_g4_tx,
1684 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1685 .rx = sm8350_ufsphy_g4_rx,
1686 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1687 .pcs = sm8350_ufsphy_g4_pcs,
1688 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1689 .max_gear = UFS_HS_G4,
1690 },
1691 .vreg_list = sm8450_ufsphy_vreg_l,
1692 .num_vregs = ARRAY_SIZE(sm8450_ufsphy_vreg_l),
1693 .regs = ufsphy_v5_regs_layout,
1694 };
1695
1696 static const struct qmp_phy_cfg sm8475_ufsphy_cfg = {
1697 .lanes = 2,
1698
1699 .offsets = &qmp_ufs_offsets_v6,
1700 .max_supported_gear = UFS_HS_G4,
1701
1702 .tbls = {
1703 .serdes = sm8475_ufsphy_serdes,
1704 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_serdes),
1705 .tx = sm8550_ufsphy_tx,
1706 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx),
1707 .rx = sm8550_ufsphy_rx,
1708 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx),
1709 .pcs = sm8550_ufsphy_pcs,
1710 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
1711 },
1712 .tbls_hs_b = {
1713 .serdes = sm8550_ufsphy_hs_b_serdes,
1714 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
1715 },
1716 .tbls_hs_overlay[0] = {
1717 .serdes = sm8475_ufsphy_g4_serdes,
1718 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_g4_serdes),
1719 .tx = sm8550_ufsphy_g4_tx,
1720 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
1721 .rx = sm8550_ufsphy_g4_rx,
1722 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
1723 .pcs = sm8475_ufsphy_g4_pcs,
1724 .pcs_num = ARRAY_SIZE(sm8475_ufsphy_g4_pcs),
1725 .max_gear = UFS_HS_G4,
1726 },
1727 .vreg_list = sm8475_ufsphy_vreg_l,
1728 .num_vregs = ARRAY_SIZE(sm8475_ufsphy_vreg_l),
1729 .regs = ufsphy_v6_regs_layout,
1730 };
1731
1732 static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
1733 .lanes = 2,
1734
1735 .offsets = &qmp_ufs_offsets_v6,
1736 .max_supported_gear = UFS_HS_G5,
1737
1738 .tbls = {
1739 .serdes = sm8550_ufsphy_serdes,
1740 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes),
1741 .tx = sm8550_ufsphy_tx,
1742 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx),
1743 .rx = sm8550_ufsphy_rx,
1744 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx),
1745 .pcs = sm8550_ufsphy_pcs,
1746 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
1747 },
1748 .tbls_hs_b = {
1749 .serdes = sm8550_ufsphy_hs_b_serdes,
1750 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
1751 },
1752 .tbls_hs_overlay[0] = {
1753 .serdes = sm8550_ufsphy_g4_serdes,
1754 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
1755 .tx = sm8550_ufsphy_g4_tx,
1756 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
1757 .rx = sm8550_ufsphy_g4_rx,
1758 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
1759 .pcs = sm8550_ufsphy_g4_pcs,
1760 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
1761 .max_gear = UFS_HS_G4,
1762 },
1763 .tbls_hs_overlay[1] = {
1764 .serdes = sm8550_ufsphy_g5_serdes,
1765 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
1766 .rx = sm8550_ufsphy_g5_rx,
1767 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
1768 .pcs = sm8550_ufsphy_g5_pcs,
1769 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
1770 .max_gear = UFS_HS_G5,
1771 },
1772 .vreg_list = sm8550_ufsphy_vreg_l,
1773 .num_vregs = ARRAY_SIZE(sm8550_ufsphy_vreg_l),
1774 .regs = ufsphy_v6_regs_layout,
1775 };
1776
1777 static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
1778 .lanes = 2,
1779
1780 .offsets = &qmp_ufs_offsets_v6,
1781 .max_supported_gear = UFS_HS_G5,
1782
1783 .tbls = {
1784 .serdes = sm8650_ufsphy_serdes,
1785 .serdes_num = ARRAY_SIZE(sm8650_ufsphy_serdes),
1786 .tx = sm8650_ufsphy_tx,
1787 .tx_num = ARRAY_SIZE(sm8650_ufsphy_tx),
1788 .rx = sm8650_ufsphy_rx,
1789 .rx_num = ARRAY_SIZE(sm8650_ufsphy_rx),
1790 .pcs = sm8650_ufsphy_pcs,
1791 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_pcs),
1792 },
1793 .tbls_hs_overlay[0] = {
1794 .pcs = sm8650_ufsphy_g4_pcs,
1795 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g4_pcs),
1796 .max_gear = UFS_HS_G4,
1797 },
1798 .tbls_hs_overlay[1] = {
1799 .pcs = sm8650_ufsphy_g5_pcs,
1800 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs),
1801 .max_gear = UFS_HS_G5,
1802 },
1803
1804 .vreg_list = sm8650_ufsphy_vreg_l,
1805 .num_vregs = ARRAY_SIZE(sm8650_ufsphy_vreg_l),
1806 .regs = ufsphy_v6_regs_layout,
1807 };
1808
1809 static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
1810 .lanes = 2,
1811
1812 .offsets = &qmp_ufs_offsets_v6,
1813 .max_supported_gear = UFS_HS_G5,
1814
1815 .tbls = {
1816 .serdes = sm8750_ufsphy_serdes,
1817 .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
1818 .tx = sm8750_ufsphy_tx,
1819 .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
1820 .rx = sm8750_ufsphy_rx,
1821 .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx),
1822 .pcs = sm8750_ufsphy_pcs,
1823 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
1824 },
1825
1826 .tbls_hs_b = {
1827 .pcs = sm8750_ufsphy_hs_b_pcs,
1828 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
1829 },
1830
1831 .tbls_hs_overlay[0] = {
1832 .pcs = sm8750_ufsphy_g4_pcs,
1833 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
1834 .max_gear = UFS_HS_G4,
1835 },
1836 .tbls_hs_overlay[1] = {
1837 .pcs = sm8650_ufsphy_g5_pcs,
1838 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs),
1839 .max_gear = UFS_HS_G5,
1840 },
1841
1842 .vreg_list = sm8750_ufsphy_vreg_l,
1843 .num_vregs = ARRAY_SIZE(sm8750_ufsphy_vreg_l),
1844 .regs = ufsphy_v6_regs_layout,
1845
1846 };
1847
qmp_ufs_serdes_init(struct qmp_ufs * qmp,const struct qmp_phy_cfg_tbls * tbls)1848 static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1849 {
1850 void __iomem *serdes = qmp->serdes;
1851
1852 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);
1853 }
1854
qmp_ufs_lanes_init(struct qmp_ufs * qmp,const struct qmp_phy_cfg_tbls * tbls)1855 static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1856 {
1857 const struct qmp_phy_cfg *cfg = qmp->cfg;
1858 void __iomem *tx = qmp->tx;
1859 void __iomem *rx = qmp->rx;
1860
1861 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1);
1862 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1);
1863
1864 if (cfg->lanes >= 2) {
1865 qmp_configure_lane(qmp->dev, qmp->tx2, tbls->tx, tbls->tx_num, 2);
1866 qmp_configure_lane(qmp->dev, qmp->rx2, tbls->rx, tbls->rx_num, 2);
1867 }
1868 }
1869
qmp_ufs_pcs_init(struct qmp_ufs * qmp,const struct qmp_phy_cfg_tbls * tbls)1870 static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1871 {
1872 void __iomem *pcs = qmp->pcs;
1873
1874 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);
1875 }
1876
qmp_ufs_get_gear_overlay(struct qmp_ufs * qmp,const struct qmp_phy_cfg * cfg)1877 static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
1878 {
1879 u32 max_gear, floor_max_gear = cfg->max_supported_gear;
1880 int idx, ret = -EINVAL;
1881
1882 for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) {
1883 max_gear = cfg->tbls_hs_overlay[idx].max_gear;
1884
1885 /* Skip if the table is not available */
1886 if (max_gear == 0)
1887 continue;
1888
1889 /* Direct matching, bail */
1890 if (qmp->submode == max_gear)
1891 return idx;
1892
1893 /* If no direct matching, the lowest gear is the best matching */
1894 if (max_gear < floor_max_gear) {
1895 ret = idx;
1896 floor_max_gear = max_gear;
1897 }
1898 }
1899
1900 return ret;
1901 }
1902
qmp_ufs_init_all(struct qmp_ufs * qmp,const struct qmp_phy_cfg_tbls * tbls)1903 static void qmp_ufs_init_all(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1904 {
1905 qmp_ufs_serdes_init(qmp, tbls);
1906 qmp_ufs_lanes_init(qmp, tbls);
1907 qmp_ufs_pcs_init(qmp, tbls);
1908 }
1909
qmp_ufs_init_registers(struct qmp_ufs * qmp,const struct qmp_phy_cfg * cfg)1910 static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
1911 {
1912 int i;
1913
1914 qmp_ufs_init_all(qmp, &cfg->tbls);
1915
1916 i = qmp_ufs_get_gear_overlay(qmp, cfg);
1917 if (i >= 0) {
1918 qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]);
1919 }
1920
1921 if (qmp->mode == PHY_MODE_UFS_HS_B)
1922 qmp_ufs_init_all(qmp, &cfg->tbls_hs_b);
1923 }
1924
qmp_ufs_power_on(struct phy * phy)1925 static int qmp_ufs_power_on(struct phy *phy)
1926 {
1927 struct qmp_ufs *qmp = phy_get_drvdata(phy);
1928 const struct qmp_phy_cfg *cfg = qmp->cfg;
1929 void __iomem *pcs = qmp->pcs;
1930 int ret;
1931
1932 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1933 if (ret) {
1934 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1935 return ret;
1936 }
1937
1938 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1939 if (ret)
1940 goto err_disable_regulators;
1941
1942 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1943 return 0;
1944
1945 err_disable_regulators:
1946 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1947 return ret;
1948 }
1949
qmp_ufs_phy_calibrate(struct phy * phy)1950 static int qmp_ufs_phy_calibrate(struct phy *phy)
1951 {
1952 struct qmp_ufs *qmp = phy_get_drvdata(phy);
1953 const struct qmp_phy_cfg *cfg = qmp->cfg;
1954 void __iomem *pcs = qmp->pcs;
1955 void __iomem *status;
1956 unsigned int val;
1957 int ret;
1958
1959 ret = reset_control_assert(qmp->ufs_reset);
1960 if (ret)
1961 return ret;
1962
1963 qmp_ufs_init_registers(qmp, cfg);
1964
1965 ret = reset_control_deassert(qmp->ufs_reset);
1966 if (ret)
1967 return ret;
1968
1969 /* Pull PHY out of reset state */
1970 if (!cfg->no_pcs_sw_reset)
1971 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1972
1973 /* start SerDes */
1974 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1975
1976 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1977 ret = readl_poll_timeout(status, val, (val & PCS_READY), 200,
1978 PHY_INIT_COMPLETE_TIMEOUT);
1979 if (ret) {
1980 dev_err(qmp->dev, "phy initialization timed-out\n");
1981 return ret;
1982 }
1983
1984 return 0;
1985 }
1986
qmp_ufs_power_off(struct phy * phy)1987 static int qmp_ufs_power_off(struct phy *phy)
1988 {
1989 struct qmp_ufs *qmp = phy_get_drvdata(phy);
1990 const struct qmp_phy_cfg *cfg = qmp->cfg;
1991
1992 /* Put PHY into POWER DOWN state: active low */
1993 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1994 SW_PWRDN);
1995
1996 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1997
1998 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1999
2000 return 0;
2001 }
2002
qmp_ufs_set_mode(struct phy * phy,enum phy_mode mode,int submode)2003 static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
2004 {
2005 struct qmp_ufs *qmp = phy_get_drvdata(phy);
2006 const struct qmp_phy_cfg *cfg = qmp->cfg;
2007
2008 if (submode > cfg->max_supported_gear || submode == 0) {
2009 dev_err(qmp->dev, "Invalid PHY submode %d\n", submode);
2010 return -EINVAL;
2011 }
2012
2013 qmp->mode = mode;
2014 qmp->submode = submode;
2015
2016 return 0;
2017 }
2018
qmp_ufs_phy_init(struct phy * phy)2019 static int qmp_ufs_phy_init(struct phy *phy)
2020 {
2021 struct qmp_ufs *qmp = phy_get_drvdata(phy);
2022 const struct qmp_phy_cfg *cfg = qmp->cfg;
2023 int ret;
2024
2025 if (!cfg->no_pcs_sw_reset)
2026 return 0;
2027
2028 /*
2029 * Get UFS reset, which is delayed until now to avoid a
2030 * circular dependency where UFS needs its PHY, but the PHY
2031 * needs this UFS reset.
2032 */
2033 if (!qmp->ufs_reset) {
2034 qmp->ufs_reset =
2035 devm_reset_control_get_exclusive(qmp->dev, "ufsphy");
2036
2037 if (IS_ERR(qmp->ufs_reset)) {
2038 ret = PTR_ERR(qmp->ufs_reset);
2039 dev_err(qmp->dev, "failed to get PHY reset: %d\n", ret);
2040 qmp->ufs_reset = NULL;
2041 return ret;
2042 }
2043 }
2044
2045 return 0;
2046 }
2047
2048 static const struct phy_ops qcom_qmp_ufs_phy_ops = {
2049 .init = qmp_ufs_phy_init,
2050 .power_on = qmp_ufs_power_on,
2051 .power_off = qmp_ufs_power_off,
2052 .calibrate = qmp_ufs_phy_calibrate,
2053 .set_mode = qmp_ufs_set_mode,
2054 .owner = THIS_MODULE,
2055 };
2056
2057
qmp_ufs_clk_init(struct qmp_ufs * qmp)2058 static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
2059 {
2060 struct device *dev = qmp->dev;
2061
2062 qmp->num_clks = devm_clk_bulk_get_all(dev, &qmp->clks);
2063 if (qmp->num_clks < 0)
2064 return qmp->num_clks;
2065
2066 return 0;
2067 }
2068
qmp_ufs_clk_release_provider(void * res)2069 static void qmp_ufs_clk_release_provider(void *res)
2070 {
2071 of_clk_del_provider(res);
2072 }
2073
2074 #define UFS_SYMBOL_CLOCKS 3
2075
qmp_ufs_register_clocks(struct qmp_ufs * qmp,struct device_node * np)2076 static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np)
2077 {
2078 struct clk_hw_onecell_data *clk_data;
2079 struct clk_hw *hw;
2080 char name[64];
2081 int ret;
2082
2083 clk_data = devm_kzalloc(qmp->dev,
2084 struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
2085 GFP_KERNEL);
2086 if (!clk_data)
2087 return -ENOMEM;
2088
2089 clk_data->num = UFS_SYMBOL_CLOCKS;
2090
2091 snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
2092 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
2093 if (IS_ERR(hw))
2094 return PTR_ERR(hw);
2095
2096 clk_data->hws[0] = hw;
2097
2098 snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
2099 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
2100 if (IS_ERR(hw))
2101 return PTR_ERR(hw);
2102
2103 clk_data->hws[1] = hw;
2104
2105 snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
2106 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
2107 if (IS_ERR(hw))
2108 return PTR_ERR(hw);
2109
2110 clk_data->hws[2] = hw;
2111
2112 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
2113 if (ret)
2114 return ret;
2115
2116 /*
2117 * Roll a devm action because the clock provider can be a child node.
2118 */
2119 return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np);
2120 }
2121
qmp_ufs_parse_dt_legacy(struct qmp_ufs * qmp,struct device_node * np)2122 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
2123 {
2124 struct platform_device *pdev = to_platform_device(qmp->dev);
2125 const struct qmp_phy_cfg *cfg = qmp->cfg;
2126 struct device *dev = qmp->dev;
2127
2128 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2129 if (IS_ERR(qmp->serdes))
2130 return PTR_ERR(qmp->serdes);
2131
2132 /*
2133 * Get memory resources for the PHY:
2134 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2135 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2136 * For single lane PHYs: pcs_misc (optional) -> 3.
2137 */
2138 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2139 if (IS_ERR(qmp->tx))
2140 return PTR_ERR(qmp->tx);
2141
2142 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2143 if (IS_ERR(qmp->rx))
2144 return PTR_ERR(qmp->rx);
2145
2146 qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
2147 if (IS_ERR(qmp->pcs))
2148 return PTR_ERR(qmp->pcs);
2149
2150 if (cfg->lanes >= 2) {
2151 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2152 if (IS_ERR(qmp->tx2))
2153 return PTR_ERR(qmp->tx2);
2154
2155 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2156 if (IS_ERR(qmp->rx2))
2157 return PTR_ERR(qmp->rx2);
2158
2159 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
2160 } else {
2161 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2162 }
2163
2164 if (IS_ERR(qmp->pcs_misc))
2165 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2166
2167 return 0;
2168 }
2169
qmp_ufs_parse_dt(struct qmp_ufs * qmp)2170 static int qmp_ufs_parse_dt(struct qmp_ufs *qmp)
2171 {
2172 struct platform_device *pdev = to_platform_device(qmp->dev);
2173 const struct qmp_phy_cfg *cfg = qmp->cfg;
2174 const struct qmp_ufs_offsets *offs = cfg->offsets;
2175 void __iomem *base;
2176
2177 if (!offs)
2178 return -EINVAL;
2179
2180 base = devm_platform_ioremap_resource(pdev, 0);
2181 if (IS_ERR(base))
2182 return PTR_ERR(base);
2183
2184 qmp->serdes = base + offs->serdes;
2185 qmp->pcs = base + offs->pcs;
2186 qmp->tx = base + offs->tx;
2187 qmp->rx = base + offs->rx;
2188
2189 if (cfg->lanes >= 2) {
2190 qmp->tx2 = base + offs->tx2;
2191 qmp->rx2 = base + offs->rx2;
2192 }
2193
2194 return 0;
2195 }
2196
qmp_ufs_probe(struct platform_device * pdev)2197 static int qmp_ufs_probe(struct platform_device *pdev)
2198 {
2199 struct device *dev = &pdev->dev;
2200 struct phy_provider *phy_provider;
2201 struct device_node *np;
2202 struct qmp_ufs *qmp;
2203 int ret;
2204
2205 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2206 if (!qmp)
2207 return -ENOMEM;
2208
2209 qmp->dev = dev;
2210
2211 qmp->cfg = of_device_get_match_data(dev);
2212 if (!qmp->cfg)
2213 return -EINVAL;
2214
2215 ret = qmp_ufs_clk_init(qmp);
2216 if (ret)
2217 return ret;
2218
2219 ret = devm_regulator_bulk_get_const(dev, qmp->cfg->num_vregs,
2220 qmp->cfg->vreg_list,
2221 &qmp->vregs);
2222 if (ret)
2223 return ret;
2224
2225 /* Check for legacy binding with child node. */
2226 np = of_get_next_available_child(dev->of_node, NULL);
2227 if (np) {
2228 ret = qmp_ufs_parse_dt_legacy(qmp, np);
2229 } else {
2230 np = of_node_get(dev->of_node);
2231 ret = qmp_ufs_parse_dt(qmp);
2232 }
2233 if (ret)
2234 goto err_node_put;
2235
2236 ret = qmp_ufs_register_clocks(qmp, np);
2237 if (ret)
2238 goto err_node_put;
2239
2240 qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
2241 if (IS_ERR(qmp->phy)) {
2242 ret = PTR_ERR(qmp->phy);
2243 dev_err(dev, "failed to create PHY: %d\n", ret);
2244 goto err_node_put;
2245 }
2246
2247 phy_set_drvdata(qmp->phy, qmp);
2248
2249 of_node_put(np);
2250
2251 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2252
2253 return PTR_ERR_OR_ZERO(phy_provider);
2254
2255 err_node_put:
2256 of_node_put(np);
2257 return ret;
2258 }
2259
2260 static const struct of_device_id qmp_ufs_of_match_table[] = {
2261 {
2262 .compatible = "qcom,milos-qmp-ufs-phy",
2263 .data = &milos_ufsphy_cfg,
2264 }, {
2265 .compatible = "qcom,msm8996-qmp-ufs-phy",
2266 .data = &msm8996_ufsphy_cfg,
2267 }, {
2268 .compatible = "qcom,msm8998-qmp-ufs-phy",
2269 .data = &sdm845_ufsphy_cfg,
2270 }, {
2271 .compatible = "qcom,sa8775p-qmp-ufs-phy",
2272 .data = &sa8775p_ufsphy_cfg,
2273 }, {
2274 .compatible = "qcom,sc7180-qmp-ufs-phy",
2275 .data = &sm7150_ufsphy_cfg,
2276 }, {
2277 .compatible = "qcom,sc7280-qmp-ufs-phy",
2278 .data = &sc7280_ufsphy_cfg,
2279 }, {
2280 .compatible = "qcom,sc8180x-qmp-ufs-phy",
2281 .data = &sm8150_ufsphy_cfg,
2282 }, {
2283 .compatible = "qcom,sc8280xp-qmp-ufs-phy",
2284 .data = &sc8280xp_ufsphy_cfg,
2285 }, {
2286 .compatible = "qcom,sdm845-qmp-ufs-phy",
2287 .data = &sdm845_ufsphy_cfg,
2288 }, {
2289 .compatible = "qcom,sm6115-qmp-ufs-phy",
2290 .data = &sm6115_ufsphy_cfg,
2291 }, {
2292 .compatible = "qcom,sm6125-qmp-ufs-phy",
2293 .data = &sm6115_ufsphy_cfg,
2294 }, {
2295 .compatible = "qcom,sm6350-qmp-ufs-phy",
2296 .data = &sdm845_ufsphy_cfg,
2297 }, {
2298 .compatible = "qcom,sm7150-qmp-ufs-phy",
2299 .data = &sm7150_ufsphy_cfg,
2300 }, {
2301 .compatible = "qcom,sm8150-qmp-ufs-phy",
2302 .data = &sm8150_ufsphy_cfg,
2303 }, {
2304 .compatible = "qcom,sm8250-qmp-ufs-phy",
2305 .data = &sm8250_ufsphy_cfg,
2306 }, {
2307 .compatible = "qcom,sm8350-qmp-ufs-phy",
2308 .data = &sm8350_ufsphy_cfg,
2309 }, {
2310 .compatible = "qcom,sm8450-qmp-ufs-phy",
2311 .data = &sm8450_ufsphy_cfg,
2312 }, {
2313 .compatible = "qcom,sm8475-qmp-ufs-phy",
2314 .data = &sm8475_ufsphy_cfg,
2315 }, {
2316 .compatible = "qcom,sm8550-qmp-ufs-phy",
2317 .data = &sm8550_ufsphy_cfg,
2318 }, {
2319 .compatible = "qcom,sm8650-qmp-ufs-phy",
2320 .data = &sm8650_ufsphy_cfg,
2321 }, {
2322 .compatible = "qcom,sm8750-qmp-ufs-phy",
2323 .data = &sm8750_ufsphy_cfg,
2324 },
2325
2326 { },
2327 };
2328 MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
2329
2330 static struct platform_driver qmp_ufs_driver = {
2331 .probe = qmp_ufs_probe,
2332 .driver = {
2333 .name = "qcom-qmp-ufs-phy",
2334 .of_match_table = qmp_ufs_of_match_table,
2335 },
2336 };
2337
2338 module_platform_driver(qmp_ufs_driver);
2339
2340 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2341 MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver");
2342 MODULE_LICENSE("GPL v2");
2343