1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_dpm.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "soc15_common.h" 36 #include "smu_v11_0.h" 37 #include "smu11_driver_if_navi10.h" 38 #include "atom.h" 39 #include "navi10_ppt.h" 40 #include "smu_v11_0_pptable.h" 41 #include "smu_v11_0_ppsmc.h" 42 #include "nbio/nbio_2_3_offset.h" 43 #include "nbio/nbio_2_3_sh_mask.h" 44 #include "thm/thm_11_0_2_offset.h" 45 #include "thm/thm_11_0_2_sh_mask.h" 46 47 #include "asic_reg/mp/mp_11_0_sh_mask.h" 48 #include "smu_cmn.h" 49 #include "smu_11_0_cdr_table.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 #define FEATURE_MASK(feature) (1ULL << feature) 62 #define SMC_DPM_FEATURE ( \ 63 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) 71 72 #define SMU_11_0_GFX_BUSY_THRESHOLD 15 73 74 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { 75 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 76 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 77 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 78 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 79 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 80 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 81 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 82 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0), 83 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0), 84 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0), 85 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0), 86 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 87 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 88 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0), 89 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 92 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 93 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 94 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 95 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 96 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 97 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0), 98 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0), 99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 100 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 101 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 102 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 103 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 107 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0), 108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 112 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0), 113 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 114 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 115 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 116 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 117 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 118 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 119 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 120 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 121 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0), 122 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0), 123 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 124 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 125 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 126 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 127 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 128 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 129 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 130 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 131 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0), 132 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0), 133 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 134 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 135 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 136 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 137 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 138 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 139 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALDisableDummyPstateChange, 0), 140 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0), 141 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 142 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 143 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 144 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0), 145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0), 146 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0), 147 }; 148 149 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = { 150 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 151 CLK_MAP(SCLK, PPCLK_GFXCLK), 152 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 153 CLK_MAP(FCLK, PPCLK_SOCCLK), 154 CLK_MAP(UCLK, PPCLK_UCLK), 155 CLK_MAP(MCLK, PPCLK_UCLK), 156 CLK_MAP(DCLK, PPCLK_DCLK), 157 CLK_MAP(VCLK, PPCLK_VCLK), 158 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 159 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 160 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 161 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 162 }; 163 164 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = { 165 FEA_MAP(DPM_PREFETCHER), 166 FEA_MAP(DPM_GFXCLK), 167 FEA_MAP(DPM_GFX_PACE), 168 FEA_MAP(DPM_UCLK), 169 FEA_MAP(DPM_SOCCLK), 170 FEA_MAP(DPM_MP0CLK), 171 FEA_MAP(DPM_LINK), 172 FEA_MAP(DPM_DCEFCLK), 173 FEA_MAP(MEM_VDDCI_SCALING), 174 FEA_MAP(MEM_MVDD_SCALING), 175 FEA_MAP(DS_GFXCLK), 176 FEA_MAP(DS_SOCCLK), 177 FEA_MAP(DS_LCLK), 178 FEA_MAP(DS_DCEFCLK), 179 FEA_MAP(DS_UCLK), 180 FEA_MAP(GFX_ULV), 181 FEA_MAP(FW_DSTATE), 182 FEA_MAP(GFXOFF), 183 FEA_MAP(BACO), 184 FEA_MAP(VCN_PG), 185 FEA_MAP(JPEG_PG), 186 FEA_MAP(USB_PG), 187 FEA_MAP(RSMU_SMN_CG), 188 FEA_MAP(PPT), 189 FEA_MAP(TDC), 190 FEA_MAP(GFX_EDC), 191 FEA_MAP(APCC_PLUS), 192 FEA_MAP(GTHR), 193 FEA_MAP(ACDC), 194 FEA_MAP(VR0HOT), 195 FEA_MAP(VR1HOT), 196 FEA_MAP(FW_CTF), 197 FEA_MAP(FAN_CONTROL), 198 FEA_MAP(THERMAL), 199 FEA_MAP(GFX_DCS), 200 FEA_MAP(RM), 201 FEA_MAP(LED_DISPLAY), 202 FEA_MAP(GFX_SS), 203 FEA_MAP(OUT_OF_BAND_MONITOR), 204 FEA_MAP(TEMP_DEPENDENT_VMIN), 205 FEA_MAP(MMHUB_PG), 206 FEA_MAP(ATHUB_PG), 207 FEA_MAP(APCC_DFLL), 208 }; 209 210 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = { 211 TAB_MAP(PPTABLE), 212 TAB_MAP(WATERMARKS), 213 TAB_MAP(AVFS), 214 TAB_MAP(AVFS_PSM_DEBUG), 215 TAB_MAP(AVFS_FUSE_OVERRIDE), 216 TAB_MAP(PMSTATUSLOG), 217 TAB_MAP(SMU_METRICS), 218 TAB_MAP(DRIVER_SMU_CONFIG), 219 TAB_MAP(ACTIVITY_MONITOR_COEFF), 220 TAB_MAP(OVERDRIVE), 221 TAB_MAP(I2C_COMMANDS), 222 TAB_MAP(PACE), 223 }; 224 225 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 226 PWR_MAP(AC), 227 PWR_MAP(DC), 228 }; 229 230 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 231 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 238 }; 239 240 static const uint8_t navi1x_throttler_map[] = { 241 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 242 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 243 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 244 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 245 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 246 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 247 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 248 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 249 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 250 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 251 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 252 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 253 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 254 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 255 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 256 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 257 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 258 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 259 }; 260 261 262 static bool is_asic_secure(struct smu_context *smu) 263 { 264 struct amdgpu_device *adev = smu->adev; 265 bool is_secure = true; 266 uint32_t mp0_fw_intf; 267 268 mp0_fw_intf = RREG32_PCIE(MP0_Public | 269 (smnMP0_FW_INTF & 0xffffffff)); 270 271 if (!(mp0_fw_intf & (1 << 19))) 272 is_secure = false; 273 274 return is_secure; 275 } 276 277 static int 278 navi10_init_allowed_features(struct smu_context *smu) 279 { 280 struct amdgpu_device *adev = smu->adev; 281 282 smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 283 284 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT); 285 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); 286 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT); 287 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); 288 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT); 289 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT); 290 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_EDC_BIT); 291 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_PLUS_BIT); 292 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); 293 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); 294 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT); 295 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_LED_DISPLAY_BIT); 296 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); 297 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT); 298 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); 299 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); 300 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT); 301 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT); 302 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); 303 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT); 304 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TEMP_DEPENDENT_VMIN_BIT); 305 306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) 307 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); 308 309 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 310 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); 311 312 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 313 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT); 314 315 if (adev->pm.pp_feature & PP_ULV_MASK) 316 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); 317 318 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 319 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); 320 321 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 322 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); 323 324 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 325 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT); 326 327 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 328 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT); 329 330 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) 331 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VCN_PG_BIT); 332 333 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 334 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_JPEG_PG_BIT); 335 336 if (smu->dc_controlled_by_gpio) 337 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT); 338 339 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 340 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); 341 342 if (!(is_asic_secure(smu) && 343 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && 344 (adev->rev_id == 0)) && 345 (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { 346 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); 347 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT); 348 smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT); 349 } 350 351 if (is_asic_secure(smu) && 352 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && 353 (adev->rev_id == 0)) 354 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); 355 356 return 0; 357 } 358 359 static void navi10_check_bxco_support(struct smu_context *smu) 360 { 361 struct smu_table_context *table_context = &smu->smu_table; 362 struct smu_11_0_powerplay_table *powerplay_table = 363 table_context->power_play_table; 364 struct smu_baco_context *smu_baco = &smu->smu_baco; 365 struct amdgpu_device *adev = smu->adev; 366 uint32_t val; 367 368 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || 369 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { 370 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 371 smu_baco->platform_support = 372 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 373 false; 374 } 375 } 376 377 static int navi10_check_powerplay_table(struct smu_context *smu) 378 { 379 struct smu_table_context *table_context = &smu->smu_table; 380 struct smu_11_0_powerplay_table *powerplay_table = 381 table_context->power_play_table; 382 383 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC) 384 smu->dc_controlled_by_gpio = true; 385 386 navi10_check_bxco_support(smu); 387 388 table_context->thermal_controller_type = 389 powerplay_table->thermal_controller_type; 390 391 /* 392 * Instead of having its own buffer space and get overdrive_table copied, 393 * smu->od_settings just points to the actual overdrive_table 394 */ 395 smu->od_settings = &powerplay_table->overdrive_table; 396 397 return 0; 398 } 399 400 static int navi10_append_powerplay_table(struct smu_context *smu) 401 { 402 struct amdgpu_device *adev = smu->adev; 403 struct smu_table_context *table_context = &smu->smu_table; 404 PPTable_t *smc_pptable = table_context->driver_pptable; 405 struct atom_smc_dpm_info_v4_5 *smc_dpm_table; 406 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7; 407 int index, ret; 408 409 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 410 smc_dpm_info); 411 412 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 413 (uint8_t **)&smc_dpm_table); 414 if (ret) 415 return ret; 416 417 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 418 smc_dpm_table->table_header.format_revision, 419 smc_dpm_table->table_header.content_revision); 420 421 if (smc_dpm_table->table_header.format_revision != 4) { 422 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n"); 423 return -EINVAL; 424 } 425 426 switch (smc_dpm_table->table_header.content_revision) { 427 case 5: /* nv10 and nv14 */ 428 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 429 smc_dpm_table, I2cControllers); 430 break; 431 case 7: /* nv12 */ 432 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 433 (uint8_t **)&smc_dpm_table_v4_7); 434 if (ret) 435 return ret; 436 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 437 smc_dpm_table_v4_7, I2cControllers); 438 break; 439 default: 440 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n", 441 smc_dpm_table->table_header.content_revision); 442 return -EINVAL; 443 } 444 445 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { 446 /* TODO: remove it once SMU fw fix it */ 447 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN; 448 } 449 450 return 0; 451 } 452 453 static int navi10_store_powerplay_table(struct smu_context *smu) 454 { 455 struct smu_table_context *table_context = &smu->smu_table; 456 struct smu_11_0_powerplay_table *powerplay_table = 457 table_context->power_play_table; 458 459 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 460 sizeof(PPTable_t)); 461 462 return 0; 463 } 464 465 static int navi10_setup_pptable(struct smu_context *smu) 466 { 467 int ret = 0; 468 469 ret = smu_v11_0_setup_pptable(smu); 470 if (ret) 471 return ret; 472 473 ret = navi10_store_powerplay_table(smu); 474 if (ret) 475 return ret; 476 477 ret = navi10_append_powerplay_table(smu); 478 if (ret) 479 return ret; 480 481 ret = navi10_check_powerplay_table(smu); 482 if (ret) 483 return ret; 484 485 return ret; 486 } 487 488 static int navi10_tables_init(struct smu_context *smu) 489 { 490 struct smu_table_context *smu_table = &smu->smu_table; 491 struct smu_table *tables = smu_table->tables; 492 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table; 493 int ret; 494 495 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 496 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 497 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 498 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 499 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t), 500 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 501 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 503 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 505 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 507 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 508 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, 509 AMDGPU_GEM_DOMAIN_VRAM); 510 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfig_t), 511 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 512 513 dummy_read_1_table->size = 0x40000; 514 dummy_read_1_table->align = PAGE_SIZE; 515 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 516 517 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t), 518 GFP_KERNEL); 519 if (!smu_table->metrics_table) 520 goto err0_out; 521 smu_table->metrics_time = 0; 522 523 ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, 524 sizeof(struct gpu_metrics_v1_3), 525 SMU_GPU_METRICS_CACHE_INTERVAL); 526 if (ret) 527 goto err1_out; 528 529 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 530 if (!smu_table->watermarks_table) 531 goto err2_out; 532 533 smu_table->driver_smu_config_table = 534 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL); 535 if (!smu_table->driver_smu_config_table) 536 goto err3_out; 537 538 return 0; 539 540 err3_out: 541 kfree(smu_table->watermarks_table); 542 err2_out: 543 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); 544 err1_out: 545 kfree(smu_table->metrics_table); 546 err0_out: 547 return -ENOMEM; 548 } 549 550 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu, 551 MetricsMember_t member, 552 uint32_t *value) 553 { 554 struct smu_table_context *smu_table = &smu->smu_table; 555 SmuMetrics_legacy_t *metrics = 556 (SmuMetrics_legacy_t *)smu_table->metrics_table; 557 int ret = 0; 558 559 ret = smu_cmn_get_metrics_table(smu, 560 NULL, 561 false); 562 if (ret) 563 return ret; 564 565 switch (member) { 566 case METRICS_CURR_GFXCLK: 567 *value = metrics->CurrClock[PPCLK_GFXCLK]; 568 break; 569 case METRICS_CURR_SOCCLK: 570 *value = metrics->CurrClock[PPCLK_SOCCLK]; 571 break; 572 case METRICS_CURR_UCLK: 573 *value = metrics->CurrClock[PPCLK_UCLK]; 574 break; 575 case METRICS_CURR_VCLK: 576 *value = metrics->CurrClock[PPCLK_VCLK]; 577 break; 578 case METRICS_CURR_DCLK: 579 *value = metrics->CurrClock[PPCLK_DCLK]; 580 break; 581 case METRICS_CURR_DCEFCLK: 582 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 583 break; 584 case METRICS_AVERAGE_GFXCLK: 585 *value = metrics->AverageGfxclkFrequency; 586 break; 587 case METRICS_AVERAGE_SOCCLK: 588 *value = metrics->AverageSocclkFrequency; 589 break; 590 case METRICS_AVERAGE_UCLK: 591 *value = metrics->AverageUclkFrequency; 592 break; 593 case METRICS_AVERAGE_GFXACTIVITY: 594 *value = metrics->AverageGfxActivity; 595 break; 596 case METRICS_AVERAGE_MEMACTIVITY: 597 *value = metrics->AverageUclkActivity; 598 break; 599 case METRICS_AVERAGE_SOCKETPOWER: 600 *value = metrics->AverageSocketPower << 8; 601 break; 602 case METRICS_TEMPERATURE_EDGE: 603 *value = metrics->TemperatureEdge * 604 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 605 break; 606 case METRICS_TEMPERATURE_HOTSPOT: 607 *value = metrics->TemperatureHotspot * 608 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 609 break; 610 case METRICS_TEMPERATURE_MEM: 611 *value = metrics->TemperatureMem * 612 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 613 break; 614 case METRICS_TEMPERATURE_VRGFX: 615 *value = metrics->TemperatureVrGfx * 616 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 617 break; 618 case METRICS_TEMPERATURE_VRSOC: 619 *value = metrics->TemperatureVrSoc * 620 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 621 break; 622 case METRICS_THROTTLER_STATUS: 623 *value = metrics->ThrottlerStatus; 624 break; 625 case METRICS_CURR_FANSPEED: 626 *value = metrics->CurrFanSpeed; 627 break; 628 default: 629 *value = UINT_MAX; 630 break; 631 } 632 633 return ret; 634 } 635 636 static int navi10_get_smu_metrics_data(struct smu_context *smu, 637 MetricsMember_t member, 638 uint32_t *value) 639 { 640 struct smu_table_context *smu_table = &smu->smu_table; 641 SmuMetrics_t *metrics = 642 (SmuMetrics_t *)smu_table->metrics_table; 643 int ret = 0; 644 645 ret = smu_cmn_get_metrics_table(smu, 646 NULL, 647 false); 648 if (ret) 649 return ret; 650 651 switch (member) { 652 case METRICS_CURR_GFXCLK: 653 *value = metrics->CurrClock[PPCLK_GFXCLK]; 654 break; 655 case METRICS_CURR_SOCCLK: 656 *value = metrics->CurrClock[PPCLK_SOCCLK]; 657 break; 658 case METRICS_CURR_UCLK: 659 *value = metrics->CurrClock[PPCLK_UCLK]; 660 break; 661 case METRICS_CURR_VCLK: 662 *value = metrics->CurrClock[PPCLK_VCLK]; 663 break; 664 case METRICS_CURR_DCLK: 665 *value = metrics->CurrClock[PPCLK_DCLK]; 666 break; 667 case METRICS_CURR_DCEFCLK: 668 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 669 break; 670 case METRICS_AVERAGE_GFXCLK: 671 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 672 *value = metrics->AverageGfxclkFrequencyPreDs; 673 else 674 *value = metrics->AverageGfxclkFrequencyPostDs; 675 break; 676 case METRICS_AVERAGE_SOCCLK: 677 *value = metrics->AverageSocclkFrequency; 678 break; 679 case METRICS_AVERAGE_UCLK: 680 *value = metrics->AverageUclkFrequencyPostDs; 681 break; 682 case METRICS_AVERAGE_GFXACTIVITY: 683 *value = metrics->AverageGfxActivity; 684 break; 685 case METRICS_AVERAGE_MEMACTIVITY: 686 *value = metrics->AverageUclkActivity; 687 break; 688 case METRICS_AVERAGE_SOCKETPOWER: 689 *value = metrics->AverageSocketPower << 8; 690 break; 691 case METRICS_TEMPERATURE_EDGE: 692 *value = metrics->TemperatureEdge * 693 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 694 break; 695 case METRICS_TEMPERATURE_HOTSPOT: 696 *value = metrics->TemperatureHotspot * 697 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 698 break; 699 case METRICS_TEMPERATURE_MEM: 700 *value = metrics->TemperatureMem * 701 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 702 break; 703 case METRICS_TEMPERATURE_VRGFX: 704 *value = metrics->TemperatureVrGfx * 705 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 706 break; 707 case METRICS_TEMPERATURE_VRSOC: 708 *value = metrics->TemperatureVrSoc * 709 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 710 break; 711 case METRICS_THROTTLER_STATUS: 712 *value = metrics->ThrottlerStatus; 713 break; 714 case METRICS_CURR_FANSPEED: 715 *value = metrics->CurrFanSpeed; 716 break; 717 default: 718 *value = UINT_MAX; 719 break; 720 } 721 722 return ret; 723 } 724 725 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu, 726 MetricsMember_t member, 727 uint32_t *value) 728 { 729 struct smu_table_context *smu_table = &smu->smu_table; 730 SmuMetrics_NV12_legacy_t *metrics = 731 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table; 732 int ret = 0; 733 734 ret = smu_cmn_get_metrics_table(smu, 735 NULL, 736 false); 737 if (ret) 738 return ret; 739 740 switch (member) { 741 case METRICS_CURR_GFXCLK: 742 *value = metrics->CurrClock[PPCLK_GFXCLK]; 743 break; 744 case METRICS_CURR_SOCCLK: 745 *value = metrics->CurrClock[PPCLK_SOCCLK]; 746 break; 747 case METRICS_CURR_UCLK: 748 *value = metrics->CurrClock[PPCLK_UCLK]; 749 break; 750 case METRICS_CURR_VCLK: 751 *value = metrics->CurrClock[PPCLK_VCLK]; 752 break; 753 case METRICS_CURR_DCLK: 754 *value = metrics->CurrClock[PPCLK_DCLK]; 755 break; 756 case METRICS_CURR_DCEFCLK: 757 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 758 break; 759 case METRICS_AVERAGE_GFXCLK: 760 *value = metrics->AverageGfxclkFrequency; 761 break; 762 case METRICS_AVERAGE_SOCCLK: 763 *value = metrics->AverageSocclkFrequency; 764 break; 765 case METRICS_AVERAGE_UCLK: 766 *value = metrics->AverageUclkFrequency; 767 break; 768 case METRICS_AVERAGE_GFXACTIVITY: 769 *value = metrics->AverageGfxActivity; 770 break; 771 case METRICS_AVERAGE_MEMACTIVITY: 772 *value = metrics->AverageUclkActivity; 773 break; 774 case METRICS_AVERAGE_SOCKETPOWER: 775 *value = metrics->AverageSocketPower << 8; 776 break; 777 case METRICS_TEMPERATURE_EDGE: 778 *value = metrics->TemperatureEdge * 779 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 780 break; 781 case METRICS_TEMPERATURE_HOTSPOT: 782 *value = metrics->TemperatureHotspot * 783 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 784 break; 785 case METRICS_TEMPERATURE_MEM: 786 *value = metrics->TemperatureMem * 787 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 788 break; 789 case METRICS_TEMPERATURE_VRGFX: 790 *value = metrics->TemperatureVrGfx * 791 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 792 break; 793 case METRICS_TEMPERATURE_VRSOC: 794 *value = metrics->TemperatureVrSoc * 795 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 796 break; 797 case METRICS_THROTTLER_STATUS: 798 *value = metrics->ThrottlerStatus; 799 break; 800 case METRICS_CURR_FANSPEED: 801 *value = metrics->CurrFanSpeed; 802 break; 803 default: 804 *value = UINT_MAX; 805 break; 806 } 807 808 return ret; 809 } 810 811 static int navi12_get_smu_metrics_data(struct smu_context *smu, 812 MetricsMember_t member, 813 uint32_t *value) 814 { 815 struct smu_table_context *smu_table = &smu->smu_table; 816 SmuMetrics_NV12_t *metrics = 817 (SmuMetrics_NV12_t *)smu_table->metrics_table; 818 int ret = 0; 819 820 ret = smu_cmn_get_metrics_table(smu, 821 NULL, 822 false); 823 if (ret) 824 return ret; 825 826 switch (member) { 827 case METRICS_CURR_GFXCLK: 828 *value = metrics->CurrClock[PPCLK_GFXCLK]; 829 break; 830 case METRICS_CURR_SOCCLK: 831 *value = metrics->CurrClock[PPCLK_SOCCLK]; 832 break; 833 case METRICS_CURR_UCLK: 834 *value = metrics->CurrClock[PPCLK_UCLK]; 835 break; 836 case METRICS_CURR_VCLK: 837 *value = metrics->CurrClock[PPCLK_VCLK]; 838 break; 839 case METRICS_CURR_DCLK: 840 *value = metrics->CurrClock[PPCLK_DCLK]; 841 break; 842 case METRICS_CURR_DCEFCLK: 843 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 844 break; 845 case METRICS_AVERAGE_GFXCLK: 846 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 847 *value = metrics->AverageGfxclkFrequencyPreDs; 848 else 849 *value = metrics->AverageGfxclkFrequencyPostDs; 850 break; 851 case METRICS_AVERAGE_SOCCLK: 852 *value = metrics->AverageSocclkFrequency; 853 break; 854 case METRICS_AVERAGE_UCLK: 855 *value = metrics->AverageUclkFrequencyPostDs; 856 break; 857 case METRICS_AVERAGE_GFXACTIVITY: 858 *value = metrics->AverageGfxActivity; 859 break; 860 case METRICS_AVERAGE_MEMACTIVITY: 861 *value = metrics->AverageUclkActivity; 862 break; 863 case METRICS_AVERAGE_SOCKETPOWER: 864 *value = metrics->AverageSocketPower << 8; 865 break; 866 case METRICS_TEMPERATURE_EDGE: 867 *value = metrics->TemperatureEdge * 868 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 869 break; 870 case METRICS_TEMPERATURE_HOTSPOT: 871 *value = metrics->TemperatureHotspot * 872 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 873 break; 874 case METRICS_TEMPERATURE_MEM: 875 *value = metrics->TemperatureMem * 876 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 877 break; 878 case METRICS_TEMPERATURE_VRGFX: 879 *value = metrics->TemperatureVrGfx * 880 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 881 break; 882 case METRICS_TEMPERATURE_VRSOC: 883 *value = metrics->TemperatureVrSoc * 884 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 885 break; 886 case METRICS_THROTTLER_STATUS: 887 *value = metrics->ThrottlerStatus; 888 break; 889 case METRICS_CURR_FANSPEED: 890 *value = metrics->CurrFanSpeed; 891 break; 892 default: 893 *value = UINT_MAX; 894 break; 895 } 896 897 return ret; 898 } 899 900 static int navi1x_get_smu_metrics_data(struct smu_context *smu, 901 MetricsMember_t member, 902 uint32_t *value) 903 { 904 struct amdgpu_device *adev = smu->adev; 905 int ret = 0; 906 907 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 908 case IP_VERSION(11, 0, 9): 909 if (smu->smc_fw_version > 0x00341C00) 910 ret = navi12_get_smu_metrics_data(smu, member, value); 911 else 912 ret = navi12_get_legacy_smu_metrics_data(smu, member, value); 913 break; 914 case IP_VERSION(11, 0, 0): 915 case IP_VERSION(11, 0, 5): 916 default: 917 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == 918 IP_VERSION(11, 0, 5)) && 919 smu->smc_fw_version > 0x00351F00) || 920 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == 921 IP_VERSION(11, 0, 0)) && 922 smu->smc_fw_version > 0x002A3B00)) 923 ret = navi10_get_smu_metrics_data(smu, member, value); 924 else 925 ret = navi10_get_legacy_smu_metrics_data(smu, member, value); 926 break; 927 } 928 929 return ret; 930 } 931 932 static int navi10_allocate_dpm_context(struct smu_context *smu) 933 { 934 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 935 936 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 937 GFP_KERNEL); 938 if (!smu_dpm->dpm_context) 939 return -ENOMEM; 940 941 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 942 943 return 0; 944 } 945 946 static int navi10_init_smc_tables(struct smu_context *smu) 947 { 948 int ret = 0; 949 950 ret = navi10_tables_init(smu); 951 if (ret) 952 return ret; 953 954 ret = navi10_allocate_dpm_context(smu); 955 if (ret) 956 return ret; 957 958 return smu_v11_0_init_smc_tables(smu); 959 } 960 961 static int navi10_set_default_dpm_table(struct smu_context *smu) 962 { 963 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 964 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 965 struct smu_dpm_table *dpm_table; 966 int ret = 0; 967 968 /* socclk dpm table setup */ 969 dpm_table = &dpm_context->dpm_tables.soc_table; 970 dpm_table->clk_type = SMU_SOCCLK; 971 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 972 ret = smu_v11_0_set_single_dpm_table(smu, 973 SMU_SOCCLK, 974 dpm_table); 975 if (ret) 976 return ret; 977 if (!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete) 978 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; 979 } else { 980 dpm_table->count = 1; 981 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 982 dpm_table->dpm_levels[0].enabled = true; 983 } 984 985 /* gfxclk dpm table setup */ 986 dpm_table = &dpm_context->dpm_tables.gfx_table; 987 dpm_table->clk_type = SMU_GFXCLK; 988 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 989 ret = smu_v11_0_set_single_dpm_table(smu, 990 SMU_GFXCLK, 991 dpm_table); 992 if (ret) 993 return ret; 994 if (!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete) 995 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; 996 } else { 997 dpm_table->count = 1; 998 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 999 dpm_table->dpm_levels[0].enabled = true; 1000 } 1001 1002 /* uclk dpm table setup */ 1003 dpm_table = &dpm_context->dpm_tables.uclk_table; 1004 dpm_table->clk_type = SMU_UCLK; 1005 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1006 ret = smu_v11_0_set_single_dpm_table(smu, 1007 SMU_UCLK, 1008 dpm_table); 1009 if (ret) 1010 return ret; 1011 if (!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete) 1012 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; 1013 } else { 1014 dpm_table->count = 1; 1015 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 1016 dpm_table->dpm_levels[0].enabled = true; 1017 } 1018 1019 /* vclk dpm table setup */ 1020 dpm_table = &dpm_context->dpm_tables.vclk_table; 1021 dpm_table->clk_type = SMU_VCLK; 1022 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1023 ret = smu_v11_0_set_single_dpm_table(smu, 1024 SMU_VCLK, 1025 dpm_table); 1026 if (ret) 1027 return ret; 1028 if (!driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete) 1029 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; 1030 } else { 1031 dpm_table->count = 1; 1032 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 1033 dpm_table->dpm_levels[0].enabled = true; 1034 } 1035 1036 /* dclk dpm table setup */ 1037 dpm_table = &dpm_context->dpm_tables.dclk_table; 1038 dpm_table->clk_type = SMU_DCLK; 1039 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1040 ret = smu_v11_0_set_single_dpm_table(smu, 1041 SMU_DCLK, 1042 dpm_table); 1043 if (ret) 1044 return ret; 1045 if (!driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete) 1046 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; 1047 } else { 1048 dpm_table->count = 1; 1049 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 1050 dpm_table->dpm_levels[0].enabled = true; 1051 } 1052 1053 /* dcefclk dpm table setup */ 1054 dpm_table = &dpm_context->dpm_tables.dcef_table; 1055 dpm_table->clk_type = SMU_DCEFCLK; 1056 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1057 ret = smu_v11_0_set_single_dpm_table(smu, 1058 SMU_DCEFCLK, 1059 dpm_table); 1060 if (ret) 1061 return ret; 1062 if (!driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete) 1063 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; 1064 } else { 1065 dpm_table->count = 1; 1066 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1067 dpm_table->dpm_levels[0].enabled = true; 1068 } 1069 1070 /* pixelclk dpm table setup */ 1071 dpm_table = &dpm_context->dpm_tables.pixel_table; 1072 dpm_table->clk_type = SMU_PIXCLK; 1073 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1074 ret = smu_v11_0_set_single_dpm_table(smu, 1075 SMU_PIXCLK, 1076 dpm_table); 1077 if (ret) 1078 return ret; 1079 if (!driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete) 1080 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; 1081 } else { 1082 dpm_table->count = 1; 1083 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1084 dpm_table->dpm_levels[0].enabled = true; 1085 } 1086 1087 /* displayclk dpm table setup */ 1088 dpm_table = &dpm_context->dpm_tables.display_table; 1089 dpm_table->clk_type = SMU_DISPCLK; 1090 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1091 ret = smu_v11_0_set_single_dpm_table(smu, 1092 SMU_DISPCLK, 1093 dpm_table); 1094 if (ret) 1095 return ret; 1096 if (!driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete) 1097 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; 1098 } else { 1099 dpm_table->count = 1; 1100 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1101 dpm_table->dpm_levels[0].enabled = true; 1102 } 1103 1104 /* phyclk dpm table setup */ 1105 dpm_table = &dpm_context->dpm_tables.phy_table; 1106 dpm_table->clk_type = SMU_PHYCLK; 1107 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1108 ret = smu_v11_0_set_single_dpm_table(smu, 1109 SMU_PHYCLK, 1110 dpm_table); 1111 if (ret) 1112 return ret; 1113 if (!driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete) 1114 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; 1115 } else { 1116 dpm_table->count = 1; 1117 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1118 dpm_table->dpm_levels[0].enabled = true; 1119 } 1120 1121 return 0; 1122 } 1123 1124 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, 1125 bool enable, 1126 int inst) 1127 { 1128 int ret = 0; 1129 1130 if (enable) { 1131 /* vcn dpm on is a prerequisite for vcn power gate messages */ 1132 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1133 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL); 1134 if (ret) 1135 return ret; 1136 } 1137 } else { 1138 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1139 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 1140 if (ret) 1141 return ret; 1142 } 1143 } 1144 1145 return ret; 1146 } 1147 1148 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 1149 { 1150 int ret = 0; 1151 1152 if (enable) { 1153 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1154 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL); 1155 if (ret) 1156 return ret; 1157 } 1158 } else { 1159 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1160 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL); 1161 if (ret) 1162 return ret; 1163 } 1164 } 1165 1166 return ret; 1167 } 1168 1169 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, 1170 enum smu_clk_type clk_type, 1171 uint32_t *value) 1172 { 1173 MetricsMember_t member_type; 1174 int clk_id = 0; 1175 1176 clk_id = smu_cmn_to_asic_specific_index(smu, 1177 CMN2ASIC_MAPPING_CLK, 1178 clk_type); 1179 if (clk_id < 0) 1180 return clk_id; 1181 1182 switch (clk_id) { 1183 case PPCLK_GFXCLK: 1184 member_type = METRICS_CURR_GFXCLK; 1185 break; 1186 case PPCLK_UCLK: 1187 member_type = METRICS_CURR_UCLK; 1188 break; 1189 case PPCLK_SOCCLK: 1190 member_type = METRICS_CURR_SOCCLK; 1191 break; 1192 case PPCLK_VCLK: 1193 member_type = METRICS_CURR_VCLK; 1194 break; 1195 case PPCLK_DCLK: 1196 member_type = METRICS_CURR_DCLK; 1197 break; 1198 case PPCLK_DCEFCLK: 1199 member_type = METRICS_CURR_DCEFCLK; 1200 break; 1201 default: 1202 return -EINVAL; 1203 } 1204 1205 return navi1x_get_smu_metrics_data(smu, 1206 member_type, 1207 value); 1208 } 1209 1210 static int navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1211 { 1212 PPTable_t *pptable = smu->smu_table.driver_pptable; 1213 DpmDescriptor_t *dpm_desc = NULL; 1214 int clk_index = 0; 1215 1216 clk_index = smu_cmn_to_asic_specific_index(smu, 1217 CMN2ASIC_MAPPING_CLK, 1218 clk_type); 1219 if (clk_index < 0) 1220 return clk_index; 1221 1222 dpm_desc = &pptable->DpmDescriptor[clk_index]; 1223 1224 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1225 return dpm_desc->SnapToDiscrete == 0 ? 1 : 0; 1226 } 1227 1228 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) 1229 { 1230 return od_table->cap[cap]; 1231 } 1232 1233 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, 1234 enum SMU_11_0_ODSETTING_ID setting, 1235 uint32_t *min, uint32_t *max) 1236 { 1237 if (min) 1238 *min = od_table->min[setting]; 1239 if (max) 1240 *max = od_table->max[setting]; 1241 } 1242 1243 static int navi10_emit_clk_levels(struct smu_context *smu, 1244 enum smu_clk_type clk_type, 1245 char *buf, 1246 int *offset) 1247 { 1248 uint16_t *curve_settings; 1249 int ret = 0; 1250 uint32_t cur_value = 0; 1251 uint32_t i; 1252 struct smu_table_context *table_context = &smu->smu_table; 1253 uint32_t gen_speed, lane_width; 1254 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1255 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1256 OverDriveTable_t *od_table = 1257 (OverDriveTable_t *)table_context->overdrive_table; 1258 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1259 struct smu_dpm_table *single_dpm_table = NULL; 1260 struct smu_pcie_table *pcie_table; 1261 uint32_t min_value, max_value; 1262 1263 switch (clk_type) { 1264 case SMU_GFXCLK: 1265 case SMU_SCLK: 1266 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1267 break; 1268 /* FCLK and SOC CLK mapped to SOCCLK in clock map table */ 1269 case SMU_SOCCLK: 1270 case SMU_FCLK: 1271 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1272 break; 1273 case SMU_MCLK: 1274 case SMU_UCLK: 1275 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1276 break; 1277 case SMU_VCLK: 1278 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1279 break; 1280 case SMU_DCLK: 1281 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1282 break; 1283 case SMU_DCEFCLK: 1284 single_dpm_table = &(dpm_context->dpm_tables.dcef_table); 1285 break; 1286 case SMU_PCIE: 1287 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1288 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1289 pcie_table = &dpm_context->dpm_tables.pcie_table; 1290 return smu_cmn_print_pcie_levels(smu, pcie_table, gen_speed, 1291 lane_width, buf, offset); 1292 case SMU_OD_SCLK: 1293 if (!smu->od_enabled || !od_table || !od_settings) 1294 return -EOPNOTSUPP; 1295 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1296 break; 1297 *offset += sysfs_emit_at(buf, *offset, "OD_SCLK:\n0: %uMhz\n1: %uMhz\n", 1298 od_table->GfxclkFmin, od_table->GfxclkFmax); 1299 break; 1300 case SMU_OD_MCLK: 1301 if (!smu->od_enabled || !od_table || !od_settings) 1302 return -EOPNOTSUPP; 1303 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1304 break; 1305 *offset += sysfs_emit_at(buf, *offset, "OD_MCLK:\n1: %uMHz\n", od_table->UclkFmax); 1306 break; 1307 case SMU_OD_VDDC_CURVE: 1308 if (!smu->od_enabled || !od_table || !od_settings) 1309 return -EOPNOTSUPP; 1310 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1311 break; 1312 *offset += sysfs_emit_at(buf, *offset, "OD_VDDC_CURVE:\n"); 1313 for (i = 0; i < 3; i++) { 1314 switch (i) { 1315 case 0: 1316 curve_settings = &od_table->GfxclkFreq1; 1317 break; 1318 case 1: 1319 curve_settings = &od_table->GfxclkFreq2; 1320 break; 1321 case 2: 1322 curve_settings = &od_table->GfxclkFreq3; 1323 break; 1324 } 1325 *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n", 1326 i, curve_settings[0], 1327 curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1328 } 1329 break; 1330 case SMU_OD_RANGE: 1331 if (!smu->od_enabled || !od_table || !od_settings) 1332 return -EOPNOTSUPP; 1333 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE"); 1334 1335 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1336 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1337 &min_value, NULL); 1338 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1339 NULL, &max_value); 1340 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMhz %10uMhz\n", 1341 min_value, max_value); 1342 } 1343 1344 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1345 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1346 &min_value, &max_value); 1347 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMhz %10uMhz\n", 1348 min_value, max_value); 1349 } 1350 1351 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1352 navi10_od_setting_get_range(od_settings, 1353 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1354 &min_value, &max_value); 1355 *offset += sysfs_emit_at(buf, *offset, 1356 "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1357 min_value, max_value); 1358 navi10_od_setting_get_range(od_settings, 1359 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1360 &min_value, &max_value); 1361 *offset += sysfs_emit_at(buf, *offset, 1362 "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1363 min_value, max_value); 1364 navi10_od_setting_get_range(od_settings, 1365 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1366 &min_value, &max_value); 1367 *offset += sysfs_emit_at(buf, *offset, 1368 "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1369 min_value, max_value); 1370 navi10_od_setting_get_range(od_settings, 1371 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1372 &min_value, &max_value); 1373 *offset += sysfs_emit_at(buf, *offset, 1374 "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1375 min_value, max_value); 1376 navi10_od_setting_get_range(od_settings, 1377 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1378 &min_value, &max_value); 1379 *offset += sysfs_emit_at(buf, *offset, 1380 "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1381 min_value, max_value); 1382 navi10_od_setting_get_range(od_settings, 1383 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1384 &min_value, &max_value); 1385 *offset += sysfs_emit_at(buf, *offset, 1386 "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1387 min_value, max_value); 1388 } 1389 1390 break; 1391 default: 1392 break; 1393 } 1394 1395 if (single_dpm_table) { 1396 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, 1397 &cur_value); 1398 if (ret) 1399 return ret; 1400 return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, 1401 cur_value, buf, offset); 1402 } 1403 1404 return 0; 1405 } 1406 1407 static int navi10_force_clk_levels(struct smu_context *smu, 1408 enum smu_clk_type clk_type, uint32_t mask) 1409 { 1410 1411 int ret = 0; 1412 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1413 1414 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1415 soft_max_level = mask ? (fls(mask) - 1) : 0; 1416 1417 switch (clk_type) { 1418 case SMU_GFXCLK: 1419 case SMU_SCLK: 1420 case SMU_SOCCLK: 1421 case SMU_MCLK: 1422 case SMU_UCLK: 1423 case SMU_FCLK: 1424 /* There is only 2 levels for fine grained DPM */ 1425 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); 1426 if (ret < 0) 1427 return ret; 1428 1429 if (ret) { 1430 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1431 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1432 } 1433 1434 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1435 if (ret) 1436 return 0; 1437 1438 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1439 if (ret) 1440 return 0; 1441 1442 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false); 1443 if (ret) 1444 return 0; 1445 break; 1446 case SMU_DCEFCLK: 1447 dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not supported!\n"); 1448 break; 1449 1450 default: 1451 break; 1452 } 1453 1454 return 0; 1455 } 1456 1457 static int navi10_populate_umd_state_clk(struct smu_context *smu) 1458 { 1459 struct smu_11_0_dpm_context *dpm_context = 1460 smu->smu_dpm.dpm_context; 1461 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; 1462 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; 1463 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; 1464 struct smu_umd_pstate_table *pstate_table = 1465 &smu->pstate_table; 1466 struct amdgpu_device *adev = smu->adev; 1467 uint32_t sclk_freq; 1468 1469 pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table); 1470 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1471 case IP_VERSION(11, 0, 0): 1472 switch (adev->pdev->revision) { 1473 case 0xf0: /* XTX */ 1474 case 0xc0: 1475 sclk_freq = NAVI10_PEAK_SCLK_XTX; 1476 break; 1477 case 0xf1: /* XT */ 1478 case 0xc1: 1479 sclk_freq = NAVI10_PEAK_SCLK_XT; 1480 break; 1481 default: /* XL */ 1482 sclk_freq = NAVI10_PEAK_SCLK_XL; 1483 break; 1484 } 1485 break; 1486 case IP_VERSION(11, 0, 5): 1487 switch (adev->pdev->revision) { 1488 case 0xc7: /* XT */ 1489 case 0xf4: 1490 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK; 1491 break; 1492 case 0xc1: /* XTM */ 1493 case 0xf2: 1494 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK; 1495 break; 1496 case 0xc3: /* XLM */ 1497 case 0xf3: 1498 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1499 break; 1500 case 0xc5: /* XTX */ 1501 case 0xf6: 1502 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1503 break; 1504 default: /* XL */ 1505 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK; 1506 break; 1507 } 1508 break; 1509 case IP_VERSION(11, 0, 9): 1510 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK; 1511 break; 1512 default: 1513 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value; 1514 break; 1515 } 1516 pstate_table->gfxclk_pstate.peak = sclk_freq; 1517 1518 pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table); 1519 pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table); 1520 1521 pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table); 1522 pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table); 1523 1524 if (SMU_DPM_TABLE_MAX(gfx_table) > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && 1525 SMU_DPM_TABLE_MAX(mem_table) > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && 1526 SMU_DPM_TABLE_MAX(soc_table) > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) { 1527 pstate_table->gfxclk_pstate.standard = 1528 NAVI10_UMD_PSTATE_PROFILING_GFXCLK; 1529 pstate_table->uclk_pstate.standard = 1530 NAVI10_UMD_PSTATE_PROFILING_MEMCLK; 1531 pstate_table->socclk_pstate.standard = 1532 NAVI10_UMD_PSTATE_PROFILING_SOCCLK; 1533 } else { 1534 pstate_table->gfxclk_pstate.standard = 1535 pstate_table->gfxclk_pstate.min; 1536 pstate_table->uclk_pstate.standard = 1537 pstate_table->uclk_pstate.min; 1538 pstate_table->socclk_pstate.standard = 1539 pstate_table->socclk_pstate.min; 1540 } 1541 1542 return 0; 1543 } 1544 1545 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu, 1546 enum smu_clk_type clk_type, 1547 struct pp_clock_levels_with_latency *clocks) 1548 { 1549 int ret = 0, i = 0; 1550 uint32_t level_count = 0, freq = 0; 1551 1552 switch (clk_type) { 1553 case SMU_GFXCLK: 1554 case SMU_DCEFCLK: 1555 case SMU_SOCCLK: 1556 case SMU_MCLK: 1557 case SMU_UCLK: 1558 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count); 1559 if (ret) 1560 return ret; 1561 1562 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS); 1563 clocks->num_levels = level_count; 1564 1565 for (i = 0; i < level_count; i++) { 1566 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq); 1567 if (ret) 1568 return ret; 1569 1570 clocks->data[i].clocks_in_khz = freq * 1000; 1571 clocks->data[i].latency_in_us = 0; 1572 } 1573 break; 1574 default: 1575 break; 1576 } 1577 1578 return ret; 1579 } 1580 1581 static int navi10_pre_display_config_changed(struct smu_context *smu) 1582 { 1583 int ret = 0; 1584 uint32_t max_freq = 0; 1585 1586 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1587 if (ret) 1588 return ret; 1589 1590 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1591 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1592 if (ret) 1593 return ret; 1594 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1595 if (ret) 1596 return ret; 1597 } 1598 1599 return ret; 1600 } 1601 1602 static int navi10_display_config_changed(struct smu_context *smu) 1603 { 1604 int ret = 0; 1605 1606 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1607 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1608 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1609 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1610 smu->display_config->num_display, 1611 NULL); 1612 if (ret) 1613 return ret; 1614 } 1615 1616 return ret; 1617 } 1618 1619 static bool navi10_is_dpm_running(struct smu_context *smu) 1620 { 1621 int ret = 0; 1622 uint64_t feature_enabled; 1623 1624 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1625 if (ret) 1626 return false; 1627 1628 return !!(feature_enabled & SMC_DPM_FEATURE); 1629 } 1630 1631 static int navi10_get_fan_speed_rpm(struct smu_context *smu, 1632 uint32_t *speed) 1633 { 1634 int ret = 0; 1635 1636 if (!speed) 1637 return -EINVAL; 1638 1639 switch (smu_v11_0_get_fan_control_mode(smu)) { 1640 case AMD_FAN_CTRL_AUTO: 1641 ret = navi10_get_smu_metrics_data(smu, 1642 METRICS_CURR_FANSPEED, 1643 speed); 1644 break; 1645 default: 1646 ret = smu_v11_0_get_fan_speed_rpm(smu, 1647 speed); 1648 break; 1649 } 1650 1651 return ret; 1652 } 1653 1654 static int navi10_get_fan_parameters(struct smu_context *smu) 1655 { 1656 PPTable_t *pptable = smu->smu_table.driver_pptable; 1657 1658 smu->fan_max_rpm = pptable->FanMaximumRpm; 1659 1660 return 0; 1661 } 1662 1663 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf) 1664 { 1665 DpmActivityMonitorCoeffInt_t activity_monitor; 1666 uint32_t i, size = 0; 1667 int16_t workload_type = 0; 1668 static const char *title[] = { 1669 "PROFILE_INDEX(NAME)", 1670 "CLOCK_TYPE(NAME)", 1671 "FPS", 1672 "MinFreqType", 1673 "MinActiveFreqType", 1674 "MinActiveFreq", 1675 "BoosterFreqType", 1676 "BoosterFreq", 1677 "PD_Data_limit_c", 1678 "PD_Data_error_coeff", 1679 "PD_Data_error_rate_coeff"}; 1680 int result = 0; 1681 1682 if (!buf) 1683 return -EINVAL; 1684 1685 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1686 title[0], title[1], title[2], title[3], title[4], title[5], 1687 title[6], title[7], title[8], title[9], title[10]); 1688 1689 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1690 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1691 workload_type = smu_cmn_to_asic_specific_index(smu, 1692 CMN2ASIC_MAPPING_WORKLOAD, 1693 i); 1694 if (workload_type < 0) 1695 return -EINVAL; 1696 1697 result = smu_cmn_update_table(smu, 1698 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1699 (void *)(&activity_monitor), false); 1700 if (result) { 1701 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1702 return result; 1703 } 1704 1705 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1706 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1707 1708 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1709 " ", 1710 0, 1711 "GFXCLK", 1712 activity_monitor.Gfx_FPS, 1713 activity_monitor.Gfx_MinFreqStep, 1714 activity_monitor.Gfx_MinActiveFreqType, 1715 activity_monitor.Gfx_MinActiveFreq, 1716 activity_monitor.Gfx_BoosterFreqType, 1717 activity_monitor.Gfx_BoosterFreq, 1718 activity_monitor.Gfx_PD_Data_limit_c, 1719 activity_monitor.Gfx_PD_Data_error_coeff, 1720 activity_monitor.Gfx_PD_Data_error_rate_coeff); 1721 1722 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1723 " ", 1724 1, 1725 "SOCCLK", 1726 activity_monitor.Soc_FPS, 1727 activity_monitor.Soc_MinFreqStep, 1728 activity_monitor.Soc_MinActiveFreqType, 1729 activity_monitor.Soc_MinActiveFreq, 1730 activity_monitor.Soc_BoosterFreqType, 1731 activity_monitor.Soc_BoosterFreq, 1732 activity_monitor.Soc_PD_Data_limit_c, 1733 activity_monitor.Soc_PD_Data_error_coeff, 1734 activity_monitor.Soc_PD_Data_error_rate_coeff); 1735 1736 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1737 " ", 1738 2, 1739 "MEMCLK", 1740 activity_monitor.Mem_FPS, 1741 activity_monitor.Mem_MinFreqStep, 1742 activity_monitor.Mem_MinActiveFreqType, 1743 activity_monitor.Mem_MinActiveFreq, 1744 activity_monitor.Mem_BoosterFreqType, 1745 activity_monitor.Mem_BoosterFreq, 1746 activity_monitor.Mem_PD_Data_limit_c, 1747 activity_monitor.Mem_PD_Data_error_coeff, 1748 activity_monitor.Mem_PD_Data_error_rate_coeff); 1749 } 1750 1751 return size; 1752 } 1753 1754 #define NAVI10_CUSTOM_PARAMS_COUNT 10 1755 #define NAVI10_CUSTOM_PARAMS_CLOCKS_COUNT 3 1756 #define NAVI10_CUSTOM_PARAMS_SIZE (NAVI10_CUSTOM_PARAMS_CLOCKS_COUNT * NAVI10_CUSTOM_PARAMS_COUNT * sizeof(long)) 1757 1758 static int navi10_set_power_profile_mode_coeff(struct smu_context *smu, 1759 long *input) 1760 { 1761 DpmActivityMonitorCoeffInt_t activity_monitor; 1762 int ret, idx; 1763 1764 ret = smu_cmn_update_table(smu, 1765 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1766 (void *)(&activity_monitor), false); 1767 if (ret) { 1768 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1769 return ret; 1770 } 1771 1772 idx = 0 * NAVI10_CUSTOM_PARAMS_COUNT; 1773 if (input[idx]) { 1774 /* Gfxclk */ 1775 activity_monitor.Gfx_FPS = input[idx + 1]; 1776 activity_monitor.Gfx_MinFreqStep = input[idx + 2]; 1777 activity_monitor.Gfx_MinActiveFreqType = input[idx + 3]; 1778 activity_monitor.Gfx_MinActiveFreq = input[idx + 4]; 1779 activity_monitor.Gfx_BoosterFreqType = input[idx + 5]; 1780 activity_monitor.Gfx_BoosterFreq = input[idx + 6]; 1781 activity_monitor.Gfx_PD_Data_limit_c = input[idx + 7]; 1782 activity_monitor.Gfx_PD_Data_error_coeff = input[idx + 8]; 1783 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[idx + 9]; 1784 } 1785 idx = 1 * NAVI10_CUSTOM_PARAMS_COUNT; 1786 if (input[idx]) { 1787 /* Socclk */ 1788 activity_monitor.Soc_FPS = input[idx + 1]; 1789 activity_monitor.Soc_MinFreqStep = input[idx + 2]; 1790 activity_monitor.Soc_MinActiveFreqType = input[idx + 3]; 1791 activity_monitor.Soc_MinActiveFreq = input[idx + 4]; 1792 activity_monitor.Soc_BoosterFreqType = input[idx + 5]; 1793 activity_monitor.Soc_BoosterFreq = input[idx + 6]; 1794 activity_monitor.Soc_PD_Data_limit_c = input[idx + 7]; 1795 activity_monitor.Soc_PD_Data_error_coeff = input[idx + 8]; 1796 activity_monitor.Soc_PD_Data_error_rate_coeff = input[idx + 9]; 1797 } 1798 idx = 2 * NAVI10_CUSTOM_PARAMS_COUNT; 1799 if (input[idx]) { 1800 /* Memclk */ 1801 activity_monitor.Mem_FPS = input[idx + 1]; 1802 activity_monitor.Mem_MinFreqStep = input[idx + 2]; 1803 activity_monitor.Mem_MinActiveFreqType = input[idx + 3]; 1804 activity_monitor.Mem_MinActiveFreq = input[idx + 4]; 1805 activity_monitor.Mem_BoosterFreqType = input[idx + 5]; 1806 activity_monitor.Mem_BoosterFreq = input[idx + 6]; 1807 activity_monitor.Mem_PD_Data_limit_c = input[idx + 7]; 1808 activity_monitor.Mem_PD_Data_error_coeff = input[idx + 8]; 1809 activity_monitor.Mem_PD_Data_error_rate_coeff = input[idx + 9]; 1810 } 1811 1812 ret = smu_cmn_update_table(smu, 1813 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1814 (void *)(&activity_monitor), true); 1815 if (ret) { 1816 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1817 return ret; 1818 } 1819 1820 return ret; 1821 } 1822 1823 static int navi10_set_power_profile_mode(struct smu_context *smu, 1824 u32 workload_mask, 1825 long *custom_params, 1826 u32 custom_params_max_idx) 1827 { 1828 u32 backend_workload_mask = 0; 1829 int ret, idx = -1, i; 1830 1831 smu_cmn_get_backend_workload_mask(smu, workload_mask, 1832 &backend_workload_mask); 1833 1834 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) { 1835 if (!smu->custom_profile_params) { 1836 smu->custom_profile_params = kzalloc(NAVI10_CUSTOM_PARAMS_SIZE, GFP_KERNEL); 1837 if (!smu->custom_profile_params) 1838 return -ENOMEM; 1839 } 1840 if (custom_params && custom_params_max_idx) { 1841 if (custom_params_max_idx != NAVI10_CUSTOM_PARAMS_COUNT) 1842 return -EINVAL; 1843 if (custom_params[0] >= NAVI10_CUSTOM_PARAMS_CLOCKS_COUNT) 1844 return -EINVAL; 1845 idx = custom_params[0] * NAVI10_CUSTOM_PARAMS_COUNT; 1846 smu->custom_profile_params[idx] = 1; 1847 for (i = 1; i < custom_params_max_idx; i++) 1848 smu->custom_profile_params[idx + i] = custom_params[i]; 1849 } 1850 ret = navi10_set_power_profile_mode_coeff(smu, 1851 smu->custom_profile_params); 1852 if (ret) { 1853 if (idx != -1) 1854 smu->custom_profile_params[idx] = 0; 1855 return ret; 1856 } 1857 } else if (smu->custom_profile_params) { 1858 memset(smu->custom_profile_params, 0, NAVI10_CUSTOM_PARAMS_SIZE); 1859 } 1860 1861 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1862 backend_workload_mask, NULL); 1863 if (ret) { 1864 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n", 1865 workload_mask); 1866 if (idx != -1) 1867 smu->custom_profile_params[idx] = 0; 1868 return ret; 1869 } 1870 1871 return ret; 1872 } 1873 1874 static int navi10_notify_smc_display_config(struct smu_context *smu) 1875 { 1876 struct smu_clocks min_clocks = {0}; 1877 struct pp_display_clock_request clock_req; 1878 int ret = 0; 1879 1880 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 1881 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 1882 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1883 1884 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1885 clock_req.clock_type = amd_pp_dcef_clock; 1886 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 1887 1888 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 1889 if (!ret) { 1890 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 1891 ret = smu_cmn_send_smc_msg_with_param(smu, 1892 SMU_MSG_SetMinDeepSleepDcefclk, 1893 min_clocks.dcef_clock_in_sr/100, 1894 NULL); 1895 if (ret) { 1896 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 1897 return ret; 1898 } 1899 } 1900 } else { 1901 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 1902 } 1903 } 1904 1905 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1906 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 1907 if (ret) { 1908 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 1909 return ret; 1910 } 1911 } 1912 1913 return 0; 1914 } 1915 1916 static int navi10_set_watermarks_table(struct smu_context *smu, 1917 struct pp_smu_wm_range_sets *clock_ranges) 1918 { 1919 Watermarks_t *table = smu->smu_table.watermarks_table; 1920 int ret = 0; 1921 int i; 1922 1923 if (clock_ranges) { 1924 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1925 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1926 return -EINVAL; 1927 1928 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1929 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 1930 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1931 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 1932 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1933 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 1934 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1935 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 1936 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1937 1938 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 1939 clock_ranges->reader_wm_sets[i].wm_inst; 1940 } 1941 1942 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1943 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1944 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1945 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1946 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1947 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 1948 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1949 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 1950 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1951 1952 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1953 clock_ranges->writer_wm_sets[i].wm_inst; 1954 } 1955 1956 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1957 } 1958 1959 /* pass data to smu controller */ 1960 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1961 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1962 ret = smu_cmn_write_watermarks_table(smu); 1963 if (ret) { 1964 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1965 return ret; 1966 } 1967 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1968 } 1969 1970 return 0; 1971 } 1972 1973 static int navi10_read_sensor(struct smu_context *smu, 1974 enum amd_pp_sensors sensor, 1975 void *data, uint32_t *size) 1976 { 1977 int ret = 0; 1978 struct smu_table_context *table_context = &smu->smu_table; 1979 PPTable_t *pptable = table_context->driver_pptable; 1980 1981 if (!data || !size) 1982 return -EINVAL; 1983 1984 switch (sensor) { 1985 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1986 *(uint32_t *)data = pptable->FanMaximumRpm; 1987 *size = 4; 1988 break; 1989 case AMDGPU_PP_SENSOR_MEM_LOAD: 1990 ret = navi1x_get_smu_metrics_data(smu, 1991 METRICS_AVERAGE_MEMACTIVITY, 1992 (uint32_t *)data); 1993 *size = 4; 1994 break; 1995 case AMDGPU_PP_SENSOR_GPU_LOAD: 1996 ret = navi1x_get_smu_metrics_data(smu, 1997 METRICS_AVERAGE_GFXACTIVITY, 1998 (uint32_t *)data); 1999 *size = 4; 2000 break; 2001 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 2002 ret = navi1x_get_smu_metrics_data(smu, 2003 METRICS_AVERAGE_SOCKETPOWER, 2004 (uint32_t *)data); 2005 *size = 4; 2006 break; 2007 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 2008 ret = navi1x_get_smu_metrics_data(smu, 2009 METRICS_TEMPERATURE_HOTSPOT, 2010 (uint32_t *)data); 2011 *size = 4; 2012 break; 2013 case AMDGPU_PP_SENSOR_EDGE_TEMP: 2014 ret = navi1x_get_smu_metrics_data(smu, 2015 METRICS_TEMPERATURE_EDGE, 2016 (uint32_t *)data); 2017 *size = 4; 2018 break; 2019 case AMDGPU_PP_SENSOR_MEM_TEMP: 2020 ret = navi1x_get_smu_metrics_data(smu, 2021 METRICS_TEMPERATURE_MEM, 2022 (uint32_t *)data); 2023 *size = 4; 2024 break; 2025 case AMDGPU_PP_SENSOR_GFX_MCLK: 2026 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 2027 *(uint32_t *)data *= 100; 2028 *size = 4; 2029 break; 2030 case AMDGPU_PP_SENSOR_GFX_SCLK: 2031 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); 2032 *(uint32_t *)data *= 100; 2033 *size = 4; 2034 break; 2035 case AMDGPU_PP_SENSOR_VDDGFX: 2036 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 2037 *size = 4; 2038 break; 2039 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 2040 default: 2041 ret = -EOPNOTSUPP; 2042 break; 2043 } 2044 2045 return ret; 2046 } 2047 2048 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 2049 { 2050 uint32_t num_discrete_levels = 0; 2051 uint16_t *dpm_levels = NULL; 2052 uint16_t i = 0; 2053 struct smu_table_context *table_context = &smu->smu_table; 2054 PPTable_t *driver_ppt = NULL; 2055 2056 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 2057 return -EINVAL; 2058 2059 driver_ppt = table_context->driver_pptable; 2060 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; 2061 dpm_levels = driver_ppt->FreqTableUclk; 2062 2063 if (num_discrete_levels == 0 || dpm_levels == NULL) 2064 return -EINVAL; 2065 2066 *num_states = num_discrete_levels; 2067 for (i = 0; i < num_discrete_levels; i++) { 2068 /* convert to khz */ 2069 *clocks_in_khz = (*dpm_levels) * 1000; 2070 clocks_in_khz++; 2071 dpm_levels++; 2072 } 2073 2074 return 0; 2075 } 2076 2077 static int navi10_get_thermal_temperature_range(struct smu_context *smu, 2078 struct smu_temperature_range *range) 2079 { 2080 struct smu_table_context *table_context = &smu->smu_table; 2081 struct smu_11_0_powerplay_table *powerplay_table = 2082 table_context->power_play_table; 2083 PPTable_t *pptable = smu->smu_table.driver_pptable; 2084 2085 if (!range) 2086 return -EINVAL; 2087 2088 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 2089 2090 range->max = pptable->TedgeLimit * 2091 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2092 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * 2093 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2094 range->hotspot_crit_max = pptable->ThotspotLimit * 2095 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2096 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 2097 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2098 range->mem_crit_max = pptable->TmemLimit * 2099 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2100 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 2101 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2102 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2103 2104 return 0; 2105 } 2106 2107 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu, 2108 bool disable_memory_clock_switch) 2109 { 2110 int ret = 0; 2111 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 2112 (struct smu_11_0_max_sustainable_clocks *) 2113 smu->smu_table.max_sustainable_clocks; 2114 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 2115 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 2116 2117 if (smu->disable_uclk_switch == disable_memory_clock_switch) 2118 return 0; 2119 2120 if (disable_memory_clock_switch) 2121 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 2122 else 2123 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 2124 2125 if (!ret) 2126 smu->disable_uclk_switch = disable_memory_clock_switch; 2127 2128 return ret; 2129 } 2130 2131 static int navi10_get_power_limit(struct smu_context *smu, 2132 uint32_t *current_power_limit, 2133 uint32_t *default_power_limit, 2134 uint32_t *max_power_limit, 2135 uint32_t *min_power_limit) 2136 { 2137 struct smu_11_0_powerplay_table *powerplay_table = 2138 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; 2139 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 2140 PPTable_t *pptable = smu->smu_table.driver_pptable; 2141 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0; 2142 2143 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 2144 /* the last hope to figure out the ppt limit */ 2145 if (!pptable) { 2146 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 2147 return -EINVAL; 2148 } 2149 power_limit = 2150 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 2151 } 2152 2153 if (current_power_limit) 2154 *current_power_limit = power_limit; 2155 if (default_power_limit) 2156 *default_power_limit = power_limit; 2157 2158 if (powerplay_table) { 2159 if (smu->od_enabled && 2160 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { 2161 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2162 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2163 } else if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { 2164 od_percent_upper = 0; 2165 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2166 } 2167 } 2168 2169 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n", 2170 od_percent_upper, od_percent_lower, power_limit); 2171 2172 if (max_power_limit) { 2173 *max_power_limit = power_limit * (100 + od_percent_upper); 2174 *max_power_limit /= 100; 2175 } 2176 2177 if (min_power_limit) { 2178 *min_power_limit = power_limit * (100 - od_percent_lower); 2179 *min_power_limit /= 100; 2180 } 2181 2182 return 0; 2183 } 2184 2185 static int navi10_update_pcie_parameters(struct smu_context *smu, 2186 uint8_t pcie_gen_cap, 2187 uint8_t pcie_width_cap) 2188 { 2189 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 2190 PPTable_t *pptable = smu->smu_table.driver_pptable; 2191 uint32_t smu_pcie_arg; 2192 int ret = 0; 2193 int i; 2194 2195 /* lclk dpm table setup */ 2196 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2197 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; 2198 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; 2199 dpm_context->dpm_tables.pcie_table.lclk_freq[i] = 2200 pptable->LclkFreq[i]; 2201 } 2202 dpm_context->dpm_tables.pcie_table.lclk_levels = NUM_LINK_LEVELS; 2203 2204 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2205 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = 2206 pptable->PcieGenSpeed[i] > pcie_gen_cap ? 2207 pcie_gen_cap : pptable->PcieGenSpeed[i]; 2208 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = 2209 pptable->PcieLaneCount[i] > pcie_width_cap ? 2210 pcie_width_cap : pptable->PcieLaneCount[i]; 2211 smu_pcie_arg = i << 16; 2212 smu_pcie_arg |= dpm_context->dpm_tables.pcie_table.pcie_gen[i] << 8; 2213 smu_pcie_arg |= dpm_context->dpm_tables.pcie_table.pcie_lane[i]; 2214 ret = smu_cmn_send_smc_msg_with_param(smu, 2215 SMU_MSG_OverridePcieParameters, 2216 smu_pcie_arg, 2217 NULL); 2218 if (ret) 2219 return ret; 2220 } 2221 2222 return ret; 2223 } 2224 2225 static inline void navi10_dump_od_table(struct smu_context *smu, 2226 OverDriveTable_t *od_table) 2227 { 2228 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 2229 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1); 2230 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2); 2231 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3); 2232 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax); 2233 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct); 2234 } 2235 2236 static int navi10_od_setting_check_range(struct smu_context *smu, 2237 struct smu_11_0_overdrive_table *od_table, 2238 enum SMU_11_0_ODSETTING_ID setting, 2239 uint32_t value) 2240 { 2241 if (value < od_table->min[setting]) { 2242 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]); 2243 return -EINVAL; 2244 } 2245 if (value > od_table->max[setting]) { 2246 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]); 2247 return -EINVAL; 2248 } 2249 return 0; 2250 } 2251 2252 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, 2253 uint16_t *voltage, 2254 uint32_t freq) 2255 { 2256 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16); 2257 uint32_t value = 0; 2258 int ret; 2259 2260 ret = smu_cmn_send_smc_msg_with_param(smu, 2261 SMU_MSG_GetVoltageByDpm, 2262 param, 2263 &value); 2264 if (ret) { 2265 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!"); 2266 return ret; 2267 } 2268 2269 *voltage = (uint16_t)value; 2270 2271 return 0; 2272 } 2273 2274 static int navi10_baco_enter(struct smu_context *smu) 2275 { 2276 struct amdgpu_device *adev = smu->adev; 2277 2278 /* 2279 * This aims the case below: 2280 * amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded 2281 * 2282 * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To 2283 * make that possible, PMFW needs to acknowledge the dstate transition 2284 * process for both gfx(function 0) and audio(function 1) function of 2285 * the ASIC. 2286 * 2287 * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the 2288 * device representing the audio function of the ASIC. And that means 2289 * even if the sound driver(snd_hda_intel) was not loaded yet, it's still 2290 * possible runpm suspend kicked on the ASIC. However without the dstate 2291 * transition notification from audio function, pmfw cannot handle the 2292 * BACO in/exit correctly. And that will cause driver hang on runpm 2293 * resuming. 2294 * 2295 * To address this, we revert to legacy message way(driver masters the 2296 * timing for BACO in/exit) on sound driver missing. 2297 */ 2298 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2299 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2300 else 2301 return smu_v11_0_baco_enter(smu); 2302 } 2303 2304 static int navi10_baco_exit(struct smu_context *smu) 2305 { 2306 struct amdgpu_device *adev = smu->adev; 2307 2308 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2309 /* Wait for PMFW handling for the Dstate change */ 2310 msleep(10); 2311 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2312 } else { 2313 return smu_v11_0_baco_exit(smu); 2314 } 2315 } 2316 2317 static int navi10_set_default_od_settings(struct smu_context *smu) 2318 { 2319 OverDriveTable_t *od_table = 2320 (OverDriveTable_t *)smu->smu_table.overdrive_table; 2321 OverDriveTable_t *boot_od_table = 2322 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 2323 OverDriveTable_t *user_od_table = 2324 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 2325 int ret = 0; 2326 2327 /* 2328 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as 2329 * - either they already have the default OD settings got during cold bootup 2330 * - or they have some user customized OD settings which cannot be overwritten 2331 */ 2332 if (smu->adev->in_suspend) 2333 return 0; 2334 2335 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false); 2336 if (ret) { 2337 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 2338 return ret; 2339 } 2340 2341 if (!boot_od_table->GfxclkVolt1) { 2342 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2343 &boot_od_table->GfxclkVolt1, 2344 boot_od_table->GfxclkFreq1); 2345 if (ret) 2346 return ret; 2347 } 2348 2349 if (!boot_od_table->GfxclkVolt2) { 2350 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2351 &boot_od_table->GfxclkVolt2, 2352 boot_od_table->GfxclkFreq2); 2353 if (ret) 2354 return ret; 2355 } 2356 2357 if (!boot_od_table->GfxclkVolt3) { 2358 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2359 &boot_od_table->GfxclkVolt3, 2360 boot_od_table->GfxclkFreq3); 2361 if (ret) 2362 return ret; 2363 } 2364 2365 navi10_dump_od_table(smu, boot_od_table); 2366 2367 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 2368 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2369 2370 return 0; 2371 } 2372 2373 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) 2374 { 2375 int i; 2376 int ret = 0; 2377 struct smu_table_context *table_context = &smu->smu_table; 2378 OverDriveTable_t *od_table; 2379 struct smu_11_0_overdrive_table *od_settings; 2380 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting; 2381 uint16_t *freq_ptr, *voltage_ptr; 2382 od_table = (OverDriveTable_t *)table_context->overdrive_table; 2383 2384 if (!smu->od_enabled) { 2385 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2386 return -EINVAL; 2387 } 2388 2389 if (!smu->od_settings) { 2390 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2391 return -ENOENT; 2392 } 2393 2394 od_settings = smu->od_settings; 2395 2396 switch (type) { 2397 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2398 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 2399 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2400 return -ENOTSUPP; 2401 } 2402 if (!table_context->overdrive_table) { 2403 dev_err(smu->adev->dev, "Overdrive is not initialized\n"); 2404 return -EINVAL; 2405 } 2406 for (i = 0; i < size; i += 2) { 2407 if (i + 2 > size) { 2408 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2409 return -EINVAL; 2410 } 2411 switch (input[i]) { 2412 case 0: 2413 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN; 2414 freq_ptr = &od_table->GfxclkFmin; 2415 if (input[i + 1] > od_table->GfxclkFmax) { 2416 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2417 input[i + 1], 2418 od_table->GfxclkFmin); 2419 return -EINVAL; 2420 } 2421 break; 2422 case 1: 2423 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX; 2424 freq_ptr = &od_table->GfxclkFmax; 2425 if (input[i + 1] < od_table->GfxclkFmin) { 2426 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2427 input[i + 1], 2428 od_table->GfxclkFmax); 2429 return -EINVAL; 2430 } 2431 break; 2432 default: 2433 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2434 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2435 return -EINVAL; 2436 } 2437 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]); 2438 if (ret) 2439 return ret; 2440 *freq_ptr = input[i + 1]; 2441 } 2442 break; 2443 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2444 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 2445 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n"); 2446 return -ENOTSUPP; 2447 } 2448 if (size < 2) { 2449 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2450 return -EINVAL; 2451 } 2452 if (input[0] != 1) { 2453 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]); 2454 dev_info(smu->adev->dev, "Supported indices: [1:max]\n"); 2455 return -EINVAL; 2456 } 2457 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]); 2458 if (ret) 2459 return ret; 2460 od_table->UclkFmax = input[1]; 2461 break; 2462 case PP_OD_RESTORE_DEFAULT_TABLE: 2463 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2464 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2465 return -EINVAL; 2466 } 2467 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); 2468 break; 2469 case PP_OD_COMMIT_DPM_TABLE: 2470 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2471 navi10_dump_od_table(smu, od_table); 2472 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2473 if (ret) { 2474 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2475 return ret; 2476 } 2477 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2478 smu->user_dpm_profile.user_od = true; 2479 2480 if (!memcmp(table_context->user_overdrive_table, 2481 table_context->boot_overdrive_table, 2482 sizeof(OverDriveTable_t))) 2483 smu->user_dpm_profile.user_od = false; 2484 } 2485 break; 2486 case PP_OD_EDIT_VDDC_CURVE: 2487 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 2488 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n"); 2489 return -ENOTSUPP; 2490 } 2491 if (size < 3) { 2492 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2493 return -EINVAL; 2494 } 2495 if (!od_table) { 2496 dev_info(smu->adev->dev, "Overdrive is not initialized\n"); 2497 return -EINVAL; 2498 } 2499 2500 switch (input[0]) { 2501 case 0: 2502 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1; 2503 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1; 2504 freq_ptr = &od_table->GfxclkFreq1; 2505 voltage_ptr = &od_table->GfxclkVolt1; 2506 break; 2507 case 1: 2508 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2; 2509 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2; 2510 freq_ptr = &od_table->GfxclkFreq2; 2511 voltage_ptr = &od_table->GfxclkVolt2; 2512 break; 2513 case 2: 2514 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3; 2515 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3; 2516 freq_ptr = &od_table->GfxclkFreq3; 2517 voltage_ptr = &od_table->GfxclkVolt3; 2518 break; 2519 default: 2520 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]); 2521 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n"); 2522 return -EINVAL; 2523 } 2524 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]); 2525 if (ret) 2526 return ret; 2527 // Allow setting zero to disable the OverDrive VDDC curve 2528 if (input[2] != 0) { 2529 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]); 2530 if (ret) 2531 return ret; 2532 *freq_ptr = input[1]; 2533 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE; 2534 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr); 2535 } else { 2536 // If setting 0, disable all voltage curve settings 2537 od_table->GfxclkVolt1 = 0; 2538 od_table->GfxclkVolt2 = 0; 2539 od_table->GfxclkVolt3 = 0; 2540 } 2541 navi10_dump_od_table(smu, od_table); 2542 break; 2543 default: 2544 return -ENOSYS; 2545 } 2546 return ret; 2547 } 2548 2549 static int navi10_run_btc(struct smu_context *smu) 2550 { 2551 int ret = 0; 2552 2553 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL); 2554 if (ret) 2555 dev_err(smu->adev->dev, "RunBtc failed!\n"); 2556 2557 return ret; 2558 } 2559 2560 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu) 2561 { 2562 struct amdgpu_device *adev = smu->adev; 2563 2564 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2565 return false; 2566 2567 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0) || 2568 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5)) 2569 return true; 2570 2571 return false; 2572 } 2573 2574 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu) 2575 { 2576 uint32_t uclk_count, uclk_min, uclk_max; 2577 int ret = 0; 2578 2579 /* This workaround can be applied only with uclk dpm enabled */ 2580 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2581 return 0; 2582 2583 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count); 2584 if (ret) 2585 return ret; 2586 2587 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max); 2588 if (ret) 2589 return ret; 2590 2591 /* 2592 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz. 2593 * This workaround is needed only when the max uclk frequency 2594 * not greater than that. 2595 */ 2596 if (uclk_max > 0x2EE) 2597 return 0; 2598 2599 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min); 2600 if (ret) 2601 return ret; 2602 2603 /* Force UCLK out of the highest DPM */ 2604 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min); 2605 if (ret) 2606 return ret; 2607 2608 /* Revert the UCLK Hardmax */ 2609 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max); 2610 if (ret) 2611 return ret; 2612 2613 /* 2614 * In this case, SMU already disabled dummy pstate during enablement 2615 * of UCLK DPM, we have to re-enabled it. 2616 */ 2617 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL); 2618 } 2619 2620 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu) 2621 { 2622 struct smu_table_context *smu_table = &smu->smu_table; 2623 struct smu_table *dummy_read_table = 2624 &smu_table->dummy_read_1_table; 2625 char *dummy_table = dummy_read_table->cpu_addr; 2626 int ret = 0; 2627 uint32_t i; 2628 2629 for (i = 0; i < 0x40000; i += 0x1000 * 2) { 2630 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000); 2631 dummy_table += 0x1000; 2632 memcpy(dummy_table, &DbiPrbs7[0], 0x1000); 2633 dummy_table += 0x1000; 2634 } 2635 2636 amdgpu_hdp_flush(smu->adev, NULL); 2637 2638 ret = smu_cmn_send_smc_msg_with_param(smu, 2639 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, 2640 upper_32_bits(dummy_read_table->mc_address), 2641 NULL); 2642 if (ret) 2643 return ret; 2644 2645 return smu_cmn_send_smc_msg_with_param(smu, 2646 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, 2647 lower_32_bits(dummy_read_table->mc_address), 2648 NULL); 2649 } 2650 2651 static int navi10_run_umc_cdr_workaround(struct smu_context *smu) 2652 { 2653 struct amdgpu_device *adev = smu->adev; 2654 uint8_t umc_fw_greater_than_v136 = false; 2655 uint8_t umc_fw_disable_cdr = false; 2656 uint32_t param; 2657 int ret = 0; 2658 2659 if (!navi10_need_umc_cdr_workaround(smu)) 2660 return 0; 2661 2662 /* 2663 * The messages below are only supported by Navi10 42.53.0 and later 2664 * PMFWs and Navi14 53.29.0 and later PMFWs. 2665 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh 2666 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow 2667 * - PPSMC_MSG_GetUMCFWWA 2668 */ 2669 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && 2670 (smu->smc_fw_version >= 0x2a3500)) || 2671 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5)) && 2672 (smu->smc_fw_version >= 0x351D00))) { 2673 ret = smu_cmn_send_smc_msg_with_param(smu, 2674 SMU_MSG_GET_UMC_FW_WA, 2675 0, 2676 ¶m); 2677 if (ret) 2678 return ret; 2679 2680 /* First bit indicates if the UMC f/w is above v137 */ 2681 umc_fw_greater_than_v136 = param & 0x1; 2682 2683 /* Second bit indicates if hybrid-cdr is disabled */ 2684 umc_fw_disable_cdr = param & 0x2; 2685 2686 /* w/a only allowed if UMC f/w is <= 136 */ 2687 if (umc_fw_greater_than_v136) 2688 return 0; 2689 2690 if (umc_fw_disable_cdr) { 2691 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == 2692 IP_VERSION(11, 0, 0)) 2693 return navi10_umc_hybrid_cdr_workaround(smu); 2694 } else { 2695 return navi10_set_dummy_pstates_table_location(smu); 2696 } 2697 } else { 2698 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == 2699 IP_VERSION(11, 0, 0)) 2700 return navi10_umc_hybrid_cdr_workaround(smu); 2701 } 2702 2703 return 0; 2704 } 2705 2706 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, 2707 void **table) 2708 { 2709 struct smu_table_context *smu_table = &smu->smu_table; 2710 struct gpu_metrics_v1_3 *gpu_metrics = 2711 (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( 2712 smu, SMU_DRIVER_TABLE_GPU_METRICS); 2713 SmuMetrics_legacy_t metrics; 2714 int ret = 0; 2715 2716 ret = smu_cmn_get_metrics_table(smu, 2717 NULL, 2718 true); 2719 if (ret) 2720 return ret; 2721 2722 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t)); 2723 2724 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2725 2726 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2727 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2728 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2729 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2730 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2731 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2732 2733 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2734 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2735 2736 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2737 2738 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2739 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2740 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2741 2742 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2743 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2744 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2745 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2746 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2747 2748 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2749 gpu_metrics->indep_throttle_status = 2750 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 2751 navi1x_throttler_map); 2752 2753 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2754 2755 gpu_metrics->pcie_link_width = 2756 smu_v11_0_get_current_pcie_link_width(smu); 2757 gpu_metrics->pcie_link_speed = 2758 smu_v11_0_get_current_pcie_link_speed(smu); 2759 2760 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2761 2762 if (metrics.CurrGfxVoltageOffset) 2763 gpu_metrics->voltage_gfx = 2764 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 2765 if (metrics.CurrMemVidOffset) 2766 gpu_metrics->voltage_mem = 2767 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 2768 if (metrics.CurrSocVoltageOffset) 2769 gpu_metrics->voltage_soc = 2770 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 2771 2772 *table = (void *)gpu_metrics; 2773 2774 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); 2775 2776 return sizeof(struct gpu_metrics_v1_3); 2777 } 2778 2779 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap, 2780 struct i2c_msg *msg, int num_msgs) 2781 { 2782 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 2783 struct amdgpu_device *adev = smu_i2c->adev; 2784 struct smu_context *smu = adev->powerplay.pp_handle; 2785 struct smu_table_context *smu_table = &smu->smu_table; 2786 struct smu_table *table = &smu_table->driver_table; 2787 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 2788 int i, j, r, c; 2789 u16 dir; 2790 2791 if (!adev->pm.dpm_enabled) 2792 return -EBUSY; 2793 2794 req = kzalloc(sizeof(*req), GFP_KERNEL); 2795 if (!req) 2796 return -ENOMEM; 2797 2798 req->I2CcontrollerPort = smu_i2c->port; 2799 req->I2CSpeed = I2C_SPEED_FAST_400K; 2800 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 2801 dir = msg[0].flags & I2C_M_RD; 2802 2803 for (c = i = 0; i < num_msgs; i++) { 2804 for (j = 0; j < msg[i].len; j++, c++) { 2805 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 2806 2807 if (!(msg[i].flags & I2C_M_RD)) { 2808 /* write */ 2809 cmd->Cmd = I2C_CMD_WRITE; 2810 cmd->RegisterAddr = msg[i].buf[j]; 2811 } 2812 2813 if ((dir ^ msg[i].flags) & I2C_M_RD) { 2814 /* The direction changes. 2815 */ 2816 dir = msg[i].flags & I2C_M_RD; 2817 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 2818 } 2819 2820 req->NumCmds++; 2821 2822 /* 2823 * Insert STOP if we are at the last byte of either last 2824 * message for the transaction or the client explicitly 2825 * requires a STOP at this particular message. 2826 */ 2827 if ((j == msg[i].len - 1) && 2828 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 2829 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 2830 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 2831 } 2832 } 2833 } 2834 mutex_lock(&adev->pm.mutex); 2835 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 2836 if (r) 2837 goto fail; 2838 2839 for (c = i = 0; i < num_msgs; i++) { 2840 if (!(msg[i].flags & I2C_M_RD)) { 2841 c += msg[i].len; 2842 continue; 2843 } 2844 for (j = 0; j < msg[i].len; j++, c++) { 2845 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 2846 2847 msg[i].buf[j] = cmd->Data; 2848 } 2849 } 2850 r = num_msgs; 2851 fail: 2852 mutex_unlock(&adev->pm.mutex); 2853 kfree(req); 2854 return r; 2855 } 2856 2857 static u32 navi10_i2c_func(struct i2c_adapter *adap) 2858 { 2859 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 2860 } 2861 2862 2863 static const struct i2c_algorithm navi10_i2c_algo = { 2864 .master_xfer = navi10_i2c_xfer, 2865 .functionality = navi10_i2c_func, 2866 }; 2867 2868 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = { 2869 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 2870 .max_read_len = MAX_SW_I2C_COMMANDS, 2871 .max_write_len = MAX_SW_I2C_COMMANDS, 2872 .max_comb_1st_msg_len = 2, 2873 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 2874 }; 2875 2876 static int navi10_i2c_control_init(struct smu_context *smu) 2877 { 2878 struct amdgpu_device *adev = smu->adev; 2879 int res, i; 2880 2881 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2882 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2883 struct i2c_adapter *control = &smu_i2c->adapter; 2884 2885 smu_i2c->adev = adev; 2886 smu_i2c->port = i; 2887 mutex_init(&smu_i2c->mutex); 2888 control->owner = THIS_MODULE; 2889 control->class = I2C_CLASS_HWMON; 2890 control->dev.parent = &adev->pdev->dev; 2891 control->algo = &navi10_i2c_algo; 2892 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 2893 control->quirks = &navi10_i2c_control_quirks; 2894 i2c_set_adapdata(control, smu_i2c); 2895 2896 res = devm_i2c_add_adapter(adev->dev, control); 2897 if (res) { 2898 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2899 return res; 2900 } 2901 } 2902 2903 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 2904 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 2905 2906 return 0; 2907 } 2908 2909 static void navi10_i2c_control_fini(struct smu_context *smu) 2910 { 2911 struct amdgpu_device *adev = smu->adev; 2912 2913 adev->pm.ras_eeprom_i2c_bus = NULL; 2914 adev->pm.fru_eeprom_i2c_bus = NULL; 2915 } 2916 2917 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, 2918 void **table) 2919 { 2920 struct smu_table_context *smu_table = &smu->smu_table; 2921 struct gpu_metrics_v1_3 *gpu_metrics = 2922 (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( 2923 smu, SMU_DRIVER_TABLE_GPU_METRICS); 2924 SmuMetrics_t metrics; 2925 int ret = 0; 2926 2927 ret = smu_cmn_get_metrics_table(smu, 2928 NULL, 2929 true); 2930 if (ret) 2931 return ret; 2932 2933 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t)); 2934 2935 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2936 2937 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2938 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2939 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2940 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2941 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2942 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2943 2944 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2945 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2946 2947 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2948 2949 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 2950 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 2951 else 2952 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 2953 2954 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2955 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 2956 2957 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2958 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2959 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2960 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2961 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2962 2963 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2964 gpu_metrics->indep_throttle_status = 2965 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 2966 navi1x_throttler_map); 2967 2968 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2969 2970 gpu_metrics->pcie_link_width = metrics.PcieWidth; 2971 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 2972 2973 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2974 2975 if (metrics.CurrGfxVoltageOffset) 2976 gpu_metrics->voltage_gfx = 2977 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 2978 if (metrics.CurrMemVidOffset) 2979 gpu_metrics->voltage_mem = 2980 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 2981 if (metrics.CurrSocVoltageOffset) 2982 gpu_metrics->voltage_soc = 2983 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 2984 2985 *table = (void *)gpu_metrics; 2986 2987 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); 2988 2989 return sizeof(struct gpu_metrics_v1_3); 2990 } 2991 2992 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, 2993 void **table) 2994 { 2995 struct smu_table_context *smu_table = &smu->smu_table; 2996 struct gpu_metrics_v1_3 *gpu_metrics = 2997 (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( 2998 smu, SMU_DRIVER_TABLE_GPU_METRICS); 2999 SmuMetrics_NV12_legacy_t metrics; 3000 int ret = 0; 3001 3002 ret = smu_cmn_get_metrics_table(smu, 3003 NULL, 3004 true); 3005 if (ret) 3006 return ret; 3007 3008 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t)); 3009 3010 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3011 3012 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3013 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3014 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3015 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3016 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3017 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3018 3019 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3020 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3021 3022 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3023 3024 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 3025 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3026 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 3027 3028 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3029 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3030 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3031 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3032 3033 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3034 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3035 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3036 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3037 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3038 3039 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3040 gpu_metrics->indep_throttle_status = 3041 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3042 navi1x_throttler_map); 3043 3044 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3045 3046 gpu_metrics->pcie_link_width = 3047 smu_v11_0_get_current_pcie_link_width(smu); 3048 gpu_metrics->pcie_link_speed = 3049 smu_v11_0_get_current_pcie_link_speed(smu); 3050 3051 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3052 3053 if (metrics.CurrGfxVoltageOffset) 3054 gpu_metrics->voltage_gfx = 3055 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3056 if (metrics.CurrMemVidOffset) 3057 gpu_metrics->voltage_mem = 3058 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3059 if (metrics.CurrSocVoltageOffset) 3060 gpu_metrics->voltage_soc = 3061 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3062 3063 *table = (void *)gpu_metrics; 3064 3065 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); 3066 3067 return sizeof(struct gpu_metrics_v1_3); 3068 } 3069 3070 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, 3071 void **table) 3072 { 3073 struct smu_table_context *smu_table = &smu->smu_table; 3074 struct gpu_metrics_v1_3 *gpu_metrics = 3075 (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( 3076 smu, SMU_DRIVER_TABLE_GPU_METRICS); 3077 SmuMetrics_NV12_t metrics; 3078 int ret = 0; 3079 3080 ret = smu_cmn_get_metrics_table(smu, 3081 NULL, 3082 true); 3083 if (ret) 3084 return ret; 3085 3086 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t)); 3087 3088 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3089 3090 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3091 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3092 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3093 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3094 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3095 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3096 3097 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3098 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3099 3100 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3101 3102 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 3103 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 3104 else 3105 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 3106 3107 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3108 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 3109 3110 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3111 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3112 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3113 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3114 3115 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3116 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3117 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3118 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3119 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3120 3121 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3122 gpu_metrics->indep_throttle_status = 3123 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3124 navi1x_throttler_map); 3125 3126 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3127 3128 gpu_metrics->pcie_link_width = metrics.PcieWidth; 3129 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 3130 3131 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3132 3133 if (metrics.CurrGfxVoltageOffset) 3134 gpu_metrics->voltage_gfx = 3135 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3136 if (metrics.CurrMemVidOffset) 3137 gpu_metrics->voltage_mem = 3138 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3139 if (metrics.CurrSocVoltageOffset) 3140 gpu_metrics->voltage_soc = 3141 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3142 3143 *table = (void *)gpu_metrics; 3144 3145 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); 3146 3147 return sizeof(struct gpu_metrics_v1_3); 3148 } 3149 3150 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, 3151 void **table) 3152 { 3153 struct amdgpu_device *adev = smu->adev; 3154 int ret = 0; 3155 3156 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 3157 case IP_VERSION(11, 0, 9): 3158 if (smu->smc_fw_version > 0x00341C00) 3159 ret = navi12_get_gpu_metrics(smu, table); 3160 else 3161 ret = navi12_get_legacy_gpu_metrics(smu, table); 3162 break; 3163 case IP_VERSION(11, 0, 0): 3164 case IP_VERSION(11, 0, 5): 3165 default: 3166 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == 3167 IP_VERSION(11, 0, 5)) && 3168 smu->smc_fw_version > 0x00351F00) || 3169 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == 3170 IP_VERSION(11, 0, 0)) && 3171 smu->smc_fw_version > 0x002A3B00)) 3172 ret = navi10_get_gpu_metrics(smu, table); 3173 else 3174 ret = navi10_get_legacy_gpu_metrics(smu, table); 3175 break; 3176 } 3177 3178 return ret; 3179 } 3180 3181 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) 3182 { 3183 struct smu_table_context *table_context = &smu->smu_table; 3184 PPTable_t *smc_pptable = table_context->driver_pptable; 3185 struct amdgpu_device *adev = smu->adev; 3186 uint32_t param = 0; 3187 3188 /* Navi12 does not support this */ 3189 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) 3190 return 0; 3191 3192 /* 3193 * Skip the MGpuFanBoost setting for those ASICs 3194 * which do not support it 3195 */ 3196 if (!smc_pptable->MGpuFanBoostLimitRpm) 3197 return 0; 3198 3199 /* Workaround for WS SKU */ 3200 if (adev->pdev->device == 0x7312 && 3201 adev->pdev->revision == 0) 3202 param = 0xD188; 3203 3204 return smu_cmn_send_smc_msg_with_param(smu, 3205 SMU_MSG_SetMGpuFanBoostLimitRpm, 3206 param, 3207 NULL); 3208 } 3209 3210 static int navi10_post_smu_init(struct smu_context *smu) 3211 { 3212 struct amdgpu_device *adev = smu->adev; 3213 int ret = 0; 3214 3215 if (amdgpu_sriov_vf(adev)) 3216 return 0; 3217 3218 ret = navi10_run_umc_cdr_workaround(smu); 3219 if (ret) 3220 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n"); 3221 3222 return ret; 3223 } 3224 3225 static int navi10_get_default_config_table_settings(struct smu_context *smu, 3226 struct config_table_setting *table) 3227 { 3228 if (!table) 3229 return -EINVAL; 3230 3231 table->gfxclk_average_tau = 10; 3232 table->socclk_average_tau = 10; 3233 table->uclk_average_tau = 10; 3234 table->gfx_activity_average_tau = 10; 3235 table->mem_activity_average_tau = 10; 3236 table->socket_power_average_tau = 10; 3237 3238 return 0; 3239 } 3240 3241 static int navi10_set_config_table(struct smu_context *smu, 3242 struct config_table_setting *table) 3243 { 3244 DriverSmuConfig_t driver_smu_config_table; 3245 3246 if (!table) 3247 return -EINVAL; 3248 3249 memset(&driver_smu_config_table, 3250 0, 3251 sizeof(driver_smu_config_table)); 3252 3253 driver_smu_config_table.GfxclkAverageLpfTau = 3254 table->gfxclk_average_tau; 3255 driver_smu_config_table.SocclkAverageLpfTau = 3256 table->socclk_average_tau; 3257 driver_smu_config_table.UclkAverageLpfTau = 3258 table->uclk_average_tau; 3259 driver_smu_config_table.GfxActivityLpfTau = 3260 table->gfx_activity_average_tau; 3261 driver_smu_config_table.UclkActivityLpfTau = 3262 table->mem_activity_average_tau; 3263 driver_smu_config_table.SocketPowerLpfTau = 3264 table->socket_power_average_tau; 3265 3266 return smu_cmn_update_table(smu, 3267 SMU_TABLE_DRIVER_SMU_CONFIG, 3268 0, 3269 (void *)&driver_smu_config_table, 3270 true); 3271 } 3272 3273 static const struct pptable_funcs navi10_ppt_funcs = { 3274 .init_allowed_features = navi10_init_allowed_features, 3275 .set_default_dpm_table = navi10_set_default_dpm_table, 3276 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, 3277 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable, 3278 .i2c_init = navi10_i2c_control_init, 3279 .i2c_fini = navi10_i2c_control_fini, 3280 .emit_clk_levels = navi10_emit_clk_levels, 3281 .force_clk_levels = navi10_force_clk_levels, 3282 .populate_umd_state_clk = navi10_populate_umd_state_clk, 3283 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency, 3284 .pre_display_config_changed = navi10_pre_display_config_changed, 3285 .display_config_changed = navi10_display_config_changed, 3286 .notify_smc_display_config = navi10_notify_smc_display_config, 3287 .is_dpm_running = navi10_is_dpm_running, 3288 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 3289 .get_fan_speed_rpm = navi10_get_fan_speed_rpm, 3290 .get_power_profile_mode = navi10_get_power_profile_mode, 3291 .set_power_profile_mode = navi10_set_power_profile_mode, 3292 .set_watermarks_table = navi10_set_watermarks_table, 3293 .read_sensor = navi10_read_sensor, 3294 .get_uclk_dpm_states = navi10_get_uclk_dpm_states, 3295 .set_performance_level = smu_v11_0_set_performance_level, 3296 .get_thermal_temperature_range = navi10_get_thermal_temperature_range, 3297 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch, 3298 .get_power_limit = navi10_get_power_limit, 3299 .update_pcie_parameters = navi10_update_pcie_parameters, 3300 .init_microcode = smu_v11_0_init_microcode, 3301 .load_microcode = smu_v11_0_load_microcode, 3302 .fini_microcode = smu_v11_0_fini_microcode, 3303 .init_smc_tables = navi10_init_smc_tables, 3304 .fini_smc_tables = smu_v11_0_fini_smc_tables, 3305 .init_power = smu_v11_0_init_power, 3306 .fini_power = smu_v11_0_fini_power, 3307 .check_fw_status = smu_v11_0_check_fw_status, 3308 .setup_pptable = navi10_setup_pptable, 3309 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 3310 .check_fw_version = smu_v11_0_check_fw_version, 3311 .write_pptable = smu_cmn_write_pptable, 3312 .set_driver_table_location = smu_v11_0_set_driver_table_location, 3313 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3314 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3315 .system_features_control = smu_v11_0_system_features_control, 3316 .init_display_count = smu_v11_0_init_display_count, 3317 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3318 .get_enabled_mask = smu_cmn_get_enabled_mask, 3319 .feature_is_enabled = smu_cmn_feature_is_enabled, 3320 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 3321 .notify_display_change = smu_v11_0_notify_display_change, 3322 .set_power_limit = smu_v11_0_set_power_limit, 3323 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 3324 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 3325 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 3326 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk, 3327 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 3328 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 3329 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 3330 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 3331 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 3332 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 3333 .gfx_off_control = smu_v11_0_gfx_off_control, 3334 .register_irq_handler = smu_v11_0_register_irq_handler, 3335 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 3336 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 3337 .get_bamaco_support = smu_v11_0_get_bamaco_support, 3338 .baco_enter = navi10_baco_enter, 3339 .baco_exit = navi10_baco_exit, 3340 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, 3341 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 3342 .set_default_od_settings = navi10_set_default_od_settings, 3343 .od_edit_dpm_table = navi10_od_edit_dpm_table, 3344 .restore_user_od_settings = smu_v11_0_restore_user_od_settings, 3345 .run_btc = navi10_run_btc, 3346 .set_power_source = smu_v11_0_set_power_source, 3347 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 3348 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 3349 .get_gpu_metrics = navi1x_get_gpu_metrics, 3350 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost, 3351 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 3352 .deep_sleep_control = smu_v11_0_deep_sleep_control, 3353 .get_fan_parameters = navi10_get_fan_parameters, 3354 .post_init = navi10_post_smu_init, 3355 .interrupt_work = smu_v11_0_interrupt_work, 3356 .set_mp1_state = smu_cmn_set_mp1_state, 3357 .get_default_config_table_settings = navi10_get_default_config_table_settings, 3358 .set_config_table = navi10_set_config_table, 3359 }; 3360 3361 void navi10_set_ppt_funcs(struct smu_context *smu) 3362 { 3363 smu->ppt_funcs = &navi10_ppt_funcs; 3364 smu->clock_map = navi10_clk_map; 3365 smu->feature_map = navi10_feature_mask_map; 3366 smu->table_map = navi10_table_map; 3367 smu->pwr_src_map = navi10_pwr_src_map; 3368 smu->workload_map = navi10_workload_map; 3369 smu_v11_0_init_msg_ctl(smu, navi10_message_map); 3370 } 3371