1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/math.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/tty.h>
18 #include <linux/serial_reg.h>
19 #include <linux/serial_core.h>
20 #include <linux/8250_pci.h>
21 #include <linux/bitops.h>
22 #include <linux/bitfield.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28 #include "8250_pcilib.h"
29
30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
32 #define PCI_DEVICE_ID_OCTPRO 0x0001
33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
46 #define PCI_DEVICE_ID_TITAN_200I 0x8028
47 #define PCI_DEVICE_ID_TITAN_400I 0x8048
48 #define PCI_DEVICE_ID_TITAN_800I 0x8088
49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
52 #define PCI_DEVICE_ID_TITAN_100E 0xA010
53 #define PCI_DEVICE_ID_TITAN_200E 0xA012
54 #define PCI_DEVICE_ID_TITAN_400E 0xA013
55 #define PCI_DEVICE_ID_TITAN_800E 0xA014
56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
67
68 #define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253
69 #define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173
70
71 #define PCI_VENDOR_ID_AGESTAR 0x5372
72 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
73 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
74 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
75
76 #define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470
77 #define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853
78
79 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
80 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
81 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027
82 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
83 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046
84 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121
85 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
86 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145
87 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
88 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
89 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
90 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
91 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
92 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323
93 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
94 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343
95 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
96 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
97
98 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500 0x7003
99 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG 0x7024
100 #define PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG 0x7025
101 #define PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG 0x7026
102
103 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
104 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
105 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
106
107 /*
108 * init function returns:
109 * > 0 - number of ports
110 * = 0 - use board->num_ports
111 * < 0 - error
112 */
113 struct pci_serial_quirk {
114 u32 vendor;
115 u32 device;
116 u32 subvendor;
117 u32 subdevice;
118 int (*probe)(struct pci_dev *dev);
119 int (*init)(struct pci_dev *dev);
120 int (*setup)(struct serial_private *,
121 const struct pciserial_board *,
122 struct uart_8250_port *, int);
123 void (*exit)(struct pci_dev *dev);
124 };
125
126 struct f815xxa_data {
127 spinlock_t lock;
128 int idx;
129 };
130
131 struct serial_private {
132 struct pci_dev *dev;
133 unsigned int nr;
134 struct pci_serial_quirk *quirk;
135 const struct pciserial_board *board;
136 int line[];
137 };
138
139 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
140 #define PCIE_VENDOR_ID_ASIX 0x125B
141 #define PCIE_DEVICE_ID_AX99100 0x9100
142
143 static const struct pci_device_id pci_use_msi[] = {
144 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
145 0xA000, 0x1000) },
146 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
147 0xA000, 0x1000) },
148 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
149 0xA000, 0x1000) },
150 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
151 0xA000, 0x1000) },
152 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
153 PCI_ANY_ID, PCI_ANY_ID) },
154 { PCI_DEVICE_SUB(PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100,
155 0xA000, 0x1000) },
156 { }
157 };
158
159 static int pci_default_setup(struct serial_private*,
160 const struct pciserial_board*, struct uart_8250_port *, int);
161
moan_device(const char * str,struct pci_dev * dev)162 static void moan_device(const char *str, struct pci_dev *dev)
163 {
164 pci_err(dev, "%s\n"
165 "Please send the output of lspci -vv, this\n"
166 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
167 "manufacturer and name of serial board or\n"
168 "modem board to <linux-serial@vger.kernel.org>.\n",
169 str, dev->vendor, dev->device,
170 dev->subsystem_vendor, dev->subsystem_device);
171 }
172
173 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)174 setup_port(struct serial_private *priv, struct uart_8250_port *port,
175 u8 bar, unsigned int offset, int regshift)
176 {
177 void __iomem *iomem = NULL;
178
179 if (pci_resource_flags(priv->dev, bar) & IORESOURCE_MEM) {
180 iomem = pcim_iomap(priv->dev, bar, 0);
181 if (!iomem)
182 return -ENOMEM;
183 }
184
185 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift, iomem);
186 }
187
188 /*
189 * ADDI-DATA GmbH communication cards <info@addi-data.com>
190 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)191 static int addidata_apci7800_setup(struct serial_private *priv,
192 const struct pciserial_board *board,
193 struct uart_8250_port *port, int idx)
194 {
195 unsigned int bar = 0, offset = board->first_offset;
196 bar = FL_GET_BASE(board->flags);
197
198 if (idx < 2) {
199 offset += idx * board->uart_offset;
200 } else if ((idx >= 2) && (idx < 4)) {
201 bar += 1;
202 offset += ((idx - 2) * board->uart_offset);
203 } else if ((idx >= 4) && (idx < 6)) {
204 bar += 2;
205 offset += ((idx - 4) * board->uart_offset);
206 } else if (idx >= 6) {
207 bar += 3;
208 offset += ((idx - 6) * board->uart_offset);
209 }
210
211 return setup_port(priv, port, bar, offset, board->reg_shift);
212 }
213
214 /*
215 * AFAVLAB uses a different mixture of BARs and offsets
216 * Not that ugly ;) -- HW
217 */
218 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)219 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
220 struct uart_8250_port *port, int idx)
221 {
222 unsigned int bar, offset = board->first_offset;
223
224 bar = FL_GET_BASE(board->flags);
225 if (idx < 4)
226 bar += idx;
227 else {
228 bar = 4;
229 offset += (idx - 4) * board->uart_offset;
230 }
231
232 return setup_port(priv, port, bar, offset, board->reg_shift);
233 }
234
235 /*
236 * HP's Remote Management Console. The Diva chip came in several
237 * different versions. N-class, L2000 and A500 have two Diva chips, each
238 * with 3 UARTs (the third UART on the second chip is unused). Superdome
239 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
240 * one Diva chip, but it has been expanded to 5 UARTs.
241 */
pci_hp_diva_init(struct pci_dev * dev)242 static int pci_hp_diva_init(struct pci_dev *dev)
243 {
244 int rc = 0;
245
246 switch (dev->subsystem_device) {
247 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
248 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
249 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
250 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
251 rc = 3;
252 break;
253 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
254 rc = 2;
255 break;
256 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
257 rc = 4;
258 break;
259 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
260 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
261 rc = 1;
262 break;
263 }
264
265 return rc;
266 }
267
268 /*
269 * HP's Diva chip puts the 4th/5th serial port further out, and
270 * some serial ports are supposed to be hidden on certain models.
271 */
272 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)273 pci_hp_diva_setup(struct serial_private *priv,
274 const struct pciserial_board *board,
275 struct uart_8250_port *port, int idx)
276 {
277 unsigned int offset = board->first_offset;
278 unsigned int bar = FL_GET_BASE(board->flags);
279
280 switch (priv->dev->subsystem_device) {
281 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
282 if (idx == 3)
283 idx++;
284 break;
285 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
286 if (idx > 0)
287 idx++;
288 if (idx > 2)
289 idx++;
290 break;
291 }
292 if (idx > 2)
293 offset = 0x18;
294
295 offset += idx * board->uart_offset;
296
297 return setup_port(priv, port, bar, offset, board->reg_shift);
298 }
299
300 /*
301 * Added for EKF Intel i960 serial boards
302 */
pci_inteli960ni_init(struct pci_dev * dev)303 static int pci_inteli960ni_init(struct pci_dev *dev)
304 {
305 u32 oldval;
306
307 if (!(dev->subsystem_device & 0x1000))
308 return -ENODEV;
309
310 /* is firmware started? */
311 pci_read_config_dword(dev, 0x44, &oldval);
312 if (oldval == 0x00001000L) { /* RESET value */
313 pci_dbg(dev, "Local i960 firmware missing\n");
314 return -ENODEV;
315 }
316 return 0;
317 }
318
319 /*
320 * Some PCI serial cards using the PLX 9050 PCI interface chip require
321 * that the card interrupt be explicitly enabled or disabled. This
322 * seems to be mainly needed on card using the PLX which also use I/O
323 * mapped memory.
324 */
pci_plx9050_init(struct pci_dev * dev)325 static int pci_plx9050_init(struct pci_dev *dev)
326 {
327 u8 irq_config;
328 void __iomem *p;
329
330 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
331 moan_device("no memory in bar 0", dev);
332 return 0;
333 }
334
335 irq_config = 0x41;
336 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
337 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
338 irq_config = 0x43;
339
340 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
341 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
342 /*
343 * As the megawolf cards have the int pins active
344 * high, and have 2 UART chips, both ints must be
345 * enabled on the 9050. Also, the UARTS are set in
346 * 16450 mode by default, so we have to enable the
347 * 16C950 'enhanced' mode so that we can use the
348 * deep FIFOs
349 */
350 irq_config = 0x5b;
351 /*
352 * enable/disable interrupts
353 */
354 p = ioremap(pci_resource_start(dev, 0), 0x80);
355 if (p == NULL)
356 return -ENOMEM;
357 writel(irq_config, p + 0x4c);
358
359 /*
360 * Read the register back to ensure that it took effect.
361 */
362 readl(p + 0x4c);
363 iounmap(p);
364
365 return 0;
366 }
367
pci_plx9050_exit(struct pci_dev * dev)368 static void pci_plx9050_exit(struct pci_dev *dev)
369 {
370 u8 __iomem *p;
371
372 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
373 return;
374
375 /*
376 * disable interrupts
377 */
378 p = ioremap(pci_resource_start(dev, 0), 0x80);
379 if (p != NULL) {
380 writel(0, p + 0x4c);
381
382 /*
383 * Read the register back to ensure that it took effect.
384 */
385 readl(p + 0x4c);
386 iounmap(p);
387 }
388 }
389
390 #define NI8420_INT_ENABLE_REG 0x38
391 #define NI8420_INT_ENABLE_BIT 0x2000
392
pci_ni8420_exit(struct pci_dev * dev)393 static void pci_ni8420_exit(struct pci_dev *dev)
394 {
395 void __iomem *p;
396 unsigned int bar = 0;
397
398 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
399 moan_device("no memory in bar", dev);
400 return;
401 }
402
403 p = pci_ioremap_bar(dev, bar);
404 if (p == NULL)
405 return;
406
407 /* Disable the CPU Interrupt */
408 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
409 p + NI8420_INT_ENABLE_REG);
410 iounmap(p);
411 }
412
413
414 /* MITE registers */
415 #define MITE_IOWBSR1 0xc4
416 #define MITE_IOWCR1 0xf4
417 #define MITE_LCIMR1 0x08
418 #define MITE_LCIMR2 0x10
419
420 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
421
pci_ni8430_exit(struct pci_dev * dev)422 static void pci_ni8430_exit(struct pci_dev *dev)
423 {
424 void __iomem *p;
425 unsigned int bar = 0;
426
427 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
428 moan_device("no memory in bar", dev);
429 return;
430 }
431
432 p = pci_ioremap_bar(dev, bar);
433 if (p == NULL)
434 return;
435
436 /* Disable the CPU Interrupt */
437 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
438 iounmap(p);
439 }
440
441 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
442 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)443 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
444 struct uart_8250_port *port, int idx)
445 {
446 unsigned int bar, offset = board->first_offset;
447
448 bar = 0;
449
450 if (idx < 4) {
451 /* first four channels map to 0, 0x100, 0x200, 0x300 */
452 offset += idx * board->uart_offset;
453 } else if (idx < 8) {
454 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
455 offset += idx * board->uart_offset + 0xC00;
456 } else /* we have only 8 ports on PMC-OCTALPRO */
457 return 1;
458
459 return setup_port(priv, port, bar, offset, board->reg_shift);
460 }
461
462 /*
463 * This does initialization for PMC OCTALPRO cards:
464 * maps the device memory, resets the UARTs (needed, bc
465 * if the module is removed and inserted again, the card
466 * is in the sleep mode) and enables global interrupt.
467 */
468
469 /* global control register offset for SBS PMC-OctalPro */
470 #define OCT_REG_CR_OFF 0x500
471
sbs_init(struct pci_dev * dev)472 static int sbs_init(struct pci_dev *dev)
473 {
474 u8 __iomem *p;
475
476 p = pci_ioremap_bar(dev, 0);
477
478 if (p == NULL)
479 return -ENOMEM;
480 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
481 writeb(0x10, p + OCT_REG_CR_OFF);
482 udelay(50);
483 writeb(0x0, p + OCT_REG_CR_OFF);
484
485 /* Set bit-2 (INTENABLE) of Control Register */
486 writeb(0x4, p + OCT_REG_CR_OFF);
487 iounmap(p);
488
489 return 0;
490 }
491
492 /*
493 * Disables the global interrupt of PMC-OctalPro
494 */
495
sbs_exit(struct pci_dev * dev)496 static void sbs_exit(struct pci_dev *dev)
497 {
498 u8 __iomem *p;
499
500 p = pci_ioremap_bar(dev, 0);
501 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
502 if (p != NULL)
503 writeb(0, p + OCT_REG_CR_OFF);
504 iounmap(p);
505 }
506
507 /*
508 * SIIG serial cards have an PCI interface chip which also controls
509 * the UART clocking frequency. Each UART can be clocked independently
510 * (except cards equipped with 4 UARTs) and initial clocking settings
511 * are stored in the EEPROM chip. It can cause problems because this
512 * version of serial driver doesn't support differently clocked UART's
513 * on single PCI card. To prevent this, initialization functions set
514 * high frequency clocking for all UART's on given card. It is safe (I
515 * hope) because it doesn't touch EEPROM settings to prevent conflicts
516 * with other OSes (like M$ DOS).
517 *
518 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
519 *
520 * There is two family of SIIG serial cards with different PCI
521 * interface chip and different configuration methods:
522 * - 10x cards have control registers in IO and/or memory space;
523 * - 20x cards have control registers in standard PCI configuration space.
524 *
525 * Note: all 10x cards have PCI device ids 0x10..
526 * all 20x cards have PCI device ids 0x20..
527 *
528 * There are also Quartet Serial cards which use Oxford Semiconductor
529 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
530 *
531 * Note: some SIIG cards are probed by the parport_serial object.
532 */
533
534 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
535 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
536
pci_siig10x_init(struct pci_dev * dev)537 static int pci_siig10x_init(struct pci_dev *dev)
538 {
539 u16 data;
540 void __iomem *p;
541
542 switch (dev->device & 0xfff8) {
543 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
544 data = 0xffdf;
545 break;
546 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
547 data = 0xf7ff;
548 break;
549 default: /* 1S1P, 4S */
550 data = 0xfffb;
551 break;
552 }
553
554 p = ioremap(pci_resource_start(dev, 0), 0x80);
555 if (p == NULL)
556 return -ENOMEM;
557
558 writew(readw(p + 0x28) & data, p + 0x28);
559 readw(p + 0x28);
560 iounmap(p);
561 return 0;
562 }
563
564 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
565 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
566
pci_siig20x_init(struct pci_dev * dev)567 static int pci_siig20x_init(struct pci_dev *dev)
568 {
569 u8 data;
570
571 /* Change clock frequency for the first UART. */
572 pci_read_config_byte(dev, 0x6f, &data);
573 pci_write_config_byte(dev, 0x6f, data & 0xef);
574
575 /* If this card has 2 UART, we have to do the same with second UART. */
576 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
577 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
578 pci_read_config_byte(dev, 0x73, &data);
579 pci_write_config_byte(dev, 0x73, data & 0xef);
580 }
581 return 0;
582 }
583
pci_siig_init(struct pci_dev * dev)584 static int pci_siig_init(struct pci_dev *dev)
585 {
586 unsigned int type = dev->device & 0xff00;
587
588 if (type == 0x1000)
589 return pci_siig10x_init(dev);
590 if (type == 0x2000)
591 return pci_siig20x_init(dev);
592
593 moan_device("Unknown SIIG card", dev);
594 return -ENODEV;
595 }
596
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)597 static int pci_siig_setup(struct serial_private *priv,
598 const struct pciserial_board *board,
599 struct uart_8250_port *port, int idx)
600 {
601 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
602
603 if (idx > 3) {
604 bar = 4;
605 offset = (idx - 4) * 8;
606 }
607
608 return setup_port(priv, port, bar, offset, 0);
609 }
610
611 /*
612 * Timedia has an explosion of boards, and to avoid the PCI table from
613 * growing *huge*, we use this function to collapse some 70 entries
614 * in the PCI table into one, for sanity's and compactness's sake.
615 */
616 static const unsigned short timedia_single_port[] = {
617 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
618 };
619
620 static const unsigned short timedia_dual_port[] = {
621 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
622 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
623 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
624 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
625 0xD079, 0
626 };
627
628 static const unsigned short timedia_quad_port[] = {
629 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
630 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
631 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
632 0xB157, 0
633 };
634
635 static const unsigned short timedia_eight_port[] = {
636 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
637 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
638 };
639
640 static const struct timedia_struct {
641 int num;
642 const unsigned short *ids;
643 } timedia_data[] = {
644 { 1, timedia_single_port },
645 { 2, timedia_dual_port },
646 { 4, timedia_quad_port },
647 { 8, timedia_eight_port }
648 };
649
650 /*
651 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
652 * listing them individually, this driver merely grabs them all with
653 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
654 * and should be left free to be claimed by parport_serial instead.
655 */
pci_timedia_probe(struct pci_dev * dev)656 static int pci_timedia_probe(struct pci_dev *dev)
657 {
658 /*
659 * Check the third digit of the subdevice ID
660 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
661 */
662 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
663 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
664 dev->subsystem_device);
665 return -ENODEV;
666 }
667
668 return 0;
669 }
670
pci_timedia_init(struct pci_dev * dev)671 static int pci_timedia_init(struct pci_dev *dev)
672 {
673 const unsigned short *ids;
674 int i, j;
675
676 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
677 ids = timedia_data[i].ids;
678 for (j = 0; ids[j]; j++)
679 if (dev->subsystem_device == ids[j])
680 return timedia_data[i].num;
681 }
682 return 0;
683 }
684
685 /*
686 * Timedia/SUNIX uses a mixture of BARs and offsets
687 * Ugh, this is ugly as all hell --- TYT
688 */
689 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)690 pci_timedia_setup(struct serial_private *priv,
691 const struct pciserial_board *board,
692 struct uart_8250_port *port, int idx)
693 {
694 unsigned int bar = 0, offset = board->first_offset;
695
696 switch (idx) {
697 case 0:
698 bar = 0;
699 break;
700 case 1:
701 offset = board->uart_offset;
702 bar = 0;
703 break;
704 case 2:
705 bar = 1;
706 break;
707 case 3:
708 offset = board->uart_offset;
709 fallthrough;
710 case 4: /* BAR 2 */
711 case 5: /* BAR 3 */
712 case 6: /* BAR 4 */
713 case 7: /* BAR 5 */
714 bar = idx - 2;
715 }
716
717 return setup_port(priv, port, bar, offset, board->reg_shift);
718 }
719
720 /*
721 * Some Titan cards are also a little weird
722 */
723 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)724 titan_400l_800l_setup(struct serial_private *priv,
725 const struct pciserial_board *board,
726 struct uart_8250_port *port, int idx)
727 {
728 unsigned int bar, offset = board->first_offset;
729
730 switch (idx) {
731 case 0:
732 bar = 1;
733 break;
734 case 1:
735 bar = 2;
736 break;
737 default:
738 bar = 4;
739 offset = (idx - 2) * board->uart_offset;
740 }
741
742 return setup_port(priv, port, bar, offset, board->reg_shift);
743 }
744
pci_xircom_init(struct pci_dev * dev)745 static int pci_xircom_init(struct pci_dev *dev)
746 {
747 msleep(100);
748 return 0;
749 }
750
pci_ni8420_init(struct pci_dev * dev)751 static int pci_ni8420_init(struct pci_dev *dev)
752 {
753 void __iomem *p;
754 unsigned int bar = 0;
755
756 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
757 moan_device("no memory in bar", dev);
758 return 0;
759 }
760
761 p = pci_ioremap_bar(dev, bar);
762 if (p == NULL)
763 return -ENOMEM;
764
765 /* Enable CPU Interrupt */
766 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
767 p + NI8420_INT_ENABLE_REG);
768
769 iounmap(p);
770 return 0;
771 }
772
773 #define MITE_IOWBSR1_WSIZE 0xa
774 #define MITE_IOWBSR1_WIN_OFFSET 0x800
775 #define MITE_IOWBSR1_WENAB (1 << 7)
776 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
777 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
778 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
779
pci_ni8430_init(struct pci_dev * dev)780 static int pci_ni8430_init(struct pci_dev *dev)
781 {
782 void __iomem *p;
783 struct pci_bus_region region;
784 u32 device_window;
785 unsigned int bar = 0;
786
787 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
788 moan_device("no memory in bar", dev);
789 return 0;
790 }
791
792 p = pci_ioremap_bar(dev, bar);
793 if (p == NULL)
794 return -ENOMEM;
795
796 /*
797 * Set device window address and size in BAR0, while acknowledging that
798 * the resource structure may contain a translated address that differs
799 * from the address the device responds to.
800 */
801 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
802 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
803 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
804 writel(device_window, p + MITE_IOWBSR1);
805
806 /* Set window access to go to RAMSEL IO address space */
807 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
808 p + MITE_IOWCR1);
809
810 /* Enable IO Bus Interrupt 0 */
811 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
812
813 /* Enable CPU Interrupt */
814 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
815
816 iounmap(p);
817 return 0;
818 }
819
820 /* UART Port Control Register */
821 #define NI8430_PORTCON 0x0f
822 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
823
824 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)825 pci_ni8430_setup(struct serial_private *priv,
826 const struct pciserial_board *board,
827 struct uart_8250_port *port, int idx)
828 {
829 struct pci_dev *dev = priv->dev;
830 void __iomem *p;
831 unsigned int bar, offset = board->first_offset;
832
833 if (idx >= board->num_ports)
834 return 1;
835
836 bar = FL_GET_BASE(board->flags);
837 offset += idx * board->uart_offset;
838
839 p = pci_ioremap_bar(dev, bar);
840 if (!p)
841 return -ENOMEM;
842
843 /* enable the transceiver */
844 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
845 p + offset + NI8430_PORTCON);
846
847 iounmap(p);
848
849 return setup_port(priv, port, bar, offset, board->reg_shift);
850 }
851
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)852 static int pci_netmos_9900_setup(struct serial_private *priv,
853 const struct pciserial_board *board,
854 struct uart_8250_port *port, int idx)
855 {
856 unsigned int bar;
857
858 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
859 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
860 /* netmos apparently orders BARs by datasheet layout, so serial
861 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
862 */
863 bar = 3 * idx;
864
865 return setup_port(priv, port, bar, 0, board->reg_shift);
866 }
867
868 return pci_default_setup(priv, board, port, idx);
869 }
870
871 /* the 99xx series comes with a range of device IDs and a variety
872 * of capabilities:
873 *
874 * 9900 has varying capabilities and can cascade to sub-controllers
875 * (cascading should be purely internal)
876 * 9904 is hardwired with 4 serial ports
877 * 9912 and 9922 are hardwired with 2 serial ports
878 */
pci_netmos_9900_numports(struct pci_dev * dev)879 static int pci_netmos_9900_numports(struct pci_dev *dev)
880 {
881 unsigned int c = dev->class;
882 unsigned int pi;
883 unsigned short sub_serports;
884
885 pi = c & 0xff;
886
887 if (pi == 2)
888 return 1;
889
890 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
891 /* two possibilities: 0x30ps encodes number of parallel and
892 * serial ports, or 0x1000 indicates *something*. This is not
893 * immediately obvious, since the 2s1p+4s configuration seems
894 * to offer all functionality on functions 0..2, while still
895 * advertising the same function 3 as the 4s+2s1p config.
896 */
897 sub_serports = dev->subsystem_device & 0xf;
898 if (sub_serports > 0)
899 return sub_serports;
900
901 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
902 return 0;
903 }
904
905 moan_device("unknown NetMos/Mostech program interface", dev);
906 return 0;
907 }
908
pci_netmos_init(struct pci_dev * dev)909 static int pci_netmos_init(struct pci_dev *dev)
910 {
911 /* subdevice 0x00PS means <P> parallel, <S> serial */
912 unsigned int num_serial = dev->subsystem_device & 0xf;
913
914 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
915 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
916 return 0;
917
918 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
919 dev->subsystem_device == 0x0299)
920 return 0;
921
922 switch (dev->device) { /* FALLTHROUGH on all */
923 case PCI_DEVICE_ID_NETMOS_9904:
924 case PCI_DEVICE_ID_NETMOS_9912:
925 case PCI_DEVICE_ID_NETMOS_9922:
926 case PCI_DEVICE_ID_NETMOS_9900:
927 case PCIE_DEVICE_ID_AX99100:
928 num_serial = pci_netmos_9900_numports(dev);
929 break;
930
931 default:
932 break;
933 }
934
935 if (num_serial == 0) {
936 moan_device("unknown NetMos/Mostech device", dev);
937 return -ENODEV;
938 }
939
940 return num_serial;
941 }
942
943 /*
944 * These chips are available with optionally one parallel port and up to
945 * two serial ports. Unfortunately they all have the same product id.
946 *
947 * Basic configuration is done over a region of 32 I/O ports. The base
948 * ioport is called INTA or INTC, depending on docs/other drivers.
949 *
950 * The region of the 32 I/O ports is configured in POSIO0R...
951 */
952
953 /* registers */
954 #define ITE_887x_MISCR 0x9c
955 #define ITE_887x_INTCBAR 0x78
956 #define ITE_887x_UARTBAR 0x7c
957 #define ITE_887x_PS0BAR 0x10
958 #define ITE_887x_POSIO0 0x60
959
960 /* I/O space size */
961 #define ITE_887x_IOSIZE 32
962 /* I/O space size (bits 26-24; 8 bytes = 011b) */
963 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
964 /* I/O space size (bits 26-24; 32 bytes = 101b) */
965 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
966 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
967 #define ITE_887x_POSIO_SPEED (3 << 29)
968 /* enable IO_Space bit */
969 #define ITE_887x_POSIO_ENABLE (1 << 31)
970
971 /* inta_addr are the configuration addresses of the ITE */
972 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
pci_ite887x_init(struct pci_dev * dev)973 static int pci_ite887x_init(struct pci_dev *dev)
974 {
975 int ret, i, type;
976 struct resource *iobase = NULL;
977 u32 miscr, uartbar, ioport;
978
979 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
980 return serial_8250_warn_need_ioport(dev);
981
982 /* search for the base-ioport */
983 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
984 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
985 "ite887x");
986 if (iobase != NULL) {
987 /* write POSIO0R - speed | size | ioport */
988 pci_write_config_dword(dev, ITE_887x_POSIO0,
989 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
990 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
991 /* write INTCBAR - ioport */
992 pci_write_config_dword(dev, ITE_887x_INTCBAR,
993 inta_addr[i]);
994 ret = inb(inta_addr[i]);
995 if (ret != 0xff) {
996 /* ioport connected */
997 break;
998 }
999 release_region(iobase->start, ITE_887x_IOSIZE);
1000 }
1001 }
1002
1003 if (i == ARRAY_SIZE(inta_addr)) {
1004 pci_err(dev, "could not find iobase\n");
1005 return -ENODEV;
1006 }
1007
1008 /* start of undocumented type checking (see parport_pc.c) */
1009 type = inb(iobase->start + 0x18) & 0x0f;
1010
1011 switch (type) {
1012 case 0x2: /* ITE8871 (1P) */
1013 case 0xa: /* ITE8875 (1P) */
1014 ret = 0;
1015 break;
1016 case 0xe: /* ITE8872 (2S1P) */
1017 ret = 2;
1018 break;
1019 case 0x6: /* ITE8873 (1S) */
1020 ret = 1;
1021 break;
1022 case 0x8: /* ITE8874 (2S) */
1023 ret = 2;
1024 break;
1025 default:
1026 moan_device("Unknown ITE887x", dev);
1027 ret = -ENODEV;
1028 }
1029
1030 /* configure all serial ports */
1031 for (i = 0; i < ret; i++) {
1032 /* read the I/O port from the device */
1033 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
1034 &ioport);
1035 ioport &= 0x0000FF00; /* the actual base address */
1036 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
1037 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
1038 ITE_887x_POSIO_IOSIZE_8 | ioport);
1039
1040 /* write the ioport to the UARTBAR */
1041 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
1042 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
1043 uartbar |= (ioport << (16 * i)); /* set the ioport */
1044 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
1045
1046 /* get current config */
1047 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
1048 /* disable interrupts (UARTx_Routing[3:0]) */
1049 miscr &= ~(0xf << (12 - 4 * i));
1050 /* activate the UART (UARTx_En) */
1051 miscr |= 1 << (23 - i);
1052 /* write new config with activated UART */
1053 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
1054 }
1055
1056 if (ret <= 0) {
1057 /* the device has no UARTs if we get here */
1058 release_region(iobase->start, ITE_887x_IOSIZE);
1059 }
1060
1061 return ret;
1062 }
1063
pci_ite887x_exit(struct pci_dev * dev)1064 static void pci_ite887x_exit(struct pci_dev *dev)
1065 {
1066 u32 ioport;
1067 /* the ioport is bit 0-15 in POSIO0R */
1068 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1069 ioport &= 0xffff;
1070 release_region(ioport, ITE_887x_IOSIZE);
1071 }
1072
1073 /*
1074 * Oxford Semiconductor Inc.
1075 * Check if an OxSemi device is part of the Tornado range of devices.
1076 */
1077 #define PCI_VENDOR_ID_ENDRUN 0x7401
1078 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1079
pci_oxsemi_tornado_p(struct pci_dev * dev)1080 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1081 {
1082 /* OxSemi Tornado devices are all 0xCxxx */
1083 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1084 (dev->device & 0xf000) != 0xc000)
1085 return false;
1086
1087 /* EndRun devices are all 0xExxx */
1088 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1089 (dev->device & 0xf000) != 0xe000)
1090 return false;
1091
1092 return true;
1093 }
1094
1095 /*
1096 * Determine the number of ports available on a Tornado device.
1097 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1098 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1099 {
1100 u8 __iomem *p;
1101 unsigned long deviceID;
1102 unsigned int number_uarts = 0;
1103
1104 if (!pci_oxsemi_tornado_p(dev))
1105 return 0;
1106
1107 p = pci_iomap(dev, 0, 5);
1108 if (p == NULL)
1109 return -ENOMEM;
1110
1111 deviceID = ioread32(p);
1112 /* Tornado device */
1113 if (deviceID == 0x07000200) {
1114 number_uarts = ioread8(p + 4);
1115 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1116 number_uarts,
1117 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1118 "EndRun" : "Oxford");
1119 }
1120 pci_iounmap(dev, p);
1121 return number_uarts;
1122 }
1123
1124 /* Tornado-specific constants for the TCR and CPR registers; see below. */
1125 #define OXSEMI_TORNADO_TCR_MASK 0xf
1126 #define OXSEMI_TORNADO_CPR_MASK 0x1ff
1127 #define OXSEMI_TORNADO_CPR_MIN 0x008
1128 #define OXSEMI_TORNADO_CPR_DEF 0x10f
1129
1130 /*
1131 * Determine the oversampling rate, the clock prescaler, and the clock
1132 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1133 * which is four times the baud base, and the prescaler increments in
1134 * steps of 1/8. Therefore to make calculations on integers we need
1135 * to use a scaled clock rate, which is the baud base multiplied by 32
1136 * (or our assumed UART clock rate multiplied by 2).
1137 *
1138 * The allowed oversampling rates are from 4 up to 16 inclusive (values
1139 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1140 * values between 1.000 and 63.875 inclusive (operation for values from
1141 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1142 * unsigned 16-bit integer.
1143 *
1144 * For the most accurate baud rate we use a table of predetermined
1145 * oversampling rates and clock prescalers that records all possible
1146 * products of the two parameters in the range from 4 up to 255 inclusive,
1147 * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1148 * by 8. The table is sorted by the decreasing value of the oversampling
1149 * rate and ties are resolved by sorting by the decreasing value of the
1150 * product. This way preference is given to higher oversampling rates.
1151 *
1152 * We iterate over the table and choose the product of an oversampling
1153 * rate and a clock prescaler that gives the lowest integer division
1154 * result deviation, or if an exact integer divider is found we stop
1155 * looking for it right away. We do some fixup if the resulting clock
1156 * divisor required would be out of its unsigned 16-bit integer range.
1157 *
1158 * Finally we abuse the supposed fractional part returned to encode the
1159 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1160 * prescaler which will end up in the TCR and CPR/CPR2 registers.
1161 */
pci_oxsemi_tornado_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)1162 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1163 unsigned int baud,
1164 unsigned int *frac)
1165 {
1166 static u8 p[][2] = {
1167 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1168 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
1169 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1170 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
1171 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1172 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1173 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
1174 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1175 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
1176 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
1177 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1178 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1179 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
1180 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1181 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
1182 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
1183 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
1184 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
1185 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
1186 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
1187 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
1188 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
1189 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
1190 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
1191 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
1192 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
1193 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
1194 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
1195 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
1196 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
1197 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
1198 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
1199 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
1200 { 4, 9, }, { 4, 8, },
1201 };
1202 /* Scale the quotient for comparison to get the fractional part. */
1203 const unsigned int quot_scale = 65536;
1204 unsigned int sclk = port->uartclk * 2;
1205 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1206 unsigned int best_squot;
1207 unsigned int squot;
1208 unsigned int quot;
1209 u16 cpr;
1210 u8 tcr;
1211 int i;
1212
1213 best_squot = quot_scale;
1214 for (i = 0; i < ARRAY_SIZE(p); i++) {
1215 unsigned int spre;
1216 unsigned int srem;
1217 u8 cp;
1218 u8 tc;
1219
1220 tc = p[i][0];
1221 cp = p[i][1];
1222 spre = tc * cp;
1223
1224 srem = sdiv % spre;
1225 if (srem > spre / 2)
1226 srem = spre - srem;
1227 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1228
1229 if (srem == 0) {
1230 tcr = tc;
1231 cpr = cp;
1232 quot = sdiv / spre;
1233 break;
1234 } else if (squot < best_squot) {
1235 best_squot = squot;
1236 tcr = tc;
1237 cpr = cp;
1238 quot = DIV_ROUND_CLOSEST(sdiv, spre);
1239 }
1240 }
1241 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1242 quot % 2 == 0) {
1243 quot >>= 1;
1244 tcr <<= 1;
1245 }
1246 while (quot > UART_DIV_MAX) {
1247 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1248 quot >>= 1;
1249 tcr <<= 1;
1250 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1251 quot >>= 1;
1252 cpr <<= 1;
1253 } else {
1254 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1255 cpr = OXSEMI_TORNADO_CPR_MASK;
1256 }
1257 }
1258
1259 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1260 return quot;
1261 }
1262
1263 /*
1264 * Set the oversampling rate in the transmitter clock cycle register (TCR),
1265 * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1266 * the clock divisor in the divisor latch (DLL and DLM). Note that for
1267 * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1268 * has to be written first, followed by CPR2, which occupies the location
1269 * of CKS used with earlier UART designs.
1270 */
pci_oxsemi_tornado_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1271 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1272 unsigned int baud,
1273 unsigned int quot,
1274 unsigned int quot_frac)
1275 {
1276 struct uart_8250_port *up = up_to_u8250p(port);
1277 u8 cpr2 = quot_frac >> 16;
1278 u8 cpr = quot_frac >> 8;
1279 u8 tcr = quot_frac;
1280
1281 serial_icr_write(up, UART_TCR, tcr);
1282 serial_icr_write(up, UART_CPR, cpr);
1283 serial_icr_write(up, UART_CKS, cpr2);
1284 serial8250_do_set_divisor(port, baud, quot);
1285 }
1286
1287 /*
1288 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1289 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
1290 */
pci_oxsemi_tornado_set_mctrl(struct uart_port * port,unsigned int mctrl)1291 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1292 unsigned int mctrl)
1293 {
1294 struct uart_8250_port *up = up_to_u8250p(port);
1295
1296 up->mcr |= UART_MCR_CLKSEL;
1297 serial8250_do_set_mctrl(port, mctrl);
1298 }
1299
1300 /*
1301 * We require EFR features for clock programming, so set UPF_FULL_PROBE
1302 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
1303 */
pci_oxsemi_tornado_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * up,int idx)1304 static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1305 const struct pciserial_board *board,
1306 struct uart_8250_port *up, int idx)
1307 {
1308 struct pci_dev *dev = priv->dev;
1309
1310 if (pci_oxsemi_tornado_p(dev)) {
1311 up->port.flags |= UPF_FULL_PROBE;
1312 up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1313 up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1314 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1315 }
1316
1317 return pci_default_setup(priv, board, up, idx);
1318 }
1319
1320 #define QPCR_TEST_FOR1 0x3F
1321 #define QPCR_TEST_GET1 0x00
1322 #define QPCR_TEST_FOR2 0x40
1323 #define QPCR_TEST_GET2 0x40
1324 #define QPCR_TEST_FOR3 0x80
1325 #define QPCR_TEST_GET3 0x40
1326 #define QPCR_TEST_FOR4 0xC0
1327 #define QPCR_TEST_GET4 0x80
1328
1329 #define QOPR_CLOCK_X1 0x0000
1330 #define QOPR_CLOCK_X2 0x0001
1331 #define QOPR_CLOCK_X4 0x0002
1332 #define QOPR_CLOCK_X8 0x0003
1333 #define QOPR_CLOCK_RATE_MASK 0x0003
1334
1335 /* Quatech devices have their own extra interface features */
1336 static struct pci_device_id quatech_cards[] = {
1337 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) },
1338 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) },
1339 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1340 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) },
1341 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1342 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) },
1343 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) },
1344 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) },
1345 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) },
1346 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) },
1347 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) },
1348 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1349 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1350 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1351 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1352 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1353 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1354 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1355 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1356 { 0, }
1357 };
1358
pci_quatech_rqopr(struct uart_8250_port * port)1359 static int pci_quatech_rqopr(struct uart_8250_port *port)
1360 {
1361 unsigned long base = port->port.iobase;
1362 u8 LCR, val;
1363
1364 LCR = inb(base + UART_LCR);
1365 outb(0xBF, base + UART_LCR);
1366 val = inb(base + UART_SCR);
1367 outb(LCR, base + UART_LCR);
1368 return val;
1369 }
1370
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1371 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1372 {
1373 unsigned long base = port->port.iobase;
1374 u8 LCR;
1375
1376 LCR = inb(base + UART_LCR);
1377 outb(0xBF, base + UART_LCR);
1378 inb(base + UART_SCR);
1379 outb(qopr, base + UART_SCR);
1380 outb(LCR, base + UART_LCR);
1381 }
1382
pci_quatech_rqmcr(struct uart_8250_port * port)1383 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1384 {
1385 unsigned long base = port->port.iobase;
1386 u8 LCR, val, qmcr;
1387
1388 LCR = inb(base + UART_LCR);
1389 outb(0xBF, base + UART_LCR);
1390 val = inb(base + UART_SCR);
1391 outb(val | 0x10, base + UART_SCR);
1392 qmcr = inb(base + UART_MCR);
1393 outb(val, base + UART_SCR);
1394 outb(LCR, base + UART_LCR);
1395
1396 return qmcr;
1397 }
1398
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1399 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1400 {
1401 unsigned long base = port->port.iobase;
1402 u8 LCR, val;
1403
1404 LCR = inb(base + UART_LCR);
1405 outb(0xBF, base + UART_LCR);
1406 val = inb(base + UART_SCR);
1407 outb(val | 0x10, base + UART_SCR);
1408 outb(qmcr, base + UART_MCR);
1409 outb(val, base + UART_SCR);
1410 outb(LCR, base + UART_LCR);
1411 }
1412
pci_quatech_has_qmcr(struct uart_8250_port * port)1413 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1414 {
1415 unsigned long base = port->port.iobase;
1416 u8 LCR, val;
1417
1418 LCR = inb(base + UART_LCR);
1419 outb(0xBF, base + UART_LCR);
1420 val = inb(base + UART_SCR);
1421 if (val & 0x20) {
1422 outb(0x80, UART_LCR);
1423 if (!(inb(UART_SCR) & 0x20)) {
1424 outb(LCR, base + UART_LCR);
1425 return 1;
1426 }
1427 }
1428 return 0;
1429 }
1430
pci_quatech_test(struct uart_8250_port * port)1431 static int pci_quatech_test(struct uart_8250_port *port)
1432 {
1433 u8 reg, qopr;
1434
1435 qopr = pci_quatech_rqopr(port);
1436 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1437 reg = pci_quatech_rqopr(port) & 0xC0;
1438 if (reg != QPCR_TEST_GET1)
1439 return -EINVAL;
1440 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1441 reg = pci_quatech_rqopr(port) & 0xC0;
1442 if (reg != QPCR_TEST_GET2)
1443 return -EINVAL;
1444 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1445 reg = pci_quatech_rqopr(port) & 0xC0;
1446 if (reg != QPCR_TEST_GET3)
1447 return -EINVAL;
1448 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1449 reg = pci_quatech_rqopr(port) & 0xC0;
1450 if (reg != QPCR_TEST_GET4)
1451 return -EINVAL;
1452
1453 pci_quatech_wqopr(port, qopr);
1454 return 0;
1455 }
1456
pci_quatech_clock(struct uart_8250_port * port)1457 static int pci_quatech_clock(struct uart_8250_port *port)
1458 {
1459 u8 qopr, reg, set;
1460 unsigned long clock;
1461
1462 if (pci_quatech_test(port) < 0)
1463 return 1843200;
1464
1465 qopr = pci_quatech_rqopr(port);
1466
1467 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1468 reg = pci_quatech_rqopr(port);
1469 if (reg & QOPR_CLOCK_X8) {
1470 clock = 1843200;
1471 goto out;
1472 }
1473 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1474 reg = pci_quatech_rqopr(port);
1475 if (!(reg & QOPR_CLOCK_X8)) {
1476 clock = 1843200;
1477 goto out;
1478 }
1479 reg &= QOPR_CLOCK_X8;
1480 if (reg == QOPR_CLOCK_X2) {
1481 clock = 3685400;
1482 set = QOPR_CLOCK_X2;
1483 } else if (reg == QOPR_CLOCK_X4) {
1484 clock = 7372800;
1485 set = QOPR_CLOCK_X4;
1486 } else if (reg == QOPR_CLOCK_X8) {
1487 clock = 14745600;
1488 set = QOPR_CLOCK_X8;
1489 } else {
1490 clock = 1843200;
1491 set = QOPR_CLOCK_X1;
1492 }
1493 qopr &= ~QOPR_CLOCK_RATE_MASK;
1494 qopr |= set;
1495
1496 out:
1497 pci_quatech_wqopr(port, qopr);
1498 return clock;
1499 }
1500
pci_quatech_rs422(struct uart_8250_port * port)1501 static int pci_quatech_rs422(struct uart_8250_port *port)
1502 {
1503 u8 qmcr;
1504 int rs422 = 0;
1505
1506 if (!pci_quatech_has_qmcr(port))
1507 return 0;
1508 qmcr = pci_quatech_rqmcr(port);
1509 pci_quatech_wqmcr(port, 0xFF);
1510 if (pci_quatech_rqmcr(port))
1511 rs422 = 1;
1512 pci_quatech_wqmcr(port, qmcr);
1513 return rs422;
1514 }
1515
pci_quatech_init(struct pci_dev * dev)1516 static int pci_quatech_init(struct pci_dev *dev)
1517 {
1518 const struct pci_device_id *match;
1519 bool amcc = false;
1520
1521 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1522 return serial_8250_warn_need_ioport(dev);
1523
1524 match = pci_match_id(quatech_cards, dev);
1525 if (match)
1526 amcc = match->driver_data;
1527 else
1528 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1529
1530 if (amcc) {
1531 unsigned long base = pci_resource_start(dev, 0);
1532 if (base) {
1533 u32 tmp;
1534
1535 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1536 tmp = inl(base + 0x3c);
1537 outl(tmp | 0x01000000, base + 0x3c);
1538 outl(tmp & ~0x01000000, base + 0x3c);
1539 }
1540 }
1541 return 0;
1542 }
1543
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1544 static int pci_quatech_setup(struct serial_private *priv,
1545 const struct pciserial_board *board,
1546 struct uart_8250_port *port, int idx)
1547 {
1548 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1549 return serial_8250_warn_need_ioport(priv->dev);
1550
1551 /* Needed by pci_quatech calls below */
1552 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1553 /* Set up the clocking */
1554 port->port.uartclk = pci_quatech_clock(port);
1555 /* For now just warn about RS422 */
1556 if (pci_quatech_rs422(port))
1557 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1558 return pci_default_setup(priv, board, port, idx);
1559 }
1560
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1561 static int pci_default_setup(struct serial_private *priv,
1562 const struct pciserial_board *board,
1563 struct uart_8250_port *port, int idx)
1564 {
1565 unsigned int bar, offset = board->first_offset, maxnr;
1566
1567 bar = FL_GET_BASE(board->flags);
1568 if (board->flags & FL_BASE_BARS)
1569 bar += idx;
1570 else
1571 offset += idx * board->uart_offset;
1572
1573 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1574 (board->reg_shift + 3);
1575
1576 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1577 return 1;
1578
1579 return setup_port(priv, port, bar, offset, board->reg_shift);
1580 }
1581
1582 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1583 ce4100_serial_setup(struct serial_private *priv,
1584 const struct pciserial_board *board,
1585 struct uart_8250_port *port, int idx)
1586 {
1587 int ret;
1588
1589 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1590 port->port.iotype = UPIO_MEM32;
1591 port->port.type = PORT_XSCALE;
1592 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1593 port->port.regshift = 2;
1594
1595 return ret;
1596 }
1597
1598 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1599 pci_omegapci_setup(struct serial_private *priv,
1600 const struct pciserial_board *board,
1601 struct uart_8250_port *port, int idx)
1602 {
1603 return setup_port(priv, port, 2, idx * 8, 0);
1604 }
1605
1606 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1607 pci_brcm_trumanage_setup(struct serial_private *priv,
1608 const struct pciserial_board *board,
1609 struct uart_8250_port *port, int idx)
1610 {
1611 int ret = pci_default_setup(priv, board, port, idx);
1612
1613 port->port.type = PORT_BRCM_TRUMANAGE;
1614 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1615 return ret;
1616 }
1617
1618 /* RTS will control by MCR if this bit is 0 */
1619 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1620 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1621 #define FINTEK_RTS_INVERT BIT(5)
1622
1623 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1624 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
1625 struct serial_rs485 *rs485)
1626 {
1627 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1628 u8 setting;
1629 u8 *index = (u8 *) port->private_data;
1630
1631 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1632
1633 if (rs485->flags & SER_RS485_ENABLED) {
1634 /* Enable RTS H/W control mode */
1635 setting |= FINTEK_RTS_CONTROL_BY_HW;
1636
1637 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1638 /* RTS driving high on TX */
1639 setting &= ~FINTEK_RTS_INVERT;
1640 } else {
1641 /* RTS driving low on TX */
1642 setting |= FINTEK_RTS_INVERT;
1643 }
1644 } else {
1645 /* Disable RTS H/W control mode */
1646 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1647 }
1648
1649 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1650
1651 return 0;
1652 }
1653
1654 static const struct serial_rs485 pci_fintek_rs485_supported = {
1655 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
1656 /* F81504/508/512 does not support RTS delay before or after send */
1657 };
1658
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1659 static int pci_fintek_setup(struct serial_private *priv,
1660 const struct pciserial_board *board,
1661 struct uart_8250_port *port, int idx)
1662 {
1663 struct pci_dev *pdev = priv->dev;
1664 u8 *data;
1665 u8 config_base;
1666 u16 iobase;
1667
1668 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1669 return serial_8250_warn_need_ioport(pdev);
1670
1671 config_base = 0x40 + 0x08 * idx;
1672
1673 /* Get the io address from configuration space */
1674 pci_read_config_word(pdev, config_base + 4, &iobase);
1675
1676 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1677
1678 port->port.iotype = UPIO_PORT;
1679 port->port.iobase = iobase;
1680 port->port.rs485_config = pci_fintek_rs485_config;
1681 port->port.rs485_supported = pci_fintek_rs485_supported;
1682
1683 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1684 if (!data)
1685 return -ENOMEM;
1686
1687 /* preserve index in PCI configuration space */
1688 *data = idx;
1689 port->port.private_data = data;
1690
1691 return 0;
1692 }
1693
pci_fintek_init(struct pci_dev * dev)1694 static int pci_fintek_init(struct pci_dev *dev)
1695 {
1696 unsigned long iobase;
1697 u32 max_port, i;
1698 resource_size_t bar_data[3];
1699 u8 config_base;
1700 struct serial_private *priv = pci_get_drvdata(dev);
1701
1702 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1703 return serial_8250_warn_need_ioport(dev);
1704
1705 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1706 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1707 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1708 return -ENODEV;
1709
1710 switch (dev->device) {
1711 case 0x1104: /* 4 ports */
1712 case 0x1108: /* 8 ports */
1713 max_port = dev->device & 0xff;
1714 break;
1715 case 0x1112: /* 12 ports */
1716 max_port = 12;
1717 break;
1718 default:
1719 return -EINVAL;
1720 }
1721
1722 /* Get the io address dispatch from the BIOS */
1723 bar_data[0] = pci_resource_start(dev, 5);
1724 bar_data[1] = pci_resource_start(dev, 4);
1725 bar_data[2] = pci_resource_start(dev, 3);
1726
1727 for (i = 0; i < max_port; ++i) {
1728 /* UART0 configuration offset start from 0x40 */
1729 config_base = 0x40 + 0x08 * i;
1730
1731 /* Calculate Real IO Port */
1732 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1733
1734 /* Enable UART I/O port */
1735 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1736
1737 /* Select 128-byte FIFO and 8x FIFO threshold */
1738 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1739
1740 /* LSB UART */
1741 pci_write_config_byte(dev, config_base + 0x04,
1742 (u8)(iobase & 0xff));
1743
1744 /* MSB UART */
1745 pci_write_config_byte(dev, config_base + 0x05,
1746 (u8)((iobase & 0xff00) >> 8));
1747
1748 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1749
1750 if (!priv) {
1751 /* First init without port data
1752 * force init to RS232 Mode
1753 */
1754 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1755 }
1756 }
1757
1758 return max_port;
1759 }
1760
f815xxa_mem_serial_out(struct uart_port * p,unsigned int offset,u32 value)1761 static void f815xxa_mem_serial_out(struct uart_port *p, unsigned int offset, u32 value)
1762 {
1763 struct f815xxa_data *data = p->private_data;
1764 unsigned long flags;
1765
1766 spin_lock_irqsave(&data->lock, flags);
1767 writeb(value, p->membase + offset);
1768 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1769 spin_unlock_irqrestore(&data->lock, flags);
1770 }
1771
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1772 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1773 const struct pciserial_board *board,
1774 struct uart_8250_port *port, int idx)
1775 {
1776 struct pci_dev *pdev = priv->dev;
1777 struct f815xxa_data *data;
1778
1779 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1780 if (!data)
1781 return -ENOMEM;
1782
1783 data->idx = idx;
1784 spin_lock_init(&data->lock);
1785
1786 port->port.private_data = data;
1787 port->port.iotype = UPIO_MEM;
1788 port->port.flags |= UPF_IOREMAP;
1789 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1790 port->port.serial_out = f815xxa_mem_serial_out;
1791
1792 return 0;
1793 }
1794
pci_fintek_f815xxa_init(struct pci_dev * dev)1795 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1796 {
1797 u32 max_port, i;
1798 int config_base;
1799
1800 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1801 return -ENODEV;
1802
1803 switch (dev->device) {
1804 case 0x1204: /* 4 ports */
1805 case 0x1208: /* 8 ports */
1806 max_port = dev->device & 0xff;
1807 break;
1808 case 0x1212: /* 12 ports */
1809 max_port = 12;
1810 break;
1811 default:
1812 return -EINVAL;
1813 }
1814
1815 /* Set to mmio decode */
1816 pci_write_config_byte(dev, 0x209, 0x40);
1817
1818 for (i = 0; i < max_port; ++i) {
1819 /* UART0 configuration offset start from 0x2A0 */
1820 config_base = 0x2A0 + 0x08 * i;
1821
1822 /* Select 128-byte FIFO and 8x FIFO threshold */
1823 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1824
1825 /* Enable UART I/O port */
1826 pci_write_config_byte(dev, config_base + 0, 0x01);
1827 }
1828
1829 return max_port;
1830 }
1831
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1832 static int skip_tx_en_setup(struct serial_private *priv,
1833 const struct pciserial_board *board,
1834 struct uart_8250_port *port, int idx)
1835 {
1836 port->port.quirks |= UPQ_NO_TXEN_TEST;
1837 pci_dbg(priv->dev,
1838 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1839 priv->dev->vendor, priv->dev->device,
1840 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1841
1842 return pci_default_setup(priv, board, port, idx);
1843 }
1844
kt_handle_break(struct uart_port * p)1845 static void kt_handle_break(struct uart_port *p)
1846 {
1847 struct uart_8250_port *up = up_to_u8250p(p);
1848 /*
1849 * On receipt of a BI, serial device in Intel ME (Intel
1850 * management engine) needs to have its fifos cleared for sane
1851 * SOL (Serial Over Lan) output.
1852 */
1853 serial8250_clear_and_reinit_fifos(up);
1854 }
1855
kt_serial_in(struct uart_port * p,unsigned int offset)1856 static u32 kt_serial_in(struct uart_port *p, unsigned int offset)
1857 {
1858 struct uart_8250_port *up = up_to_u8250p(p);
1859 u32 val;
1860
1861 /*
1862 * When the Intel ME (management engine) gets reset its serial
1863 * port registers could return 0 momentarily. Functions like
1864 * serial8250_console_write, read and save the IER, perform
1865 * some operation and then restore it. In order to avoid
1866 * setting IER register inadvertently to 0, if the value read
1867 * is 0, double check with ier value in uart_8250_port and use
1868 * that instead. up->ier should be the same value as what is
1869 * currently configured.
1870 */
1871 val = inb(p->iobase + offset);
1872 if (offset == UART_IER) {
1873 if (val == 0)
1874 val = up->ier;
1875 }
1876 return val;
1877 }
1878
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1879 static int kt_serial_setup(struct serial_private *priv,
1880 const struct pciserial_board *board,
1881 struct uart_8250_port *port, int idx)
1882 {
1883 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1884 return serial_8250_warn_need_ioport(priv->dev);
1885
1886 port->port.flags |= UPF_BUG_THRE;
1887 port->port.serial_in = kt_serial_in;
1888 port->port.handle_break = kt_handle_break;
1889 return skip_tx_en_setup(priv, board, port, idx);
1890 }
1891
pci_eg20t_init(struct pci_dev * dev)1892 static int pci_eg20t_init(struct pci_dev *dev)
1893 {
1894 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1895 return -ENODEV;
1896 #else
1897 return 0;
1898 #endif
1899 }
1900
1901 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1902 pci_wch_ch353_setup(struct serial_private *priv,
1903 const struct pciserial_board *board,
1904 struct uart_8250_port *port, int idx)
1905 {
1906 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1907 return serial_8250_warn_need_ioport(priv->dev);
1908
1909 port->port.flags |= UPF_FIXED_TYPE;
1910 port->port.type = PORT_16550A;
1911 return pci_default_setup(priv, board, port, idx);
1912 }
1913
1914 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1915 pci_wch_ch355_setup(struct serial_private *priv,
1916 const struct pciserial_board *board,
1917 struct uart_8250_port *port, int idx)
1918 {
1919 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1920 return serial_8250_warn_need_ioport(priv->dev);
1921
1922 port->port.flags |= UPF_FIXED_TYPE;
1923 port->port.type = PORT_16550A;
1924 return pci_default_setup(priv, board, port, idx);
1925 }
1926
1927 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1928 pci_wch_ch38x_setup(struct serial_private *priv,
1929 const struct pciserial_board *board,
1930 struct uart_8250_port *port, int idx)
1931 {
1932 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1933 return serial_8250_warn_need_ioport(priv->dev);
1934
1935 port->port.flags |= UPF_FIXED_TYPE;
1936 port->port.type = PORT_16850;
1937 return pci_default_setup(priv, board, port, idx);
1938 }
1939
1940
1941 #define CH384_XINT_ENABLE_REG 0xEB
1942 #define CH384_XINT_ENABLE_BIT 0x02
1943
pci_wch_ch38x_init(struct pci_dev * dev)1944 static int pci_wch_ch38x_init(struct pci_dev *dev)
1945 {
1946 int max_port;
1947 unsigned long iobase;
1948
1949 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1950 return serial_8250_warn_need_ioport(dev);
1951
1952 switch (dev->device) {
1953 case 0x3853: /* 8 ports */
1954 max_port = 8;
1955 break;
1956 default:
1957 return -EINVAL;
1958 }
1959
1960 iobase = pci_resource_start(dev, 0);
1961 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1962
1963 return max_port;
1964 }
1965
pci_wch_ch38x_exit(struct pci_dev * dev)1966 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1967 {
1968 unsigned long iobase;
1969
1970 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) {
1971 serial_8250_warn_need_ioport(dev);
1972 return;
1973 }
1974
1975 iobase = pci_resource_start(dev, 0);
1976 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1977 }
1978
1979
1980 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1981 pci_sunix_setup(struct serial_private *priv,
1982 const struct pciserial_board *board,
1983 struct uart_8250_port *port, int idx)
1984 {
1985 int bar;
1986 int offset;
1987
1988 port->port.flags |= UPF_FIXED_TYPE;
1989 port->port.type = PORT_SUNIX;
1990
1991 if (idx < 4) {
1992 bar = 0;
1993 offset = idx * board->uart_offset;
1994 } else {
1995 bar = 1;
1996 idx -= 4;
1997 idx = div_s64_rem(idx, 4, &offset);
1998 offset = idx * 64 + offset * board->uart_offset;
1999 }
2000
2001 return setup_port(priv, port, bar, offset, 0);
2002 }
2003
2004 #define MOXA_PUART_GPIO_EN 0x09
2005 #define MOXA_PUART_GPIO_OUT 0x0A
2006
2007 #define MOXA_GPIO_PIN2 BIT(2)
2008
2009 #define MOXA_RS232 0x00
2010 #define MOXA_RS422 0x01
2011 #define MOXA_RS485_4W 0x0B
2012 #define MOXA_RS485_2W 0x0F
2013 #define MOXA_UIR_OFFSET 0x04
2014 #define MOXA_EVEN_RS_MASK GENMASK(3, 0)
2015 #define MOXA_ODD_RS_MASK GENMASK(7, 4)
2016
2017 enum {
2018 MOXA_SUPP_RS232 = BIT(0),
2019 MOXA_SUPP_RS422 = BIT(1),
2020 MOXA_SUPP_RS485 = BIT(2),
2021 };
2022
moxa_get_nports(unsigned short device)2023 static unsigned short moxa_get_nports(unsigned short device)
2024 {
2025 switch (device) {
2026 case PCI_DEVICE_ID_MOXA_CP116E_A_A:
2027 case PCI_DEVICE_ID_MOXA_CP116E_A_B:
2028 return 8;
2029 }
2030
2031 return FIELD_GET(0x00F0, device);
2032 }
2033
pci_moxa_is_mini_pcie(unsigned short device)2034 static bool pci_moxa_is_mini_pcie(unsigned short device)
2035 {
2036 if (device == PCI_DEVICE_ID_MOXA_CP102N ||
2037 device == PCI_DEVICE_ID_MOXA_CP104N ||
2038 device == PCI_DEVICE_ID_MOXA_CP112N ||
2039 device == PCI_DEVICE_ID_MOXA_CP114N ||
2040 device == PCI_DEVICE_ID_MOXA_CP132N ||
2041 device == PCI_DEVICE_ID_MOXA_CP134N)
2042 return true;
2043
2044 return false;
2045 }
2046
pci_moxa_supported_rs(struct pci_dev * dev)2047 static unsigned int pci_moxa_supported_rs(struct pci_dev *dev)
2048 {
2049 switch (dev->device & 0x0F00) {
2050 case 0x0000:
2051 case 0x0600:
2052 return MOXA_SUPP_RS232;
2053 case 0x0100:
2054 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2055 case 0x0300:
2056 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2057 }
2058 return 0;
2059 }
2060
pci_moxa_set_interface(const struct pci_dev * dev,unsigned int port_idx,u8 mode)2061 static int pci_moxa_set_interface(const struct pci_dev *dev,
2062 unsigned int port_idx,
2063 u8 mode)
2064 {
2065 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2066 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
2067 u8 val;
2068
2069 val = inb(UIR_addr);
2070
2071 if (port_idx % 2) {
2072 val &= ~MOXA_ODD_RS_MASK;
2073 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
2074 } else {
2075 val &= ~MOXA_EVEN_RS_MASK;
2076 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
2077 }
2078 outb(val, UIR_addr);
2079
2080 return 0;
2081 }
2082
pci_moxa_init(struct pci_dev * dev)2083 static int pci_moxa_init(struct pci_dev *dev)
2084 {
2085 unsigned short device = dev->device;
2086 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2087 unsigned int i, num_ports = moxa_get_nports(device);
2088 u8 val, init_mode = MOXA_RS232;
2089
2090 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2091 return serial_8250_warn_need_ioport(dev);
2092
2093 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) {
2094 init_mode = MOXA_RS422;
2095 }
2096 for (i = 0; i < num_ports; ++i)
2097 pci_moxa_set_interface(dev, i, init_mode);
2098
2099 /*
2100 * Enable hardware buffer to prevent break signal output when system boots up.
2101 * This hardware buffer is only supported on Mini PCIe series.
2102 */
2103 if (pci_moxa_is_mini_pcie(device)) {
2104 /* Set GPIO direction */
2105 val = inb(iobar_addr + MOXA_PUART_GPIO_EN);
2106 val |= MOXA_GPIO_PIN2;
2107 outb(val, iobar_addr + MOXA_PUART_GPIO_EN);
2108 /* Enable low GPIO */
2109 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT);
2110 val &= ~MOXA_GPIO_PIN2;
2111 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT);
2112 }
2113
2114 return num_ports;
2115 }
2116
2117 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)2118 pci_moxa_setup(struct serial_private *priv,
2119 const struct pciserial_board *board,
2120 struct uart_8250_port *port, int idx)
2121 {
2122 unsigned int bar = FL_GET_BASE(board->flags);
2123 int offset;
2124
2125 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2126 return serial_8250_warn_need_ioport(priv->dev);
2127
2128 if (board->num_ports == 4 && idx == 3)
2129 offset = 7 * board->uart_offset;
2130 else
2131 offset = idx * board->uart_offset;
2132
2133 return setup_port(priv, port, bar, offset, 0);
2134 }
2135
2136 /*
2137 * Master list of serial port init/setup/exit quirks.
2138 * This does not describe the general nature of the port.
2139 * (ie, baud base, number and location of ports, etc)
2140 *
2141 * This list is ordered alphabetically by vendor then device.
2142 * Specific entries must come before more generic entries.
2143 */
2144 static struct pci_serial_quirk pci_serial_quirks[] = {
2145 /*
2146 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2147 */
2148 {
2149 .vendor = PCI_VENDOR_ID_AMCC,
2150 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2151 .subvendor = PCI_ANY_ID,
2152 .subdevice = PCI_ANY_ID,
2153 .setup = addidata_apci7800_setup,
2154 },
2155 /*
2156 * AFAVLAB cards - these may be called via parport_serial
2157 * It is not clear whether this applies to all products.
2158 */
2159 {
2160 .vendor = PCI_VENDOR_ID_AFAVLAB,
2161 .device = PCI_ANY_ID,
2162 .subvendor = PCI_ANY_ID,
2163 .subdevice = PCI_ANY_ID,
2164 .setup = afavlab_setup,
2165 },
2166 /*
2167 * HP Diva
2168 */
2169 {
2170 .vendor = PCI_VENDOR_ID_HP,
2171 .device = PCI_DEVICE_ID_HP_DIVA,
2172 .subvendor = PCI_ANY_ID,
2173 .subdevice = PCI_ANY_ID,
2174 .init = pci_hp_diva_init,
2175 .setup = pci_hp_diva_setup,
2176 },
2177 /*
2178 * HPE PCI serial device
2179 */
2180 {
2181 .vendor = PCI_VENDOR_ID_HP_3PAR,
2182 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2183 .subvendor = PCI_ANY_ID,
2184 .subdevice = PCI_ANY_ID,
2185 .setup = pci_hp_diva_setup,
2186 },
2187 /*
2188 * Intel
2189 */
2190 {
2191 .vendor = PCI_VENDOR_ID_INTEL,
2192 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2193 .subvendor = 0xe4bf,
2194 .subdevice = PCI_ANY_ID,
2195 .init = pci_inteli960ni_init,
2196 .setup = pci_default_setup,
2197 },
2198 {
2199 .vendor = PCI_VENDOR_ID_INTEL,
2200 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2201 .subvendor = PCI_ANY_ID,
2202 .subdevice = PCI_ANY_ID,
2203 .setup = skip_tx_en_setup,
2204 },
2205 {
2206 .vendor = PCI_VENDOR_ID_INTEL,
2207 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2208 .subvendor = PCI_ANY_ID,
2209 .subdevice = PCI_ANY_ID,
2210 .setup = skip_tx_en_setup,
2211 },
2212 {
2213 .vendor = PCI_VENDOR_ID_INTEL,
2214 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2215 .subvendor = PCI_ANY_ID,
2216 .subdevice = PCI_ANY_ID,
2217 .setup = skip_tx_en_setup,
2218 },
2219 {
2220 .vendor = PCI_VENDOR_ID_INTEL,
2221 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2222 .subvendor = PCI_ANY_ID,
2223 .subdevice = PCI_ANY_ID,
2224 .setup = ce4100_serial_setup,
2225 },
2226 {
2227 .vendor = PCI_VENDOR_ID_INTEL,
2228 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2229 .subvendor = PCI_ANY_ID,
2230 .subdevice = PCI_ANY_ID,
2231 .setup = kt_serial_setup,
2232 },
2233 /*
2234 * ITE
2235 */
2236 {
2237 .vendor = PCI_VENDOR_ID_ITE,
2238 .device = PCI_DEVICE_ID_ITE_8872,
2239 .subvendor = PCI_ANY_ID,
2240 .subdevice = PCI_ANY_ID,
2241 .init = pci_ite887x_init,
2242 .setup = pci_default_setup,
2243 .exit = pci_ite887x_exit,
2244 },
2245 /*
2246 * National Instruments
2247 */
2248 {
2249 .vendor = PCI_VENDOR_ID_NI,
2250 .device = PCI_DEVICE_ID_NI_PCI23216,
2251 .subvendor = PCI_ANY_ID,
2252 .subdevice = PCI_ANY_ID,
2253 .init = pci_ni8420_init,
2254 .setup = pci_default_setup,
2255 .exit = pci_ni8420_exit,
2256 },
2257 {
2258 .vendor = PCI_VENDOR_ID_NI,
2259 .device = PCI_DEVICE_ID_NI_PCI2328,
2260 .subvendor = PCI_ANY_ID,
2261 .subdevice = PCI_ANY_ID,
2262 .init = pci_ni8420_init,
2263 .setup = pci_default_setup,
2264 .exit = pci_ni8420_exit,
2265 },
2266 {
2267 .vendor = PCI_VENDOR_ID_NI,
2268 .device = PCI_DEVICE_ID_NI_PCI2324,
2269 .subvendor = PCI_ANY_ID,
2270 .subdevice = PCI_ANY_ID,
2271 .init = pci_ni8420_init,
2272 .setup = pci_default_setup,
2273 .exit = pci_ni8420_exit,
2274 },
2275 {
2276 .vendor = PCI_VENDOR_ID_NI,
2277 .device = PCI_DEVICE_ID_NI_PCI2322,
2278 .subvendor = PCI_ANY_ID,
2279 .subdevice = PCI_ANY_ID,
2280 .init = pci_ni8420_init,
2281 .setup = pci_default_setup,
2282 .exit = pci_ni8420_exit,
2283 },
2284 {
2285 .vendor = PCI_VENDOR_ID_NI,
2286 .device = PCI_DEVICE_ID_NI_PCI2324I,
2287 .subvendor = PCI_ANY_ID,
2288 .subdevice = PCI_ANY_ID,
2289 .init = pci_ni8420_init,
2290 .setup = pci_default_setup,
2291 .exit = pci_ni8420_exit,
2292 },
2293 {
2294 .vendor = PCI_VENDOR_ID_NI,
2295 .device = PCI_DEVICE_ID_NI_PCI2322I,
2296 .subvendor = PCI_ANY_ID,
2297 .subdevice = PCI_ANY_ID,
2298 .init = pci_ni8420_init,
2299 .setup = pci_default_setup,
2300 .exit = pci_ni8420_exit,
2301 },
2302 {
2303 .vendor = PCI_VENDOR_ID_NI,
2304 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2305 .subvendor = PCI_ANY_ID,
2306 .subdevice = PCI_ANY_ID,
2307 .init = pci_ni8420_init,
2308 .setup = pci_default_setup,
2309 .exit = pci_ni8420_exit,
2310 },
2311 {
2312 .vendor = PCI_VENDOR_ID_NI,
2313 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2314 .subvendor = PCI_ANY_ID,
2315 .subdevice = PCI_ANY_ID,
2316 .init = pci_ni8420_init,
2317 .setup = pci_default_setup,
2318 .exit = pci_ni8420_exit,
2319 },
2320 {
2321 .vendor = PCI_VENDOR_ID_NI,
2322 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2323 .subvendor = PCI_ANY_ID,
2324 .subdevice = PCI_ANY_ID,
2325 .init = pci_ni8420_init,
2326 .setup = pci_default_setup,
2327 .exit = pci_ni8420_exit,
2328 },
2329 {
2330 .vendor = PCI_VENDOR_ID_NI,
2331 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2332 .subvendor = PCI_ANY_ID,
2333 .subdevice = PCI_ANY_ID,
2334 .init = pci_ni8420_init,
2335 .setup = pci_default_setup,
2336 .exit = pci_ni8420_exit,
2337 },
2338 {
2339 .vendor = PCI_VENDOR_ID_NI,
2340 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2341 .subvendor = PCI_ANY_ID,
2342 .subdevice = PCI_ANY_ID,
2343 .init = pci_ni8420_init,
2344 .setup = pci_default_setup,
2345 .exit = pci_ni8420_exit,
2346 },
2347 {
2348 .vendor = PCI_VENDOR_ID_NI,
2349 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2350 .subvendor = PCI_ANY_ID,
2351 .subdevice = PCI_ANY_ID,
2352 .init = pci_ni8420_init,
2353 .setup = pci_default_setup,
2354 .exit = pci_ni8420_exit,
2355 },
2356 {
2357 .vendor = PCI_VENDOR_ID_NI,
2358 .device = PCI_ANY_ID,
2359 .subvendor = PCI_ANY_ID,
2360 .subdevice = PCI_ANY_ID,
2361 .init = pci_ni8430_init,
2362 .setup = pci_ni8430_setup,
2363 .exit = pci_ni8430_exit,
2364 },
2365 /* Quatech */
2366 {
2367 .vendor = PCI_VENDOR_ID_QUATECH,
2368 .device = PCI_ANY_ID,
2369 .subvendor = PCI_ANY_ID,
2370 .subdevice = PCI_ANY_ID,
2371 .init = pci_quatech_init,
2372 .setup = pci_quatech_setup,
2373 },
2374 /*
2375 * Panacom
2376 */
2377 {
2378 .vendor = PCI_VENDOR_ID_PANACOM,
2379 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2380 .subvendor = PCI_ANY_ID,
2381 .subdevice = PCI_ANY_ID,
2382 .init = pci_plx9050_init,
2383 .setup = pci_default_setup,
2384 .exit = pci_plx9050_exit,
2385 },
2386 {
2387 .vendor = PCI_VENDOR_ID_PANACOM,
2388 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2389 .subvendor = PCI_ANY_ID,
2390 .subdevice = PCI_ANY_ID,
2391 .init = pci_plx9050_init,
2392 .setup = pci_default_setup,
2393 .exit = pci_plx9050_exit,
2394 },
2395 /*
2396 * PLX
2397 */
2398 {
2399 .vendor = PCI_VENDOR_ID_PLX,
2400 .device = PCI_DEVICE_ID_PLX_9050,
2401 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2402 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2403 .init = pci_plx9050_init,
2404 .setup = pci_default_setup,
2405 .exit = pci_plx9050_exit,
2406 },
2407 {
2408 .vendor = PCI_VENDOR_ID_PLX,
2409 .device = PCI_DEVICE_ID_PLX_9050,
2410 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2411 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2412 .init = pci_plx9050_init,
2413 .setup = pci_default_setup,
2414 .exit = pci_plx9050_exit,
2415 },
2416 {
2417 .vendor = PCI_VENDOR_ID_PLX,
2418 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2419 .subvendor = PCI_VENDOR_ID_PLX,
2420 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2421 .init = pci_plx9050_init,
2422 .setup = pci_default_setup,
2423 .exit = pci_plx9050_exit,
2424 },
2425 /*
2426 * SBS Technologies, Inc., PMC-OCTALPRO 232
2427 */
2428 {
2429 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2430 .device = PCI_DEVICE_ID_OCTPRO,
2431 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2432 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2433 .init = sbs_init,
2434 .setup = sbs_setup,
2435 .exit = sbs_exit,
2436 },
2437 /*
2438 * SBS Technologies, Inc., PMC-OCTALPRO 422
2439 */
2440 {
2441 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2442 .device = PCI_DEVICE_ID_OCTPRO,
2443 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2444 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2445 .init = sbs_init,
2446 .setup = sbs_setup,
2447 .exit = sbs_exit,
2448 },
2449 /*
2450 * SBS Technologies, Inc., P-Octal 232
2451 */
2452 {
2453 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2454 .device = PCI_DEVICE_ID_OCTPRO,
2455 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2456 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2457 .init = sbs_init,
2458 .setup = sbs_setup,
2459 .exit = sbs_exit,
2460 },
2461 /*
2462 * SBS Technologies, Inc., P-Octal 422
2463 */
2464 {
2465 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2466 .device = PCI_DEVICE_ID_OCTPRO,
2467 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2468 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2469 .init = sbs_init,
2470 .setup = sbs_setup,
2471 .exit = sbs_exit,
2472 },
2473 /*
2474 * SIIG cards - these may be called via parport_serial
2475 */
2476 {
2477 .vendor = PCI_VENDOR_ID_SIIG,
2478 .device = PCI_ANY_ID,
2479 .subvendor = PCI_ANY_ID,
2480 .subdevice = PCI_ANY_ID,
2481 .init = pci_siig_init,
2482 .setup = pci_siig_setup,
2483 },
2484 /*
2485 * Titan cards
2486 */
2487 {
2488 .vendor = PCI_VENDOR_ID_TITAN,
2489 .device = PCI_DEVICE_ID_TITAN_400L,
2490 .subvendor = PCI_ANY_ID,
2491 .subdevice = PCI_ANY_ID,
2492 .setup = titan_400l_800l_setup,
2493 },
2494 {
2495 .vendor = PCI_VENDOR_ID_TITAN,
2496 .device = PCI_DEVICE_ID_TITAN_800L,
2497 .subvendor = PCI_ANY_ID,
2498 .subdevice = PCI_ANY_ID,
2499 .setup = titan_400l_800l_setup,
2500 },
2501 /*
2502 * Timedia cards
2503 */
2504 {
2505 .vendor = PCI_VENDOR_ID_TIMEDIA,
2506 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2507 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2508 .subdevice = PCI_ANY_ID,
2509 .probe = pci_timedia_probe,
2510 .init = pci_timedia_init,
2511 .setup = pci_timedia_setup,
2512 },
2513 {
2514 .vendor = PCI_VENDOR_ID_TIMEDIA,
2515 .device = PCI_ANY_ID,
2516 .subvendor = PCI_ANY_ID,
2517 .subdevice = PCI_ANY_ID,
2518 .setup = pci_timedia_setup,
2519 },
2520 /*
2521 * Sunix PCI serial boards
2522 */
2523 {
2524 .vendor = PCI_VENDOR_ID_SUNIX,
2525 .device = PCI_DEVICE_ID_SUNIX_1999,
2526 .subvendor = PCI_VENDOR_ID_SUNIX,
2527 .subdevice = PCI_ANY_ID,
2528 .setup = pci_sunix_setup,
2529 },
2530 /*
2531 * Xircom cards
2532 */
2533 {
2534 .vendor = PCI_VENDOR_ID_XIRCOM,
2535 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2536 .subvendor = PCI_ANY_ID,
2537 .subdevice = PCI_ANY_ID,
2538 .init = pci_xircom_init,
2539 .setup = pci_default_setup,
2540 },
2541 /*
2542 * Netmos cards - these may be called via parport_serial
2543 */
2544 {
2545 .vendor = PCI_VENDOR_ID_NETMOS,
2546 .device = PCI_ANY_ID,
2547 .subvendor = PCI_ANY_ID,
2548 .subdevice = PCI_ANY_ID,
2549 .init = pci_netmos_init,
2550 .setup = pci_netmos_9900_setup,
2551 },
2552 {
2553 .vendor = PCIE_VENDOR_ID_ASIX,
2554 .device = PCI_ANY_ID,
2555 .subvendor = PCI_ANY_ID,
2556 .subdevice = PCI_ANY_ID,
2557 .init = pci_netmos_init,
2558 .setup = pci_netmos_9900_setup,
2559 },
2560 /*
2561 * EndRun Technologies
2562 */
2563 {
2564 .vendor = PCI_VENDOR_ID_ENDRUN,
2565 .device = PCI_ANY_ID,
2566 .subvendor = PCI_ANY_ID,
2567 .subdevice = PCI_ANY_ID,
2568 .init = pci_oxsemi_tornado_init,
2569 .setup = pci_default_setup,
2570 },
2571 /*
2572 * For Oxford Semiconductor Tornado based devices
2573 */
2574 {
2575 .vendor = PCI_VENDOR_ID_OXSEMI,
2576 .device = PCI_ANY_ID,
2577 .subvendor = PCI_ANY_ID,
2578 .subdevice = PCI_ANY_ID,
2579 .init = pci_oxsemi_tornado_init,
2580 .setup = pci_oxsemi_tornado_setup,
2581 },
2582 {
2583 .vendor = PCI_VENDOR_ID_MAINPINE,
2584 .device = PCI_ANY_ID,
2585 .subvendor = PCI_ANY_ID,
2586 .subdevice = PCI_ANY_ID,
2587 .init = pci_oxsemi_tornado_init,
2588 .setup = pci_oxsemi_tornado_setup,
2589 },
2590 {
2591 .vendor = PCI_VENDOR_ID_DIGI,
2592 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2593 .subvendor = PCI_SUBVENDOR_ID_IBM,
2594 .subdevice = PCI_ANY_ID,
2595 .init = pci_oxsemi_tornado_init,
2596 .setup = pci_oxsemi_tornado_setup,
2597 },
2598 /*
2599 * Brainboxes devices - all Oxsemi based
2600 */
2601 {
2602 .vendor = PCI_VENDOR_ID_INTASHIELD,
2603 .device = 0x4027,
2604 .subvendor = PCI_ANY_ID,
2605 .subdevice = PCI_ANY_ID,
2606 .init = pci_oxsemi_tornado_init,
2607 .setup = pci_oxsemi_tornado_setup,
2608 },
2609 {
2610 .vendor = PCI_VENDOR_ID_INTASHIELD,
2611 .device = 0x4028,
2612 .subvendor = PCI_ANY_ID,
2613 .subdevice = PCI_ANY_ID,
2614 .init = pci_oxsemi_tornado_init,
2615 .setup = pci_oxsemi_tornado_setup,
2616 },
2617 {
2618 .vendor = PCI_VENDOR_ID_INTASHIELD,
2619 .device = 0x4029,
2620 .subvendor = PCI_ANY_ID,
2621 .subdevice = PCI_ANY_ID,
2622 .init = pci_oxsemi_tornado_init,
2623 .setup = pci_oxsemi_tornado_setup,
2624 },
2625 {
2626 .vendor = PCI_VENDOR_ID_INTASHIELD,
2627 .device = 0x4019,
2628 .subvendor = PCI_ANY_ID,
2629 .subdevice = PCI_ANY_ID,
2630 .init = pci_oxsemi_tornado_init,
2631 .setup = pci_oxsemi_tornado_setup,
2632 },
2633 {
2634 .vendor = PCI_VENDOR_ID_INTASHIELD,
2635 .device = 0x4016,
2636 .subvendor = PCI_ANY_ID,
2637 .subdevice = PCI_ANY_ID,
2638 .init = pci_oxsemi_tornado_init,
2639 .setup = pci_oxsemi_tornado_setup,
2640 },
2641 {
2642 .vendor = PCI_VENDOR_ID_INTASHIELD,
2643 .device = 0x4015,
2644 .subvendor = PCI_ANY_ID,
2645 .subdevice = PCI_ANY_ID,
2646 .init = pci_oxsemi_tornado_init,
2647 .setup = pci_oxsemi_tornado_setup,
2648 },
2649 {
2650 .vendor = PCI_VENDOR_ID_INTASHIELD,
2651 .device = 0x400A,
2652 .subvendor = PCI_ANY_ID,
2653 .subdevice = PCI_ANY_ID,
2654 .init = pci_oxsemi_tornado_init,
2655 .setup = pci_oxsemi_tornado_setup,
2656 },
2657 {
2658 .vendor = PCI_VENDOR_ID_INTASHIELD,
2659 .device = 0x400E,
2660 .subvendor = PCI_ANY_ID,
2661 .subdevice = PCI_ANY_ID,
2662 .init = pci_oxsemi_tornado_init,
2663 .setup = pci_oxsemi_tornado_setup,
2664 },
2665 {
2666 .vendor = PCI_VENDOR_ID_INTASHIELD,
2667 .device = 0x400C,
2668 .subvendor = PCI_ANY_ID,
2669 .subdevice = PCI_ANY_ID,
2670 .init = pci_oxsemi_tornado_init,
2671 .setup = pci_oxsemi_tornado_setup,
2672 },
2673 {
2674 .vendor = PCI_VENDOR_ID_INTASHIELD,
2675 .device = 0x400B,
2676 .subvendor = PCI_ANY_ID,
2677 .subdevice = PCI_ANY_ID,
2678 .init = pci_oxsemi_tornado_init,
2679 .setup = pci_oxsemi_tornado_setup,
2680 },
2681 {
2682 .vendor = PCI_VENDOR_ID_INTASHIELD,
2683 .device = 0x400F,
2684 .subvendor = PCI_ANY_ID,
2685 .subdevice = PCI_ANY_ID,
2686 .init = pci_oxsemi_tornado_init,
2687 .setup = pci_oxsemi_tornado_setup,
2688 },
2689 {
2690 .vendor = PCI_VENDOR_ID_INTASHIELD,
2691 .device = 0x4010,
2692 .subvendor = PCI_ANY_ID,
2693 .subdevice = PCI_ANY_ID,
2694 .init = pci_oxsemi_tornado_init,
2695 .setup = pci_oxsemi_tornado_setup,
2696 },
2697 {
2698 .vendor = PCI_VENDOR_ID_INTASHIELD,
2699 .device = 0x4011,
2700 .subvendor = PCI_ANY_ID,
2701 .subdevice = PCI_ANY_ID,
2702 .init = pci_oxsemi_tornado_init,
2703 .setup = pci_oxsemi_tornado_setup,
2704 },
2705 {
2706 .vendor = PCI_VENDOR_ID_INTASHIELD,
2707 .device = 0x401D,
2708 .subvendor = PCI_ANY_ID,
2709 .subdevice = PCI_ANY_ID,
2710 .init = pci_oxsemi_tornado_init,
2711 .setup = pci_oxsemi_tornado_setup,
2712 },
2713 {
2714 .vendor = PCI_VENDOR_ID_INTASHIELD,
2715 .device = 0x401E,
2716 .subvendor = PCI_ANY_ID,
2717 .subdevice = PCI_ANY_ID,
2718 .init = pci_oxsemi_tornado_init,
2719 .setup = pci_oxsemi_tornado_setup,
2720 },
2721 {
2722 .vendor = PCI_VENDOR_ID_INTASHIELD,
2723 .device = 0x4013,
2724 .subvendor = PCI_ANY_ID,
2725 .subdevice = PCI_ANY_ID,
2726 .init = pci_oxsemi_tornado_init,
2727 .setup = pci_oxsemi_tornado_setup,
2728 },
2729 {
2730 .vendor = PCI_VENDOR_ID_INTASHIELD,
2731 .device = 0x4017,
2732 .subvendor = PCI_ANY_ID,
2733 .subdevice = PCI_ANY_ID,
2734 .init = pci_oxsemi_tornado_init,
2735 .setup = pci_oxsemi_tornado_setup,
2736 },
2737 {
2738 .vendor = PCI_VENDOR_ID_INTASHIELD,
2739 .device = 0x4018,
2740 .subvendor = PCI_ANY_ID,
2741 .subdevice = PCI_ANY_ID,
2742 .init = pci_oxsemi_tornado_init,
2743 .setup = pci_oxsemi_tornado_setup,
2744 },
2745 {
2746 .vendor = PCI_VENDOR_ID_INTASHIELD,
2747 .device = 0x4026,
2748 .subvendor = PCI_ANY_ID,
2749 .subdevice = PCI_ANY_ID,
2750 .init = pci_oxsemi_tornado_init,
2751 .setup = pci_oxsemi_tornado_setup,
2752 },
2753 {
2754 .vendor = PCI_VENDOR_ID_INTASHIELD,
2755 .device = 0x4021,
2756 .subvendor = PCI_ANY_ID,
2757 .subdevice = PCI_ANY_ID,
2758 .init = pci_oxsemi_tornado_init,
2759 .setup = pci_oxsemi_tornado_setup,
2760 },
2761 {
2762 .vendor = PCI_VENDOR_ID_INTEL,
2763 .device = 0x8811,
2764 .subvendor = PCI_ANY_ID,
2765 .subdevice = PCI_ANY_ID,
2766 .init = pci_eg20t_init,
2767 .setup = pci_default_setup,
2768 },
2769 {
2770 .vendor = PCI_VENDOR_ID_INTEL,
2771 .device = 0x8812,
2772 .subvendor = PCI_ANY_ID,
2773 .subdevice = PCI_ANY_ID,
2774 .init = pci_eg20t_init,
2775 .setup = pci_default_setup,
2776 },
2777 {
2778 .vendor = PCI_VENDOR_ID_INTEL,
2779 .device = 0x8813,
2780 .subvendor = PCI_ANY_ID,
2781 .subdevice = PCI_ANY_ID,
2782 .init = pci_eg20t_init,
2783 .setup = pci_default_setup,
2784 },
2785 {
2786 .vendor = PCI_VENDOR_ID_INTEL,
2787 .device = 0x8814,
2788 .subvendor = PCI_ANY_ID,
2789 .subdevice = PCI_ANY_ID,
2790 .init = pci_eg20t_init,
2791 .setup = pci_default_setup,
2792 },
2793 {
2794 .vendor = 0x10DB,
2795 .device = 0x8027,
2796 .subvendor = PCI_ANY_ID,
2797 .subdevice = PCI_ANY_ID,
2798 .init = pci_eg20t_init,
2799 .setup = pci_default_setup,
2800 },
2801 {
2802 .vendor = 0x10DB,
2803 .device = 0x8028,
2804 .subvendor = PCI_ANY_ID,
2805 .subdevice = PCI_ANY_ID,
2806 .init = pci_eg20t_init,
2807 .setup = pci_default_setup,
2808 },
2809 {
2810 .vendor = 0x10DB,
2811 .device = 0x8029,
2812 .subvendor = PCI_ANY_ID,
2813 .subdevice = PCI_ANY_ID,
2814 .init = pci_eg20t_init,
2815 .setup = pci_default_setup,
2816 },
2817 {
2818 .vendor = 0x10DB,
2819 .device = 0x800C,
2820 .subvendor = PCI_ANY_ID,
2821 .subdevice = PCI_ANY_ID,
2822 .init = pci_eg20t_init,
2823 .setup = pci_default_setup,
2824 },
2825 {
2826 .vendor = 0x10DB,
2827 .device = 0x800D,
2828 .subvendor = PCI_ANY_ID,
2829 .subdevice = PCI_ANY_ID,
2830 .init = pci_eg20t_init,
2831 .setup = pci_default_setup,
2832 },
2833 /*
2834 * Cronyx Omega PCI (PLX-chip based)
2835 */
2836 {
2837 .vendor = PCI_VENDOR_ID_PLX,
2838 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2839 .subvendor = PCI_ANY_ID,
2840 .subdevice = PCI_ANY_ID,
2841 .setup = pci_omegapci_setup,
2842 },
2843 /* WCH CH353 1S1P card (16550 clone) */
2844 {
2845 .vendor = PCI_VENDOR_ID_WCHCN,
2846 .device = PCI_DEVICE_ID_WCHCN_CH353_1S1P,
2847 .subvendor = PCI_ANY_ID,
2848 .subdevice = PCI_ANY_ID,
2849 .setup = pci_wch_ch353_setup,
2850 },
2851 /* WCH CH353 2S1P card (16550 clone) */
2852 {
2853 .vendor = PCI_VENDOR_ID_WCHCN,
2854 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1P,
2855 .subvendor = PCI_ANY_ID,
2856 .subdevice = PCI_ANY_ID,
2857 .setup = pci_wch_ch353_setup,
2858 },
2859 /* WCH CH353 4S card (16550 clone) */
2860 {
2861 .vendor = PCI_VENDOR_ID_WCHCN,
2862 .device = PCI_DEVICE_ID_WCHCN_CH353_4S,
2863 .subvendor = PCI_ANY_ID,
2864 .subdevice = PCI_ANY_ID,
2865 .setup = pci_wch_ch353_setup,
2866 },
2867 /* WCH CH353 2S1PF card (16550 clone) */
2868 {
2869 .vendor = PCI_VENDOR_ID_WCHCN,
2870 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
2871 .subvendor = PCI_ANY_ID,
2872 .subdevice = PCI_ANY_ID,
2873 .setup = pci_wch_ch353_setup,
2874 },
2875 /* WCH CH352 2S card (16550 clone) */
2876 {
2877 .vendor = PCI_VENDOR_ID_WCHCN,
2878 .device = PCI_DEVICE_ID_WCHCN_CH352_2S,
2879 .subvendor = PCI_ANY_ID,
2880 .subdevice = PCI_ANY_ID,
2881 .setup = pci_wch_ch353_setup,
2882 },
2883 /* WCH CH355 4S card (16550 clone) */
2884 {
2885 .vendor = PCI_VENDOR_ID_WCHCN,
2886 .device = PCI_DEVICE_ID_WCHCN_CH355_4S,
2887 .subvendor = PCI_ANY_ID,
2888 .subdevice = PCI_ANY_ID,
2889 .setup = pci_wch_ch355_setup,
2890 },
2891 /* WCH CH382 2S card (16850 clone) */
2892 {
2893 .vendor = PCI_VENDOR_ID_WCHIC,
2894 .device = PCI_DEVICE_ID_WCHIC_CH382_2S,
2895 .subvendor = PCI_ANY_ID,
2896 .subdevice = PCI_ANY_ID,
2897 .setup = pci_wch_ch38x_setup,
2898 },
2899 /* WCH CH382 2S1P card (16850 clone) */
2900 {
2901 .vendor = PCI_VENDOR_ID_WCHIC,
2902 .device = PCI_DEVICE_ID_WCHIC_CH382_2S1P,
2903 .subvendor = PCI_ANY_ID,
2904 .subdevice = PCI_ANY_ID,
2905 .setup = pci_wch_ch38x_setup,
2906 },
2907 /* WCH CH384 4S card (16850 clone) */
2908 {
2909 .vendor = PCI_VENDOR_ID_WCHIC,
2910 .device = PCI_DEVICE_ID_WCHIC_CH384_4S,
2911 .subvendor = PCI_ANY_ID,
2912 .subdevice = PCI_ANY_ID,
2913 .setup = pci_wch_ch38x_setup,
2914 },
2915 /* WCH CH384 8S card (16850 clone) */
2916 {
2917 .vendor = PCI_VENDOR_ID_WCHIC,
2918 .device = PCI_DEVICE_ID_WCHIC_CH384_8S,
2919 .subvendor = PCI_ANY_ID,
2920 .subdevice = PCI_ANY_ID,
2921 .init = pci_wch_ch38x_init,
2922 .exit = pci_wch_ch38x_exit,
2923 .setup = pci_wch_ch38x_setup,
2924 },
2925 /*
2926 * Broadcom TruManage (NetXtreme)
2927 */
2928 {
2929 .vendor = PCI_VENDOR_ID_BROADCOM,
2930 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2931 .subvendor = PCI_ANY_ID,
2932 .subdevice = PCI_ANY_ID,
2933 .setup = pci_brcm_trumanage_setup,
2934 },
2935 {
2936 .vendor = 0x1c29,
2937 .device = 0x1104,
2938 .subvendor = PCI_ANY_ID,
2939 .subdevice = PCI_ANY_ID,
2940 .setup = pci_fintek_setup,
2941 .init = pci_fintek_init,
2942 },
2943 {
2944 .vendor = 0x1c29,
2945 .device = 0x1108,
2946 .subvendor = PCI_ANY_ID,
2947 .subdevice = PCI_ANY_ID,
2948 .setup = pci_fintek_setup,
2949 .init = pci_fintek_init,
2950 },
2951 {
2952 .vendor = 0x1c29,
2953 .device = 0x1112,
2954 .subvendor = PCI_ANY_ID,
2955 .subdevice = PCI_ANY_ID,
2956 .setup = pci_fintek_setup,
2957 .init = pci_fintek_init,
2958 },
2959 /*
2960 * MOXA
2961 */
2962 {
2963 .vendor = PCI_VENDOR_ID_MOXA,
2964 .device = PCI_ANY_ID,
2965 .subvendor = PCI_ANY_ID,
2966 .subdevice = PCI_ANY_ID,
2967 .init = pci_moxa_init,
2968 .setup = pci_moxa_setup,
2969 },
2970 {
2971 .vendor = 0x1c29,
2972 .device = 0x1204,
2973 .subvendor = PCI_ANY_ID,
2974 .subdevice = PCI_ANY_ID,
2975 .setup = pci_fintek_f815xxa_setup,
2976 .init = pci_fintek_f815xxa_init,
2977 },
2978 {
2979 .vendor = 0x1c29,
2980 .device = 0x1208,
2981 .subvendor = PCI_ANY_ID,
2982 .subdevice = PCI_ANY_ID,
2983 .setup = pci_fintek_f815xxa_setup,
2984 .init = pci_fintek_f815xxa_init,
2985 },
2986 {
2987 .vendor = 0x1c29,
2988 .device = 0x1212,
2989 .subvendor = PCI_ANY_ID,
2990 .subdevice = PCI_ANY_ID,
2991 .setup = pci_fintek_f815xxa_setup,
2992 .init = pci_fintek_f815xxa_init,
2993 },
2994
2995 /*
2996 * Default "match everything" terminator entry
2997 */
2998 {
2999 .vendor = PCI_ANY_ID,
3000 .device = PCI_ANY_ID,
3001 .subvendor = PCI_ANY_ID,
3002 .subdevice = PCI_ANY_ID,
3003 .setup = pci_default_setup,
3004 }
3005 };
3006
quirk_id_matches(u32 quirk_id,u32 dev_id)3007 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
3008 {
3009 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
3010 }
3011
find_quirk(struct pci_dev * dev)3012 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
3013 {
3014 struct pci_serial_quirk *quirk;
3015
3016 for (quirk = pci_serial_quirks; ; quirk++)
3017 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
3018 quirk_id_matches(quirk->device, dev->device) &&
3019 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
3020 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
3021 break;
3022 return quirk;
3023 }
3024
3025 /*
3026 * This is the configuration table for all of the PCI serial boards
3027 * which we support. It is directly indexed by the pci_board_num_t enum
3028 * value, which is encoded in the pci_device_id PCI probe table's
3029 * driver_data member.
3030 *
3031 * The makeup of these names are:
3032 * pbn_bn{_bt}_n_baud{_offsetinhex}
3033 *
3034 * bn = PCI BAR number
3035 * bt = Index using PCI BARs
3036 * n = number of serial ports
3037 * baud = baud rate
3038 * offsetinhex = offset for each sequential port (in hex)
3039 *
3040 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
3041 *
3042 * Please note: in theory if n = 1, _bt infix should make no difference.
3043 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
3044 */
3045 enum pci_board_num_t {
3046 pbn_default = 0,
3047
3048 pbn_b0_1_115200,
3049 pbn_b0_2_115200,
3050 pbn_b0_4_115200,
3051 pbn_b0_5_115200,
3052 pbn_b0_8_115200,
3053
3054 pbn_b0_1_921600,
3055 pbn_b0_2_921600,
3056 pbn_b0_4_921600,
3057
3058 pbn_b0_2_1130000,
3059
3060 pbn_b0_4_1152000,
3061
3062 pbn_b0_4_1250000,
3063
3064 pbn_b0_2_1843200,
3065 pbn_b0_4_1843200,
3066
3067 pbn_b0_1_15625000,
3068
3069 pbn_b0_bt_1_115200,
3070 pbn_b0_bt_2_115200,
3071 pbn_b0_bt_4_115200,
3072 pbn_b0_bt_8_115200,
3073
3074 pbn_b0_bt_1_460800,
3075 pbn_b0_bt_2_460800,
3076 pbn_b0_bt_4_460800,
3077
3078 pbn_b0_bt_1_921600,
3079 pbn_b0_bt_2_921600,
3080 pbn_b0_bt_4_921600,
3081 pbn_b0_bt_8_921600,
3082
3083 pbn_b1_1_115200,
3084 pbn_b1_2_115200,
3085 pbn_b1_4_115200,
3086 pbn_b1_8_115200,
3087 pbn_b1_16_115200,
3088
3089 pbn_b1_1_921600,
3090 pbn_b1_2_921600,
3091 pbn_b1_4_921600,
3092 pbn_b1_8_921600,
3093
3094 pbn_b1_2_1250000,
3095
3096 pbn_b1_bt_1_115200,
3097 pbn_b1_bt_2_115200,
3098 pbn_b1_bt_4_115200,
3099
3100 pbn_b1_bt_2_921600,
3101
3102 pbn_b1_1_1382400,
3103 pbn_b1_2_1382400,
3104 pbn_b1_4_1382400,
3105 pbn_b1_8_1382400,
3106
3107 pbn_b2_1_115200,
3108 pbn_b2_2_115200,
3109 pbn_b2_4_115200,
3110 pbn_b2_8_115200,
3111
3112 pbn_b2_1_460800,
3113 pbn_b2_4_460800,
3114 pbn_b2_8_460800,
3115 pbn_b2_16_460800,
3116
3117 pbn_b2_1_921600,
3118 pbn_b2_4_921600,
3119 pbn_b2_8_921600,
3120
3121 pbn_b2_8_1152000,
3122
3123 pbn_b2_bt_1_115200,
3124 pbn_b2_bt_2_115200,
3125 pbn_b2_bt_4_115200,
3126
3127 pbn_b2_bt_2_921600,
3128 pbn_b2_bt_4_921600,
3129
3130 pbn_b3_2_115200,
3131 pbn_b3_4_115200,
3132 pbn_b3_8_115200,
3133
3134 pbn_b4_bt_2_921600,
3135 pbn_b4_bt_4_921600,
3136 pbn_b4_bt_8_921600,
3137
3138 /*
3139 * Board-specific versions.
3140 */
3141 pbn_panacom,
3142 pbn_panacom2,
3143 pbn_panacom4,
3144 pbn_plx_romulus,
3145 pbn_oxsemi,
3146 pbn_oxsemi_1_15625000,
3147 pbn_oxsemi_2_15625000,
3148 pbn_oxsemi_4_15625000,
3149 pbn_oxsemi_8_15625000,
3150 pbn_intel_i960,
3151 pbn_sgi_ioc3,
3152 pbn_computone_4,
3153 pbn_computone_6,
3154 pbn_computone_8,
3155 pbn_sbsxrsio,
3156 pbn_pasemi_1682M,
3157 pbn_ni8430_2,
3158 pbn_ni8430_4,
3159 pbn_ni8430_8,
3160 pbn_ni8430_16,
3161 pbn_ADDIDATA_PCIe_1_3906250,
3162 pbn_ADDIDATA_PCIe_2_3906250,
3163 pbn_ADDIDATA_PCIe_4_3906250,
3164 pbn_ADDIDATA_PCIe_8_3906250,
3165 pbn_ce4100_1_115200,
3166 pbn_omegapci,
3167 pbn_NETMOS9900_2s_115200,
3168 pbn_brcm_trumanage,
3169 pbn_fintek_4,
3170 pbn_fintek_8,
3171 pbn_fintek_12,
3172 pbn_fintek_F81504A,
3173 pbn_fintek_F81508A,
3174 pbn_fintek_F81512A,
3175 pbn_wch382_2,
3176 pbn_wch384_4,
3177 pbn_wch384_8,
3178 pbn_sunix_pci_1s,
3179 pbn_sunix_pci_2s,
3180 pbn_sunix_pci_4s,
3181 pbn_sunix_pci_8s,
3182 pbn_sunix_pci_16s,
3183 pbn_titan_1_4000000,
3184 pbn_titan_2_4000000,
3185 pbn_titan_4_4000000,
3186 pbn_titan_8_4000000,
3187 pbn_moxa_2,
3188 pbn_moxa_4,
3189 pbn_moxa_8,
3190 };
3191
3192 /*
3193 * uart_offset - the space between channels
3194 * reg_shift - describes how the UART registers are mapped
3195 * to PCI memory by the card.
3196 * For example IER register on SBS, Inc. PMC-OctPro is located at
3197 * offset 0x10 from the UART base, while UART_IER is defined as 1
3198 * in include/linux/serial_reg.h,
3199 * see first lines of serial_in() and serial_out() in 8250.c
3200 */
3201
3202 static struct pciserial_board pci_boards[] = {
3203 [pbn_default] = {
3204 .flags = FL_BASE0,
3205 .num_ports = 1,
3206 .base_baud = 115200,
3207 .uart_offset = 8,
3208 },
3209 [pbn_b0_1_115200] = {
3210 .flags = FL_BASE0,
3211 .num_ports = 1,
3212 .base_baud = 115200,
3213 .uart_offset = 8,
3214 },
3215 [pbn_b0_2_115200] = {
3216 .flags = FL_BASE0,
3217 .num_ports = 2,
3218 .base_baud = 115200,
3219 .uart_offset = 8,
3220 },
3221 [pbn_b0_4_115200] = {
3222 .flags = FL_BASE0,
3223 .num_ports = 4,
3224 .base_baud = 115200,
3225 .uart_offset = 8,
3226 },
3227 [pbn_b0_5_115200] = {
3228 .flags = FL_BASE0,
3229 .num_ports = 5,
3230 .base_baud = 115200,
3231 .uart_offset = 8,
3232 },
3233 [pbn_b0_8_115200] = {
3234 .flags = FL_BASE0,
3235 .num_ports = 8,
3236 .base_baud = 115200,
3237 .uart_offset = 8,
3238 },
3239 [pbn_b0_1_921600] = {
3240 .flags = FL_BASE0,
3241 .num_ports = 1,
3242 .base_baud = 921600,
3243 .uart_offset = 8,
3244 },
3245 [pbn_b0_2_921600] = {
3246 .flags = FL_BASE0,
3247 .num_ports = 2,
3248 .base_baud = 921600,
3249 .uart_offset = 8,
3250 },
3251 [pbn_b0_4_921600] = {
3252 .flags = FL_BASE0,
3253 .num_ports = 4,
3254 .base_baud = 921600,
3255 .uart_offset = 8,
3256 },
3257
3258 [pbn_b0_2_1130000] = {
3259 .flags = FL_BASE0,
3260 .num_ports = 2,
3261 .base_baud = 1130000,
3262 .uart_offset = 8,
3263 },
3264
3265 [pbn_b0_4_1152000] = {
3266 .flags = FL_BASE0,
3267 .num_ports = 4,
3268 .base_baud = 1152000,
3269 .uart_offset = 8,
3270 },
3271
3272 [pbn_b0_4_1250000] = {
3273 .flags = FL_BASE0,
3274 .num_ports = 4,
3275 .base_baud = 1250000,
3276 .uart_offset = 8,
3277 },
3278
3279 [pbn_b0_2_1843200] = {
3280 .flags = FL_BASE0,
3281 .num_ports = 2,
3282 .base_baud = 1843200,
3283 .uart_offset = 8,
3284 },
3285 [pbn_b0_4_1843200] = {
3286 .flags = FL_BASE0,
3287 .num_ports = 4,
3288 .base_baud = 1843200,
3289 .uart_offset = 8,
3290 },
3291
3292 [pbn_b0_1_15625000] = {
3293 .flags = FL_BASE0,
3294 .num_ports = 1,
3295 .base_baud = 15625000,
3296 .uart_offset = 8,
3297 },
3298
3299 [pbn_b0_bt_1_115200] = {
3300 .flags = FL_BASE0|FL_BASE_BARS,
3301 .num_ports = 1,
3302 .base_baud = 115200,
3303 .uart_offset = 8,
3304 },
3305 [pbn_b0_bt_2_115200] = {
3306 .flags = FL_BASE0|FL_BASE_BARS,
3307 .num_ports = 2,
3308 .base_baud = 115200,
3309 .uart_offset = 8,
3310 },
3311 [pbn_b0_bt_4_115200] = {
3312 .flags = FL_BASE0|FL_BASE_BARS,
3313 .num_ports = 4,
3314 .base_baud = 115200,
3315 .uart_offset = 8,
3316 },
3317 [pbn_b0_bt_8_115200] = {
3318 .flags = FL_BASE0|FL_BASE_BARS,
3319 .num_ports = 8,
3320 .base_baud = 115200,
3321 .uart_offset = 8,
3322 },
3323
3324 [pbn_b0_bt_1_460800] = {
3325 .flags = FL_BASE0|FL_BASE_BARS,
3326 .num_ports = 1,
3327 .base_baud = 460800,
3328 .uart_offset = 8,
3329 },
3330 [pbn_b0_bt_2_460800] = {
3331 .flags = FL_BASE0|FL_BASE_BARS,
3332 .num_ports = 2,
3333 .base_baud = 460800,
3334 .uart_offset = 8,
3335 },
3336 [pbn_b0_bt_4_460800] = {
3337 .flags = FL_BASE0|FL_BASE_BARS,
3338 .num_ports = 4,
3339 .base_baud = 460800,
3340 .uart_offset = 8,
3341 },
3342
3343 [pbn_b0_bt_1_921600] = {
3344 .flags = FL_BASE0|FL_BASE_BARS,
3345 .num_ports = 1,
3346 .base_baud = 921600,
3347 .uart_offset = 8,
3348 },
3349 [pbn_b0_bt_2_921600] = {
3350 .flags = FL_BASE0|FL_BASE_BARS,
3351 .num_ports = 2,
3352 .base_baud = 921600,
3353 .uart_offset = 8,
3354 },
3355 [pbn_b0_bt_4_921600] = {
3356 .flags = FL_BASE0|FL_BASE_BARS,
3357 .num_ports = 4,
3358 .base_baud = 921600,
3359 .uart_offset = 8,
3360 },
3361 [pbn_b0_bt_8_921600] = {
3362 .flags = FL_BASE0|FL_BASE_BARS,
3363 .num_ports = 8,
3364 .base_baud = 921600,
3365 .uart_offset = 8,
3366 },
3367
3368 [pbn_b1_1_115200] = {
3369 .flags = FL_BASE1,
3370 .num_ports = 1,
3371 .base_baud = 115200,
3372 .uart_offset = 8,
3373 },
3374 [pbn_b1_2_115200] = {
3375 .flags = FL_BASE1,
3376 .num_ports = 2,
3377 .base_baud = 115200,
3378 .uart_offset = 8,
3379 },
3380 [pbn_b1_4_115200] = {
3381 .flags = FL_BASE1,
3382 .num_ports = 4,
3383 .base_baud = 115200,
3384 .uart_offset = 8,
3385 },
3386 [pbn_b1_8_115200] = {
3387 .flags = FL_BASE1,
3388 .num_ports = 8,
3389 .base_baud = 115200,
3390 .uart_offset = 8,
3391 },
3392 [pbn_b1_16_115200] = {
3393 .flags = FL_BASE1,
3394 .num_ports = 16,
3395 .base_baud = 115200,
3396 .uart_offset = 8,
3397 },
3398
3399 [pbn_b1_1_921600] = {
3400 .flags = FL_BASE1,
3401 .num_ports = 1,
3402 .base_baud = 921600,
3403 .uart_offset = 8,
3404 },
3405 [pbn_b1_2_921600] = {
3406 .flags = FL_BASE1,
3407 .num_ports = 2,
3408 .base_baud = 921600,
3409 .uart_offset = 8,
3410 },
3411 [pbn_b1_4_921600] = {
3412 .flags = FL_BASE1,
3413 .num_ports = 4,
3414 .base_baud = 921600,
3415 .uart_offset = 8,
3416 },
3417 [pbn_b1_8_921600] = {
3418 .flags = FL_BASE1,
3419 .num_ports = 8,
3420 .base_baud = 921600,
3421 .uart_offset = 8,
3422 },
3423 [pbn_b1_2_1250000] = {
3424 .flags = FL_BASE1,
3425 .num_ports = 2,
3426 .base_baud = 1250000,
3427 .uart_offset = 8,
3428 },
3429
3430 [pbn_b1_bt_1_115200] = {
3431 .flags = FL_BASE1|FL_BASE_BARS,
3432 .num_ports = 1,
3433 .base_baud = 115200,
3434 .uart_offset = 8,
3435 },
3436 [pbn_b1_bt_2_115200] = {
3437 .flags = FL_BASE1|FL_BASE_BARS,
3438 .num_ports = 2,
3439 .base_baud = 115200,
3440 .uart_offset = 8,
3441 },
3442 [pbn_b1_bt_4_115200] = {
3443 .flags = FL_BASE1|FL_BASE_BARS,
3444 .num_ports = 4,
3445 .base_baud = 115200,
3446 .uart_offset = 8,
3447 },
3448
3449 [pbn_b1_bt_2_921600] = {
3450 .flags = FL_BASE1|FL_BASE_BARS,
3451 .num_ports = 2,
3452 .base_baud = 921600,
3453 .uart_offset = 8,
3454 },
3455
3456 [pbn_b1_1_1382400] = {
3457 .flags = FL_BASE1,
3458 .num_ports = 1,
3459 .base_baud = 1382400,
3460 .uart_offset = 8,
3461 },
3462 [pbn_b1_2_1382400] = {
3463 .flags = FL_BASE1,
3464 .num_ports = 2,
3465 .base_baud = 1382400,
3466 .uart_offset = 8,
3467 },
3468 [pbn_b1_4_1382400] = {
3469 .flags = FL_BASE1,
3470 .num_ports = 4,
3471 .base_baud = 1382400,
3472 .uart_offset = 8,
3473 },
3474 [pbn_b1_8_1382400] = {
3475 .flags = FL_BASE1,
3476 .num_ports = 8,
3477 .base_baud = 1382400,
3478 .uart_offset = 8,
3479 },
3480
3481 [pbn_b2_1_115200] = {
3482 .flags = FL_BASE2,
3483 .num_ports = 1,
3484 .base_baud = 115200,
3485 .uart_offset = 8,
3486 },
3487 [pbn_b2_2_115200] = {
3488 .flags = FL_BASE2,
3489 .num_ports = 2,
3490 .base_baud = 115200,
3491 .uart_offset = 8,
3492 },
3493 [pbn_b2_4_115200] = {
3494 .flags = FL_BASE2,
3495 .num_ports = 4,
3496 .base_baud = 115200,
3497 .uart_offset = 8,
3498 },
3499 [pbn_b2_8_115200] = {
3500 .flags = FL_BASE2,
3501 .num_ports = 8,
3502 .base_baud = 115200,
3503 .uart_offset = 8,
3504 },
3505
3506 [pbn_b2_1_460800] = {
3507 .flags = FL_BASE2,
3508 .num_ports = 1,
3509 .base_baud = 460800,
3510 .uart_offset = 8,
3511 },
3512 [pbn_b2_4_460800] = {
3513 .flags = FL_BASE2,
3514 .num_ports = 4,
3515 .base_baud = 460800,
3516 .uart_offset = 8,
3517 },
3518 [pbn_b2_8_460800] = {
3519 .flags = FL_BASE2,
3520 .num_ports = 8,
3521 .base_baud = 460800,
3522 .uart_offset = 8,
3523 },
3524 [pbn_b2_16_460800] = {
3525 .flags = FL_BASE2,
3526 .num_ports = 16,
3527 .base_baud = 460800,
3528 .uart_offset = 8,
3529 },
3530
3531 [pbn_b2_1_921600] = {
3532 .flags = FL_BASE2,
3533 .num_ports = 1,
3534 .base_baud = 921600,
3535 .uart_offset = 8,
3536 },
3537 [pbn_b2_4_921600] = {
3538 .flags = FL_BASE2,
3539 .num_ports = 4,
3540 .base_baud = 921600,
3541 .uart_offset = 8,
3542 },
3543 [pbn_b2_8_921600] = {
3544 .flags = FL_BASE2,
3545 .num_ports = 8,
3546 .base_baud = 921600,
3547 .uart_offset = 8,
3548 },
3549
3550 [pbn_b2_8_1152000] = {
3551 .flags = FL_BASE2,
3552 .num_ports = 8,
3553 .base_baud = 1152000,
3554 .uart_offset = 8,
3555 },
3556
3557 [pbn_b2_bt_1_115200] = {
3558 .flags = FL_BASE2|FL_BASE_BARS,
3559 .num_ports = 1,
3560 .base_baud = 115200,
3561 .uart_offset = 8,
3562 },
3563 [pbn_b2_bt_2_115200] = {
3564 .flags = FL_BASE2|FL_BASE_BARS,
3565 .num_ports = 2,
3566 .base_baud = 115200,
3567 .uart_offset = 8,
3568 },
3569 [pbn_b2_bt_4_115200] = {
3570 .flags = FL_BASE2|FL_BASE_BARS,
3571 .num_ports = 4,
3572 .base_baud = 115200,
3573 .uart_offset = 8,
3574 },
3575
3576 [pbn_b2_bt_2_921600] = {
3577 .flags = FL_BASE2|FL_BASE_BARS,
3578 .num_ports = 2,
3579 .base_baud = 921600,
3580 .uart_offset = 8,
3581 },
3582 [pbn_b2_bt_4_921600] = {
3583 .flags = FL_BASE2|FL_BASE_BARS,
3584 .num_ports = 4,
3585 .base_baud = 921600,
3586 .uart_offset = 8,
3587 },
3588
3589 [pbn_b3_2_115200] = {
3590 .flags = FL_BASE3,
3591 .num_ports = 2,
3592 .base_baud = 115200,
3593 .uart_offset = 8,
3594 },
3595 [pbn_b3_4_115200] = {
3596 .flags = FL_BASE3,
3597 .num_ports = 4,
3598 .base_baud = 115200,
3599 .uart_offset = 8,
3600 },
3601 [pbn_b3_8_115200] = {
3602 .flags = FL_BASE3,
3603 .num_ports = 8,
3604 .base_baud = 115200,
3605 .uart_offset = 8,
3606 },
3607
3608 [pbn_b4_bt_2_921600] = {
3609 .flags = FL_BASE4,
3610 .num_ports = 2,
3611 .base_baud = 921600,
3612 .uart_offset = 8,
3613 },
3614 [pbn_b4_bt_4_921600] = {
3615 .flags = FL_BASE4,
3616 .num_ports = 4,
3617 .base_baud = 921600,
3618 .uart_offset = 8,
3619 },
3620 [pbn_b4_bt_8_921600] = {
3621 .flags = FL_BASE4,
3622 .num_ports = 8,
3623 .base_baud = 921600,
3624 .uart_offset = 8,
3625 },
3626
3627 /*
3628 * Entries following this are board-specific.
3629 */
3630
3631 /*
3632 * Panacom - IOMEM
3633 */
3634 [pbn_panacom] = {
3635 .flags = FL_BASE2,
3636 .num_ports = 2,
3637 .base_baud = 921600,
3638 .uart_offset = 0x400,
3639 .reg_shift = 7,
3640 },
3641 [pbn_panacom2] = {
3642 .flags = FL_BASE2|FL_BASE_BARS,
3643 .num_ports = 2,
3644 .base_baud = 921600,
3645 .uart_offset = 0x400,
3646 .reg_shift = 7,
3647 },
3648 [pbn_panacom4] = {
3649 .flags = FL_BASE2|FL_BASE_BARS,
3650 .num_ports = 4,
3651 .base_baud = 921600,
3652 .uart_offset = 0x400,
3653 .reg_shift = 7,
3654 },
3655
3656 /* I think this entry is broken - the first_offset looks wrong --rmk */
3657 [pbn_plx_romulus] = {
3658 .flags = FL_BASE2,
3659 .num_ports = 4,
3660 .base_baud = 921600,
3661 .uart_offset = 8 << 2,
3662 .reg_shift = 2,
3663 .first_offset = 0x03,
3664 },
3665
3666 /*
3667 * This board uses the size of PCI Base region 0 to
3668 * signal now many ports are available
3669 */
3670 [pbn_oxsemi] = {
3671 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3672 .num_ports = 32,
3673 .base_baud = 115200,
3674 .uart_offset = 8,
3675 },
3676 [pbn_oxsemi_1_15625000] = {
3677 .flags = FL_BASE0,
3678 .num_ports = 1,
3679 .base_baud = 15625000,
3680 .uart_offset = 0x200,
3681 .first_offset = 0x1000,
3682 },
3683 [pbn_oxsemi_2_15625000] = {
3684 .flags = FL_BASE0,
3685 .num_ports = 2,
3686 .base_baud = 15625000,
3687 .uart_offset = 0x200,
3688 .first_offset = 0x1000,
3689 },
3690 [pbn_oxsemi_4_15625000] = {
3691 .flags = FL_BASE0,
3692 .num_ports = 4,
3693 .base_baud = 15625000,
3694 .uart_offset = 0x200,
3695 .first_offset = 0x1000,
3696 },
3697 [pbn_oxsemi_8_15625000] = {
3698 .flags = FL_BASE0,
3699 .num_ports = 8,
3700 .base_baud = 15625000,
3701 .uart_offset = 0x200,
3702 .first_offset = 0x1000,
3703 },
3704
3705
3706 /*
3707 * EKF addition for i960 Boards form EKF with serial port.
3708 * Max 256 ports.
3709 */
3710 [pbn_intel_i960] = {
3711 .flags = FL_BASE0,
3712 .num_ports = 32,
3713 .base_baud = 921600,
3714 .uart_offset = 8 << 2,
3715 .reg_shift = 2,
3716 .first_offset = 0x10000,
3717 },
3718 [pbn_sgi_ioc3] = {
3719 .flags = FL_BASE0|FL_NOIRQ,
3720 .num_ports = 1,
3721 .base_baud = 458333,
3722 .uart_offset = 8,
3723 .reg_shift = 0,
3724 .first_offset = 0x20178,
3725 },
3726
3727 /*
3728 * Computone - uses IOMEM.
3729 */
3730 [pbn_computone_4] = {
3731 .flags = FL_BASE0,
3732 .num_ports = 4,
3733 .base_baud = 921600,
3734 .uart_offset = 0x40,
3735 .reg_shift = 2,
3736 .first_offset = 0x200,
3737 },
3738 [pbn_computone_6] = {
3739 .flags = FL_BASE0,
3740 .num_ports = 6,
3741 .base_baud = 921600,
3742 .uart_offset = 0x40,
3743 .reg_shift = 2,
3744 .first_offset = 0x200,
3745 },
3746 [pbn_computone_8] = {
3747 .flags = FL_BASE0,
3748 .num_ports = 8,
3749 .base_baud = 921600,
3750 .uart_offset = 0x40,
3751 .reg_shift = 2,
3752 .first_offset = 0x200,
3753 },
3754 [pbn_sbsxrsio] = {
3755 .flags = FL_BASE0,
3756 .num_ports = 8,
3757 .base_baud = 460800,
3758 .uart_offset = 256,
3759 .reg_shift = 4,
3760 },
3761 /*
3762 * PA Semi PWRficient PA6T-1682M on-chip UART
3763 */
3764 [pbn_pasemi_1682M] = {
3765 .flags = FL_BASE0,
3766 .num_ports = 1,
3767 .base_baud = 8333333,
3768 },
3769 /*
3770 * National Instruments 843x
3771 */
3772 [pbn_ni8430_16] = {
3773 .flags = FL_BASE0,
3774 .num_ports = 16,
3775 .base_baud = 3686400,
3776 .uart_offset = 0x10,
3777 .first_offset = 0x800,
3778 },
3779 [pbn_ni8430_8] = {
3780 .flags = FL_BASE0,
3781 .num_ports = 8,
3782 .base_baud = 3686400,
3783 .uart_offset = 0x10,
3784 .first_offset = 0x800,
3785 },
3786 [pbn_ni8430_4] = {
3787 .flags = FL_BASE0,
3788 .num_ports = 4,
3789 .base_baud = 3686400,
3790 .uart_offset = 0x10,
3791 .first_offset = 0x800,
3792 },
3793 [pbn_ni8430_2] = {
3794 .flags = FL_BASE0,
3795 .num_ports = 2,
3796 .base_baud = 3686400,
3797 .uart_offset = 0x10,
3798 .first_offset = 0x800,
3799 },
3800 /*
3801 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3802 */
3803 [pbn_ADDIDATA_PCIe_1_3906250] = {
3804 .flags = FL_BASE0,
3805 .num_ports = 1,
3806 .base_baud = 3906250,
3807 .uart_offset = 0x200,
3808 .first_offset = 0x1000,
3809 },
3810 [pbn_ADDIDATA_PCIe_2_3906250] = {
3811 .flags = FL_BASE0,
3812 .num_ports = 2,
3813 .base_baud = 3906250,
3814 .uart_offset = 0x200,
3815 .first_offset = 0x1000,
3816 },
3817 [pbn_ADDIDATA_PCIe_4_3906250] = {
3818 .flags = FL_BASE0,
3819 .num_ports = 4,
3820 .base_baud = 3906250,
3821 .uart_offset = 0x200,
3822 .first_offset = 0x1000,
3823 },
3824 [pbn_ADDIDATA_PCIe_8_3906250] = {
3825 .flags = FL_BASE0,
3826 .num_ports = 8,
3827 .base_baud = 3906250,
3828 .uart_offset = 0x200,
3829 .first_offset = 0x1000,
3830 },
3831 [pbn_ce4100_1_115200] = {
3832 .flags = FL_BASE_BARS,
3833 .num_ports = 2,
3834 .base_baud = 921600,
3835 .reg_shift = 2,
3836 },
3837 [pbn_omegapci] = {
3838 .flags = FL_BASE0,
3839 .num_ports = 8,
3840 .base_baud = 115200,
3841 .uart_offset = 0x200,
3842 },
3843 [pbn_NETMOS9900_2s_115200] = {
3844 .flags = FL_BASE0,
3845 .num_ports = 2,
3846 .base_baud = 115200,
3847 },
3848 [pbn_brcm_trumanage] = {
3849 .flags = FL_BASE0,
3850 .num_ports = 1,
3851 .reg_shift = 2,
3852 .base_baud = 115200,
3853 },
3854 [pbn_fintek_4] = {
3855 .num_ports = 4,
3856 .uart_offset = 8,
3857 .base_baud = 115200,
3858 .first_offset = 0x40,
3859 },
3860 [pbn_fintek_8] = {
3861 .num_ports = 8,
3862 .uart_offset = 8,
3863 .base_baud = 115200,
3864 .first_offset = 0x40,
3865 },
3866 [pbn_fintek_12] = {
3867 .num_ports = 12,
3868 .uart_offset = 8,
3869 .base_baud = 115200,
3870 .first_offset = 0x40,
3871 },
3872 [pbn_fintek_F81504A] = {
3873 .num_ports = 4,
3874 .uart_offset = 8,
3875 .base_baud = 115200,
3876 },
3877 [pbn_fintek_F81508A] = {
3878 .num_ports = 8,
3879 .uart_offset = 8,
3880 .base_baud = 115200,
3881 },
3882 [pbn_fintek_F81512A] = {
3883 .num_ports = 12,
3884 .uart_offset = 8,
3885 .base_baud = 115200,
3886 },
3887 [pbn_wch382_2] = {
3888 .flags = FL_BASE0,
3889 .num_ports = 2,
3890 .base_baud = 115200,
3891 .uart_offset = 8,
3892 .first_offset = 0xC0,
3893 },
3894 [pbn_wch384_4] = {
3895 .flags = FL_BASE0,
3896 .num_ports = 4,
3897 .base_baud = 115200,
3898 .uart_offset = 8,
3899 .first_offset = 0xC0,
3900 },
3901 [pbn_wch384_8] = {
3902 .flags = FL_BASE0,
3903 .num_ports = 8,
3904 .base_baud = 115200,
3905 .uart_offset = 8,
3906 .first_offset = 0x00,
3907 },
3908 [pbn_sunix_pci_1s] = {
3909 .num_ports = 1,
3910 .base_baud = 921600,
3911 .uart_offset = 0x8,
3912 },
3913 [pbn_sunix_pci_2s] = {
3914 .num_ports = 2,
3915 .base_baud = 921600,
3916 .uart_offset = 0x8,
3917 },
3918 [pbn_sunix_pci_4s] = {
3919 .num_ports = 4,
3920 .base_baud = 921600,
3921 .uart_offset = 0x8,
3922 },
3923 [pbn_sunix_pci_8s] = {
3924 .num_ports = 8,
3925 .base_baud = 921600,
3926 .uart_offset = 0x8,
3927 },
3928 [pbn_sunix_pci_16s] = {
3929 .num_ports = 16,
3930 .base_baud = 921600,
3931 .uart_offset = 0x8,
3932 },
3933 [pbn_titan_1_4000000] = {
3934 .flags = FL_BASE0,
3935 .num_ports = 1,
3936 .base_baud = 4000000,
3937 .uart_offset = 0x200,
3938 .first_offset = 0x1000,
3939 },
3940 [pbn_titan_2_4000000] = {
3941 .flags = FL_BASE0,
3942 .num_ports = 2,
3943 .base_baud = 4000000,
3944 .uart_offset = 0x200,
3945 .first_offset = 0x1000,
3946 },
3947 [pbn_titan_4_4000000] = {
3948 .flags = FL_BASE0,
3949 .num_ports = 4,
3950 .base_baud = 4000000,
3951 .uart_offset = 0x200,
3952 .first_offset = 0x1000,
3953 },
3954 [pbn_titan_8_4000000] = {
3955 .flags = FL_BASE0,
3956 .num_ports = 8,
3957 .base_baud = 4000000,
3958 .uart_offset = 0x200,
3959 .first_offset = 0x1000,
3960 },
3961 [pbn_moxa_2] = {
3962 .flags = FL_BASE1,
3963 .num_ports = 2,
3964 .base_baud = 921600,
3965 .uart_offset = 0x200,
3966 },
3967 [pbn_moxa_4] = {
3968 .flags = FL_BASE1,
3969 .num_ports = 4,
3970 .base_baud = 921600,
3971 .uart_offset = 0x200,
3972 },
3973 [pbn_moxa_8] = {
3974 .flags = FL_BASE1,
3975 .num_ports = 8,
3976 .base_baud = 921600,
3977 .uart_offset = 0x200,
3978 },
3979 };
3980
3981 #define REPORT_CONFIG(option) \
3982 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3983 #define REPORT_8250_CONFIG(option) \
3984 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
3985 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3986
3987 static const struct pci_device_id blacklist[] = {
3988 /* softmodems */
3989 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3990 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3991 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3992
3993 /* multi-io cards handled by parport_serial */
3994 /* WCH CH353 2S1P */
3995 { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), },
3996 /* WCH CH353 1S1P */
3997 { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), },
3998 /* WCH CH382 2S1P */
3999 { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), },
4000
4001 /* Intel platforms with MID UART */
4002 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
4003 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
4004 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
4005 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
4006 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
4007 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
4008
4009 /* Intel platforms with DesignWare UART */
4010 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
4011 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
4012 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
4013 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
4014 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
4015 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
4016 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
4017 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
4018 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
4019 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
4020 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
4021 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
4022 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
4023
4024 /* Exar devices */
4025 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4026 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4027
4028 /* Pericom devices */
4029 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4030 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4031
4032 /* End of the black list */
4033 { }
4034 };
4035
serial_pci_is_class_communication(struct pci_dev * dev)4036 static int serial_pci_is_class_communication(struct pci_dev *dev)
4037 {
4038 /*
4039 * If it is not a communications device or the programming
4040 * interface is greater than 6, give up.
4041 */
4042 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
4043 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
4044 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
4045 (dev->class & 0xff) > 6)
4046 return -ENODEV;
4047
4048 return 0;
4049 }
4050
4051 /*
4052 * Given a complete unknown PCI device, try to use some heuristics to
4053 * guess what the configuration might be, based on the pitiful PCI
4054 * serial specs. Returns 0 on success, -ENODEV on failure.
4055 */
4056 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)4057 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
4058 {
4059 int num_iomem, num_port, first_port = -1, i;
4060 int rc;
4061
4062 rc = serial_pci_is_class_communication(dev);
4063 if (rc)
4064 return rc;
4065
4066 /*
4067 * Should we try to make guesses for multiport serial devices later?
4068 */
4069 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
4070 return -ENODEV;
4071
4072 num_iomem = num_port = 0;
4073 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4074 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4075 num_port++;
4076 if (first_port == -1)
4077 first_port = i;
4078 }
4079 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4080 num_iomem++;
4081 }
4082
4083 /*
4084 * If there is 1 or 0 iomem regions, and exactly one port,
4085 * use it. We guess the number of ports based on the IO
4086 * region size.
4087 */
4088 if (num_iomem <= 1 && num_port == 1) {
4089 board->flags = first_port;
4090 board->num_ports = pci_resource_len(dev, first_port) / 8;
4091 return 0;
4092 }
4093
4094 /*
4095 * Now guess if we've got a board which indexes by BARs.
4096 * Each IO BAR should be 8 bytes, and they should follow
4097 * consecutively.
4098 */
4099 first_port = -1;
4100 num_port = 0;
4101 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4102 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4103 pci_resource_len(dev, i) == 8 &&
4104 (first_port == -1 || (first_port + num_port) == i)) {
4105 num_port++;
4106 if (first_port == -1)
4107 first_port = i;
4108 }
4109 }
4110
4111 if (num_port > 1) {
4112 board->flags = first_port | FL_BASE_BARS;
4113 board->num_ports = num_port;
4114 return 0;
4115 }
4116
4117 return -ENODEV;
4118 }
4119
4120 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)4121 serial_pci_matches(const struct pciserial_board *board,
4122 const struct pciserial_board *guessed)
4123 {
4124 return
4125 board->num_ports == guessed->num_ports &&
4126 board->base_baud == guessed->base_baud &&
4127 board->uart_offset == guessed->uart_offset &&
4128 board->reg_shift == guessed->reg_shift &&
4129 board->first_offset == guessed->first_offset;
4130 }
4131
4132 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)4133 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4134 {
4135 struct uart_8250_port uart;
4136 struct serial_private *priv;
4137 struct pci_serial_quirk *quirk;
4138 int rc, nr_ports, i;
4139
4140 nr_ports = board->num_ports;
4141
4142 /*
4143 * Find an init and setup quirks.
4144 */
4145 quirk = find_quirk(dev);
4146
4147 /*
4148 * Run the new-style initialization function.
4149 * The initialization function returns:
4150 * <0 - error
4151 * 0 - use board->num_ports
4152 * >0 - number of ports
4153 */
4154 if (quirk->init) {
4155 rc = quirk->init(dev);
4156 if (rc < 0) {
4157 priv = ERR_PTR(rc);
4158 goto err_out;
4159 }
4160 if (rc)
4161 nr_ports = rc;
4162 }
4163
4164 priv = kzalloc_flex(*priv, line, nr_ports);
4165 if (!priv) {
4166 priv = ERR_PTR(-ENOMEM);
4167 goto err_deinit;
4168 }
4169
4170 priv->dev = dev;
4171 priv->quirk = quirk;
4172
4173 memset(&uart, 0, sizeof(uart));
4174 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4175 uart.port.uartclk = board->base_baud * 16;
4176
4177 if (board->flags & FL_NOIRQ) {
4178 uart.port.irq = 0;
4179 } else {
4180 if (pci_match_id(pci_use_msi, dev)) {
4181 pci_dbg(dev, "Using MSI(-X) interrupts\n");
4182 pci_set_master(dev);
4183 uart.port.flags &= ~UPF_SHARE_IRQ;
4184 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4185 } else {
4186 pci_dbg(dev, "Using legacy interrupts\n");
4187 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_INTX);
4188 }
4189 if (rc < 0) {
4190 kfree(priv);
4191 priv = ERR_PTR(rc);
4192 goto err_deinit;
4193 }
4194
4195 uart.port.irq = pci_irq_vector(dev, 0);
4196 }
4197
4198 uart.port.dev = &dev->dev;
4199
4200 for (i = 0; i < nr_ports; i++) {
4201 if (quirk->setup(priv, board, &uart, i))
4202 break;
4203
4204 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4205 uart.port.iobase, uart.port.irq, uart.port.iotype);
4206
4207 priv->line[i] = serial8250_register_8250_port(&uart);
4208 if (priv->line[i] < 0) {
4209 pci_err(dev,
4210 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4211 uart.port.iobase, uart.port.irq,
4212 uart.port.iotype, priv->line[i]);
4213 break;
4214 }
4215 }
4216 priv->nr = i;
4217 priv->board = board;
4218 return priv;
4219
4220 err_deinit:
4221 if (quirk->exit)
4222 quirk->exit(dev);
4223 err_out:
4224 return priv;
4225 }
4226 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4227
pciserial_detach_ports(struct serial_private * priv)4228 static void pciserial_detach_ports(struct serial_private *priv)
4229 {
4230 struct pci_serial_quirk *quirk;
4231 int i;
4232
4233 for (i = 0; i < priv->nr; i++)
4234 serial8250_unregister_port(priv->line[i]);
4235
4236 /*
4237 * Find the exit quirks.
4238 */
4239 quirk = find_quirk(priv->dev);
4240 if (quirk->exit)
4241 quirk->exit(priv->dev);
4242 }
4243
pciserial_remove_ports(struct serial_private * priv)4244 void pciserial_remove_ports(struct serial_private *priv)
4245 {
4246 pciserial_detach_ports(priv);
4247 kfree(priv);
4248 }
4249 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4250
pciserial_suspend_ports(struct serial_private * priv)4251 void pciserial_suspend_ports(struct serial_private *priv)
4252 {
4253 int i;
4254
4255 for (i = 0; i < priv->nr; i++)
4256 if (priv->line[i] >= 0)
4257 serial8250_suspend_port(priv->line[i]);
4258
4259 /*
4260 * Ensure that every init quirk is properly torn down
4261 */
4262 if (priv->quirk->exit)
4263 priv->quirk->exit(priv->dev);
4264 }
4265 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4266
pciserial_resume_ports(struct serial_private * priv)4267 void pciserial_resume_ports(struct serial_private *priv)
4268 {
4269 int i;
4270
4271 /*
4272 * Ensure that the board is correctly configured.
4273 */
4274 if (priv->quirk->init)
4275 priv->quirk->init(priv->dev);
4276
4277 for (i = 0; i < priv->nr; i++)
4278 if (priv->line[i] >= 0)
4279 serial8250_resume_port(priv->line[i]);
4280 }
4281 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4282
4283 /*
4284 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4285 * to the arrangement of serial ports on a PCI card.
4286 */
4287 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4288 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4289 {
4290 struct pci_serial_quirk *quirk;
4291 struct serial_private *priv;
4292 const struct pciserial_board *board;
4293 const struct pci_device_id *exclude;
4294 struct pciserial_board tmp;
4295 int rc;
4296
4297 quirk = find_quirk(dev);
4298 if (quirk->probe) {
4299 rc = quirk->probe(dev);
4300 if (rc)
4301 return rc;
4302 }
4303
4304 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4305 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4306 return -EINVAL;
4307 }
4308
4309 board = &pci_boards[ent->driver_data];
4310
4311 exclude = pci_match_id(blacklist, dev);
4312 if (exclude) {
4313 if (exclude->driver_data)
4314 pci_warn(dev, "ignoring port, enable %s to handle\n",
4315 (const char *)exclude->driver_data);
4316 return -ENODEV;
4317 }
4318
4319 rc = pcim_enable_device(dev);
4320 pci_save_state(dev);
4321 if (rc)
4322 return rc;
4323
4324 if (ent->driver_data == pbn_default) {
4325 /*
4326 * Use a copy of the pci_board entry for this;
4327 * avoid changing entries in the table.
4328 */
4329 memcpy(&tmp, board, sizeof(struct pciserial_board));
4330 board = &tmp;
4331
4332 /*
4333 * We matched one of our class entries. Try to
4334 * determine the parameters of this board.
4335 */
4336 rc = serial_pci_guess_board(dev, &tmp);
4337 if (rc)
4338 return rc;
4339 } else {
4340 /*
4341 * We matched an explicit entry. If we are able to
4342 * detect this boards settings with our heuristic,
4343 * then we no longer need this entry.
4344 */
4345 memcpy(&tmp, &pci_boards[pbn_default],
4346 sizeof(struct pciserial_board));
4347 rc = serial_pci_guess_board(dev, &tmp);
4348 if (rc == 0 && serial_pci_matches(board, &tmp))
4349 moan_device("Redundant entry in serial pci_table.",
4350 dev);
4351 }
4352
4353 priv = pciserial_init_ports(dev, board);
4354 if (IS_ERR(priv))
4355 return PTR_ERR(priv);
4356
4357 pci_set_drvdata(dev, priv);
4358 return 0;
4359 }
4360
pciserial_remove_one(struct pci_dev * dev)4361 static void pciserial_remove_one(struct pci_dev *dev)
4362 {
4363 struct serial_private *priv = pci_get_drvdata(dev);
4364
4365 pciserial_remove_ports(priv);
4366 }
4367
4368 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4369 static int pciserial_suspend_one(struct device *dev)
4370 {
4371 struct serial_private *priv = dev_get_drvdata(dev);
4372
4373 if (priv)
4374 pciserial_suspend_ports(priv);
4375
4376 return 0;
4377 }
4378
pciserial_resume_one(struct device * dev)4379 static int pciserial_resume_one(struct device *dev)
4380 {
4381 struct pci_dev *pdev = to_pci_dev(dev);
4382 struct serial_private *priv = pci_get_drvdata(pdev);
4383 int err;
4384
4385 if (priv) {
4386 /*
4387 * The device may have been disabled. Re-enable it.
4388 */
4389 err = pci_enable_device(pdev);
4390 /* FIXME: We cannot simply error out here */
4391 if (err)
4392 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4393 pciserial_resume_ports(priv);
4394 }
4395 return 0;
4396 }
4397 #endif
4398
4399 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4400 pciserial_resume_one);
4401
4402 static const struct pci_device_id serial_pci_tbl[] = {
4403 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4404 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4405 pbn_b0_4_921600 },
4406 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4407 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4408 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4409 pbn_b2_8_921600 },
4410 /* Advantech also use 0x3618 and 0xf618 */
4411 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4412 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4413 pbn_b0_4_921600 },
4414 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4415 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4416 pbn_b0_4_921600 },
4417 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4418 PCI_SUBVENDOR_ID_CONNECT_TECH,
4419 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4420 pbn_b1_8_1382400 },
4421 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4422 PCI_SUBVENDOR_ID_CONNECT_TECH,
4423 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4424 pbn_b1_4_1382400 },
4425 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4426 PCI_SUBVENDOR_ID_CONNECT_TECH,
4427 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4428 pbn_b1_2_1382400 },
4429 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4430 PCI_SUBVENDOR_ID_CONNECT_TECH,
4431 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4432 pbn_b1_8_1382400 },
4433 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4434 PCI_SUBVENDOR_ID_CONNECT_TECH,
4435 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4436 pbn_b1_4_1382400 },
4437 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4438 PCI_SUBVENDOR_ID_CONNECT_TECH,
4439 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4440 pbn_b1_2_1382400 },
4441 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4442 PCI_SUBVENDOR_ID_CONNECT_TECH,
4443 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4444 pbn_b1_8_921600 },
4445 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4446 PCI_SUBVENDOR_ID_CONNECT_TECH,
4447 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4448 pbn_b1_8_921600 },
4449 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4450 PCI_SUBVENDOR_ID_CONNECT_TECH,
4451 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4452 pbn_b1_4_921600 },
4453 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4454 PCI_SUBVENDOR_ID_CONNECT_TECH,
4455 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4456 pbn_b1_4_921600 },
4457 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4458 PCI_SUBVENDOR_ID_CONNECT_TECH,
4459 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4460 pbn_b1_2_921600 },
4461 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4462 PCI_SUBVENDOR_ID_CONNECT_TECH,
4463 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4464 pbn_b1_8_921600 },
4465 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4466 PCI_SUBVENDOR_ID_CONNECT_TECH,
4467 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4468 pbn_b1_8_921600 },
4469 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4470 PCI_SUBVENDOR_ID_CONNECT_TECH,
4471 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4472 pbn_b1_4_921600 },
4473 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4474 PCI_SUBVENDOR_ID_CONNECT_TECH,
4475 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4476 pbn_b1_2_1250000 },
4477 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4478 PCI_SUBVENDOR_ID_CONNECT_TECH,
4479 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4480 pbn_b0_2_1843200 },
4481 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4482 PCI_SUBVENDOR_ID_CONNECT_TECH,
4483 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4484 pbn_b0_4_1843200 },
4485 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4486 PCI_VENDOR_ID_AFAVLAB,
4487 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4488 pbn_b0_4_1152000 },
4489 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 pbn_b2_bt_1_115200 },
4492 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 pbn_b2_bt_2_115200 },
4495 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_b2_bt_4_115200 },
4498 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_b2_bt_2_115200 },
4501 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_b2_bt_4_115200 },
4504 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506 pbn_b2_8_115200 },
4507 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509 pbn_b2_8_460800 },
4510 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512 pbn_b2_8_115200 },
4513
4514 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 pbn_b2_bt_2_115200 },
4517 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519 pbn_b2_bt_2_921600 },
4520 /*
4521 * VScom SPCOM800, from sl@s.pl
4522 */
4523 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 pbn_b2_8_921600 },
4526 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528 pbn_b2_4_921600 },
4529 /* Unknown card - subdevice 0x1584 */
4530 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4531 PCI_VENDOR_ID_PLX,
4532 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4533 pbn_b2_4_115200 },
4534 /* Unknown card - subdevice 0x1588 */
4535 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4536 PCI_VENDOR_ID_PLX,
4537 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4538 pbn_b2_8_115200 },
4539 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4540 PCI_SUBVENDOR_ID_KEYSPAN,
4541 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4542 pbn_panacom },
4543 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 pbn_panacom4 },
4546 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_panacom2 },
4549 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4550 PCI_VENDOR_ID_ESDGMBH,
4551 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4552 pbn_b2_4_115200 },
4553 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4554 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4555 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4556 pbn_b2_4_460800 },
4557 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4558 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4559 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4560 pbn_b2_8_460800 },
4561 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4562 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4563 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4564 pbn_b2_16_460800 },
4565 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4566 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4567 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4568 pbn_b2_16_460800 },
4569 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4570 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4571 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4572 pbn_b2_4_460800 },
4573 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4574 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4575 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4576 pbn_b2_8_460800 },
4577 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4578 PCI_SUBVENDOR_ID_EXSYS,
4579 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4580 pbn_b2_4_115200 },
4581 /*
4582 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4583 * (Exoray@isys.ca)
4584 */
4585 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4586 0x10b5, 0x106a, 0, 0,
4587 pbn_plx_romulus },
4588 /*
4589 * Quatech cards. These actually have configurable clocks but for
4590 * now we just use the default.
4591 *
4592 * 100 series are RS232, 200 series RS422,
4593 */
4594 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b1_4_115200 },
4597 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_b1_2_115200 },
4600 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_b2_2_115200 },
4603 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b1_2_115200 },
4606 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_b2_2_115200 },
4609 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_b1_4_115200 },
4612 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_b1_8_115200 },
4615 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_b1_8_115200 },
4618 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_b1_4_115200 },
4621 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_b1_2_115200 },
4624 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_b1_4_115200 },
4627 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_b1_2_115200 },
4630 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_b2_4_115200 },
4633 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_b2_2_115200 },
4636 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_b2_1_115200 },
4639 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_b2_4_115200 },
4642 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_b2_2_115200 },
4645 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_b2_1_115200 },
4648 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_b0_8_115200 },
4651
4652 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4653 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4654 0, 0,
4655 pbn_b0_4_921600 },
4656 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4657 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4658 0, 0,
4659 pbn_b0_4_1152000 },
4660 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_b0_bt_2_921600 },
4663
4664 /*
4665 * The below card is a little controversial since it is the
4666 * subject of a PCI vendor/device ID clash. (See
4667 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4668 * For now just used the hex ID 0x950a.
4669 */
4670 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4671 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4672 0, 0, pbn_b0_2_115200 },
4673 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4674 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4675 0, 0, pbn_b0_2_115200 },
4676 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_b0_2_1130000 },
4679 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4680 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4681 pbn_b0_1_921600 },
4682 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_b0_4_115200 },
4685 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b0_bt_2_921600 },
4688 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_b2_8_1152000 },
4691
4692 /*
4693 * Oxford Semiconductor Inc. Tornado PCI express device range.
4694 */
4695 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 pbn_b0_1_15625000 },
4698 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 pbn_b0_1_15625000 },
4701 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703 pbn_oxsemi_1_15625000 },
4704 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4706 pbn_oxsemi_1_15625000 },
4707 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709 pbn_b0_1_15625000 },
4710 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4712 pbn_b0_1_15625000 },
4713 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715 pbn_oxsemi_1_15625000 },
4716 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718 pbn_oxsemi_1_15625000 },
4719 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721 pbn_b0_1_15625000 },
4722 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724 pbn_b0_1_15625000 },
4725 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727 pbn_b0_1_15625000 },
4728 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730 pbn_b0_1_15625000 },
4731 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 pbn_oxsemi_2_15625000 },
4734 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736 pbn_oxsemi_2_15625000 },
4737 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739 pbn_oxsemi_4_15625000 },
4740 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742 pbn_oxsemi_4_15625000 },
4743 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_oxsemi_8_15625000 },
4746 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 pbn_oxsemi_8_15625000 },
4749 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4751 pbn_oxsemi_1_15625000 },
4752 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754 pbn_oxsemi_1_15625000 },
4755 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757 pbn_oxsemi_1_15625000 },
4758 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 pbn_oxsemi_1_15625000 },
4761 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 pbn_oxsemi_1_15625000 },
4764 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_oxsemi_1_15625000 },
4767 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_oxsemi_1_15625000 },
4770 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772 pbn_oxsemi_1_15625000 },
4773 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775 pbn_oxsemi_1_15625000 },
4776 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778 pbn_oxsemi_1_15625000 },
4779 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 pbn_oxsemi_1_15625000 },
4782 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_oxsemi_1_15625000 },
4785 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 pbn_oxsemi_1_15625000 },
4788 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_oxsemi_1_15625000 },
4791 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 pbn_oxsemi_1_15625000 },
4794 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 pbn_oxsemi_1_15625000 },
4797 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_oxsemi_1_15625000 },
4800 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 pbn_oxsemi_1_15625000 },
4803 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 pbn_oxsemi_1_15625000 },
4806 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808 pbn_oxsemi_1_15625000 },
4809 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 pbn_oxsemi_1_15625000 },
4812 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814 pbn_oxsemi_1_15625000 },
4815 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817 pbn_oxsemi_1_15625000 },
4818 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820 pbn_oxsemi_1_15625000 },
4821 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823 pbn_oxsemi_1_15625000 },
4824 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826 pbn_oxsemi_1_15625000 },
4827 /*
4828 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4829 */
4830 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4831 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4832 pbn_oxsemi_1_15625000 },
4833 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4834 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4835 pbn_oxsemi_2_15625000 },
4836 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4837 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4838 pbn_oxsemi_4_15625000 },
4839 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4840 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4841 pbn_oxsemi_8_15625000 },
4842
4843 /*
4844 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4845 */
4846 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4847 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4848 pbn_oxsemi_2_15625000 },
4849 /*
4850 * EndRun Technologies. PCI express device range.
4851 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4852 */
4853 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4855 pbn_oxsemi_2_15625000 },
4856
4857 /*
4858 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4859 * from skokodyn@yahoo.com
4860 */
4861 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4862 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4863 pbn_sbsxrsio },
4864 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4865 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4866 pbn_sbsxrsio },
4867 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4868 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4869 pbn_sbsxrsio },
4870 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4871 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4872 pbn_sbsxrsio },
4873
4874 /*
4875 * Digitan DS560-558, from jimd@esoft.com
4876 */
4877 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879 pbn_b1_1_115200 },
4880
4881 /*
4882 * Titan Electronic cards
4883 * The 400L and 800L have a custom setup quirk.
4884 */
4885 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887 pbn_b0_1_921600 },
4888 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4890 pbn_b0_2_921600 },
4891 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893 pbn_b0_4_921600 },
4894 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 pbn_b0_4_921600 },
4897 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899 pbn_b1_1_921600 },
4900 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 pbn_b1_bt_2_921600 },
4903 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 pbn_b0_bt_4_921600 },
4906 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_b0_bt_8_921600 },
4909 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 pbn_b4_bt_2_921600 },
4912 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914 pbn_b4_bt_4_921600 },
4915 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917 pbn_b4_bt_8_921600 },
4918 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920 pbn_b0_4_921600 },
4921 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 pbn_b0_4_921600 },
4924 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926 pbn_b0_4_921600 },
4927 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929 pbn_titan_1_4000000 },
4930 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932 pbn_titan_2_4000000 },
4933 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935 pbn_titan_4_4000000 },
4936 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 pbn_titan_8_4000000 },
4939 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941 pbn_titan_2_4000000 },
4942 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_titan_2_4000000 },
4945 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 pbn_b0_bt_2_921600 },
4948 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 pbn_b0_4_921600 },
4951 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953 pbn_b0_4_921600 },
4954 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956 pbn_b0_4_921600 },
4957 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959 pbn_b0_4_921600 },
4960
4961 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963 pbn_b2_1_460800 },
4964 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4966 pbn_b2_1_460800 },
4967 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4969 pbn_b2_1_460800 },
4970 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4972 pbn_b2_bt_2_921600 },
4973 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 pbn_b2_bt_2_921600 },
4976 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 pbn_b2_bt_2_921600 },
4979 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981 pbn_b2_bt_4_921600 },
4982 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 pbn_b2_bt_4_921600 },
4985 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4987 pbn_b2_bt_4_921600 },
4988 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4990 pbn_b0_1_921600 },
4991 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993 pbn_b0_1_921600 },
4994 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 pbn_b0_1_921600 },
4997 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 pbn_b0_bt_2_921600 },
5000 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002 pbn_b0_bt_2_921600 },
5003 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005 pbn_b0_bt_2_921600 },
5006 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
5007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008 pbn_b0_bt_4_921600 },
5009 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
5010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011 pbn_b0_bt_4_921600 },
5012 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
5013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014 pbn_b0_bt_4_921600 },
5015 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
5016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5017 pbn_b0_bt_8_921600 },
5018 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
5019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020 pbn_b0_bt_8_921600 },
5021 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
5022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023 pbn_b0_bt_8_921600 },
5024
5025 /*
5026 * Computone devices submitted by Doug McNash dmcnash@computone.com
5027 */
5028 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5029 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
5030 0, 0, pbn_computone_4 },
5031 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5032 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
5033 0, 0, pbn_computone_8 },
5034 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5035 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
5036 0, 0, pbn_computone_6 },
5037
5038 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
5039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5040 pbn_oxsemi },
5041 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
5042 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5043 pbn_b0_bt_1_921600 },
5044
5045 /*
5046 * Sunix PCI serial boards
5047 */
5048 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5049 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
5050 pbn_sunix_pci_1s },
5051 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5052 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
5053 pbn_sunix_pci_2s },
5054 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5055 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
5056 pbn_sunix_pci_4s },
5057 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5058 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
5059 pbn_sunix_pci_4s },
5060 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5061 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
5062 pbn_sunix_pci_8s },
5063 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5064 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
5065 pbn_sunix_pci_8s },
5066 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5067 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
5068 pbn_sunix_pci_16s },
5069
5070 /*
5071 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5072 */
5073 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5075 pbn_b0_bt_8_115200 },
5076 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5078 pbn_b0_bt_8_115200 },
5079
5080 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5082 pbn_b0_bt_2_115200 },
5083 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5085 pbn_b0_bt_2_115200 },
5086 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5088 pbn_b0_bt_2_115200 },
5089 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5091 pbn_b0_bt_4_460800 },
5092 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5094 pbn_b0_bt_4_460800 },
5095 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5097 pbn_b0_bt_2_460800 },
5098 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5100 pbn_b0_bt_2_460800 },
5101 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5103 pbn_b0_bt_2_460800 },
5104 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5106 pbn_b0_bt_1_115200 },
5107 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5109 pbn_b0_bt_1_460800 },
5110
5111 /*
5112 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5113 * Cards are identified by their subsystem vendor IDs, which
5114 * (in hex) match the model number.
5115 *
5116 * Note that JC140x are RS422/485 cards which require ox950
5117 * ACR = 0x10, and as such are not currently fully supported.
5118 */
5119 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5120 0x1204, 0x0004, 0, 0,
5121 pbn_b0_4_921600 },
5122 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5123 0x1208, 0x0004, 0, 0,
5124 pbn_b0_4_921600 },
5125 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5126 0x1402, 0x0002, 0, 0,
5127 pbn_b0_2_921600 }, */
5128 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5129 0x1404, 0x0004, 0, 0,
5130 pbn_b0_4_921600 }, */
5131 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5132 0x1208, 0x0004, 0, 0,
5133 pbn_b0_4_921600 },
5134
5135 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5136 0x1204, 0x0004, 0, 0,
5137 pbn_b0_4_921600 },
5138 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5139 0x1208, 0x0004, 0, 0,
5140 pbn_b0_4_921600 },
5141 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5142 0x1208, 0x0004, 0, 0,
5143 pbn_b0_4_921600 },
5144 /*
5145 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5146 */
5147 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5149 pbn_b1_1_1382400 },
5150
5151 /*
5152 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5153 */
5154 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5156 pbn_b1_1_1382400 },
5157
5158 /*
5159 * RAStel 2 port modem, gerg@moreton.com.au
5160 */
5161 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5163 pbn_b2_bt_2_115200 },
5164
5165 /*
5166 * EKF addition for i960 Boards form EKF with serial port
5167 */
5168 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5169 0xE4BF, PCI_ANY_ID, 0, 0,
5170 pbn_intel_i960 },
5171
5172 /*
5173 * Xircom Cardbus/Ethernet combos
5174 */
5175 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5177 pbn_b0_1_115200 },
5178 /*
5179 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5180 */
5181 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5183 pbn_b0_1_115200 },
5184
5185 /*
5186 * Untested PCI modems, sent in from various folks...
5187 */
5188
5189 /*
5190 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5191 */
5192 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5193 0x1048, 0x1500, 0, 0,
5194 pbn_b1_1_115200 },
5195
5196 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5197 0xFF00, 0, 0, 0,
5198 pbn_sgi_ioc3 },
5199
5200 /*
5201 * HP Diva card
5202 */
5203 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5204 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5205 pbn_b1_1_115200 },
5206 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5208 pbn_b0_5_115200 },
5209 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5211 pbn_b2_1_115200 },
5212 /* HPE PCI serial device */
5213 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5215 pbn_b1_1_115200 },
5216
5217 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5219 pbn_b3_2_115200 },
5220 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5222 pbn_b3_4_115200 },
5223 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5225 pbn_b3_8_115200 },
5226 /*
5227 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5228 */
5229 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5231 pbn_b0_1_115200 },
5232 /*
5233 * ITE
5234 */
5235 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5236 PCI_ANY_ID, PCI_ANY_ID,
5237 0, 0,
5238 pbn_b1_bt_1_115200 },
5239
5240 /*
5241 * IntaShield IS-100
5242 */
5243 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5245 pbn_b2_1_115200 },
5246 /*
5247 * IntaShield IS-200
5248 */
5249 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
5251 pbn_b2_2_115200 },
5252 /*
5253 * IntaShield IS-400
5254 */
5255 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5257 pbn_b2_4_115200 },
5258 /*
5259 * IntaShield IX-100
5260 */
5261 { PCI_VENDOR_ID_INTASHIELD, 0x4027,
5262 PCI_ANY_ID, PCI_ANY_ID,
5263 0, 0,
5264 pbn_oxsemi_1_15625000 },
5265 /*
5266 * IntaShield IX-200
5267 */
5268 { PCI_VENDOR_ID_INTASHIELD, 0x4028,
5269 PCI_ANY_ID, PCI_ANY_ID,
5270 0, 0,
5271 pbn_oxsemi_2_15625000 },
5272 /*
5273 * IntaShield IX-400
5274 */
5275 { PCI_VENDOR_ID_INTASHIELD, 0x4029,
5276 PCI_ANY_ID, PCI_ANY_ID,
5277 0, 0,
5278 pbn_oxsemi_4_15625000 },
5279 /* Brainboxes Devices */
5280 /*
5281 * Brainboxes UC-101
5282 */
5283 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5284 PCI_ANY_ID, PCI_ANY_ID,
5285 0, 0,
5286 pbn_b2_2_115200 },
5287 { PCI_VENDOR_ID_INTASHIELD, 0x0BA2,
5288 PCI_ANY_ID, PCI_ANY_ID,
5289 0, 0,
5290 pbn_b2_2_115200 },
5291 { PCI_VENDOR_ID_INTASHIELD, 0x0BA3,
5292 PCI_ANY_ID, PCI_ANY_ID,
5293 0, 0,
5294 pbn_b2_2_115200 },
5295 /*
5296 * Brainboxes UC-235/246
5297 */
5298 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5299 PCI_ANY_ID, PCI_ANY_ID,
5300 0, 0,
5301 pbn_b2_1_115200 },
5302 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5303 PCI_ANY_ID, PCI_ANY_ID,
5304 0, 0,
5305 pbn_b2_1_115200 },
5306 /*
5307 * Brainboxes UC-253/UC-734
5308 */
5309 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5310 PCI_ANY_ID, PCI_ANY_ID,
5311 0, 0,
5312 pbn_b2_2_115200 },
5313 /*
5314 * Brainboxes UC-260/271/701/756
5315 */
5316 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5317 PCI_ANY_ID, PCI_ANY_ID,
5318 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5319 pbn_b2_4_115200 },
5320 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5321 PCI_ANY_ID, PCI_ANY_ID,
5322 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5323 pbn_b2_4_115200 },
5324 /*
5325 * Brainboxes UC-268
5326 */
5327 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5328 PCI_ANY_ID, PCI_ANY_ID,
5329 0, 0,
5330 pbn_b2_4_115200 },
5331 /*
5332 * Brainboxes UC-275/279
5333 */
5334 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5335 PCI_ANY_ID, PCI_ANY_ID,
5336 0, 0,
5337 pbn_b2_8_115200 },
5338 /*
5339 * Brainboxes UC-302
5340 */
5341 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5342 PCI_ANY_ID, PCI_ANY_ID,
5343 0, 0,
5344 pbn_b2_2_115200 },
5345 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5346 PCI_ANY_ID, PCI_ANY_ID,
5347 0, 0,
5348 pbn_b2_2_115200 },
5349 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5350 PCI_ANY_ID, PCI_ANY_ID,
5351 0, 0,
5352 pbn_b2_2_115200 },
5353 /*
5354 * Brainboxes UC-310
5355 */
5356 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5357 PCI_ANY_ID, PCI_ANY_ID,
5358 0, 0,
5359 pbn_b2_2_115200 },
5360 /*
5361 * Brainboxes UC-313
5362 */
5363 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5364 PCI_ANY_ID, PCI_ANY_ID,
5365 0, 0,
5366 pbn_b2_2_115200 },
5367 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5368 PCI_ANY_ID, PCI_ANY_ID,
5369 0, 0,
5370 pbn_b2_2_115200 },
5371 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5372 PCI_ANY_ID, PCI_ANY_ID,
5373 0, 0,
5374 pbn_b2_2_115200 },
5375 /*
5376 * Brainboxes UC-320/324
5377 */
5378 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5379 PCI_ANY_ID, PCI_ANY_ID,
5380 0, 0,
5381 pbn_b2_1_115200 },
5382 /*
5383 * Brainboxes UC-346
5384 */
5385 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5386 PCI_ANY_ID, PCI_ANY_ID,
5387 0, 0,
5388 pbn_b2_4_115200 },
5389 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5390 PCI_ANY_ID, PCI_ANY_ID,
5391 0, 0,
5392 pbn_b2_4_115200 },
5393 /*
5394 * Brainboxes UC-357
5395 */
5396 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5397 PCI_ANY_ID, PCI_ANY_ID,
5398 0, 0,
5399 pbn_b2_2_115200 },
5400 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5401 PCI_ANY_ID, PCI_ANY_ID,
5402 0, 0,
5403 pbn_b2_2_115200 },
5404 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5405 PCI_ANY_ID, PCI_ANY_ID,
5406 0, 0,
5407 pbn_b2_2_115200 },
5408 /*
5409 * Brainboxes UC-368
5410 */
5411 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5412 PCI_ANY_ID, PCI_ANY_ID,
5413 0, 0,
5414 pbn_b2_4_115200 },
5415 { PCI_VENDOR_ID_INTASHIELD, 0x0C42,
5416 PCI_ANY_ID, PCI_ANY_ID,
5417 0, 0,
5418 pbn_b2_4_115200 },
5419 { PCI_VENDOR_ID_INTASHIELD, 0x0C43,
5420 PCI_ANY_ID, PCI_ANY_ID,
5421 0, 0,
5422 pbn_b2_4_115200 },
5423 /*
5424 * Brainboxes UC-420
5425 */
5426 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5427 PCI_ANY_ID, PCI_ANY_ID,
5428 0, 0,
5429 pbn_b2_4_115200 },
5430 /*
5431 * Brainboxes UC-607
5432 */
5433 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5434 PCI_ANY_ID, PCI_ANY_ID,
5435 0, 0,
5436 pbn_b2_2_115200 },
5437 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5438 PCI_ANY_ID, PCI_ANY_ID,
5439 0, 0,
5440 pbn_b2_2_115200 },
5441 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5442 PCI_ANY_ID, PCI_ANY_ID,
5443 0, 0,
5444 pbn_b2_2_115200 },
5445 /*
5446 * Brainboxes UC-836
5447 */
5448 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5449 PCI_ANY_ID, PCI_ANY_ID,
5450 0, 0,
5451 pbn_b2_4_115200 },
5452 /*
5453 * Brainboxes UP-189
5454 */
5455 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5456 PCI_ANY_ID, PCI_ANY_ID,
5457 0, 0,
5458 pbn_b2_2_115200 },
5459 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5460 PCI_ANY_ID, PCI_ANY_ID,
5461 0, 0,
5462 pbn_b2_2_115200 },
5463 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5464 PCI_ANY_ID, PCI_ANY_ID,
5465 0, 0,
5466 pbn_b2_2_115200 },
5467 /*
5468 * Brainboxes UP-200
5469 */
5470 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5471 PCI_ANY_ID, PCI_ANY_ID,
5472 0, 0,
5473 pbn_b2_2_115200 },
5474 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5475 PCI_ANY_ID, PCI_ANY_ID,
5476 0, 0,
5477 pbn_b2_2_115200 },
5478 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5479 PCI_ANY_ID, PCI_ANY_ID,
5480 0, 0,
5481 pbn_b2_2_115200 },
5482 /*
5483 * Brainboxes UP-869
5484 */
5485 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5486 PCI_ANY_ID, PCI_ANY_ID,
5487 0, 0,
5488 pbn_b2_2_115200 },
5489 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5490 PCI_ANY_ID, PCI_ANY_ID,
5491 0, 0,
5492 pbn_b2_2_115200 },
5493 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5494 PCI_ANY_ID, PCI_ANY_ID,
5495 0, 0,
5496 pbn_b2_2_115200 },
5497 /*
5498 * Brainboxes UP-880
5499 */
5500 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5501 PCI_ANY_ID, PCI_ANY_ID,
5502 0, 0,
5503 pbn_b2_2_115200 },
5504 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5505 PCI_ANY_ID, PCI_ANY_ID,
5506 0, 0,
5507 pbn_b2_2_115200 },
5508 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5509 PCI_ANY_ID, PCI_ANY_ID,
5510 0, 0,
5511 pbn_b2_2_115200 },
5512 /*
5513 * Brainboxes PX-101
5514 */
5515 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5516 PCI_ANY_ID, PCI_ANY_ID,
5517 0, 0,
5518 pbn_b0_2_115200 },
5519 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5520 PCI_ANY_ID, PCI_ANY_ID,
5521 0, 0,
5522 pbn_oxsemi_2_15625000 },
5523 /*
5524 * Brainboxes PX-235/246
5525 */
5526 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5527 PCI_ANY_ID, PCI_ANY_ID,
5528 0, 0,
5529 pbn_b0_1_115200 },
5530 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5531 PCI_ANY_ID, PCI_ANY_ID,
5532 0, 0,
5533 pbn_oxsemi_1_15625000 },
5534 /*
5535 * Brainboxes PX-203/PX-257
5536 */
5537 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5538 PCI_ANY_ID, PCI_ANY_ID,
5539 0, 0,
5540 pbn_b0_2_115200 },
5541 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5542 PCI_ANY_ID, PCI_ANY_ID,
5543 0, 0,
5544 pbn_oxsemi_2_15625000 },
5545 /*
5546 * Brainboxes PX-260/PX-701
5547 */
5548 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5549 PCI_ANY_ID, PCI_ANY_ID,
5550 0, 0,
5551 pbn_oxsemi_4_15625000 },
5552 /*
5553 * Brainboxes PX-275/279
5554 */
5555 { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5556 PCI_ANY_ID, PCI_ANY_ID,
5557 0, 0,
5558 pbn_b2_8_115200 },
5559 /*
5560 * Brainboxes PX-310
5561 */
5562 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5563 PCI_ANY_ID, PCI_ANY_ID,
5564 0, 0,
5565 pbn_oxsemi_2_15625000 },
5566 /*
5567 * Brainboxes PX-313
5568 */
5569 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5570 PCI_ANY_ID, PCI_ANY_ID,
5571 0, 0,
5572 pbn_oxsemi_2_15625000 },
5573 /*
5574 * Brainboxes PX-320/324/PX-376/PX-387
5575 */
5576 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5577 PCI_ANY_ID, PCI_ANY_ID,
5578 0, 0,
5579 pbn_oxsemi_1_15625000 },
5580 /*
5581 * Brainboxes PX-335/346
5582 */
5583 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5584 PCI_ANY_ID, PCI_ANY_ID,
5585 0, 0,
5586 pbn_oxsemi_4_15625000 },
5587 /*
5588 * Brainboxes PX-368
5589 */
5590 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5591 PCI_ANY_ID, PCI_ANY_ID,
5592 0, 0,
5593 pbn_oxsemi_4_15625000 },
5594 /*
5595 * Brainboxes PX-420
5596 */
5597 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5598 PCI_ANY_ID, PCI_ANY_ID,
5599 0, 0,
5600 pbn_b0_4_115200 },
5601 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5602 PCI_ANY_ID, PCI_ANY_ID,
5603 0, 0,
5604 pbn_oxsemi_4_15625000 },
5605 /*
5606 * Brainboxes PX-475
5607 */
5608 { PCI_VENDOR_ID_INTASHIELD, 0x401D,
5609 PCI_ANY_ID, PCI_ANY_ID,
5610 0, 0,
5611 pbn_oxsemi_1_15625000 },
5612 /*
5613 * Brainboxes PX-803/PX-857
5614 */
5615 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5616 PCI_ANY_ID, PCI_ANY_ID,
5617 0, 0,
5618 pbn_b0_2_115200 },
5619 { PCI_VENDOR_ID_INTASHIELD, 0x4018,
5620 PCI_ANY_ID, PCI_ANY_ID,
5621 0, 0,
5622 pbn_oxsemi_2_15625000 },
5623 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5624 PCI_ANY_ID, PCI_ANY_ID,
5625 0, 0,
5626 pbn_oxsemi_2_15625000 },
5627 /*
5628 * Brainboxes PX-820
5629 */
5630 { PCI_VENDOR_ID_INTASHIELD, 0x4002,
5631 PCI_ANY_ID, PCI_ANY_ID,
5632 0, 0,
5633 pbn_b0_4_115200 },
5634 { PCI_VENDOR_ID_INTASHIELD, 0x4013,
5635 PCI_ANY_ID, PCI_ANY_ID,
5636 0, 0,
5637 pbn_oxsemi_4_15625000 },
5638 /*
5639 * Brainboxes PX-835/PX-846
5640 */
5641 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5642 PCI_ANY_ID, PCI_ANY_ID,
5643 0, 0,
5644 pbn_b0_1_115200 },
5645 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5646 PCI_ANY_ID, PCI_ANY_ID,
5647 0, 0,
5648 pbn_oxsemi_1_15625000 },
5649 /*
5650 * Brainboxes XC-235
5651 */
5652 { PCI_VENDOR_ID_INTASHIELD, 0x4026,
5653 PCI_ANY_ID, PCI_ANY_ID,
5654 0, 0,
5655 pbn_oxsemi_1_15625000 },
5656 /*
5657 * Brainboxes XC-475
5658 */
5659 { PCI_VENDOR_ID_INTASHIELD, 0x4021,
5660 PCI_ANY_ID, PCI_ANY_ID,
5661 0, 0,
5662 pbn_oxsemi_1_15625000 },
5663
5664 /*
5665 * Perle PCI-RAS cards
5666 */
5667 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5668 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5669 0, 0, pbn_b2_4_921600 },
5670 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5671 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5672 0, 0, pbn_b2_8_921600 },
5673
5674 /*
5675 * Mainpine series cards: Fairly standard layout but fools
5676 * parts of the autodetect in some cases and uses otherwise
5677 * unmatched communications subclasses in the PCI Express case
5678 */
5679
5680 { /* RockForceDUO */
5681 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5682 PCI_VENDOR_ID_MAINPINE, 0x0200,
5683 0, 0, pbn_b0_2_115200 },
5684 { /* RockForceQUATRO */
5685 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5686 PCI_VENDOR_ID_MAINPINE, 0x0300,
5687 0, 0, pbn_b0_4_115200 },
5688 { /* RockForceDUO+ */
5689 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5690 PCI_VENDOR_ID_MAINPINE, 0x0400,
5691 0, 0, pbn_b0_2_115200 },
5692 { /* RockForceQUATRO+ */
5693 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5694 PCI_VENDOR_ID_MAINPINE, 0x0500,
5695 0, 0, pbn_b0_4_115200 },
5696 { /* RockForce+ */
5697 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5698 PCI_VENDOR_ID_MAINPINE, 0x0600,
5699 0, 0, pbn_b0_2_115200 },
5700 { /* RockForce+ */
5701 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5702 PCI_VENDOR_ID_MAINPINE, 0x0700,
5703 0, 0, pbn_b0_4_115200 },
5704 { /* RockForceOCTO+ */
5705 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5706 PCI_VENDOR_ID_MAINPINE, 0x0800,
5707 0, 0, pbn_b0_8_115200 },
5708 { /* RockForceDUO+ */
5709 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5710 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5711 0, 0, pbn_b0_2_115200 },
5712 { /* RockForceQUARTRO+ */
5713 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5714 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5715 0, 0, pbn_b0_4_115200 },
5716 { /* RockForceOCTO+ */
5717 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5718 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5719 0, 0, pbn_b0_8_115200 },
5720 { /* RockForceD1 */
5721 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5722 PCI_VENDOR_ID_MAINPINE, 0x2000,
5723 0, 0, pbn_b0_1_115200 },
5724 { /* RockForceF1 */
5725 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5726 PCI_VENDOR_ID_MAINPINE, 0x2100,
5727 0, 0, pbn_b0_1_115200 },
5728 { /* RockForceD2 */
5729 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5730 PCI_VENDOR_ID_MAINPINE, 0x2200,
5731 0, 0, pbn_b0_2_115200 },
5732 { /* RockForceF2 */
5733 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5734 PCI_VENDOR_ID_MAINPINE, 0x2300,
5735 0, 0, pbn_b0_2_115200 },
5736 { /* RockForceD4 */
5737 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5738 PCI_VENDOR_ID_MAINPINE, 0x2400,
5739 0, 0, pbn_b0_4_115200 },
5740 { /* RockForceF4 */
5741 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5742 PCI_VENDOR_ID_MAINPINE, 0x2500,
5743 0, 0, pbn_b0_4_115200 },
5744 { /* RockForceD8 */
5745 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5746 PCI_VENDOR_ID_MAINPINE, 0x2600,
5747 0, 0, pbn_b0_8_115200 },
5748 { /* RockForceF8 */
5749 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5750 PCI_VENDOR_ID_MAINPINE, 0x2700,
5751 0, 0, pbn_b0_8_115200 },
5752 { /* IQ Express D1 */
5753 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5754 PCI_VENDOR_ID_MAINPINE, 0x3000,
5755 0, 0, pbn_b0_1_115200 },
5756 { /* IQ Express F1 */
5757 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5758 PCI_VENDOR_ID_MAINPINE, 0x3100,
5759 0, 0, pbn_b0_1_115200 },
5760 { /* IQ Express D2 */
5761 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5762 PCI_VENDOR_ID_MAINPINE, 0x3200,
5763 0, 0, pbn_b0_2_115200 },
5764 { /* IQ Express F2 */
5765 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5766 PCI_VENDOR_ID_MAINPINE, 0x3300,
5767 0, 0, pbn_b0_2_115200 },
5768 { /* IQ Express D4 */
5769 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5770 PCI_VENDOR_ID_MAINPINE, 0x3400,
5771 0, 0, pbn_b0_4_115200 },
5772 { /* IQ Express F4 */
5773 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5774 PCI_VENDOR_ID_MAINPINE, 0x3500,
5775 0, 0, pbn_b0_4_115200 },
5776 { /* IQ Express D8 */
5777 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5778 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5779 0, 0, pbn_b0_8_115200 },
5780 { /* IQ Express F8 */
5781 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5782 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5783 0, 0, pbn_b0_8_115200 },
5784
5785
5786 /*
5787 * PA Semi PA6T-1682M on-chip UART
5788 */
5789 { PCI_VENDOR_ID_PASEMI, 0xa004,
5790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5791 pbn_pasemi_1682M },
5792
5793 /*
5794 * National Instruments
5795 */
5796 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5798 pbn_b1_16_115200 },
5799 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5801 pbn_b1_8_115200 },
5802 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5804 pbn_b1_bt_4_115200 },
5805 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5807 pbn_b1_bt_2_115200 },
5808 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5810 pbn_b1_bt_4_115200 },
5811 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5813 pbn_b1_bt_2_115200 },
5814 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5816 pbn_b1_16_115200 },
5817 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5819 pbn_b1_8_115200 },
5820 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5822 pbn_b1_bt_4_115200 },
5823 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5825 pbn_b1_bt_2_115200 },
5826 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5828 pbn_b1_bt_4_115200 },
5829 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5831 pbn_b1_bt_2_115200 },
5832 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5834 pbn_ni8430_2 },
5835 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5837 pbn_ni8430_2 },
5838 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5840 pbn_ni8430_4 },
5841 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5843 pbn_ni8430_4 },
5844 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5846 pbn_ni8430_8 },
5847 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5849 pbn_ni8430_8 },
5850 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5852 pbn_ni8430_16 },
5853 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5855 pbn_ni8430_16 },
5856 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5858 pbn_ni8430_2 },
5859 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5861 pbn_ni8430_2 },
5862 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5864 pbn_ni8430_4 },
5865 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5867 pbn_ni8430_4 },
5868
5869 /*
5870 * MOXA
5871 */
5872 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
5873 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 },
5874 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 },
5875 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 },
5876 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 },
5877 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 },
5878 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 },
5879 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 },
5880 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 },
5881 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 },
5882 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 },
5883 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 },
5884 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 },
5885 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 },
5886 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 },
5887 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 },
5888 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 },
5889 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 },
5890
5891 /*
5892 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5893 */
5894 { PCI_VENDOR_ID_ADDIDATA,
5895 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5896 PCI_ANY_ID,
5897 PCI_ANY_ID,
5898 0,
5899 0,
5900 pbn_b0_4_115200 },
5901
5902 { PCI_VENDOR_ID_ADDIDATA,
5903 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5904 PCI_ANY_ID,
5905 PCI_ANY_ID,
5906 0,
5907 0,
5908 pbn_b0_2_115200 },
5909
5910 { PCI_VENDOR_ID_ADDIDATA,
5911 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5912 PCI_ANY_ID,
5913 PCI_ANY_ID,
5914 0,
5915 0,
5916 pbn_b0_1_115200 },
5917
5918 { PCI_VENDOR_ID_AMCC,
5919 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5920 PCI_ANY_ID,
5921 PCI_ANY_ID,
5922 0,
5923 0,
5924 pbn_b1_8_115200 },
5925
5926 { PCI_VENDOR_ID_ADDIDATA,
5927 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5928 PCI_ANY_ID,
5929 PCI_ANY_ID,
5930 0,
5931 0,
5932 pbn_b0_4_115200 },
5933
5934 { PCI_VENDOR_ID_ADDIDATA,
5935 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5936 PCI_ANY_ID,
5937 PCI_ANY_ID,
5938 0,
5939 0,
5940 pbn_b0_2_115200 },
5941
5942 { PCI_VENDOR_ID_ADDIDATA,
5943 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5944 PCI_ANY_ID,
5945 PCI_ANY_ID,
5946 0,
5947 0,
5948 pbn_b0_1_115200 },
5949
5950 { PCI_VENDOR_ID_ADDIDATA,
5951 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5952 PCI_ANY_ID,
5953 PCI_ANY_ID,
5954 0,
5955 0,
5956 pbn_b0_4_115200 },
5957
5958 { PCI_VENDOR_ID_ADDIDATA,
5959 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5960 PCI_ANY_ID,
5961 PCI_ANY_ID,
5962 0,
5963 0,
5964 pbn_b0_2_115200 },
5965
5966 { PCI_VENDOR_ID_ADDIDATA,
5967 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5968 PCI_ANY_ID,
5969 PCI_ANY_ID,
5970 0,
5971 0,
5972 pbn_b0_1_115200 },
5973
5974 { PCI_VENDOR_ID_ADDIDATA,
5975 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5976 PCI_ANY_ID,
5977 PCI_ANY_ID,
5978 0,
5979 0,
5980 pbn_b0_8_115200 },
5981
5982 { PCI_VENDOR_ID_ADDIDATA,
5983 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5984 PCI_ANY_ID,
5985 PCI_ANY_ID,
5986 0,
5987 0,
5988 pbn_ADDIDATA_PCIe_4_3906250 },
5989
5990 { PCI_VENDOR_ID_ADDIDATA,
5991 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5992 PCI_ANY_ID,
5993 PCI_ANY_ID,
5994 0,
5995 0,
5996 pbn_ADDIDATA_PCIe_2_3906250 },
5997
5998 { PCI_VENDOR_ID_ADDIDATA,
5999 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
6000 PCI_ANY_ID,
6001 PCI_ANY_ID,
6002 0,
6003 0,
6004 pbn_ADDIDATA_PCIe_1_3906250 },
6005
6006 { PCI_VENDOR_ID_ADDIDATA,
6007 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
6008 PCI_ANY_ID,
6009 PCI_ANY_ID,
6010 0,
6011 0,
6012 pbn_ADDIDATA_PCIe_8_3906250 },
6013
6014 { PCI_VENDOR_ID_ADDIDATA,
6015 PCI_DEVICE_ID_ADDIDATA_CPCI7500,
6016 PCI_ANY_ID,
6017 PCI_ANY_ID,
6018 0,
6019 0,
6020 pbn_b0_4_115200 },
6021
6022 { PCI_VENDOR_ID_ADDIDATA,
6023 PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG,
6024 PCI_ANY_ID,
6025 PCI_ANY_ID,
6026 0,
6027 0,
6028 pbn_b0_4_115200 },
6029
6030 { PCI_VENDOR_ID_ADDIDATA,
6031 PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG,
6032 PCI_ANY_ID,
6033 PCI_ANY_ID,
6034 0,
6035 0,
6036 pbn_b0_2_115200 },
6037
6038 { PCI_VENDOR_ID_ADDIDATA,
6039 PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG,
6040 PCI_ANY_ID,
6041 PCI_ANY_ID,
6042 0,
6043 0,
6044 pbn_b0_1_115200 },
6045
6046 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
6047 PCI_VENDOR_ID_IBM, 0x0299,
6048 0, 0, pbn_b0_bt_2_115200 },
6049
6050 /*
6051 * other NetMos 9835 devices are most likely handled by the
6052 * parport_serial driver, check drivers/parport/parport_serial.c
6053 * before adding them here.
6054 */
6055
6056 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
6057 0xA000, 0x1000,
6058 0, 0, pbn_b0_1_115200 },
6059
6060 /* the 9901 is a rebranded 9912 */
6061 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
6062 0xA000, 0x1000,
6063 0, 0, pbn_b0_1_115200 },
6064
6065 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
6066 0xA000, 0x1000,
6067 0, 0, pbn_b0_1_115200 },
6068
6069 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
6070 0xA000, 0x1000,
6071 0, 0, pbn_b0_1_115200 },
6072
6073 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
6074 0xA000, 0x1000,
6075 0, 0, pbn_b0_1_115200 },
6076
6077 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
6078 0xA000, 0x3002,
6079 0, 0, pbn_NETMOS9900_2s_115200 },
6080
6081 { PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100,
6082 0xA000, 0x1000,
6083 0, 0, pbn_b0_1_115200 },
6084
6085 /*
6086 * Best Connectivity and Rosewill PCI Multi I/O cards
6087 */
6088
6089 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6090 0xA000, 0x1000,
6091 0, 0, pbn_b0_1_115200 },
6092
6093 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6094 0xA000, 0x3002,
6095 0, 0, pbn_b0_bt_2_115200 },
6096
6097 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6098 0xA000, 0x3004,
6099 0, 0, pbn_b0_bt_4_115200 },
6100
6101 /*
6102 * ASIX AX99100 PCIe to Multi I/O Controller
6103 */
6104 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
6105 0xA000, 0x1000,
6106 0, 0, pbn_b0_1_115200 },
6107
6108 /* Intel CE4100 */
6109 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
6110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6111 pbn_ce4100_1_115200 },
6112
6113 /*
6114 * Cronyx Omega PCI
6115 */
6116 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
6117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6118 pbn_omegapci },
6119
6120 /*
6121 * Broadcom TruManage
6122 */
6123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
6124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6125 pbn_brcm_trumanage },
6126
6127 /*
6128 * AgeStar as-prs2-009
6129 */
6130 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
6131 PCI_ANY_ID, PCI_ANY_ID,
6132 0, 0, pbn_b0_bt_2_115200 },
6133
6134 /*
6135 * WCH CH353 series devices: The 2S1P is handled by parport_serial
6136 * so not listed here.
6137 */
6138 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S,
6139 PCI_ANY_ID, PCI_ANY_ID,
6140 0, 0, pbn_b0_bt_4_115200 },
6141
6142 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
6143 PCI_ANY_ID, PCI_ANY_ID,
6144 0, 0, pbn_b0_bt_2_115200 },
6145
6146 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S,
6147 PCI_ANY_ID, PCI_ANY_ID,
6148 0, 0, pbn_b0_bt_4_115200 },
6149
6150 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S,
6151 PCI_ANY_ID, PCI_ANY_ID,
6152 0, 0, pbn_wch382_2 },
6153
6154 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S,
6155 PCI_ANY_ID, PCI_ANY_ID,
6156 0, 0, pbn_wch384_4 },
6157
6158 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S,
6159 PCI_ANY_ID, PCI_ANY_ID,
6160 0, 0, pbn_wch384_8 },
6161 /*
6162 * Realtek RealManage
6163 */
6164 { PCI_VENDOR_ID_REALTEK, 0x816a,
6165 PCI_ANY_ID, PCI_ANY_ID,
6166 0, 0, pbn_b0_1_115200 },
6167
6168 { PCI_VENDOR_ID_REALTEK, 0x816b,
6169 PCI_ANY_ID, PCI_ANY_ID,
6170 0, 0, pbn_b0_1_115200 },
6171
6172 /* Fintek PCI serial cards */
6173 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
6174 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
6175 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
6176 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
6177 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
6178 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
6179
6180 /* MKS Tenta SCOM-080x serial cards */
6181 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
6182 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
6183
6184 /* Amazon PCI serial device */
6185 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
6186
6187 /*
6188 * These entries match devices with class COMMUNICATION_SERIAL,
6189 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
6190 */
6191 { PCI_ANY_ID, PCI_ANY_ID,
6192 PCI_ANY_ID, PCI_ANY_ID,
6193 PCI_CLASS_COMMUNICATION_SERIAL << 8,
6194 0xffff00, pbn_default },
6195 { PCI_ANY_ID, PCI_ANY_ID,
6196 PCI_ANY_ID, PCI_ANY_ID,
6197 PCI_CLASS_COMMUNICATION_MODEM << 8,
6198 0xffff00, pbn_default },
6199 { PCI_ANY_ID, PCI_ANY_ID,
6200 PCI_ANY_ID, PCI_ANY_ID,
6201 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
6202 0xffff00, pbn_default },
6203 { 0, }
6204 };
6205
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)6206 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
6207 pci_channel_state_t state)
6208 {
6209 struct serial_private *priv = pci_get_drvdata(dev);
6210
6211 if (state == pci_channel_io_perm_failure)
6212 return PCI_ERS_RESULT_DISCONNECT;
6213
6214 if (priv)
6215 pciserial_detach_ports(priv);
6216
6217 pci_disable_device(dev);
6218
6219 return PCI_ERS_RESULT_NEED_RESET;
6220 }
6221
serial8250_io_slot_reset(struct pci_dev * dev)6222 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
6223 {
6224 int rc;
6225
6226 rc = pci_enable_device(dev);
6227
6228 if (rc)
6229 return PCI_ERS_RESULT_DISCONNECT;
6230
6231 pci_restore_state(dev);
6232
6233 return PCI_ERS_RESULT_RECOVERED;
6234 }
6235
serial8250_io_resume(struct pci_dev * dev)6236 static void serial8250_io_resume(struct pci_dev *dev)
6237 {
6238 struct serial_private *priv = pci_get_drvdata(dev);
6239 struct serial_private *new;
6240
6241 if (!priv)
6242 return;
6243
6244 new = pciserial_init_ports(dev, priv->board);
6245 if (!IS_ERR(new)) {
6246 pci_set_drvdata(dev, new);
6247 kfree(priv);
6248 }
6249 }
6250
6251 static const struct pci_error_handlers serial8250_err_handler = {
6252 .error_detected = serial8250_io_error_detected,
6253 .slot_reset = serial8250_io_slot_reset,
6254 .resume = serial8250_io_resume,
6255 };
6256
6257 static struct pci_driver serial_pci_driver = {
6258 .name = "serial",
6259 .probe = pciserial_init_one,
6260 .remove = pciserial_remove_one,
6261 .driver = {
6262 .pm = &pciserial_pm_ops,
6263 },
6264 .id_table = serial_pci_tbl,
6265 .err_handler = &serial8250_err_handler,
6266 };
6267
6268 module_pci_driver(serial_pci_driver);
6269
6270 MODULE_LICENSE("GPL");
6271 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
6272 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
6273 MODULE_IMPORT_NS("SERIAL_8250_PCI");
6274