1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/power/amlogic,t7-pwrc.h> 8#include "amlogic-t7-reset.h" 9#include <dt-bindings/clock/amlogic,t7-scmi.h> 10#include <dt-bindings/clock/amlogic,t7-pll-clkc.h> 11#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h> 12 13/ { 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <0x2>; 20 #size-cells = <0x0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu100>; 26 }; 27 core1 { 28 cpu = <&cpu101>; 29 }; 30 core2 { 31 cpu = <&cpu102>; 32 }; 33 core3 { 34 cpu = <&cpu103>; 35 }; 36 }; 37 38 cluster1 { 39 core0 { 40 cpu = <&cpu0>; 41 }; 42 core1 { 43 cpu = <&cpu1>; 44 }; 45 core2 { 46 cpu = <&cpu2>; 47 }; 48 core3 { 49 cpu = <&cpu3>; 50 }; 51 }; 52 }; 53 54 cpu100: cpu@100 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53"; 57 reg = <0x0 0x100>; 58 enable-method = "psci"; 59 d-cache-line-size = <32>; 60 d-cache-size = <0x8000>; 61 d-cache-sets = <32>; 62 i-cache-line-size = <32>; 63 i-cache-size = <0x8000>; 64 i-cache-sets = <32>; 65 next-level-cache = <&l2_cache_l>; 66 }; 67 68 cpu101: cpu@101 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x101>; 72 enable-method = "psci"; 73 d-cache-line-size = <32>; 74 d-cache-size = <0x8000>; 75 d-cache-sets = <32>; 76 i-cache-line-size = <32>; 77 i-cache-size = <0x8000>; 78 i-cache-sets = <32>; 79 next-level-cache = <&l2_cache_l>; 80 }; 81 82 cpu102: cpu@102 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x0 0x102>; 86 enable-method = "psci"; 87 d-cache-line-size = <32>; 88 d-cache-size = <0x8000>; 89 d-cache-sets = <32>; 90 i-cache-line-size = <32>; 91 i-cache-size = <0x8000>; 92 i-cache-sets = <32>; 93 next-level-cache = <&l2_cache_l>; 94 }; 95 96 cpu103: cpu@103 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x103>; 100 enable-method = "psci"; 101 d-cache-line-size = <32>; 102 d-cache-size = <0x8000>; 103 d-cache-sets = <32>; 104 i-cache-line-size = <32>; 105 i-cache-size = <0x8000>; 106 i-cache-sets = <32>; 107 next-level-cache = <&l2_cache_l>; 108 }; 109 110 cpu0: cpu@0 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a73"; 113 reg = <0x0 0x0>; 114 enable-method = "psci"; 115 d-cache-line-size = <64>; 116 d-cache-size = <0x10000>; 117 d-cache-sets = <64>; 118 i-cache-line-size = <64>; 119 i-cache-size = <0x10000>; 120 i-cache-sets = <64>; 121 next-level-cache = <&l2_cache_b>; 122 }; 123 124 cpu1: cpu@1 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a73"; 127 reg = <0x0 0x1>; 128 enable-method = "psci"; 129 d-cache-line-size = <64>; 130 d-cache-size = <0x10000>; 131 d-cache-sets = <64>; 132 i-cache-line-size = <64>; 133 i-cache-size = <0x10000>; 134 i-cache-sets = <64>; 135 next-level-cache = <&l2_cache_b>; 136 }; 137 138 cpu2: cpu@2 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a73"; 141 reg = <0x0 0x2>; 142 enable-method = "psci"; 143 d-cache-line-size = <64>; 144 d-cache-size = <0x10000>; 145 d-cache-sets = <64>; 146 i-cache-line-size = <64>; 147 i-cache-size = <0x10000>; 148 i-cache-sets = <64>; 149 next-level-cache = <&l2_cache_b>; 150 }; 151 152 cpu3: cpu@3 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a73"; 155 reg = <0x0 0x3>; 156 enable-method = "psci"; 157 d-cache-line-size = <64>; 158 d-cache-size = <0x10000>; 159 d-cache-sets = <64>; 160 i-cache-line-size = <64>; 161 i-cache-size = <0x10000>; 162 i-cache-sets = <64>; 163 next-level-cache = <&l2_cache_b>; 164 }; 165 166 l2_cache_l: l2-cache-cluster0 { 167 compatible = "cache"; 168 cache-level = <2>; 169 cache-unified; 170 cache-size = <0x40000>; /* L2. 256 KB */ 171 cache-line-size = <64>; 172 cache-sets = <512>; 173 }; 174 175 l2_cache_b: l2-cache-cluster1 { 176 compatible = "cache"; 177 cache-level = <2>; 178 cache-unified; 179 cache-size = <0x100000>; /* L2. 1 Mb */ 180 cache-line-size = <64>; 181 cache-sets = <512>; 182 }; 183 }; 184 185 timer { 186 compatible = "arm,armv8-timer"; 187 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 188 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 189 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 190 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 191 }; 192 193 psci { 194 compatible = "arm,psci-1.0"; 195 method = "smc"; 196 }; 197 198 sm: secure-monitor { 199 compatible = "amlogic,meson-gxbb-sm"; 200 201 pwrc: power-controller { 202 compatible = "amlogic,t7-pwrc"; 203 #power-domain-cells = <1>; 204 }; 205 }; 206 207 sram@f7042000 { 208 compatible = "mmio-sram"; 209 reg = <0x0 0xf7042000 0x0 0x100>; 210 #address-cells = <1>; 211 #size-cells = <1>; 212 ranges = <0 0x0 0xf7042000 0x100>; 213 214 scmi_shmem: sram@0 { 215 compatible = "arm,scmi-shmem"; 216 reg = <0x0 0x100>; 217 }; 218 }; 219 220 firmware { 221 scmi: scmi { 222 compatible = "arm,scmi-smc"; 223 arm,smc-id = <0x820000c1>; 224 shmem = <&scmi_shmem>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 228 scmi_clk: protocol@14 { 229 reg = <0x14>; 230 #clock-cells = <1>; 231 }; 232 }; 233 }; 234 235 soc { 236 compatible = "simple-bus"; 237 #address-cells = <2>; 238 #size-cells = <2>; 239 ranges; 240 241 gic: interrupt-controller@fff01000 { 242 compatible = "arm,gic-400"; 243 #interrupt-cells = <3>; 244 #address-cells = <0>; 245 interrupt-controller; 246 reg = <0x0 0xfff01000 0 0x1000>, 247 <0x0 0xfff02000 0 0x2000>, 248 <0x0 0xfff04000 0 0x2000>, 249 <0x0 0xfff06000 0 0x2000>; 250 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 251 }; 252 253 apb4: bus@fe000000 { 254 compatible = "simple-bus"; 255 reg = <0x0 0xfe000000 0x0 0x480000>; 256 #address-cells = <2>; 257 #size-cells = <2>; 258 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 259 260 clkc_periphs: clock-controller@0 { 261 compatible = "amlogic,t7-peripherals-clkc"; 262 reg = <0x0 0x0 0x0 0x1c8>; 263 #clock-cells = <1>; 264 clocks = <&xtal>, 265 <&scmi_clk CLKID_SYS_CLK>, 266 <&scmi_clk CLKID_FIXED_PLL>, 267 <&scmi_clk CLKID_FCLK_DIV2>, 268 <&scmi_clk CLKID_FCLK_DIV2P5>, 269 <&scmi_clk CLKID_FCLK_DIV3>, 270 <&scmi_clk CLKID_FCLK_DIV4>, 271 <&scmi_clk CLKID_FCLK_DIV5>, 272 <&scmi_clk CLKID_FCLK_DIV7>, 273 <&hifi CLKID_HIFI_PLL>, 274 <&gp0 CLKID_GP0_PLL>, 275 <&gp1 CLKID_GP1_PLL>, 276 <&mpll CLKID_MPLL1>, 277 <&mpll CLKID_MPLL2>, 278 <&mpll CLKID_MPLL3>; 279 clock-names = "xtal", 280 "sys", 281 "fix", 282 "fdiv2", 283 "fdiv2p5", 284 "fdiv3", 285 "fdiv4", 286 "fdiv5", 287 "fdiv7", 288 "hifi", 289 "gp0", 290 "gp1", 291 "mpll1", 292 "mpll2", 293 "mpll3"; 294 }; 295 296 reset: reset-controller@2000 { 297 compatible = "amlogic,t7-reset"; 298 reg = <0x0 0x2000 0x0 0x98>; 299 #reset-cells = <1>; 300 }; 301 302 watchdog@2100 { 303 compatible = "amlogic,t7-wdt"; 304 reg = <0x0 0x2100 0x0 0x10>; 305 clocks = <&xtal>; 306 }; 307 308 periphs_pinctrl: pinctrl@4000 { 309 compatible = "amlogic,t7-periphs-pinctrl"; 310 #address-cells = <2>; 311 #size-cells = <2>; 312 ranges; 313 314 gpio: bank@4000 { 315 reg = <0x0 0x4000 0x0 0x0064>, 316 <0x0 0x40c0 0x0 0x0220>; 317 reg-names = "mux", "gpio"; 318 gpio-controller; 319 #gpio-cells = <2>; 320 gpio-ranges = <&periphs_pinctrl 0 0 157>; 321 }; 322 323 emmc_ctrl_pins: emmc-ctrl { 324 mux-0 { 325 groups = "emmc_cmd"; 326 function = "emmc"; 327 bias-pull-up; 328 }; 329 330 mux-1 { 331 groups = "emmc_clk"; 332 function = "emmc"; 333 bias-disable; 334 }; 335 }; 336 337 emmc_data_4b_pins: emmc-data-4b { 338 mux { 339 groups = "emmc_nand_d0", 340 "emmc_nand_d1", 341 "emmc_nand_d2", 342 "emmc_nand_d3"; 343 function = "emmc"; 344 bias-pull-up; 345 }; 346 }; 347 348 emmc_data_8b_pins: emmc-data-8b { 349 mux { 350 groups = "emmc_nand_d0", 351 "emmc_nand_d1", 352 "emmc_nand_d2", 353 "emmc_nand_d3", 354 "emmc_nand_d4", 355 "emmc_nand_d5", 356 "emmc_nand_d6", 357 "emmc_nand_d7"; 358 function = "emmc"; 359 bias-pull-up; 360 }; 361 }; 362 363 emmc_ds_pins: emmc-ds { 364 mux { 365 groups = "emmc_nand_ds"; 366 function = "emmc"; 367 bias-pull-down; 368 }; 369 }; 370 371 emmc_clk_gate_pins: emmc-clk-gate { 372 mux { 373 groups = "GPIOB_8"; 374 function = "gpio_periphs"; 375 bias-pull-down; 376 }; 377 }; 378 379 i2c0_ao_d_pins: i2c0-ao-d { 380 mux { 381 groups = "i2c0_ao_sck_d", 382 "i2c0_ao_sda_d"; 383 function = "i2c0_ao"; 384 bias-disable; 385 drive-strength-microamp = <3000>; 386 }; 387 }; 388 389 pwm_a_pins: pwm-a { 390 mux { 391 groups = "pwm_a"; 392 function = "pwm_a"; 393 bias-disable; 394 }; 395 }; 396 397 pwm_ao_a_pins: pwm-ao-a { 398 mux { 399 groups = "pwm_ao_a"; 400 function = "pwm_ao_a"; 401 bias-disable; 402 }; 403 }; 404 405 pwm_ao_b_pins: pwm-ao-b { 406 mux { 407 groups = "pwm_ao_b"; 408 function = "pwm_ao_b"; 409 bias-disable; 410 }; 411 }; 412 413 pwm_ao_c_d_pins: pwm-ao-c-d { 414 mux { 415 groups = "pwm_ao_c_d"; 416 function = "pwm_ao_c"; 417 bias-disable; 418 }; 419 }; 420 421 pwm_ao_c_e_pins: pwm-ao-c-e { 422 mux { 423 groups = "pwm_ao_c_e"; 424 function = "pwm_ao_c"; 425 bias-disable; 426 }; 427 }; 428 429 pwm_ao_c_hiz_pins: pwm-ao-c-hiz { 430 mux { 431 groups = "pwm_ao_c_hiz"; 432 function = "pwm_ao_c_hiz"; 433 bias-disable; 434 }; 435 }; 436 437 pwm_ao_d_pins: pwm-ao-d { 438 mux { 439 groups = "pwm_ao_d"; 440 function = "pwm_ao_d"; 441 bias-disable; 442 }; 443 }; 444 445 pwm_ao_e_pins: pwm-ao-e { 446 mux { 447 groups = "pwm_ao_e"; 448 function = "pwm_ao_e"; 449 bias-disable; 450 }; 451 }; 452 453 pwm_ao_f_pins: pwm-ao-f { 454 mux { 455 groups = "pwm_ao_f"; 456 function = "pwm_ao_f"; 457 bias-disable; 458 }; 459 }; 460 461 pwm_ao_g_d11_pins: pwm-ao-g-d11 { 462 mux { 463 groups = "pwm_ao_g_d11"; 464 function = "pwm_ao_g"; 465 bias-disable; 466 }; 467 }; 468 469 pwm_ao_g_d7_pins: pwm-ao-g-d7 { 470 mux { 471 groups = "pwm_ao_g_d7"; 472 function = "pwm_ao_g"; 473 bias-disable; 474 }; 475 }; 476 477 pwm_ao_g_e_pins: pwm-ao-g-e { 478 mux { 479 groups = "pwm_ao_g_e"; 480 function = "pwm_ao_g"; 481 bias-disable; 482 }; 483 }; 484 485 pwm_ao_g_hiz_pins: pwm-ao-g-hiz { 486 mux { 487 groups = "pwm_ao_g_hiz"; 488 function = "pwm_ao_g_hiz"; 489 bias-disable; 490 }; 491 }; 492 493 pwm_ao_h_d5_pins: pwm-ao-h-d5 { 494 mux { 495 groups = "pwm_ao_h_d5"; 496 function = "pwm_ao_h"; 497 bias-disable; 498 }; 499 }; 500 501 pwm_ao_h_d10_pins: pwm-ao-h-d10 { 502 mux { 503 groups = "pwm_ao_h_d10"; 504 function = "pwm_ao_h"; 505 bias-disable; 506 }; 507 }; 508 509 pwm_b_pins: pwm-b { 510 mux { 511 groups = "pwm_b"; 512 function = "pwm_b"; 513 bias-disable; 514 }; 515 }; 516 517 pwm_c_pins: pwm-c { 518 mux { 519 groups = "pwm_c"; 520 function = "pwm_c"; 521 bias-disable; 522 }; 523 }; 524 525 pwm_d_pins: pwm-d { 526 mux { 527 groups = "pwm_d"; 528 function = "pwm_d"; 529 bias-disable; 530 }; 531 }; 532 533 pwm_e_pins: pwm-e { 534 mux { 535 groups = "pwm_e"; 536 function = "pwm_e"; 537 bias-disable; 538 }; 539 }; 540 541 pwm_f_pins: pwm-f { 542 mux { 543 groups = "pwm_f"; 544 function = "pwm_f"; 545 bias-disable; 546 }; 547 }; 548 549 pwm_vs_y_pins: pwm-vs-y { 550 mux { 551 groups = "pwm_vs_y"; 552 function = "pwm_vs"; 553 bias-disable; 554 }; 555 }; 556 557 pwm_vs_h_pins: pwm-vs-h { 558 mux { 559 groups = "pwm_vs_h"; 560 function = "pwm_vs"; 561 bias-disable; 562 }; 563 }; 564 565 sdcard_pins: sdcard { 566 mux { 567 groups = "sdcard_d0", 568 "sdcard_d1", 569 "sdcard_d2", 570 "sdcard_d3", 571 "sdcard_clk", 572 "sdcard_cmd"; 573 function = "sdcard"; 574 bias-pull-up; 575 }; 576 }; 577 578 sdcard_clk_gate_pins: sdcard-clk-gate { 579 mux { 580 groups = "GPIOC_4"; 581 function = "gpio_periphs"; 582 bias-pull-down; 583 }; 584 }; 585 586 sdio_pins: sdio { 587 mux { 588 groups = "sdio_d0", 589 "sdio_d1", 590 "sdio_d2", 591 "sdio_d3", 592 "sdio_clk", 593 "sdio_cmd"; 594 function = "sdio"; 595 bias-pull-up; 596 }; 597 }; 598 599 sdio_clk_gate_pins: sdio-clk-gate { 600 mux { 601 groups = "GPIOX_4"; 602 function = "gpio_periphs"; 603 bias-pull-up; 604 }; 605 }; 606 }; 607 608 gpio_intc: interrupt-controller@4080 { 609 compatible = "amlogic,t7-gpio-intc", 610 "amlogic,meson-gpio-intc"; 611 reg = <0x0 0x4080 0x0 0x20>; 612 interrupt-controller; 613 #interrupt-cells = <2>; 614 amlogic,channel-interrupts = 615 <10 11 12 13 14 15 16 17 18 19 20 21>; 616 }; 617 618 uart_a: serial@78000 { 619 compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart"; 620 reg = <0x0 0x78000 0x0 0x18>; 621 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 622 status = "disabled"; 623 }; 624 625 gp0: clock-controller@8080 { 626 compatible = "amlogic,t7-gp0-pll"; 627 reg = <0x0 0x8080 0x0 0x20>; 628 clocks = <&scmi_clk CLKID_TOP_PLL_OSC>; 629 clock-names = "in0"; 630 #clock-cells = <1>; 631 }; 632 633 gp1: clock-controller@80c0 { 634 compatible = "amlogic,t7-gp1-pll"; 635 reg = <0x0 0x80c0 0x0 0x14>; 636 clocks = <&scmi_clk CLKID_TOP_PLL_OSC>; 637 clock-names = "in0"; 638 #clock-cells = <1>; 639 }; 640 641 hifi: clock-controller@8100 { 642 compatible = "amlogic,t7-hifi-pll"; 643 reg = <0x0 0x8100 0x0 0x20>; 644 clocks = <&scmi_clk CLKID_TOP_PLL_OSC>; 645 clock-names = "in0"; 646 #clock-cells = <1>; 647 }; 648 649 pcie: clock-controller@8140 { 650 compatible = "amlogic,t7-pcie-pll"; 651 reg = <0x0 0x8140 0x0 0x1c>; 652 clocks = <&scmi_clk CLKID_PCIE_OSC>; 653 clock-names = "in0"; 654 #clock-cells = <1>; 655 }; 656 657 mpll: clock-controller@8180 { 658 compatible = "amlogic,t7-mpll"; 659 reg = <0x0 0x8180 0x0 0x28>; 660 clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>; 661 clock-names = "in0"; 662 #clock-cells = <1>; 663 }; 664 665 hdmi: clock-controller@81c0 { 666 compatible = "amlogic,t7-hdmi-pll"; 667 reg = <0x0 0x81c0 0x0 0x20>; 668 clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>; 669 clock-names = "in0"; 670 #clock-cells = <1>; 671 }; 672 673 mclk: clock-controller@8300 { 674 compatible = "amlogic,t7-mclk-pll"; 675 reg = <0x0 0x8300 0x0 0x18>; 676 clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>, 677 <&xtal>, 678 <&scmi_clk CLKID_FCLK_50M>; 679 clock-names = "in0", "in1", "in2"; 680 #clock-cells = <1>; 681 }; 682 683 sec_ao: ao-secure@10220 { 684 compatible = "amlogic,t7-ao-secure", 685 "amlogic,meson-gx-ao-secure", 686 "syscon"; 687 reg = <0x0 0x10220 0x0 0x140>; 688 amlogic,has-chip-id; 689 }; 690 691 pwm_ao_ef: pwm@30000 { 692 compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; 693 reg = <0x0 0x30000 0x0 0x24>; 694 clocks = <&clkc_periphs CLKID_PWM_AO_E>, 695 <&clkc_periphs CLKID_PWM_AO_F>; 696 #pwm-cells = <3>; 697 status = "disabled"; 698 }; 699 700 pwm_ao_gh: pwm@32000 { 701 compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; 702 reg = <0x0 0x32000 0x0 0x24>; 703 clocks = <&clkc_periphs CLKID_PWM_AO_G>, 704 <&clkc_periphs CLKID_PWM_AO_H>; 705 #pwm-cells = <3>; 706 status = "disabled"; 707 }; 708 709 clock-measurer@48000 { 710 compatible = "amlogic,t7-clk-measure"; 711 reg = <0x0 0x48000 0x0 0x1c>; 712 }; 713 714 pwm_ab: pwm@58000 { 715 compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; 716 reg = <0x0 0x58000 0x0 0x24>; 717 clocks = <&clkc_periphs CLKID_PWM_A>, 718 <&clkc_periphs CLKID_PWM_B>; 719 #pwm-cells = <3>; 720 status = "disabled"; 721 }; 722 723 pwm_cd: pwm@5a000 { 724 compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; 725 reg = <0x0 0x5a000 0x0 0x24>; 726 clocks = <&clkc_periphs CLKID_PWM_C>, 727 <&clkc_periphs CLKID_PWM_D>; 728 #pwm-cells = <3>; 729 status = "disabled"; 730 }; 731 732 pwm_ef: pwm@5c000 { 733 compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; 734 reg = <0x0 0x5c000 0x0 0x24>; 735 clocks = <&clkc_periphs CLKID_PWM_E>, 736 <&clkc_periphs CLKID_PWM_F>; 737 #pwm-cells = <3>; 738 status = "disabled"; 739 }; 740 741 pwm_ao_ab: pwm@5e000 { 742 compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; 743 reg = <0x0 0x5e000 0x0 0x24>; 744 clocks = <&clkc_periphs CLKID_PWM_AO_A>, 745 <&clkc_periphs CLKID_PWM_AO_B>; 746 #pwm-cells = <3>; 747 status = "disabled"; 748 }; 749 750 pwm_ao_cd: pwm@60000 { 751 compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; 752 reg = <0x0 0x60000 0x0 0x24>; 753 clocks = <&clkc_periphs CLKID_PWM_AO_C>, 754 <&clkc_periphs CLKID_PWM_AO_D>; 755 #pwm-cells = <3>; 756 status = "disabled"; 757 }; 758 759 sd_emmc_a: mmc@88000 { 760 compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc"; 761 reg = <0x0 0x88000 0x0 0x800>; 762 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>, 764 <&clkc_periphs CLKID_SD_EMMC_A>, 765 <&scmi_clk CLKID_FCLK_DIV2>; 766 clock-names = "core", "clkin0", "clkin1"; 767 resets = <&reset RESET_SD_EMMC_A>; 768 assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A_SEL>; 769 assigned-clock-parents = <&xtal>; 770 status = "disabled"; 771 }; 772 773 sd_emmc_b: mmc@8a000 { 774 compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc"; 775 reg = <0x0 0x8a000 0x0 0x800>; 776 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; 777 clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>, 778 <&clkc_periphs CLKID_SD_EMMC_B>, 779 <&scmi_clk CLKID_FCLK_DIV2>; 780 clock-names = "core", "clkin0", "clkin1"; 781 resets = <&reset RESET_SD_EMMC_B>; 782 assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B_SEL>; 783 assigned-clock-parents = <&xtal>; 784 status = "disabled"; 785 }; 786 787 sd_emmc_c: mmc@8c000 { 788 compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc"; 789 reg = <0x0 0x8c000 0x0 0x800>; 790 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 791 clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>, 792 <&clkc_periphs CLKID_SD_EMMC_C>, 793 <&scmi_clk CLKID_FCLK_DIV2>; 794 clock-names = "core", "clkin0", "clkin1"; 795 resets = <&reset RESET_SD_EMMC_C>; 796 assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C_SEL>; 797 assigned-clock-parents = <&xtal>; 798 status = "disabled"; 799 }; 800 }; 801 802 }; 803}; 804