1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/dma/fsl-edma.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10 11dma_ipg_clk: clock-dma-ipg { 12 compatible = "fixed-clock"; 13 #clock-cells = <0>; 14 clock-frequency = <120000000>; 15 clock-output-names = "dma_ipg_clk"; 16}; 17 18dma_subsys: bus@5a000000 { 19 compatible = "simple-bus"; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; 23 24 lpspi0: spi@5a000000 { 25 compatible = "fsl,imx7ulp-spi"; 26 reg = <0x5a000000 0x10000>; 27 #address-cells = <1>; 28 #size-cells = <0>; 29 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-parent = <&gic>; 31 clocks = <&spi0_lpcg IMX_LPCG_CLK_0>, 32 <&spi0_lpcg IMX_LPCG_CLK_4>; 33 clock-names = "per", "ipg"; 34 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; 35 assigned-clock-rates = <60000000>; 36 power-domains = <&pd IMX_SC_R_SPI_0>; 37 dmas = <&edma2 1 0 0>, <&edma2 0 0 FSL_EDMA_RX>; 38 dma-names = "tx", "rx"; 39 status = "disabled"; 40 }; 41 42 lpspi1: spi@5a010000 { 43 compatible = "fsl,imx7ulp-spi"; 44 reg = <0x5a010000 0x10000>; 45 #address-cells = <1>; 46 #size-cells = <0>; 47 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 48 interrupt-parent = <&gic>; 49 clocks = <&spi1_lpcg IMX_LPCG_CLK_0>, 50 <&spi1_lpcg IMX_LPCG_CLK_4>; 51 clock-names = "per", "ipg"; 52 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; 53 assigned-clock-rates = <60000000>; 54 power-domains = <&pd IMX_SC_R_SPI_1>; 55 dmas = <&edma2 3 0 0>, <&edma2 2 0 FSL_EDMA_RX>; 56 dma-names = "tx", "rx"; 57 status = "disabled"; 58 }; 59 60 lpspi2: spi@5a020000 { 61 compatible = "fsl,imx7ulp-spi"; 62 reg = <0x5a020000 0x10000>; 63 #address-cells = <1>; 64 #size-cells = <0>; 65 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 66 interrupt-parent = <&gic>; 67 clocks = <&spi2_lpcg IMX_LPCG_CLK_0>, 68 <&spi2_lpcg IMX_LPCG_CLK_4>; 69 clock-names = "per", "ipg"; 70 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; 71 assigned-clock-rates = <60000000>; 72 power-domains = <&pd IMX_SC_R_SPI_2>; 73 dmas = <&edma2 5 0 0>, <&edma2 4 0 FSL_EDMA_RX>; 74 dma-names = "tx", "rx"; 75 status = "disabled"; 76 }; 77 78 lpspi3: spi@5a030000 { 79 compatible = "fsl,imx7ulp-spi"; 80 reg = <0x5a030000 0x10000>; 81 #address-cells = <1>; 82 #size-cells = <0>; 83 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-parent = <&gic>; 85 clocks = <&spi3_lpcg IMX_LPCG_CLK_0>, 86 <&spi3_lpcg IMX_LPCG_CLK_4>; 87 clock-names = "per", "ipg"; 88 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; 89 assigned-clock-rates = <60000000>; 90 power-domains = <&pd IMX_SC_R_SPI_3>; 91 dmas = <&edma2 7 0 0>, <&edma2 6 0 FSL_EDMA_RX>; 92 dma-names = "tx", "rx"; 93 status = "disabled"; 94 }; 95 96 lpuart0: serial@5a060000 { 97 reg = <0x5a060000 0x1000>; 98 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, 100 <&uart0_lpcg IMX_LPCG_CLK_0>; 101 clock-names = "ipg", "baud"; 102 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; 103 assigned-clock-rates = <80000000>; 104 power-domains = <&pd IMX_SC_R_UART_0>; 105 dma-names = "rx", "tx"; 106 dmas = <&edma2 8 0 FSL_EDMA_RX>, <&edma2 9 0 0>; 107 status = "disabled"; 108 }; 109 110 lpuart1: serial@5a070000 { 111 reg = <0x5a070000 0x1000>; 112 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, 114 <&uart1_lpcg IMX_LPCG_CLK_0>; 115 clock-names = "ipg", "baud"; 116 assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; 117 assigned-clock-rates = <80000000>; 118 power-domains = <&pd IMX_SC_R_UART_1>; 119 dma-names = "rx", "tx"; 120 dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 11 0 0>; 121 status = "disabled"; 122 }; 123 124 lpuart2: serial@5a080000 { 125 reg = <0x5a080000 0x1000>; 126 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, 128 <&uart2_lpcg IMX_LPCG_CLK_0>; 129 clock-names = "ipg", "baud"; 130 assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; 131 assigned-clock-rates = <80000000>; 132 power-domains = <&pd IMX_SC_R_UART_2>; 133 dma-names = "rx", "tx"; 134 dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>; 135 status = "disabled"; 136 }; 137 138 lpuart3: serial@5a090000 { 139 reg = <0x5a090000 0x1000>; 140 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, 142 <&uart3_lpcg IMX_LPCG_CLK_0>; 143 clock-names = "ipg", "baud"; 144 assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; 145 assigned-clock-rates = <80000000>; 146 power-domains = <&pd IMX_SC_R_UART_3>; 147 dma-names = "rx", "tx"; 148 dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>; 149 status = "disabled"; 150 }; 151 152 adma_pwm: pwm@5a190000 { 153 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; 154 reg = <0x5a190000 0x1000>; 155 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&adma_pwm_lpcg IMX_LPCG_CLK_4>, 157 <&adma_pwm_lpcg IMX_LPCG_CLK_0>; 158 clock-names = "ipg", "per"; 159 assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>; 160 assigned-clock-rates = <24000000>; 161 #pwm-cells = <3>; 162 power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; 163 }; 164 165 edma2: dma-controller@5a1f0000 { 166 compatible = "fsl,imx8qm-edma"; 167 reg = <0x5a1f0000 0x170000>; 168 #dma-cells = <3>; 169 dma-channels = <16>; 170 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 187 power-domains = <&pd IMX_SC_R_DMA_2_CH0>, 188 <&pd IMX_SC_R_DMA_2_CH1>, 189 <&pd IMX_SC_R_DMA_2_CH2>, 190 <&pd IMX_SC_R_DMA_2_CH3>, 191 <&pd IMX_SC_R_DMA_2_CH4>, 192 <&pd IMX_SC_R_DMA_2_CH5>, 193 <&pd IMX_SC_R_DMA_2_CH6>, 194 <&pd IMX_SC_R_DMA_2_CH7>, 195 <&pd IMX_SC_R_DMA_2_CH8>, 196 <&pd IMX_SC_R_DMA_2_CH9>, 197 <&pd IMX_SC_R_DMA_2_CH10>, 198 <&pd IMX_SC_R_DMA_2_CH11>, 199 <&pd IMX_SC_R_DMA_2_CH12>, 200 <&pd IMX_SC_R_DMA_2_CH13>, 201 <&pd IMX_SC_R_DMA_2_CH14>, 202 <&pd IMX_SC_R_DMA_2_CH15>; 203 }; 204 205 spi0_lpcg: clock-controller@5a400000 { 206 compatible = "fsl,imx8qxp-lpcg"; 207 reg = <0x5a400000 0x10000>; 208 #clock-cells = <1>; 209 clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, 210 <&dma_ipg_clk>; 211 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 212 clock-output-names = "spi0_lpcg_clk", 213 "spi0_lpcg_ipg_clk"; 214 power-domains = <&pd IMX_SC_R_SPI_0>; 215 }; 216 217 spi1_lpcg: clock-controller@5a410000 { 218 compatible = "fsl,imx8qxp-lpcg"; 219 reg = <0x5a410000 0x10000>; 220 #clock-cells = <1>; 221 clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, 222 <&dma_ipg_clk>; 223 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 224 clock-output-names = "spi1_lpcg_clk", 225 "spi1_lpcg_ipg_clk"; 226 power-domains = <&pd IMX_SC_R_SPI_1>; 227 }; 228 229 spi2_lpcg: clock-controller@5a420000 { 230 compatible = "fsl,imx8qxp-lpcg"; 231 reg = <0x5a420000 0x10000>; 232 #clock-cells = <1>; 233 clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, 234 <&dma_ipg_clk>; 235 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 236 clock-output-names = "spi2_lpcg_clk", 237 "spi2_lpcg_ipg_clk"; 238 power-domains = <&pd IMX_SC_R_SPI_2>; 239 }; 240 241 spi3_lpcg: clock-controller@5a430000 { 242 compatible = "fsl,imx8qxp-lpcg"; 243 reg = <0x5a430000 0x10000>; 244 #clock-cells = <1>; 245 clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, 246 <&dma_ipg_clk>; 247 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 248 clock-output-names = "spi3_lpcg_clk", 249 "spi3_lpcg_ipg_clk"; 250 power-domains = <&pd IMX_SC_R_SPI_3>; 251 }; 252 253 uart0_lpcg: clock-controller@5a460000 { 254 compatible = "fsl,imx8qxp-lpcg"; 255 reg = <0x5a460000 0x10000>; 256 #clock-cells = <1>; 257 clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, 258 <&dma_ipg_clk>; 259 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 260 clock-output-names = "uart0_lpcg_baud_clk", 261 "uart0_lpcg_ipg_clk"; 262 power-domains = <&pd IMX_SC_R_UART_0>; 263 }; 264 265 uart1_lpcg: clock-controller@5a470000 { 266 compatible = "fsl,imx8qxp-lpcg"; 267 reg = <0x5a470000 0x10000>; 268 #clock-cells = <1>; 269 clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, 270 <&dma_ipg_clk>; 271 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 272 clock-output-names = "uart1_lpcg_baud_clk", 273 "uart1_lpcg_ipg_clk"; 274 power-domains = <&pd IMX_SC_R_UART_1>; 275 }; 276 277 uart2_lpcg: clock-controller@5a480000 { 278 compatible = "fsl,imx8qxp-lpcg"; 279 reg = <0x5a480000 0x10000>; 280 #clock-cells = <1>; 281 clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, 282 <&dma_ipg_clk>; 283 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 284 clock-output-names = "uart2_lpcg_baud_clk", 285 "uart2_lpcg_ipg_clk"; 286 power-domains = <&pd IMX_SC_R_UART_2>; 287 }; 288 289 uart3_lpcg: clock-controller@5a490000 { 290 compatible = "fsl,imx8qxp-lpcg"; 291 reg = <0x5a490000 0x10000>; 292 #clock-cells = <1>; 293 clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, 294 <&dma_ipg_clk>; 295 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 296 clock-output-names = "uart3_lpcg_baud_clk", 297 "uart3_lpcg_ipg_clk"; 298 power-domains = <&pd IMX_SC_R_UART_3>; 299 }; 300 301 adma_pwm_lpcg: clock-controller@5a590000 { 302 compatible = "fsl,imx8qxp-lpcg"; 303 reg = <0x5a590000 0x10000>; 304 #clock-cells = <1>; 305 clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>, 306 <&dma_ipg_clk>; 307 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 308 clock-output-names = "adma_pwm_lpcg_clk", 309 "adma_pwm_lpcg_ipg_clk"; 310 power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; 311 }; 312 313 i2c0: i2c@5a800000 { 314 reg = <0x5a800000 0x4000>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>, 319 <&i2c0_lpcg IMX_LPCG_CLK_4>; 320 clock-names = "per", "ipg"; 321 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; 322 assigned-clock-rates = <24000000>; 323 power-domains = <&pd IMX_SC_R_I2C_0>; 324 status = "disabled"; 325 }; 326 327 i2c1: i2c@5a810000 { 328 reg = <0x5a810000 0x4000>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>, 333 <&i2c1_lpcg IMX_LPCG_CLK_4>; 334 clock-names = "per", "ipg"; 335 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; 336 assigned-clock-rates = <24000000>; 337 power-domains = <&pd IMX_SC_R_I2C_1>; 338 status = "disabled"; 339 }; 340 341 i2c2: i2c@5a820000 { 342 reg = <0x5a820000 0x4000>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>, 347 <&i2c2_lpcg IMX_LPCG_CLK_4>; 348 clock-names = "per", "ipg"; 349 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; 350 assigned-clock-rates = <24000000>; 351 power-domains = <&pd IMX_SC_R_I2C_2>; 352 status = "disabled"; 353 }; 354 355 i2c3: i2c@5a830000 { 356 reg = <0x5a830000 0x4000>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>, 361 <&i2c3_lpcg IMX_LPCG_CLK_4>; 362 clock-names = "per", "ipg"; 363 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; 364 assigned-clock-rates = <24000000>; 365 power-domains = <&pd IMX_SC_R_I2C_3>; 366 status = "disabled"; 367 }; 368 369 adc0: adc@5a880000 { 370 compatible = "nxp,imx8qxp-adc"; 371 #io-channel-cells = <1>; 372 reg = <0x5a880000 0x10000>; 373 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 374 interrupt-parent = <&gic>; 375 clocks = <&adc0_lpcg IMX_LPCG_CLK_0>, 376 <&adc0_lpcg IMX_LPCG_CLK_4>; 377 clock-names = "per", "ipg"; 378 assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; 379 assigned-clock-rates = <24000000>; 380 power-domains = <&pd IMX_SC_R_ADC_0>; 381 status = "disabled"; 382 }; 383 384 adc1: adc@5a890000 { 385 compatible = "nxp,imx8qxp-adc"; 386 #io-channel-cells = <1>; 387 reg = <0x5a890000 0x10000>; 388 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 389 interrupt-parent = <&gic>; 390 clocks = <&adc1_lpcg IMX_LPCG_CLK_0>, 391 <&adc1_lpcg IMX_LPCG_CLK_4>; 392 clock-names = "per", "ipg"; 393 assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; 394 assigned-clock-rates = <24000000>; 395 power-domains = <&pd IMX_SC_R_ADC_1>; 396 status = "disabled"; 397 }; 398 399 flexcan1: can@5a8d0000 { 400 compatible = "fsl,imx8qm-flexcan"; 401 reg = <0x5a8d0000 0x10000>; 402 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 403 interrupt-parent = <&gic>; 404 clocks = <&can0_lpcg IMX_LPCG_CLK_4>, 405 <&can0_lpcg IMX_LPCG_CLK_0>; 406 clock-names = "ipg", "per"; 407 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 408 assigned-clock-rates = <40000000>; 409 power-domains = <&pd IMX_SC_R_CAN_0>; 410 /* SLSlice[4] */ 411 fsl,clk-source = /bits/ 8 <0>; 412 fsl,scu-index = /bits/ 8 <0>; 413 status = "disabled"; 414 }; 415 416 flexcan2: can@5a8e0000 { 417 compatible = "fsl,imx8qm-flexcan"; 418 reg = <0x5a8e0000 0x10000>; 419 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 420 interrupt-parent = <&gic>; 421 /* CAN0 clock and PD is shared among all CAN instances as 422 * CAN1 shares CAN0's clock and to enable CAN0's clock it 423 * has to be powered on. 424 */ 425 clocks = <&can0_lpcg IMX_LPCG_CLK_4>, 426 <&can0_lpcg IMX_LPCG_CLK_0>; 427 clock-names = "ipg", "per"; 428 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 429 assigned-clock-rates = <40000000>; 430 power-domains = <&pd IMX_SC_R_CAN_1>; 431 /* SLSlice[4] */ 432 fsl,clk-source = /bits/ 8 <0>; 433 fsl,scu-index = /bits/ 8 <1>; 434 status = "disabled"; 435 }; 436 437 flexcan3: can@5a8f0000 { 438 compatible = "fsl,imx8qm-flexcan"; 439 reg = <0x5a8f0000 0x10000>; 440 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 441 interrupt-parent = <&gic>; 442 /* CAN0 clock and PD is shared among all CAN instances as 443 * CAN2 shares CAN0's clock and to enable CAN0's clock it 444 * has to be powered on. 445 */ 446 clocks = <&can0_lpcg IMX_LPCG_CLK_4>, 447 <&can0_lpcg IMX_LPCG_CLK_0>; 448 clock-names = "ipg", "per"; 449 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 450 assigned-clock-rates = <40000000>; 451 power-domains = <&pd IMX_SC_R_CAN_2>; 452 /* SLSlice[4] */ 453 fsl,clk-source = /bits/ 8 <0>; 454 fsl,scu-index = /bits/ 8 <2>; 455 status = "disabled"; 456 }; 457 458 edma3: dma-controller@5a9f0000 { 459 compatible = "fsl,imx8qm-edma"; 460 reg = <0x5a9f0000 0x90000>; 461 #dma-cells = <3>; 462 dma-channels = <8>; 463 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 472 power-domains = <&pd IMX_SC_R_DMA_3_CH0>, 473 <&pd IMX_SC_R_DMA_3_CH1>, 474 <&pd IMX_SC_R_DMA_3_CH2>, 475 <&pd IMX_SC_R_DMA_3_CH3>, 476 <&pd IMX_SC_R_DMA_3_CH4>, 477 <&pd IMX_SC_R_DMA_3_CH5>, 478 <&pd IMX_SC_R_DMA_3_CH6>, 479 <&pd IMX_SC_R_DMA_3_CH7>; 480 }; 481 482 i2c0_lpcg: clock-controller@5ac00000 { 483 compatible = "fsl,imx8qxp-lpcg"; 484 reg = <0x5ac00000 0x10000>; 485 #clock-cells = <1>; 486 clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, 487 <&dma_ipg_clk>; 488 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 489 clock-output-names = "i2c0_lpcg_clk", 490 "i2c0_lpcg_ipg_clk"; 491 power-domains = <&pd IMX_SC_R_I2C_0>; 492 }; 493 494 i2c1_lpcg: clock-controller@5ac10000 { 495 compatible = "fsl,imx8qxp-lpcg"; 496 reg = <0x5ac10000 0x10000>; 497 #clock-cells = <1>; 498 clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, 499 <&dma_ipg_clk>; 500 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 501 clock-output-names = "i2c1_lpcg_clk", 502 "i2c1_lpcg_ipg_clk"; 503 power-domains = <&pd IMX_SC_R_I2C_1>; 504 }; 505 506 i2c2_lpcg: clock-controller@5ac20000 { 507 compatible = "fsl,imx8qxp-lpcg"; 508 reg = <0x5ac20000 0x10000>; 509 #clock-cells = <1>; 510 clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, 511 <&dma_ipg_clk>; 512 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 513 clock-output-names = "i2c2_lpcg_clk", 514 "i2c2_lpcg_ipg_clk"; 515 power-domains = <&pd IMX_SC_R_I2C_2>; 516 }; 517 518 i2c3_lpcg: clock-controller@5ac30000 { 519 compatible = "fsl,imx8qxp-lpcg"; 520 reg = <0x5ac30000 0x10000>; 521 #clock-cells = <1>; 522 clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, 523 <&dma_ipg_clk>; 524 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 525 clock-output-names = "i2c3_lpcg_clk", 526 "i2c3_lpcg_ipg_clk"; 527 power-domains = <&pd IMX_SC_R_I2C_3>; 528 }; 529 530 adc0_lpcg: clock-controller@5ac80000 { 531 compatible = "fsl,imx8qxp-lpcg"; 532 reg = <0x5ac80000 0x10000>; 533 #clock-cells = <1>; 534 clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, 535 <&dma_ipg_clk>; 536 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 537 clock-output-names = "adc0_lpcg_clk", 538 "adc0_lpcg_ipg_clk"; 539 power-domains = <&pd IMX_SC_R_ADC_0>; 540 }; 541 542 adc1_lpcg: clock-controller@5ac90000 { 543 compatible = "fsl,imx8qxp-lpcg"; 544 reg = <0x5ac90000 0x10000>; 545 #clock-cells = <1>; 546 clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, 547 <&dma_ipg_clk>; 548 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 549 clock-output-names = "adc1_lpcg_clk", 550 "adc1_lpcg_ipg_clk"; 551 power-domains = <&pd IMX_SC_R_ADC_1>; 552 }; 553 554 can0_lpcg: clock-controller@5acd0000 { 555 compatible = "fsl,imx8qxp-lpcg"; 556 reg = <0x5acd0000 0x10000>; 557 #clock-cells = <1>; 558 clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, 559 <&dma_ipg_clk>, <&dma_ipg_clk>; 560 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 561 clock-output-names = "can0_lpcg_pe_clk", 562 "can0_lpcg_ipg_clk", 563 "can0_lpcg_chi_clk"; 564 power-domains = <&pd IMX_SC_R_CAN_0>; 565 }; 566}; 567