xref: /linux/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi (revision 115e74a29b530d121891238e9551c4bcdf7b04b5) 
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree nodes common for all GS101-based Pixel
4 *
5 * Copyright 2021-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/usb/pd.h>
14#include "gs101-pinctrl.h"
15#include "gs101.dtsi"
16
17/ {
18	aliases {
19		serial0 = &serial_0;
20	};
21
22	chosen {
23		/* Bootloader expects bootargs specified otherwise it crashes */
24		bootargs = "";
25		stdout-path = &serial_0;
26
27		/* Use display framebuffer as setup by bootloader */
28		framebuffer0: framebuffer-0 {
29			compatible = "simple-framebuffer";
30			memory-region = <&cont_splash_mem>;
31			/* format properties to be added by actual board */
32			status = "disabled";
33		};
34	};
35
36	gpio-keys {
37		compatible = "gpio-keys";
38		pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>;
39		pinctrl-names = "default";
40
41		button-vol-down {
42			label = "KEY_VOLUMEDOWN";
43			linux,code = <KEY_VOLUMEDOWN>;
44			gpios = <&gpa7 3 GPIO_ACTIVE_LOW>;
45			wakeup-source;
46		};
47
48		button-vol-up {
49			label = "KEY_VOLUMEUP";
50			linux,code = <KEY_VOLUMEUP>;
51			gpios = <&gpa8 1 GPIO_ACTIVE_LOW>;
52			wakeup-source;
53		};
54
55		button-power {
56			label = "KEY_POWER";
57			linux,code = <KEY_POWER>;
58			gpios = <&gpa10 1 GPIO_ACTIVE_LOW>;
59			wakeup-source;
60		};
61	};
62
63	reboot-mode {
64		compatible = "nvmem-reboot-mode";
65		nvmem-cells = <&nvmem_reboot_mode>;
66		nvmem-cell-names = "reboot-mode";
67		mode-bootloader = <0x800000fc>;
68		mode-charge = <0x8000000a>;
69		mode-dm-verity-device-corrupted = <0x80000050>;
70		mode-fastboot = <0x800000fa>;
71		mode-reboot-ab-update = <0x80000052>;
72		mode-recovery = <0x800000ff>;
73		mode-rescue = <0x800000f9>;
74		mode-shutdown-thermal = <0x80000051>;
75		mode-shutdown-thermal-battery = <0x80000051>;
76	};
77
78	/* TODO: Remove this once PMIC is implemented  */
79	reg_placeholder: regulator-0 {
80		compatible = "regulator-fixed";
81		regulator-name = "placeholder_reg";
82	};
83
84	/* TODO: Remove this once S2MPG11 slave PMIC is implemented  */
85	ufs_0_fixed_vcc_reg: regulator-1 {
86		compatible = "regulator-fixed";
87		regulator-name = "ufs-vcc";
88		gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>;
89		regulator-boot-on;
90		enable-active-high;
91	};
92
93	reserved-memory {
94		cont_splash_mem: splash@fac00000 {
95			/* size to be updated by actual board */
96			reg = <0x0 0xfac00000 0x0>;
97			no-map;
98			status = "disabled";
99		};
100	};
101};
102
103&acpm_ipc {
104	pmic {
105		compatible = "samsung,s2mpg10-pmic";
106		interrupts-extended = <&gpa0 6 IRQ_TYPE_LEVEL_LOW>;
107		pinctrl-names = "default";
108		pinctrl-0 = <&pmic_int>;
109		system-power-controller;
110		wakeup-source;
111
112		regulators {
113		};
114	};
115};
116
117&ext_24_5m {
118	clock-frequency = <24576000>;
119};
120
121&ext_200m {
122	clock-frequency = <200000000>;
123};
124
125&hsi2c_8 {
126	status = "okay";
127
128	eeprom: eeprom@50 {
129		compatible = "atmel,24c08";
130		reg = <0x50>;
131	};
132};
133
134&hsi2c_12 {
135	status = "okay";
136	/* TODO: add the devices once drivers exist */
137
138	usb-typec@25 {
139		compatible = "maxim,max77759-tcpci", "maxim,max33359";
140		reg = <0x25>;
141		interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>;
142		pinctrl-0 = <&typec_int>;
143		pinctrl-names = "default";
144
145		connector {
146			compatible = "usb-c-connector";
147			label = "USB-C";
148			data-role = "dual";
149			power-role = "dual";
150			self-powered;
151			try-power-role = "sink";
152			op-sink-microwatt = <2600000>;
153			slow-charger-loop;
154			/*
155			 * max77759 operating in reverse boost mode (0xA) can
156			 * source up to 1.5A while extboost can only do ~1A.
157			 * Since extboost is the primary path, advertise 900mA.
158			 */
159			source-pdos = <PDO_FIXED(5000, 900,
160						 (PDO_FIXED_SUSPEND
161						  | PDO_FIXED_USB_COMM
162						  | PDO_FIXED_DATA_SWAP
163						  | PDO_FIXED_DUAL_ROLE))>;
164			sink-pdos = <PDO_FIXED(5000, 3000,
165					       (PDO_FIXED_DATA_SWAP
166						| PDO_FIXED_USB_COMM
167						| PDO_FIXED_HIGHER_CAP
168						| PDO_FIXED_DUAL_ROLE))
169				     PDO_FIXED(9000, 2200, 0)
170				     PDO_PPS_APDO(5000, 11000, 3000)>;
171			sink-vdos = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
172					     IDH_PTYPE_DFP_HOST, 2, 0x18d1)
173				     VDO_CERT(0x0)
174				     VDO_PRODUCT(0x4ee1, 0x0)
175				     VDO_UFP(UFP_VDO_VER1_2,
176					     (DEV_USB2_CAPABLE
177					      | DEV_USB3_CAPABLE),
178					     UFP_RECEPTACLE, 0,
179					     AMA_VCONN_NOT_REQ, 0,
180					     UFP_ALTMODE_NOT_SUPP,
181					     UFP_USB32_GEN1)
182				     /* padding */ 0
183				     VDO_DFP(DFP_VDO_VER1_1,
184					     (HOST_USB2_CAPABLE
185					      | HOST_USB3_CAPABLE),
186					     DFP_RECEPTACLE, 0)>;
187			sink-vdos-v1 = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
188						0, 0, 0x18d1)
189					VDO_CERT(0x0)
190					VDO_PRODUCT(0x4ee1, 0x0)>;
191			/*
192			 * Until bootloader is updated to set those two when
193			 * console is enabled, we disable PD here.
194			 */
195			pd-disable;
196			typec-power-opmode = "default";
197
198			ports {
199				#address-cells = <1>;
200				#size-cells = <0>;
201
202				port@0 {
203					reg = <0>;
204
205					usbc0_orien_sw: endpoint {
206						remote-endpoint = <&usbdrd31_phy_orien_switch>;
207					};
208				};
209
210				port@1 {
211					reg = <1>;
212
213					usbc0_role_sw: endpoint {
214						remote-endpoint = <&usbdrd31_dwc3_role_switch>;
215					};
216				};
217			};
218		};
219	};
220
221	pmic@66 {
222		compatible = "maxim,max77759";
223		reg = <0x66>;
224
225		pinctrl-0 = <&if_pmic_int>;
226		pinctrl-names = "default";
227		interrupts-extended = <&gpa8 3 IRQ_TYPE_LEVEL_LOW>;
228
229		interrupt-controller;
230		#interrupt-cells = <2>;
231
232		gpio {
233			compatible = "maxim,max77759-gpio";
234
235			gpio-controller;
236			#gpio-cells = <2>;
237			/*
238			 * "Human-readable name [SIGNAL_LABEL]" where the
239			 * latter comes from the schematic
240			 */
241			gpio-line-names = "OTG boost [OTG_BOOST_EN]",
242					  "max20339 IRQ [MW_OVP_INT_L]";
243
244			interrupt-controller;
245			#interrupt-cells = <2>;
246		};
247
248		nvmem-0 {
249			compatible = "maxim,max77759-nvmem";
250
251			nvmem-layout {
252				compatible = "fixed-layout";
253				#address-cells = <1>;
254				#size-cells = <1>;
255
256				nvmem_reboot_mode: reboot-mode@0 {
257					reg = <0x0 0x4>;
258				};
259
260				boot-reason@4 {
261					reg = <0x4 0x4>;
262				};
263
264				shutdown-user-flag@8 {
265					reg = <0x8 0x1>;
266				};
267
268				rsoc@a {
269					reg = <0xa 0x2>;
270				};
271			};
272		};
273	};
274};
275
276&pinctrl_far_alive {
277	key_voldown: key-voldown-pins {
278		samsung,pins = "gpa7-3";
279		samsung,pin-function = <GS101_PIN_FUNC_EINT>;
280		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
281		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
282	};
283
284	key_volup: key-volup-pins {
285		samsung,pins = "gpa8-1";
286		samsung,pin-function = <GS101_PIN_FUNC_EINT>;
287		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
288		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
289	};
290
291	typec_int: typec-int-pins {
292		samsung,pins = "gpa8-2";
293		samsung,pin-function = <GS101_PIN_FUNC_EINT>;
294		samsung,pin-pud = <GS101_PIN_PULL_UP>;
295		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
296	};
297
298	if_pmic_int: if-pmic-int-pins {
299		samsung,pins = "gpa8-3";
300		samsung,pin-function = <GS101_PIN_FUNC_EINT>;
301		samsung,pin-pud = <GS101_PIN_PULL_UP>;
302		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
303	};
304};
305
306&pinctrl_gpio_alive {
307	pmic_int: pmic-int-pins {
308		samsung,pins = "gpa0-6";
309		samsung,pin-function = <GS101_PIN_FUNC_EINT>;
310		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
311	};
312
313	key_power: key-power-pins {
314		samsung,pins = "gpa10-1";
315		samsung,pin-function = <GS101_PIN_FUNC_EINT>;
316		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
317		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
318	};
319};
320
321&serial_0 {
322	status = "okay";
323};
324
325&ufs_0 {
326	status = "okay";
327	vcc-supply = <&ufs_0_fixed_vcc_reg>;
328};
329
330&ufs_0_phy {
331	status = "okay";
332};
333
334&usbdrd31 {
335	vdd10-supply = <&reg_placeholder>;
336	vdd33-supply = <&reg_placeholder>;
337	status = "okay";
338};
339
340&usbdrd31_dwc3 {
341	dr_mode = "otg";
342	usb-role-switch;
343	role-switch-default-mode = "peripheral";
344	maximum-speed = "super-speed-plus";
345	status = "okay";
346
347	port {
348		usbdrd31_dwc3_role_switch: endpoint {
349			remote-endpoint = <&usbc0_role_sw>;
350		};
351	};
352};
353
354&usbdrd31_phy {
355	orientation-switch;
356	/* TODO: Update these once PMIC is implemented */
357	pll-supply = <&reg_placeholder>;
358	dvdd-usb20-supply = <&reg_placeholder>;
359	vddh-usb20-supply = <&reg_placeholder>;
360	vdd33-usb20-supply = <&reg_placeholder>;
361	vdda-usbdp-supply = <&reg_placeholder>;
362	vddh-usbdp-supply = <&reg_placeholder>;
363	status = "okay";
364
365	port {
366		usbdrd31_phy_orien_switch: endpoint {
367			remote-endpoint = <&usbc0_orien_sw>;
368		};
369	};
370};
371
372&usi_uart {
373	samsung,clkreq-on; /* needed for UART mode */
374	status = "okay";
375};
376
377&usi8 {
378	samsung,mode = <USI_MODE_I2C>;
379	status = "okay";
380};
381
382&usi12 {
383	samsung,mode = <USI_MODE_I2C>;
384	status = "okay";
385};
386
387&watchdog_cl0 {
388	timeout-sec = <30>;
389	status = "okay";
390};
391