1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2023 Intel Corporation
3
4 /*
5 * Soundwire Intel ops for LunarLake
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/cleanup.h>
10 #include <linux/device.h>
11 #include <linux/soundwire/sdw_registers.h>
12 #include <linux/soundwire/sdw.h>
13 #include <linux/soundwire/sdw_intel.h>
14 #include <linux/string_choices.h>
15 #include <sound/hdaudio.h>
16 #include <sound/hda-mlink.h>
17 #include <sound/hda-sdw-bpt.h>
18 #include <sound/hda_register.h>
19 #include <sound/pcm_params.h>
20 #include "cadence_master.h"
21 #include "bus.h"
22 #include "intel.h"
23
sdw_slave_bpt_stream_add(struct sdw_slave * slave,struct sdw_stream_runtime * stream)24 static int sdw_slave_bpt_stream_add(struct sdw_slave *slave, struct sdw_stream_runtime *stream)
25 {
26 struct sdw_stream_config sconfig = {0};
27 struct sdw_port_config pconfig = {0};
28 int ret;
29
30 /* arbitrary configuration */
31 sconfig.frame_rate = 16000;
32 sconfig.ch_count = 1;
33 sconfig.bps = 32; /* this is required for BPT/BRA */
34 sconfig.direction = SDW_DATA_DIR_RX;
35 sconfig.type = SDW_STREAM_BPT;
36
37 pconfig.num = 0;
38 pconfig.ch_mask = BIT(0);
39
40 ret = sdw_stream_add_slave(slave, &sconfig, &pconfig, 1, stream);
41 if (ret)
42 dev_err(&slave->dev, "%s: failed: %d\n", __func__, ret);
43
44 return ret;
45 }
46
intel_ace2x_bpt_open_stream(struct sdw_intel * sdw,struct sdw_slave * slave,struct sdw_bpt_msg * msg)47 static int intel_ace2x_bpt_open_stream(struct sdw_intel *sdw, struct sdw_slave *slave,
48 struct sdw_bpt_msg *msg)
49 {
50 struct sdw_cdns *cdns = &sdw->cdns;
51 struct sdw_bus *bus = &cdns->bus;
52 struct sdw_master_prop *prop = &bus->prop;
53 struct sdw_stream_runtime *stream;
54 struct sdw_stream_config sconfig;
55 struct sdw_port_config *pconfig;
56 unsigned int pdi0_buffer_size;
57 unsigned int tx_dma_bandwidth;
58 unsigned int pdi1_buffer_size;
59 unsigned int rx_dma_bandwidth;
60 unsigned int data_per_frame;
61 unsigned int tx_total_bytes;
62 struct sdw_cdns_pdi *pdi0;
63 struct sdw_cdns_pdi *pdi1;
64 unsigned int num_frames;
65 int command;
66 int ret1;
67 int ret;
68 int dir;
69 int i;
70
71 stream = sdw_alloc_stream("BPT", SDW_STREAM_BPT);
72 if (!stream)
73 return -ENOMEM;
74
75 cdns->bus.bpt_stream = stream;
76
77 ret = sdw_slave_bpt_stream_add(slave, stream);
78 if (ret < 0)
79 goto release_stream;
80
81 /* handle PDI0 first */
82 dir = SDW_DATA_DIR_TX;
83
84 pdi0 = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, 1, dir, 0);
85 if (!pdi0) {
86 dev_err(cdns->dev, "%s: sdw_cdns_alloc_pdi0 failed\n", __func__);
87 ret = -EINVAL;
88 goto remove_slave;
89 }
90
91 sdw_cdns_config_stream(cdns, 1, dir, pdi0);
92
93 /* handle PDI1 */
94 dir = SDW_DATA_DIR_RX;
95
96 pdi1 = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, 1, dir, 1);
97 if (!pdi1) {
98 dev_err(cdns->dev, "%s: sdw_cdns_alloc_pdi1 failed\n", __func__);
99 ret = -EINVAL;
100 goto remove_slave;
101 }
102
103 sdw_cdns_config_stream(cdns, 1, dir, pdi1);
104
105 /*
106 * the port config direction, number of channels and frame
107 * rate is totally arbitrary
108 */
109 sconfig.direction = dir;
110 sconfig.ch_count = 1;
111 sconfig.frame_rate = 16000;
112 sconfig.type = SDW_STREAM_BPT;
113 sconfig.bps = 32; /* this is required for BPT/BRA */
114
115 /* Port configuration */
116 pconfig = kcalloc(2, sizeof(*pconfig), GFP_KERNEL);
117 if (!pconfig) {
118 ret = -ENOMEM;
119 goto remove_slave;
120 }
121
122 for (i = 0; i < 2 /* num_pdi */; i++) {
123 pconfig[i].num = i;
124 pconfig[i].ch_mask = 1;
125 }
126
127 ret = sdw_stream_add_master(&cdns->bus, &sconfig, pconfig, 2, stream);
128 kfree(pconfig);
129
130 if (ret < 0) {
131 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
132 goto remove_slave;
133 }
134
135 ret = sdw_prepare_stream(cdns->bus.bpt_stream);
136 if (ret < 0)
137 goto remove_master;
138
139 command = (msg->flags & SDW_MSG_FLAG_WRITE) ? 0 : 1;
140
141 ret = sdw_cdns_bpt_find_buffer_sizes(command, cdns->bus.params.row, cdns->bus.params.col,
142 msg->len, SDW_BPT_MSG_MAX_BYTES, &data_per_frame,
143 &pdi0_buffer_size, &pdi1_buffer_size, &num_frames);
144 if (ret < 0)
145 goto deprepare_stream;
146
147 sdw->bpt_ctx.pdi0_buffer_size = pdi0_buffer_size;
148 sdw->bpt_ctx.pdi1_buffer_size = pdi1_buffer_size;
149 sdw->bpt_ctx.num_frames = num_frames;
150 sdw->bpt_ctx.data_per_frame = data_per_frame;
151 tx_dma_bandwidth = div_u64((u64)pdi0_buffer_size * 8 * (u64)prop->default_frame_rate,
152 num_frames);
153 rx_dma_bandwidth = div_u64((u64)pdi1_buffer_size * 8 * (u64)prop->default_frame_rate,
154 num_frames);
155
156 dev_dbg(cdns->dev, "Message len %d transferred in %d frames (%d per frame)\n",
157 msg->len, num_frames, data_per_frame);
158 dev_dbg(cdns->dev, "sizes pdi0 %d pdi1 %d tx_bandwidth %d rx_bandwidth %d\n",
159 pdi0_buffer_size, pdi1_buffer_size, tx_dma_bandwidth, rx_dma_bandwidth);
160
161 ret = hda_sdw_bpt_open(cdns->dev->parent, /* PCI device */
162 sdw->instance, &sdw->bpt_ctx.bpt_tx_stream,
163 &sdw->bpt_ctx.dmab_tx_bdl, pdi0_buffer_size, tx_dma_bandwidth,
164 &sdw->bpt_ctx.bpt_rx_stream, &sdw->bpt_ctx.dmab_rx_bdl,
165 pdi1_buffer_size, rx_dma_bandwidth);
166 if (ret < 0) {
167 dev_err(cdns->dev, "%s: hda_sdw_bpt_open failed %d\n", __func__, ret);
168 goto deprepare_stream;
169 }
170
171 if (!command) {
172 ret = sdw_cdns_prepare_write_dma_buffer(msg->dev_num, msg->addr, msg->buf,
173 msg->len, data_per_frame,
174 sdw->bpt_ctx.dmab_tx_bdl.area,
175 pdi0_buffer_size, &tx_total_bytes);
176 } else {
177 ret = sdw_cdns_prepare_read_dma_buffer(msg->dev_num, msg->addr, msg->len,
178 data_per_frame,
179 sdw->bpt_ctx.dmab_tx_bdl.area,
180 pdi0_buffer_size, &tx_total_bytes);
181 }
182
183 if (!ret)
184 return 0;
185
186 dev_err(cdns->dev, "%s: sdw_prepare_%s_dma_buffer failed %d\n",
187 __func__, str_read_write(command), ret);
188
189 ret1 = hda_sdw_bpt_close(cdns->dev->parent, /* PCI device */
190 sdw->bpt_ctx.bpt_tx_stream, &sdw->bpt_ctx.dmab_tx_bdl,
191 sdw->bpt_ctx.bpt_rx_stream, &sdw->bpt_ctx.dmab_rx_bdl);
192 if (ret1 < 0)
193 dev_err(cdns->dev, "%s: hda_sdw_bpt_close failed: ret %d\n",
194 __func__, ret1);
195
196 deprepare_stream:
197 sdw_deprepare_stream(cdns->bus.bpt_stream);
198
199 remove_master:
200 ret1 = sdw_stream_remove_master(&cdns->bus, cdns->bus.bpt_stream);
201 if (ret1 < 0)
202 dev_err(cdns->dev, "%s: remove master failed: %d\n",
203 __func__, ret1);
204
205 remove_slave:
206 ret1 = sdw_stream_remove_slave(slave, cdns->bus.bpt_stream);
207 if (ret1 < 0)
208 dev_err(cdns->dev, "%s: remove slave failed: %d\n",
209 __func__, ret1);
210
211 release_stream:
212 sdw_release_stream(cdns->bus.bpt_stream);
213 cdns->bus.bpt_stream = NULL;
214
215 return ret;
216 }
217
intel_ace2x_bpt_close_stream(struct sdw_intel * sdw,struct sdw_slave * slave,struct sdw_bpt_msg * msg)218 static void intel_ace2x_bpt_close_stream(struct sdw_intel *sdw, struct sdw_slave *slave,
219 struct sdw_bpt_msg *msg)
220 {
221 struct sdw_cdns *cdns = &sdw->cdns;
222 int ret;
223
224 ret = hda_sdw_bpt_close(cdns->dev->parent /* PCI device */, sdw->bpt_ctx.bpt_tx_stream,
225 &sdw->bpt_ctx.dmab_tx_bdl, sdw->bpt_ctx.bpt_rx_stream,
226 &sdw->bpt_ctx.dmab_rx_bdl);
227 if (ret < 0)
228 dev_err(cdns->dev, "%s: hda_sdw_bpt_close failed: ret %d\n",
229 __func__, ret);
230
231 ret = sdw_deprepare_stream(cdns->bus.bpt_stream);
232 if (ret < 0)
233 dev_err(cdns->dev, "%s: sdw_deprepare_stream failed: ret %d\n",
234 __func__, ret);
235
236 ret = sdw_stream_remove_master(&cdns->bus, cdns->bus.bpt_stream);
237 if (ret < 0)
238 dev_err(cdns->dev, "%s: remove master failed: %d\n",
239 __func__, ret);
240
241 ret = sdw_stream_remove_slave(slave, cdns->bus.bpt_stream);
242 if (ret < 0)
243 dev_err(cdns->dev, "%s: remove slave failed: %d\n",
244 __func__, ret);
245
246 cdns->bus.bpt_stream = NULL;
247 }
248
249 #define INTEL_BPT_MSG_BYTE_MIN 16
250
intel_ace2x_bpt_send_async(struct sdw_intel * sdw,struct sdw_slave * slave,struct sdw_bpt_msg * msg)251 static int intel_ace2x_bpt_send_async(struct sdw_intel *sdw, struct sdw_slave *slave,
252 struct sdw_bpt_msg *msg)
253 {
254 struct sdw_cdns *cdns = &sdw->cdns;
255 int ret;
256
257 if (msg->len < INTEL_BPT_MSG_BYTE_MIN) {
258 dev_err(cdns->dev, "BPT message length %d is less than the minimum bytes %d\n",
259 msg->len, INTEL_BPT_MSG_BYTE_MIN);
260 return -EINVAL;
261 }
262
263 dev_dbg(cdns->dev, "BPT Transfer start\n");
264
265 ret = intel_ace2x_bpt_open_stream(sdw, slave, msg);
266 if (ret < 0)
267 return ret;
268
269 ret = hda_sdw_bpt_send_async(cdns->dev->parent, /* PCI device */
270 sdw->bpt_ctx.bpt_tx_stream, sdw->bpt_ctx.bpt_rx_stream);
271 if (ret < 0) {
272 dev_err(cdns->dev, "%s: hda_sdw_bpt_send_async failed: %d\n",
273 __func__, ret);
274
275 intel_ace2x_bpt_close_stream(sdw, slave, msg);
276
277 return ret;
278 }
279
280 ret = sdw_enable_stream(cdns->bus.bpt_stream);
281 if (ret < 0) {
282 dev_err(cdns->dev, "%s: sdw_stream_enable failed: %d\n",
283 __func__, ret);
284 intel_ace2x_bpt_close_stream(sdw, slave, msg);
285 }
286
287 return ret;
288 }
289
intel_ace2x_bpt_wait(struct sdw_intel * sdw,struct sdw_slave * slave,struct sdw_bpt_msg * msg)290 static int intel_ace2x_bpt_wait(struct sdw_intel *sdw, struct sdw_slave *slave,
291 struct sdw_bpt_msg *msg)
292 {
293 struct sdw_cdns *cdns = &sdw->cdns;
294 int ret;
295
296 dev_dbg(cdns->dev, "BPT Transfer wait\n");
297
298 ret = hda_sdw_bpt_wait(cdns->dev->parent, /* PCI device */
299 sdw->bpt_ctx.bpt_tx_stream, sdw->bpt_ctx.bpt_rx_stream);
300 if (ret < 0)
301 dev_err(cdns->dev, "%s: hda_sdw_bpt_wait failed: %d\n", __func__, ret);
302
303 ret = sdw_disable_stream(cdns->bus.bpt_stream);
304 if (ret < 0) {
305 dev_err(cdns->dev, "%s: sdw_stream_enable failed: %d\n",
306 __func__, ret);
307 goto err;
308 }
309
310 if (msg->flags & SDW_MSG_FLAG_WRITE) {
311 ret = sdw_cdns_check_write_response(cdns->dev, sdw->bpt_ctx.dmab_rx_bdl.area,
312 sdw->bpt_ctx.pdi1_buffer_size,
313 sdw->bpt_ctx.num_frames);
314 if (ret < 0)
315 dev_err(cdns->dev, "%s: BPT Write failed %d\n", __func__, ret);
316 } else {
317 ret = sdw_cdns_check_read_response(cdns->dev, sdw->bpt_ctx.dmab_rx_bdl.area,
318 sdw->bpt_ctx.pdi1_buffer_size,
319 msg->buf, msg->len, sdw->bpt_ctx.num_frames,
320 sdw->bpt_ctx.data_per_frame);
321 if (ret < 0)
322 dev_err(cdns->dev, "%s: BPT Read failed %d\n", __func__, ret);
323 }
324
325 err:
326 intel_ace2x_bpt_close_stream(sdw, slave, msg);
327
328 return ret;
329 }
330
331 /*
332 * shim vendor-specific (vs) ops
333 */
334
intel_shim_vs_init(struct sdw_intel * sdw)335 static void intel_shim_vs_init(struct sdw_intel *sdw)
336 {
337 void __iomem *shim_vs = sdw->link_res->shim_vs;
338 struct sdw_bus *bus = &sdw->cdns.bus;
339 struct sdw_intel_prop *intel_prop;
340 u16 clde;
341 u16 doaise2;
342 u16 dodse2;
343 u16 clds;
344 u16 clss;
345 u16 doaise;
346 u16 doais;
347 u16 dodse;
348 u16 dods;
349 u16 act;
350
351 intel_prop = bus->vendor_specific_prop;
352 clde = intel_prop->clde;
353 doaise2 = intel_prop->doaise2;
354 dodse2 = intel_prop->dodse2;
355 clds = intel_prop->clds;
356 clss = intel_prop->clss;
357 doaise = intel_prop->doaise;
358 doais = intel_prop->doais;
359 dodse = intel_prop->dodse;
360 dods = intel_prop->dods;
361
362 act = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL);
363 u16p_replace_bits(&act, clde, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE);
364 u16p_replace_bits(&act, doaise2, SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2);
365 u16p_replace_bits(&act, dodse2, SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2);
366 u16p_replace_bits(&act, clds, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS);
367 u16p_replace_bits(&act, clss, SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS);
368 u16p_replace_bits(&act, doaise, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE);
369 u16p_replace_bits(&act, doais, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS);
370 u16p_replace_bits(&act, dodse, SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE);
371 u16p_replace_bits(&act, dods, SDW_SHIM2_INTEL_VS_ACTMCTL_DODS);
372 act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE;
373 intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL, act);
374 usleep_range(10, 15);
375 }
376
intel_shim_vs_set_clock_source(struct sdw_intel * sdw,u32 source)377 static void intel_shim_vs_set_clock_source(struct sdw_intel *sdw, u32 source)
378 {
379 void __iomem *shim_vs = sdw->link_res->shim_vs;
380 u32 val;
381
382 val = intel_readl(shim_vs, SDW_SHIM2_INTEL_VS_LVSCTL);
383
384 u32p_replace_bits(&val, source, SDW_SHIM2_INTEL_VS_LVSCTL_MLCS);
385
386 intel_writel(shim_vs, SDW_SHIM2_INTEL_VS_LVSCTL, val);
387
388 dev_dbg(sdw->cdns.dev, "clock source %d LVSCTL %#x\n", source, val);
389 }
390
intel_shim_check_wake(struct sdw_intel * sdw)391 static int intel_shim_check_wake(struct sdw_intel *sdw)
392 {
393 /*
394 * We follow the HDaudio example and resume unconditionally
395 * without checking the WAKESTS bit for that specific link
396 */
397
398 return 1;
399 }
400
intel_shim_wake(struct sdw_intel * sdw,bool wake_enable)401 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
402 {
403 u16 lsdiid = 0;
404 u16 wake_en;
405 u16 wake_sts;
406 int ret;
407
408 mutex_lock(sdw->link_res->shim_lock);
409
410 ret = hdac_bus_eml_sdw_get_lsdiid_unlocked(sdw->link_res->hbus, sdw->instance, &lsdiid);
411 if (ret < 0)
412 goto unlock;
413
414 wake_en = snd_hdac_chip_readw(sdw->link_res->hbus, WAKEEN);
415
416 if (wake_enable) {
417 /* Enable the wakeup */
418 wake_en |= lsdiid;
419
420 snd_hdac_chip_writew(sdw->link_res->hbus, WAKEEN, wake_en);
421 } else {
422 /* Disable the wake up interrupt */
423 wake_en &= ~lsdiid;
424 snd_hdac_chip_writew(sdw->link_res->hbus, WAKEEN, wake_en);
425
426 /* Clear wake status (W1C) */
427 wake_sts = snd_hdac_chip_readw(sdw->link_res->hbus, STATESTS);
428 wake_sts |= lsdiid;
429 snd_hdac_chip_writew(sdw->link_res->hbus, STATESTS, wake_sts);
430 }
431 unlock:
432 mutex_unlock(sdw->link_res->shim_lock);
433 }
434
intel_link_power_up(struct sdw_intel * sdw)435 static int intel_link_power_up(struct sdw_intel *sdw)
436 {
437 struct sdw_bus *bus = &sdw->cdns.bus;
438 struct sdw_master_prop *prop = &bus->prop;
439 u32 *shim_mask = sdw->link_res->shim_mask;
440 unsigned int link_id = sdw->instance;
441 u32 clock_source;
442 u32 syncprd;
443 int ret;
444
445 if (prop->mclk_freq % 6000000) {
446 if (prop->mclk_freq % 2400000) {
447 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24_576;
448 clock_source = SDW_SHIM2_MLCS_CARDINAL_CLK;
449 } else {
450 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
451 clock_source = SDW_SHIM2_MLCS_XTAL_CLK;
452 }
453 } else {
454 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_96;
455 clock_source = SDW_SHIM2_MLCS_AUDIO_PLL_CLK;
456 }
457
458 mutex_lock(sdw->link_res->shim_lock);
459
460 ret = hdac_bus_eml_sdw_power_up_unlocked(sdw->link_res->hbus, link_id);
461 if (ret < 0) {
462 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_up failed: %d\n",
463 __func__, ret);
464 goto out;
465 }
466
467 intel_shim_vs_set_clock_source(sdw, clock_source);
468
469 if (!*shim_mask) {
470 /* we first need to program the SyncPRD/CPU registers */
471 dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n");
472
473 ret = hdac_bus_eml_sdw_set_syncprd_unlocked(sdw->link_res->hbus, syncprd);
474 if (ret < 0) {
475 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_set_syncprd failed: %d\n",
476 __func__, ret);
477 goto out;
478 }
479
480 /* SYNCPU will change once link is active */
481 ret = hdac_bus_eml_sdw_wait_syncpu_unlocked(sdw->link_res->hbus);
482 if (ret < 0) {
483 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_wait_syncpu failed: %d\n",
484 __func__, ret);
485 goto out;
486 }
487
488 hdac_bus_eml_enable_interrupt_unlocked(sdw->link_res->hbus, true,
489 AZX_REG_ML_LEPTR_ID_SDW, true);
490 }
491
492 *shim_mask |= BIT(link_id);
493
494 sdw->cdns.link_up = true;
495
496 intel_shim_vs_init(sdw);
497
498 out:
499 mutex_unlock(sdw->link_res->shim_lock);
500
501 return ret;
502 }
503
intel_link_power_down(struct sdw_intel * sdw)504 static int intel_link_power_down(struct sdw_intel *sdw)
505 {
506 u32 *shim_mask = sdw->link_res->shim_mask;
507 unsigned int link_id = sdw->instance;
508 int ret;
509
510 mutex_lock(sdw->link_res->shim_lock);
511
512 sdw->cdns.link_up = false;
513
514 *shim_mask &= ~BIT(link_id);
515
516 if (!*shim_mask)
517 hdac_bus_eml_enable_interrupt_unlocked(sdw->link_res->hbus, true,
518 AZX_REG_ML_LEPTR_ID_SDW, false);
519
520 ret = hdac_bus_eml_sdw_power_down_unlocked(sdw->link_res->hbus, link_id);
521 if (ret < 0) {
522 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_down failed: %d\n",
523 __func__, ret);
524
525 /*
526 * we leave the sdw->cdns.link_up flag as false since we've disabled
527 * the link at this point and cannot handle interrupts any longer.
528 */
529 }
530
531 mutex_unlock(sdw->link_res->shim_lock);
532
533 return ret;
534 }
535
intel_sync_arm(struct sdw_intel * sdw)536 static void intel_sync_arm(struct sdw_intel *sdw)
537 {
538 unsigned int link_id = sdw->instance;
539
540 mutex_lock(sdw->link_res->shim_lock);
541
542 hdac_bus_eml_sdw_sync_arm_unlocked(sdw->link_res->hbus, link_id);
543
544 mutex_unlock(sdw->link_res->shim_lock);
545 }
546
intel_sync_go_unlocked(struct sdw_intel * sdw)547 static int intel_sync_go_unlocked(struct sdw_intel *sdw)
548 {
549 int ret;
550
551 ret = hdac_bus_eml_sdw_sync_go_unlocked(sdw->link_res->hbus);
552 if (ret < 0)
553 dev_err(sdw->cdns.dev, "%s: SyncGO clear failed: %d\n", __func__, ret);
554
555 return ret;
556 }
557
intel_sync_go(struct sdw_intel * sdw)558 static int intel_sync_go(struct sdw_intel *sdw)
559 {
560 int ret;
561
562 mutex_lock(sdw->link_res->shim_lock);
563
564 ret = intel_sync_go_unlocked(sdw);
565
566 mutex_unlock(sdw->link_res->shim_lock);
567
568 return ret;
569 }
570
intel_check_cmdsync_unlocked(struct sdw_intel * sdw)571 static bool intel_check_cmdsync_unlocked(struct sdw_intel *sdw)
572 {
573 return hdac_bus_eml_sdw_check_cmdsync_unlocked(sdw->link_res->hbus);
574 }
575
576 /* DAI callbacks */
intel_params_stream(struct sdw_intel * sdw,struct snd_pcm_substream * substream,struct snd_soc_dai * dai,struct snd_pcm_hw_params * hw_params,int link_id,int alh_stream_id)577 static int intel_params_stream(struct sdw_intel *sdw,
578 struct snd_pcm_substream *substream,
579 struct snd_soc_dai *dai,
580 struct snd_pcm_hw_params *hw_params,
581 int link_id, int alh_stream_id)
582 {
583 struct sdw_intel_link_res *res = sdw->link_res;
584 struct sdw_intel_stream_params_data params_data;
585
586 params_data.substream = substream;
587 params_data.dai = dai;
588 params_data.hw_params = hw_params;
589 params_data.link_id = link_id;
590 params_data.alh_stream_id = alh_stream_id;
591
592 if (res->ops && res->ops->params_stream && res->dev)
593 return res->ops->params_stream(res->dev,
594 ¶ms_data);
595 return -EIO;
596 }
597
intel_free_stream(struct sdw_intel * sdw,struct snd_pcm_substream * substream,struct snd_soc_dai * dai,int link_id)598 static int intel_free_stream(struct sdw_intel *sdw,
599 struct snd_pcm_substream *substream,
600 struct snd_soc_dai *dai,
601 int link_id)
602
603 {
604 struct sdw_intel_link_res *res = sdw->link_res;
605 struct sdw_intel_stream_free_data free_data;
606
607 free_data.substream = substream;
608 free_data.dai = dai;
609 free_data.link_id = link_id;
610
611 if (res->ops && res->ops->free_stream && res->dev)
612 return res->ops->free_stream(res->dev,
613 &free_data);
614
615 return 0;
616 }
617
618 /*
619 * DAI operations
620 */
intel_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)621 static int intel_hw_params(struct snd_pcm_substream *substream,
622 struct snd_pcm_hw_params *params,
623 struct snd_soc_dai *dai)
624 {
625 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
626 struct sdw_intel *sdw = cdns_to_intel(cdns);
627 struct sdw_cdns_dai_runtime *dai_runtime;
628 struct sdw_cdns_pdi *pdi;
629 struct sdw_stream_config sconfig;
630 int ch, dir;
631 int ret;
632
633 dai_runtime = cdns->dai_runtime_array[dai->id];
634 if (!dai_runtime)
635 return -EIO;
636
637 ch = params_channels(params);
638 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
639 dir = SDW_DATA_DIR_RX;
640 else
641 dir = SDW_DATA_DIR_TX;
642
643 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
644 if (!pdi)
645 return -EINVAL;
646
647 /* use same definitions for alh_id as previous generations */
648 pdi->intel_alh_id = (sdw->instance * 16) + pdi->num + 3;
649 if (pdi->num >= 2)
650 pdi->intel_alh_id += 2;
651
652 /* the SHIM will be configured in the callback functions */
653
654 sdw_cdns_config_stream(cdns, ch, dir, pdi);
655
656 /* store pdi and state, may be needed in prepare step */
657 dai_runtime->paused = false;
658 dai_runtime->suspended = false;
659 dai_runtime->pdi = pdi;
660
661 /* Inform DSP about PDI stream number */
662 ret = intel_params_stream(sdw, substream, dai, params,
663 sdw->instance,
664 pdi->intel_alh_id);
665 if (ret)
666 return ret;
667
668 sconfig.direction = dir;
669 sconfig.ch_count = ch;
670 sconfig.frame_rate = params_rate(params);
671 sconfig.type = dai_runtime->stream_type;
672
673 sconfig.bps = snd_pcm_format_width(params_format(params));
674
675 /* Port configuration */
676 struct sdw_port_config *pconfig __free(kfree) = kzalloc(sizeof(*pconfig),
677 GFP_KERNEL);
678 if (!pconfig)
679 return -ENOMEM;
680
681 pconfig->num = pdi->num;
682 pconfig->ch_mask = (1 << ch) - 1;
683
684 ret = sdw_stream_add_master(&cdns->bus, &sconfig,
685 pconfig, 1, dai_runtime->stream);
686 if (ret)
687 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
688
689 return ret;
690 }
691
intel_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)692 static int intel_prepare(struct snd_pcm_substream *substream,
693 struct snd_soc_dai *dai)
694 {
695 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
696 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
697 struct sdw_intel *sdw = cdns_to_intel(cdns);
698 struct sdw_cdns_dai_runtime *dai_runtime;
699 struct snd_pcm_hw_params *hw_params;
700 int ch, dir;
701
702 dai_runtime = cdns->dai_runtime_array[dai->id];
703 if (!dai_runtime) {
704 dev_err(dai->dev, "failed to get dai runtime in %s\n",
705 __func__);
706 return -EIO;
707 }
708
709 hw_params = &rtd->dpcm[substream->stream].hw_params;
710 if (dai_runtime->suspended) {
711 dai_runtime->suspended = false;
712
713 /*
714 * .prepare() is called after system resume, where we
715 * need to reinitialize the SHIM/ALH/Cadence IP.
716 * .prepare() is also called to deal with underflows,
717 * but in those cases we cannot touch ALH/SHIM
718 * registers
719 */
720
721 /* configure stream */
722 ch = params_channels(hw_params);
723 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
724 dir = SDW_DATA_DIR_RX;
725 else
726 dir = SDW_DATA_DIR_TX;
727
728 /* the SHIM will be configured in the callback functions */
729
730 sdw_cdns_config_stream(cdns, ch, dir, dai_runtime->pdi);
731 }
732
733 /* Inform DSP about PDI stream number */
734 return intel_params_stream(sdw, substream, dai, hw_params, sdw->instance,
735 dai_runtime->pdi->intel_alh_id);
736 }
737
738 static int
intel_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)739 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
740 {
741 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
742 struct sdw_intel *sdw = cdns_to_intel(cdns);
743 struct sdw_cdns_dai_runtime *dai_runtime;
744 int ret;
745
746 dai_runtime = cdns->dai_runtime_array[dai->id];
747 if (!dai_runtime)
748 return -EIO;
749
750 /*
751 * The sdw stream state will transition to RELEASED when stream->
752 * master_list is empty. So the stream state will transition to
753 * DEPREPARED for the first cpu-dai and to RELEASED for the last
754 * cpu-dai.
755 */
756 ret = sdw_stream_remove_master(&cdns->bus, dai_runtime->stream);
757 if (ret < 0) {
758 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
759 dai_runtime->stream->name, ret);
760 return ret;
761 }
762
763 ret = intel_free_stream(sdw, substream, dai, sdw->instance);
764 if (ret < 0) {
765 dev_err(dai->dev, "intel_free_stream: failed %d\n", ret);
766 return ret;
767 }
768
769 dai_runtime->pdi = NULL;
770
771 return 0;
772 }
773
intel_pcm_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)774 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
775 void *stream, int direction)
776 {
777 return cdns_set_sdw_stream(dai, stream, direction);
778 }
779
intel_get_sdw_stream(struct snd_soc_dai * dai,int direction)780 static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
781 int direction)
782 {
783 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
784 struct sdw_cdns_dai_runtime *dai_runtime;
785
786 dai_runtime = cdns->dai_runtime_array[dai->id];
787 if (!dai_runtime)
788 return ERR_PTR(-EINVAL);
789
790 return dai_runtime->stream;
791 }
792
intel_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)793 static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
794 {
795 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
796 struct sdw_intel *sdw = cdns_to_intel(cdns);
797 struct sdw_intel_link_res *res = sdw->link_res;
798 struct sdw_cdns_dai_runtime *dai_runtime;
799 int ret = 0;
800
801 /*
802 * The .trigger callback is used to program HDaudio DMA and send required IPC to audio
803 * firmware.
804 */
805 if (res->ops && res->ops->trigger) {
806 ret = res->ops->trigger(substream, cmd, dai);
807 if (ret < 0)
808 return ret;
809 }
810
811 dai_runtime = cdns->dai_runtime_array[dai->id];
812 if (!dai_runtime) {
813 dev_err(dai->dev, "failed to get dai runtime in %s\n",
814 __func__);
815 return -EIO;
816 }
817
818 switch (cmd) {
819 case SNDRV_PCM_TRIGGER_SUSPEND:
820
821 /*
822 * The .prepare callback is used to deal with xruns and resume operations.
823 * In the case of xruns, the DMAs and SHIM registers cannot be touched,
824 * but for resume operations the DMAs and SHIM registers need to be initialized.
825 * the .trigger callback is used to track the suspend case only.
826 */
827
828 dai_runtime->suspended = true;
829
830 break;
831
832 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
833 dai_runtime->paused = true;
834 break;
835 case SNDRV_PCM_TRIGGER_STOP:
836 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
837 dai_runtime->paused = false;
838 break;
839 default:
840 break;
841 }
842
843 return ret;
844 }
845
846 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
847 .hw_params = intel_hw_params,
848 .prepare = intel_prepare,
849 .hw_free = intel_hw_free,
850 .trigger = intel_trigger,
851 .set_stream = intel_pcm_set_sdw_stream,
852 .get_stream = intel_get_sdw_stream,
853 };
854
855 static const struct snd_soc_component_driver dai_component = {
856 .name = "soundwire",
857 };
858
859 /*
860 * PDI routines
861 */
intel_pdi_init(struct sdw_intel * sdw,struct sdw_cdns_stream_config * config)862 static void intel_pdi_init(struct sdw_intel *sdw,
863 struct sdw_cdns_stream_config *config)
864 {
865 void __iomem *shim = sdw->link_res->shim;
866 int pcm_cap;
867
868 /* PCM Stream Capability */
869 pcm_cap = intel_readw(shim, SDW_SHIM2_PCMSCAP);
870
871 config->pcm_bd = FIELD_GET(SDW_SHIM2_PCMSCAP_BSS, pcm_cap);
872 config->pcm_in = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap);
873 config->pcm_out = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap);
874
875 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
876 config->pcm_bd, config->pcm_in, config->pcm_out);
877 }
878
879 static int
intel_pdi_get_ch_cap(struct sdw_intel * sdw,unsigned int pdi_num)880 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num)
881 {
882 void __iomem *shim = sdw->link_res->shim;
883
884 /* zero based values for channel count in register */
885 return intel_readw(shim, SDW_SHIM2_PCMSYCHC(pdi_num)) + 1;
886 }
887
intel_pdi_get_ch_update(struct sdw_intel * sdw,struct sdw_cdns_pdi * pdi,unsigned int num_pdi,unsigned int * num_ch)888 static void intel_pdi_get_ch_update(struct sdw_intel *sdw,
889 struct sdw_cdns_pdi *pdi,
890 unsigned int num_pdi,
891 unsigned int *num_ch)
892 {
893 int ch_count = 0;
894 int i;
895
896 for (i = 0; i < num_pdi; i++) {
897 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num);
898 ch_count += pdi->ch_count;
899 pdi++;
900 }
901
902 *num_ch = ch_count;
903 }
904
intel_pdi_stream_ch_update(struct sdw_intel * sdw,struct sdw_cdns_streams * stream)905 static void intel_pdi_stream_ch_update(struct sdw_intel *sdw,
906 struct sdw_cdns_streams *stream)
907 {
908 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
909 &stream->num_ch_bd);
910
911 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
912 &stream->num_ch_in);
913
914 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
915 &stream->num_ch_out);
916 }
917
intel_create_dai(struct sdw_cdns * cdns,struct snd_soc_dai_driver * dais,enum intel_pdi_type type,u32 num,u32 off,u32 max_ch)918 static int intel_create_dai(struct sdw_cdns *cdns,
919 struct snd_soc_dai_driver *dais,
920 enum intel_pdi_type type,
921 u32 num, u32 off, u32 max_ch)
922 {
923 int i;
924
925 if (!num)
926 return 0;
927
928 for (i = off; i < (off + num); i++) {
929 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
930 "SDW%d Pin%d",
931 cdns->instance, i);
932 if (!dais[i].name)
933 return -ENOMEM;
934
935 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
936 dais[i].playback.channels_min = 1;
937 dais[i].playback.channels_max = max_ch;
938 }
939
940 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
941 dais[i].capture.channels_min = 1;
942 dais[i].capture.channels_max = max_ch;
943 }
944
945 dais[i].ops = &intel_pcm_dai_ops;
946 }
947
948 return 0;
949 }
950
intel_register_dai(struct sdw_intel * sdw)951 static int intel_register_dai(struct sdw_intel *sdw)
952 {
953 struct sdw_cdns_dai_runtime **dai_runtime_array;
954 struct sdw_cdns_stream_config config;
955 struct sdw_cdns *cdns = &sdw->cdns;
956 struct sdw_cdns_streams *stream;
957 struct snd_soc_dai_driver *dais;
958 int num_dai;
959 int ret;
960 int off = 0;
961
962 /* Read the PDI config and initialize cadence PDI */
963 intel_pdi_init(sdw, &config);
964 ret = sdw_cdns_pdi_init(cdns, config);
965 if (ret)
966 return ret;
967
968 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm);
969
970 /* DAIs are created based on total number of PDIs supported */
971 num_dai = cdns->pcm.num_pdi;
972
973 dai_runtime_array = devm_kcalloc(cdns->dev, num_dai,
974 sizeof(struct sdw_cdns_dai_runtime *),
975 GFP_KERNEL);
976 if (!dai_runtime_array)
977 return -ENOMEM;
978 cdns->dai_runtime_array = dai_runtime_array;
979
980 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
981 if (!dais)
982 return -ENOMEM;
983
984 /* Create PCM DAIs */
985 stream = &cdns->pcm;
986
987 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
988 off, stream->num_ch_in);
989 if (ret)
990 return ret;
991
992 off += cdns->pcm.num_in;
993 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
994 off, stream->num_ch_out);
995 if (ret)
996 return ret;
997
998 off += cdns->pcm.num_out;
999 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
1000 off, stream->num_ch_bd);
1001 if (ret)
1002 return ret;
1003
1004 return devm_snd_soc_register_component(cdns->dev, &dai_component,
1005 dais, num_dai);
1006 }
1007
intel_program_sdi(struct sdw_intel * sdw,int dev_num)1008 static void intel_program_sdi(struct sdw_intel *sdw, int dev_num)
1009 {
1010 int ret;
1011
1012 ret = hdac_bus_eml_sdw_set_lsdiid(sdw->link_res->hbus, sdw->instance, dev_num);
1013 if (ret < 0)
1014 dev_err(sdw->cdns.dev, "%s: could not set lsdiid for link %d %d\n",
1015 __func__, sdw->instance, dev_num);
1016 }
1017
intel_get_link_count(struct sdw_intel * sdw)1018 static int intel_get_link_count(struct sdw_intel *sdw)
1019 {
1020 int ret;
1021
1022 ret = hdac_bus_eml_get_count(sdw->link_res->hbus, true, AZX_REG_ML_LEPTR_ID_SDW);
1023 if (!ret) {
1024 dev_err(sdw->cdns.dev, "%s: could not retrieve link count\n", __func__);
1025 return -ENODEV;
1026 }
1027
1028 if (ret > SDW_INTEL_MAX_LINKS) {
1029 dev_err(sdw->cdns.dev, "%s: link count %d exceed max %d\n", __func__, ret, SDW_INTEL_MAX_LINKS);
1030 return -EINVAL;
1031 }
1032
1033 return ret;
1034 }
1035
1036 const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops = {
1037 .debugfs_init = intel_ace2x_debugfs_init,
1038 .debugfs_exit = intel_ace2x_debugfs_exit,
1039
1040 .get_link_count = intel_get_link_count,
1041
1042 .register_dai = intel_register_dai,
1043
1044 .check_clock_stop = intel_check_clock_stop,
1045 .start_bus = intel_start_bus,
1046 .start_bus_after_reset = intel_start_bus_after_reset,
1047 .start_bus_after_clock_stop = intel_start_bus_after_clock_stop,
1048 .stop_bus = intel_stop_bus,
1049
1050 .link_power_up = intel_link_power_up,
1051 .link_power_down = intel_link_power_down,
1052
1053 .shim_check_wake = intel_shim_check_wake,
1054 .shim_wake = intel_shim_wake,
1055
1056 .pre_bank_switch = intel_pre_bank_switch,
1057 .post_bank_switch = intel_post_bank_switch,
1058
1059 .sync_arm = intel_sync_arm,
1060 .sync_go_unlocked = intel_sync_go_unlocked,
1061 .sync_go = intel_sync_go,
1062 .sync_check_cmdsync_unlocked = intel_check_cmdsync_unlocked,
1063
1064 .program_sdi = intel_program_sdi,
1065
1066 .bpt_send_async = intel_ace2x_bpt_send_async,
1067 .bpt_wait = intel_ace2x_bpt_wait,
1068 };
1069 EXPORT_SYMBOL_NS(sdw_intel_lnl_hw_ops, "SOUNDWIRE_INTEL");
1070
1071 MODULE_IMPORT_NS("SND_SOC_SOF_HDA_MLINK");
1072 MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_HDA_SDW_BPT");
1073