1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __MLX5_EN_H__ 33 #define __MLX5_EN_H__ 34 35 #include <linux/if_vlan.h> 36 #include <linux/etherdevice.h> 37 #include <linux/timecounter.h> 38 #include <linux/net_tstamp.h> 39 #include <linux/crash_dump.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/qp.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/port.h> 44 #include <linux/mlx5/vport.h> 45 #include <linux/mlx5/transobj.h> 46 #include <linux/mlx5/fs.h> 47 #include <linux/rhashtable.h> 48 #include <net/udp_tunnel.h> 49 #include <net/switchdev.h> 50 #include <net/psp/types.h> 51 #include <net/xdp.h> 52 #include <linux/dim.h> 53 #include <linux/bits.h> 54 #include "wq.h" 55 #include "mlx5_core.h" 56 #include "en_stats.h" 57 #include "en/dcbnl.h" 58 #include "en/fs.h" 59 #include "en/qos.h" 60 #include "lib/hv_vhca.h" 61 #include "lib/clock.h" 62 #include "en/rx_res.h" 63 #include "en/selq.h" 64 #include "lib/sd.h" 65 66 extern const struct net_device_ops mlx5e_netdev_ops; 67 struct page_pool; 68 69 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) 70 #define MLX5E_METADATA_ETHER_LEN 8 71 72 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 73 74 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) 75 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) 76 77 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE 78 79 #define MLX5_RX_HEADROOM NET_SKB_PAD 80 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ 81 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 82 83 #define MLX5E_RX_MAX_HEAD (256) 84 #define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8) 85 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE \ 86 (PAGE_SIZE >> MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE) 87 #define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE \ 88 (PAGE_SHIFT - MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE) 89 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE_SHIFT (6) 90 #define MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT (12) 91 #define MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE (16) 92 #define MLX5E_SHAMPO_WQ_RESRV_SIZE BIT(MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE) 93 94 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ 95 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ 96 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ 97 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) 98 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ 99 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) 100 101 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz. 102 * These are theoretical maximums, which can be further restricted by 103 * capabilities. These values are used for static resource allocations and 104 * sanity checks. 105 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE 106 * size actually used at runtime, but it's not a problem when calculating static 107 * array sizes. 108 */ 109 #define MLX5_UMR_MAX_FLEX_SPACE \ 110 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \ 111 MLX5_UMR_FLEX_ALIGNMENT)) 112 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \ 113 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt)) 114 115 #define MLX5E_MAX_RQ_NUM_MTTS \ 116 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */ 117 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */ 118 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) 119 120 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) 121 #define MLX5E_LOG_MAX_RX_WQE_BULK \ 122 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) 123 124 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 125 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 126 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd 127 128 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) 129 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 130 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd 131 132 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 133 134 #define MLX5E_DEFAULT_LRO_TIMEOUT 32 135 #define MLX5E_DEFAULT_SHAMPO_TIMEOUT 1024 136 137 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 138 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 139 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 140 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 141 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 142 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 143 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 144 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 145 146 #define MLX5E_MIN_NUM_CHANNELS 0x1 147 #define MLX5E_MAX_NUM_CHANNELS 256 148 #define MLX5E_TX_CQ_POLL_BUDGET 128 149 #define MLX5E_TX_XSK_POLL_BUDGET 64 150 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ 151 152 #define mlx5e_state_dereference(priv, p) \ 153 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock)) 154 155 enum mlx5e_devcom_events { 156 MPV_DEVCOM_MASTER_UP, 157 MPV_DEVCOM_MASTER_DOWN, 158 MPV_DEVCOM_IPSEC_MASTER_UP, 159 MPV_DEVCOM_IPSEC_MASTER_DOWN, 160 }; 161 162 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) 163 { 164 if (mlx5_lag_is_lacp_owner(mdev)) 165 return 1; 166 167 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); 168 } 169 170 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) 171 { 172 switch (wq_type) { 173 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 174 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, 175 wq_size / 2); 176 default: 177 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, 178 wq_size / 2); 179 } 180 } 181 182 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ 183 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) 184 { 185 return is_kdump_kernel() ? 186 MLX5E_MIN_NUM_CHANNELS : 187 min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS, 188 (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size))); 189 } 190 191 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in 192 * bytes units. Driver hardens the limitation to 1KB (16 193 * WQEBBs), unless firmware capability is stricter. 194 */ 195 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev) 196 { 197 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX); 198 199 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS, 200 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB); 201 } 202 203 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev) 204 { 205 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS. 206 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16, 207 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64) 208 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower 209 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be 210 * cache-aligned. 211 */ 212 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev); 213 214 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1); 215 #if L1_CACHE_BYTES >= 128 216 wqebbs = ALIGN_DOWN(wqebbs, 2); 217 #endif 218 return wqebbs; 219 } 220 221 struct mlx5e_tx_wqe { 222 struct mlx5_wqe_ctrl_seg ctrl; 223 struct mlx5_wqe_eth_seg eth; 224 struct mlx5_wqe_data_seg data[]; 225 }; 226 227 struct mlx5e_rx_wqe_ll { 228 struct mlx5_wqe_srq_next_seg next; 229 struct mlx5_wqe_data_seg data[]; 230 }; 231 232 struct mlx5e_rx_wqe_cyc { 233 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data); 234 }; 235 236 struct mlx5e_umr_wqe_hdr { 237 struct mlx5_wqe_ctrl_seg ctrl; 238 struct mlx5_wqe_umr_ctrl_seg uctrl; 239 struct mlx5_mkey_seg mkc; 240 }; 241 242 struct mlx5e_umr_wqe { 243 struct mlx5e_umr_wqe_hdr hdr; 244 union { 245 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts); 246 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms); 247 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms); 248 }; 249 }; 250 static_assert(offsetof(struct mlx5e_umr_wqe, inline_mtts) == sizeof(struct mlx5e_umr_wqe_hdr), 251 "struct members should be included in struct mlx5e_umr_wqe_hdr, not in struct mlx5e_umr_wqe"); 252 253 enum mlx5e_priv_flag { 254 MLX5E_PFLAG_RX_CQE_BASED_MODER, 255 MLX5E_PFLAG_TX_CQE_BASED_MODER, 256 MLX5E_PFLAG_RX_CQE_COMPRESS, 257 MLX5E_PFLAG_RX_STRIDING_RQ, 258 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, 259 MLX5E_PFLAG_XDP_TX_MPWQE, 260 MLX5E_PFLAG_SKB_TX_MPWQE, 261 MLX5E_PFLAG_TX_PORT_TS, 262 MLX5E_NUM_PFLAGS, /* Keep last */ 263 }; 264 265 #define MLX5E_SET_PFLAG(params, pflag, enable) \ 266 do { \ 267 if (enable) \ 268 (params)->pflags |= BIT(pflag); \ 269 else \ 270 (params)->pflags &= ~(BIT(pflag)); \ 271 } while (0) 272 273 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) 274 275 enum packet_merge { 276 MLX5E_PACKET_MERGE_NONE, 277 MLX5E_PACKET_MERGE_LRO, 278 MLX5E_PACKET_MERGE_SHAMPO, 279 }; 280 281 struct mlx5e_packet_merge_param { 282 enum packet_merge type; 283 u32 timeout; 284 }; 285 286 struct mlx5e_params { 287 u8 log_sq_size; 288 u8 rq_wq_type; 289 u8 log_rq_mtu_frames; 290 u16 num_channels; 291 struct { 292 u16 mode; 293 u8 num_tc; 294 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE]; 295 struct { 296 u64 max_rate[TC_MAX_QUEUE]; 297 u32 hw_id[TC_MAX_QUEUE]; 298 } channel; 299 } mqprio; 300 bool rx_cqe_compress_def; 301 struct dim_cq_moder rx_cq_moderation; 302 struct dim_cq_moder tx_cq_moderation; 303 struct mlx5e_packet_merge_param packet_merge; 304 u8 tx_min_inline_mode; 305 bool vlan_strip_disable; 306 bool scatter_fcs_en; 307 bool rx_dim_enabled; 308 bool tx_dim_enabled; 309 bool rx_moder_use_cqe_mode; 310 bool tx_moder_use_cqe_mode; 311 u32 pflags; 312 struct bpf_prog *xdp_prog; 313 struct mlx5e_xsk *xsk; 314 unsigned int sw_mtu; 315 int hard_mtu; 316 bool ptp_rx; 317 __be32 terminate_lkey_be; 318 }; 319 320 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params) 321 { 322 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ? 323 params->mqprio.num_tc : 1; 324 } 325 326 /* Keep this enum consistent with the corresponding strings array 327 * declared in en/reporter_rx.c 328 */ 329 enum { 330 MLX5E_RQ_STATE_ENABLED = 0, 331 MLX5E_RQ_STATE_RECOVERING, 332 MLX5E_RQ_STATE_DIM, 333 MLX5E_RQ_STATE_NO_CSUM_COMPLETE, 334 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ 335 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */ 336 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */ 337 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */ 338 MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */ 339 MLX5E_NUM_RQ_STATES, /* Must be kept last */ 340 }; 341 342 struct mlx5e_cq { 343 /* data path - accessed per cqe */ 344 struct mlx5_cqwq wq; 345 346 /* data path - accessed per napi poll */ 347 u16 event_ctr; 348 struct napi_struct *napi; 349 struct mlx5_uars_page *uar; 350 struct mlx5_core_cq mcq; 351 struct mlx5e_ch_stats *ch_stats; 352 353 /* control */ 354 struct net_device *netdev; 355 struct mlx5_core_dev *mdev; 356 struct workqueue_struct *workqueue; 357 struct mlx5_wq_ctrl wq_ctrl; 358 } ____cacheline_aligned_in_smp; 359 360 struct mlx5e_cq_decomp { 361 /* cqe decompression */ 362 struct mlx5_cqe64 title; 363 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; 364 u8 mini_arr_idx; 365 u16 left; 366 u16 wqe_counter; 367 bool last_cqe_title; 368 } ____cacheline_aligned_in_smp; 369 370 enum mlx5e_dma_map_type { 371 MLX5E_DMA_MAP_SINGLE, 372 MLX5E_DMA_MAP_PAGE 373 }; 374 375 struct mlx5e_sq_dma { 376 dma_addr_t addr; 377 u32 size; 378 enum mlx5e_dma_map_type type; 379 }; 380 381 /* Keep this enum consistent with the corresponding strings array 382 * declared in en/reporter_tx.c 383 */ 384 enum { 385 MLX5E_SQ_STATE_ENABLED = 0, 386 MLX5E_SQ_STATE_MPWQE, 387 MLX5E_SQ_STATE_RECOVERING, 388 MLX5E_SQ_STATE_IPSEC, 389 MLX5E_SQ_STATE_DIM, 390 MLX5E_SQ_STATE_PENDING_XSK_TX, 391 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, 392 MLX5E_SQ_STATE_LOCK_NEEDED, 393 MLX5E_NUM_SQ_STATES, /* Must be kept last */ 394 }; 395 396 struct mlx5e_tx_mpwqe { 397 /* Current MPWQE session */ 398 struct mlx5e_tx_wqe *wqe; 399 u32 bytes_count; 400 u8 ds_count; 401 u8 ds_count_max; 402 u8 pkt_count; 403 u8 inline_on; 404 }; 405 406 struct mlx5e_skb_fifo { 407 struct sk_buff **fifo; 408 u16 *pc; 409 u16 *cc; 410 u16 mask; 411 }; 412 413 struct mlx5e_ptpsq; 414 415 struct mlx5e_txqsq { 416 /* data path */ 417 418 /* dirtied @completion */ 419 u16 cc; 420 u16 skb_fifo_cc; 421 u32 dma_fifo_cc; 422 struct dim *dim; /* Adaptive Moderation */ 423 424 /* dirtied @xmit */ 425 u16 pc ____cacheline_aligned_in_smp; 426 u16 skb_fifo_pc; 427 u32 dma_fifo_pc; 428 struct mlx5e_tx_mpwqe mpwqe; 429 430 struct mlx5e_cq cq; 431 432 /* read only */ 433 struct mlx5_wq_cyc wq; 434 u32 dma_fifo_mask; 435 struct mlx5e_sq_stats *stats; 436 struct { 437 struct mlx5e_sq_dma *dma_fifo; 438 struct mlx5e_skb_fifo skb_fifo; 439 struct mlx5e_tx_wqe_info *wqe_info; 440 } db; 441 void __iomem *uar_map; 442 struct netdev_queue *txq; 443 u32 sqn; 444 u16 stop_room; 445 u8 max_sq_mpw_wqebbs; 446 u8 min_inline_mode; 447 struct device *pdev; 448 __be32 mkey_be; 449 unsigned long state; 450 unsigned int hw_mtu; 451 struct mlx5_clock *clock; 452 struct net_device *netdev; 453 struct mlx5_core_dev *mdev; 454 struct mlx5e_channel *channel; 455 struct mlx5e_priv *priv; 456 457 /* control path */ 458 struct mlx5_wq_ctrl wq_ctrl; 459 int ch_ix; 460 int txq_ix; 461 u32 rate_limit; 462 struct work_struct recover_work; 463 struct mlx5e_ptpsq *ptpsq; 464 cqe_ts_to_ns ptp_cyc2time; 465 } ____cacheline_aligned_in_smp; 466 467 struct mlx5e_xdp_info_fifo { 468 union mlx5e_xdp_info *xi; 469 u32 *cc; 470 u32 *pc; 471 u32 mask; 472 }; 473 474 struct mlx5e_xdpsq; 475 struct mlx5e_xmit_data; 476 struct xsk_tx_metadata; 477 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); 478 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, 479 struct mlx5e_xmit_data *, 480 int, 481 struct xsk_tx_metadata *); 482 483 struct mlx5e_xdpsq { 484 /* data path */ 485 486 /* dirtied @completion */ 487 u32 xdpi_fifo_cc; 488 u16 cc; 489 490 /* dirtied @xmit */ 491 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; 492 u16 pc; 493 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 494 struct mlx5e_tx_mpwqe mpwqe; 495 496 struct mlx5e_cq cq; 497 498 /* read only */ 499 struct xsk_buff_pool *xsk_pool; 500 struct mlx5_wq_cyc wq; 501 struct mlx5e_xdpsq_stats *stats; 502 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; 503 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; 504 struct { 505 struct mlx5e_xdp_wqe_info *wqe_info; 506 struct mlx5e_xdp_info_fifo xdpi_fifo; 507 } db; 508 void __iomem *uar_map; 509 u32 sqn; 510 struct device *pdev; 511 __be32 mkey_be; 512 u16 stop_room; 513 u8 max_sq_mpw_wqebbs; 514 u8 min_inline_mode; 515 unsigned long state; 516 unsigned int hw_mtu; 517 518 /* control path */ 519 struct mlx5_wq_ctrl wq_ctrl; 520 struct mlx5e_channel *channel; 521 } ____cacheline_aligned_in_smp; 522 523 struct mlx5e_xdp_buff { 524 struct xdp_buff xdp; 525 struct mlx5_cqe64 *cqe; 526 struct mlx5e_rq *rq; 527 }; 528 529 struct mlx5e_ktls_resync_resp; 530 531 struct mlx5e_icosq { 532 /* data path */ 533 u16 cc; 534 u16 pc; 535 536 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 537 struct mlx5e_cq cq; 538 539 /* write@xmit, read@completion */ 540 struct { 541 struct mlx5e_icosq_wqe_info *wqe_info; 542 } db; 543 544 /* read only */ 545 struct mlx5_wq_cyc wq; 546 void __iomem *uar_map; 547 u32 sqn; 548 u16 reserved_room; 549 unsigned long state; 550 /* icosq can be accessed from any CPU and from different contexts 551 * (NAPI softirq or process/workqueue). Always use spin_lock_bh for 552 * simplicity and correctness across all contexts. 553 */ 554 spinlock_t lock; 555 struct mlx5e_ktls_resync_resp *ktls_resync; 556 557 /* control path */ 558 struct mlx5_wq_ctrl wq_ctrl; 559 struct mlx5e_channel *channel; 560 561 struct work_struct recover_work; 562 } ____cacheline_aligned_in_smp; 563 564 struct mlx5e_frag_page { 565 netmem_ref netmem; 566 u16 frags; 567 }; 568 569 enum mlx5e_wqe_frag_flag { 570 MLX5E_WQE_FRAG_LAST_IN_PAGE, 571 MLX5E_WQE_FRAG_SKIP_RELEASE, 572 }; 573 574 struct mlx5e_wqe_frag_info { 575 union { 576 struct mlx5e_frag_page *frag_page; 577 struct xdp_buff **xskp; 578 }; 579 u32 offset; 580 u8 flags; 581 }; 582 583 union mlx5e_alloc_units { 584 DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages); 585 DECLARE_FLEX_ARRAY(struct page *, pages); 586 DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs); 587 }; 588 589 struct mlx5e_mpw_info { 590 u16 consumed_strides; 591 DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE); 592 struct mlx5e_frag_page linear_page; 593 union mlx5e_alloc_units alloc_units; 594 }; 595 596 #define MLX5E_MAX_RX_FRAGS 4 597 598 struct mlx5e_rq; 599 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); 600 typedef struct sk_buff * 601 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 602 struct mlx5_cqe64 *cqe, u16 cqe_bcnt, 603 u32 head_offset, u32 page_idx); 604 typedef struct sk_buff * 605 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi, 606 struct mlx5_cqe64 *cqe, u32 cqe_bcnt); 607 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); 608 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); 609 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool); 610 611 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk); 612 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params); 613 614 enum mlx5e_rq_flag { 615 MLX5E_RQ_FLAG_XDP_XMIT, 616 MLX5E_RQ_FLAG_XDP_REDIRECT, 617 }; 618 619 struct mlx5e_rq_frag_info { 620 int frag_size; 621 int frag_stride; 622 }; 623 624 struct mlx5e_rq_frags_info { 625 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; 626 u8 num_frags; 627 u8 log_num_frags; 628 u16 wqe_bulk; 629 u16 refill_unit; 630 u8 wqe_index_mask; 631 }; 632 633 struct mlx5e_dma_info { 634 dma_addr_t addr; 635 union { 636 struct mlx5e_frag_page *frag_page; 637 struct page *page; 638 }; 639 }; 640 641 struct mlx5e_shampo_hd { 642 u32 hd_per_wq; 643 u32 hd_buf_size; 644 u32 mkey; 645 u32 nentries; 646 DECLARE_FLEX_ARRAY(struct mlx5e_dma_info, hd_buf_pages); 647 }; 648 649 struct mlx5e_hw_gro_data { 650 struct sk_buff *skb; 651 struct flow_keys fk; 652 int second_ip_id; 653 }; 654 655 enum mlx5e_mpwrq_umr_mode { 656 MLX5E_MPWRQ_UMR_MODE_ALIGNED, 657 MLX5E_MPWRQ_UMR_MODE_UNALIGNED, 658 MLX5E_MPWRQ_UMR_MODE_OVERSIZED, 659 MLX5E_MPWRQ_UMR_MODE_TRIPLE, 660 }; 661 662 struct mlx5e_rq { 663 /* data path */ 664 union { 665 struct { 666 struct mlx5_wq_cyc wq; 667 struct mlx5e_wqe_frag_info *frags; 668 union mlx5e_alloc_units *alloc_units; 669 struct mlx5e_rq_frags_info info; 670 mlx5e_fp_skb_from_cqe skb_from_cqe; 671 } wqe; 672 struct { 673 struct mlx5_wq_ll wq; 674 struct mlx5e_umr_wqe_hdr umr_wqe; 675 struct mlx5e_mpw_info *info; 676 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; 677 __be32 umr_mkey_be; 678 u16 num_strides; 679 u16 actual_wq_head; 680 u8 log_stride_sz; 681 u8 umr_in_progress; 682 u8 umr_last_bulk; 683 u8 umr_completed; 684 u8 min_wqe_bulk; 685 u8 page_shift; 686 u8 pages_per_wqe; 687 u8 umr_wqebbs; 688 u8 mtts_per_wqe; 689 u8 umr_mode; 690 struct mlx5e_shampo_hd *shampo; 691 } mpwqe; 692 }; 693 struct { 694 u16 headroom; 695 u32 frame0_sz; 696 u8 map_dir; /* dma map direction */ 697 } buff; 698 699 struct device *pdev; 700 struct net_device *netdev; 701 struct mlx5e_rq_stats *stats; 702 struct mlx5e_cq cq; 703 struct mlx5e_cq_decomp cqd; 704 struct kernel_hwtstamp_config *hwtstamp_config; 705 struct mlx5_clock *clock; 706 struct mlx5e_icosq *icosq; 707 struct mlx5e_priv *priv; 708 709 struct mlx5e_hw_gro_data *hw_gro_data; 710 711 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 712 mlx5e_fp_post_rx_wqes post_wqes; 713 mlx5e_fp_dealloc_wqe dealloc_wqe; 714 715 unsigned long state; 716 int ix; 717 unsigned int hw_mtu; 718 719 struct dim *dim; /* Dynamic Interrupt Moderation */ 720 721 /* XDP */ 722 struct bpf_prog __rcu *xdp_prog; 723 struct mlx5e_xdpsq *xdpsq; 724 DECLARE_BITMAP(flags, 8); 725 726 /* page pools */ 727 struct page_pool *page_pool; 728 struct page_pool *hd_page_pool; 729 730 struct mlx5e_xdp_buff mxbuf; 731 732 /* AF_XDP zero-copy */ 733 struct xsk_buff_pool *xsk_pool; 734 735 struct work_struct recover_work; 736 struct work_struct rx_timeout_work; 737 738 /* control */ 739 struct mlx5_wq_ctrl wq_ctrl; 740 __be32 mkey_be; 741 u8 wq_type; 742 u32 rqn; 743 struct mlx5_core_dev *mdev; 744 struct mlx5e_channel *channel; 745 struct mlx5e_dma_info wqe_overflow; 746 747 /* XDP read-mostly */ 748 struct xdp_rxq_info xdp_rxq; 749 cqe_ts_to_ns ptp_cyc2time; 750 } ____cacheline_aligned_in_smp; 751 752 enum mlx5e_channel_state { 753 MLX5E_CHANNEL_STATE_XSK, 754 MLX5E_CHANNEL_NUM_STATES 755 }; 756 757 struct mlx5e_channel { 758 /* data path */ 759 struct mlx5e_rq rq; 760 struct mlx5e_xdpsq rq_xdpsq; 761 struct mlx5e_txqsq sq[MLX5_MAX_NUM_TC]; 762 struct mlx5e_icosq icosq; /* internal control operations */ 763 struct mlx5e_txqsq __rcu * __rcu *qos_sqs; 764 bool xdp; 765 struct napi_struct napi; 766 struct device *pdev; 767 struct net_device *netdev; 768 __be32 mkey_be; 769 u16 qos_sqs_size; 770 u8 num_tc; 771 u8 lag_port; 772 773 /* XDP_REDIRECT */ 774 struct mlx5e_xdpsq *xdpsq; 775 776 /* AF_XDP zero-copy */ 777 struct mlx5e_rq xskrq; 778 struct mlx5e_xdpsq xsksq; 779 780 /* Async ICOSQ */ 781 struct mlx5e_icosq *async_icosq; 782 783 /* data path - accessed per napi poll */ 784 const struct cpumask *aff_mask; 785 struct mlx5e_ch_stats *stats; 786 787 /* control */ 788 struct mlx5e_priv *priv; 789 struct mlx5_core_dev *mdev; 790 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); 791 int ix; 792 int vec_ix; 793 int sd_ix; 794 int cpu; 795 struct mlx5_sq_bfreg *bfreg; 796 /* Sync between icosq recovery and XSK enable/disable. */ 797 struct mutex icosq_recovery_lock; 798 799 /* coalescing configuration */ 800 struct dim_cq_moder rx_cq_moder; 801 struct dim_cq_moder tx_cq_moder; 802 }; 803 804 static inline bool mlx5e_icosq_sync_lock(struct mlx5e_icosq *sq) 805 { 806 if (likely(!test_bit(MLX5E_SQ_STATE_LOCK_NEEDED, &sq->state))) 807 return false; 808 809 spin_lock_bh(&sq->lock); 810 return true; 811 } 812 813 static inline void mlx5e_icosq_sync_unlock(struct mlx5e_icosq *sq, bool locked) 814 { 815 if (unlikely(locked)) 816 spin_unlock_bh(&sq->lock); 817 } 818 819 struct mlx5e_ptp; 820 821 struct mlx5e_channels { 822 struct mlx5e_channel **c; 823 struct mlx5e_ptp *ptp; 824 unsigned int num; 825 struct mlx5e_params params; 826 }; 827 828 struct mlx5e_channel_stats { 829 struct mlx5e_ch_stats ch; 830 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC]; 831 struct mlx5e_rq_stats rq; 832 struct mlx5e_rq_stats xskrq; 833 struct mlx5e_xdpsq_stats rq_xdpsq; 834 struct mlx5e_xdpsq_stats xdpsq; 835 struct mlx5e_xdpsq_stats xsksq; 836 } ____cacheline_aligned_in_smp; 837 838 struct mlx5e_ptp_stats { 839 struct mlx5e_ch_stats ch; 840 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC]; 841 struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC]; 842 struct mlx5e_rq_stats rq; 843 } ____cacheline_aligned_in_smp; 844 845 enum { 846 MLX5E_STATE_OPENED, 847 MLX5E_STATE_DESTROYING, 848 MLX5E_STATE_XDP_TX_ENABLED, 849 MLX5E_STATE_XDP_ACTIVE, 850 MLX5E_STATE_CHANNELS_ACTIVE, 851 }; 852 853 struct mlx5e_modify_sq_param { 854 int curr_state; 855 int next_state; 856 int rl_update; 857 int rl_index; 858 bool qos_update; 859 u16 qos_queue_group_id; 860 }; 861 862 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 863 struct mlx5e_hv_vhca_stats_agent { 864 struct mlx5_hv_vhca_agent *agent; 865 struct delayed_work work; 866 u16 delay; 867 void *buf; 868 }; 869 #endif 870 871 struct mlx5e_xsk { 872 /* XSK buffer pools are stored separately from channels, 873 * because we don't want to lose them when channels are 874 * recreated. The kernel also stores buffer pool, but it doesn't 875 * distinguish between zero-copy and non-zero-copy UMEMs, so 876 * rely on our mechanism. 877 */ 878 struct xsk_buff_pool **pools; 879 u16 refcnt; 880 bool ever_used; 881 }; 882 883 /* Temporary storage for variables that are allocated when struct mlx5e_priv is 884 * initialized, and used where we can't allocate them because that functions 885 * must not fail. Use with care and make sure the same variable is not used 886 * simultaneously by multiple users. 887 */ 888 struct mlx5e_scratchpad { 889 cpumask_var_t cpumask; 890 }; 891 892 struct mlx5e_trap; 893 struct mlx5e_htb; 894 895 struct mlx5e_priv { 896 /* priv data path fields - start */ 897 struct mlx5e_selq selq; 898 struct mlx5e_txqsq **txq2sq; 899 struct mlx5e_sq_stats **txq2sq_stats; 900 901 #ifdef CONFIG_MLX5_CORE_EN_DCB 902 struct mlx5e_dcbx_dp dcbx_dp; 903 #endif 904 /* priv data path fields - end */ 905 906 unsigned long state; 907 struct mutex state_lock; /* Protects Interface state */ 908 struct mlx5e_rq drop_rq; 909 910 struct mlx5e_channels channels; 911 struct mlx5e_rx_res *rx_res; 912 u32 *tx_rates; 913 914 struct mlx5e_flow_steering *fs; 915 916 struct workqueue_struct *wq; 917 struct work_struct update_carrier_work; 918 struct work_struct set_rx_mode_work; 919 struct work_struct tx_timeout_work; 920 struct work_struct update_stats_work; 921 struct work_struct monitor_counters_work; 922 struct mlx5_nb monitor_counters_nb; 923 924 struct mlx5_core_dev *mdev; 925 struct net_device *netdev; 926 struct mlx5e_trap *en_trap; 927 struct mlx5e_stats stats; 928 struct mlx5e_channel_stats **channel_stats; 929 struct mlx5e_channel_stats trap_stats; 930 struct mlx5e_ptp_stats ptp_stats; 931 struct mlx5e_sq_stats **htb_qos_sq_stats; 932 u16 htb_max_qos_sqs; 933 u16 stats_nch; 934 u16 max_nch; 935 u8 max_opened_tc; 936 bool tx_ptp_opened; 937 bool rx_ptp_opened; 938 bool ktls_rx_was_enabled; 939 struct kernel_hwtstamp_config hwtstamp_config; 940 u16 q_counter[MLX5_SD_MAX_GROUP_SZ]; 941 u16 drop_rq_q_counter; 942 struct notifier_block events_nb; 943 struct notifier_block blocking_events_nb; 944 945 struct mlx5e_pcie_cong_event *cong_event; 946 947 struct udp_tunnel_nic_info nic_info; 948 #ifdef CONFIG_MLX5_CORE_EN_DCB 949 struct mlx5e_dcbx dcbx; 950 #endif 951 952 const struct mlx5e_profile *profile; 953 void *ppriv; 954 #ifdef CONFIG_MLX5_MACSEC 955 struct mlx5e_macsec *macsec; 956 #endif 957 #ifdef CONFIG_MLX5_EN_IPSEC 958 struct mlx5e_ipsec *ipsec; 959 #endif 960 #ifdef CONFIG_MLX5_EN_PSP 961 struct mlx5e_psp *psp; 962 #endif 963 #ifdef CONFIG_MLX5_EN_TLS 964 struct mlx5e_tls *tls; 965 #endif 966 struct devlink_health_reporter *tx_reporter; 967 struct devlink_health_reporter *rx_reporter; 968 struct mlx5e_xsk xsk; 969 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 970 struct mlx5e_hv_vhca_stats_agent stats_agent; 971 #endif 972 struct mlx5e_scratchpad scratchpad; 973 struct mlx5e_htb *htb; 974 struct mlx5e_mqprio_rl *mqprio_rl; 975 struct dentry *dfs_root; 976 struct mlx5_devcom_comp_dev *devcom; 977 struct ethtool_fec_hist_range *fec_ranges; 978 }; 979 980 struct mlx5e_dev { 981 struct net_device *netdev; 982 struct devlink_port dl_port; 983 }; 984 985 struct mlx5e_rx_handlers { 986 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 987 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; 988 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo; 989 }; 990 991 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic; 992 993 enum mlx5e_profile_feature { 994 MLX5E_PROFILE_FEATURE_PTP_RX, 995 MLX5E_PROFILE_FEATURE_PTP_TX, 996 MLX5E_PROFILE_FEATURE_QOS_HTB, 997 MLX5E_PROFILE_FEATURE_FS_VLAN, 998 MLX5E_PROFILE_FEATURE_FS_TC, 999 }; 1000 1001 struct mlx5e_profile { 1002 int (*init)(struct mlx5_core_dev *mdev, 1003 struct net_device *netdev); 1004 void (*cleanup)(struct mlx5e_priv *priv); 1005 int (*init_rx)(struct mlx5e_priv *priv); 1006 void (*cleanup_rx)(struct mlx5e_priv *priv); 1007 int (*init_tx)(struct mlx5e_priv *priv); 1008 void (*cleanup_tx)(struct mlx5e_priv *priv); 1009 void (*enable)(struct mlx5e_priv *priv); 1010 void (*disable)(struct mlx5e_priv *priv); 1011 int (*update_rx)(struct mlx5e_priv *priv); 1012 void (*update_stats)(struct mlx5e_priv *priv); 1013 void (*update_carrier)(struct mlx5e_priv *priv); 1014 int (*max_nch_limit)(struct mlx5_core_dev *mdev); 1015 u32 (*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv, 1016 u8 lag_port, u8 tc); 1017 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); 1018 mlx5e_stats_grp_t *stats_grps; 1019 const struct mlx5e_rx_handlers *rx_handlers; 1020 int max_tc; 1021 u32 features; 1022 }; 1023 1024 u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev, 1025 struct mlx5e_priv *priv, 1026 const struct mlx5e_profile *profile, 1027 u8 lag_port, u8 tc); 1028 1029 #define mlx5e_profile_feature_cap(profile, feature) \ 1030 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature)) 1031 1032 void mlx5e_build_ptys2ethtool_map(void); 1033 1034 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, 1035 enum mlx5e_mpwrq_umr_mode umr_mode); 1036 1037 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); 1038 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); 1039 1040 int mlx5e_self_test_num(struct mlx5e_priv *priv); 1041 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data); 1042 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, 1043 u64 *buf); 1044 void mlx5e_set_rx_mode_work(struct work_struct *work); 1045 1046 int mlx5e_hwtstamp_set(struct mlx5e_priv *priv, 1047 struct kernel_hwtstamp_config *config, 1048 struct netlink_ext_ack *extack); 1049 int mlx5e_hwtstamp_get(struct mlx5e_priv *priv, 1050 struct kernel_hwtstamp_config *config); 1051 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter); 1052 1053 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, 1054 u16 vid); 1055 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, 1056 u16 vid); 1057 void mlx5e_timestamp_init(struct mlx5e_priv *priv); 1058 1059 struct mlx5e_xsk_param; 1060 1061 struct mlx5e_rq_param; 1062 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, 1063 struct mlx5e_xsk_param *xsk, int node, u16 q_counter, 1064 struct mlx5e_rq *rq); 1065 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */ 1066 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); 1067 void mlx5e_close_rq(struct mlx5e_rq *rq); 1068 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_counter); 1069 void mlx5e_destroy_rq(struct mlx5e_rq *rq); 1070 1071 bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode, 1072 bool dim_enabled); 1073 bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode, 1074 bool dim_enabled, bool keep_dim_state); 1075 1076 struct mlx5e_sq_param; 1077 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1078 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1079 struct mlx5e_xdpsq *sq, bool is_redirect); 1080 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); 1081 1082 struct mlx5e_create_cq_param { 1083 struct net_device *netdev; 1084 struct workqueue_struct *wq; 1085 struct napi_struct *napi; 1086 struct mlx5e_ch_stats *ch_stats; 1087 int node; 1088 int ix; 1089 struct mlx5_uars_page *uar; 1090 }; 1091 1092 struct mlx5e_cq_param; 1093 int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder, 1094 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1095 struct mlx5e_cq *cq); 1096 void mlx5e_close_cq(struct mlx5e_cq *cq); 1097 int mlx5e_modify_cq_period_mode(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 1098 u8 cq_period_mode); 1099 int mlx5e_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 1100 u16 cq_period, u16 cq_max_count, u8 cq_period_mode); 1101 1102 int mlx5e_open_locked(struct net_device *netdev); 1103 int mlx5e_close_locked(struct net_device *netdev); 1104 1105 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c); 1106 void mlx5e_trigger_napi_sched(struct napi_struct *napi); 1107 1108 int mlx5e_open_channels(struct mlx5e_priv *priv, 1109 struct mlx5e_channels *chs); 1110 void mlx5e_close_channels(struct mlx5e_channels *chs); 1111 1112 /* Function pointer to be used to modify HW or kernel settings while 1113 * switching channels 1114 */ 1115 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); 1116 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ 1117 int fn##_ctx(struct mlx5e_priv *priv, void *context) \ 1118 { \ 1119 return fn(priv); \ 1120 } 1121 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); 1122 int mlx5e_safe_switch_params(struct mlx5e_priv *priv, 1123 struct mlx5e_params *new_params, 1124 mlx5e_fp_preactivate preactivate, 1125 void *context, bool reset); 1126 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); 1127 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); 1128 int mlx5e_update_tc_and_tx_queues_ctx(struct mlx5e_priv *priv, void *context); 1129 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); 1130 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); 1131 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); 1132 1133 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state); 1134 void mlx5e_activate_rq(struct mlx5e_rq *rq); 1135 void mlx5e_deactivate_rq(struct mlx5e_rq *rq); 1136 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); 1137 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); 1138 1139 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1140 struct mlx5e_modify_sq_param *p); 1141 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1142 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1143 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, 1144 struct mlx5e_sq_stats *sq_stats); 1145 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); 1146 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq); 1147 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq); 1148 void mlx5e_tx_disable_queue(struct netdev_queue *txq); 1149 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa); 1150 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq); 1151 struct mlx5e_create_sq_param; 1152 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1153 struct mlx5e_sq_param *param, 1154 struct mlx5e_create_sq_param *csp, 1155 u16 qos_queue_group_id, 1156 u32 *sqn); 1157 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work); 1158 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq); 1159 1160 bool mlx5e_reset_tx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode, 1161 bool dim_enabled); 1162 bool mlx5e_reset_tx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode, 1163 bool dim_enabled, bool keep_dim_state); 1164 1165 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) 1166 { 1167 return MLX5_CAP_ETH(mdev, swp) && 1168 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); 1169 } 1170 1171 extern const struct ethtool_ops mlx5e_ethtool_ops; 1172 1173 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); 1174 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises); 1175 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); 1176 int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bool enable_uc_lb, 1177 bool enable_mc_lb); 1178 int mlx5e_refresh_tirs(struct mlx5_core_dev *mdev, bool enable_uc_lb, 1179 bool enable_mc_lb); 1180 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc); 1181 1182 /* common netdev helpers */ 1183 void mlx5e_create_q_counters(struct mlx5e_priv *priv); 1184 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); 1185 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1186 struct mlx5e_rq *drop_rq); 1187 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); 1188 1189 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); 1190 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); 1191 1192 void mlx5e_update_carrier(struct mlx5e_priv *priv); 1193 int mlx5e_close(struct net_device *netdev); 1194 int mlx5e_open(struct net_device *netdev); 1195 1196 void mlx5e_queue_update_stats(struct mlx5e_priv *priv); 1197 1198 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); 1199 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); 1200 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 1201 mlx5e_fp_preactivate preactivate); 1202 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv); 1203 1204 /* ethtool helpers */ 1205 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 1206 struct ethtool_drvinfo *drvinfo); 1207 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, 1208 u32 stringset, u8 *data); 1209 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); 1210 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 1211 struct ethtool_stats *stats, u64 *data); 1212 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 1213 struct ethtool_ringparam *param, 1214 struct kernel_ethtool_ringparam *kernel_param); 1215 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 1216 struct ethtool_ringparam *param, 1217 struct netlink_ext_ack *extack); 1218 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 1219 struct ethtool_channels *ch); 1220 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 1221 struct ethtool_channels *ch); 1222 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 1223 struct ethtool_coalesce *coal, 1224 struct kernel_ethtool_coalesce *kernel_coal, 1225 struct netlink_ext_ack *extack); 1226 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 1227 struct ethtool_coalesce *coal, 1228 struct kernel_ethtool_coalesce *kernel_coal, 1229 struct netlink_ext_ack *extack); 1230 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue, 1231 struct ethtool_coalesce *coal); 1232 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue, 1233 struct ethtool_coalesce *coal); 1234 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); 1235 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); 1236 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1237 struct kernel_ethtool_ts_info *info); 1238 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1239 struct ethtool_flash *flash); 1240 1241 /* mlx5e generic netdev management API */ 1242 static inline bool 1243 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev) 1244 { 1245 return !is_kdump_kernel() && 1246 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); 1247 } 1248 1249 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev); 1250 int mlx5e_priv_init(struct mlx5e_priv *priv, 1251 const struct mlx5e_profile *profile, 1252 struct net_device *netdev, 1253 struct mlx5_core_dev *mdev); 1254 void mlx5e_priv_cleanup(struct mlx5e_priv *priv); 1255 struct net_device * 1256 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile); 1257 int mlx5e_attach_netdev(struct mlx5e_priv *priv); 1258 void mlx5e_detach_netdev(struct mlx5e_priv *priv); 1259 void mlx5e_destroy_netdev(struct net_device *netdev); 1260 int mlx5e_netdev_change_profile(struct net_device *netdev, 1261 struct mlx5_core_dev *mdev, 1262 const struct mlx5e_profile *new_profile, 1263 void *new_ppriv); 1264 void mlx5e_netdev_attach_nic_profile(struct net_device *netdev, 1265 struct mlx5_core_dev *mdev); 1266 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); 1267 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu); 1268 1269 void mlx5e_set_xdp_feature(struct mlx5e_priv *priv); 1270 netdev_features_t mlx5e_features_check(struct sk_buff *skb, 1271 struct net_device *netdev, 1272 netdev_features_t features); 1273 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); 1274 #ifdef CONFIG_MLX5_ESWITCH 1275 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); 1276 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); 1277 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); 1278 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); 1279 #endif 1280 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); 1281 #endif /* __MLX5_EN_H__ */ 1282