1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright 2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
4 */
5
6 #include <linux/delay.h>
7 #include <linux/sched/types.h>
8 #include <linux/seq_file.h>
9 #include <linux/slab.h>
10
11 #include <media/cec-pin.h>
12 #include "cec-pin-priv.h"
13
14 /* All timings are in microseconds */
15
16 /* start bit timings */
17 #define CEC_TIM_START_BIT_LOW 3700
18 #define CEC_TIM_START_BIT_LOW_MIN 3500
19 #define CEC_TIM_START_BIT_LOW_MAX 3900
20 #define CEC_TIM_START_BIT_TOTAL 4500
21 #define CEC_TIM_START_BIT_TOTAL_MIN 4300
22 #define CEC_TIM_START_BIT_TOTAL_MAX 4700
23
24 /* data bit timings */
25 #define CEC_TIM_DATA_BIT_0_LOW 1500
26 #define CEC_TIM_DATA_BIT_0_LOW_MIN 1300
27 #define CEC_TIM_DATA_BIT_0_LOW_MAX 1700
28 #define CEC_TIM_DATA_BIT_1_LOW 600
29 #define CEC_TIM_DATA_BIT_1_LOW_MIN 400
30 #define CEC_TIM_DATA_BIT_1_LOW_MAX 800
31 #define CEC_TIM_DATA_BIT_TOTAL 2400
32 #define CEC_TIM_DATA_BIT_TOTAL_MIN 2050
33 #define CEC_TIM_DATA_BIT_TOTAL_MAX 2750
34 /* earliest safe time to sample the bit state */
35 #define CEC_TIM_DATA_BIT_SAMPLE 850
36 /* earliest time the bit is back to 1 (T7 + 50) */
37 #define CEC_TIM_DATA_BIT_HIGH 1750
38
39 /* when idle, sample once per millisecond */
40 #define CEC_TIM_IDLE_SAMPLE 1000
41 /* when processing the start bit, sample twice per millisecond */
42 #define CEC_TIM_START_BIT_SAMPLE 500
43 /* when polling for a state change, sample once every 50 microseconds */
44 #define CEC_TIM_SAMPLE 50
45
46 #define CEC_TIM_LOW_DRIVE_ERROR (1.5 * CEC_TIM_DATA_BIT_TOTAL)
47
48 /*
49 * Total data bit time that is too short/long for a valid bit,
50 * used for error injection.
51 */
52 #define CEC_TIM_DATA_BIT_TOTAL_SHORT 1800
53 #define CEC_TIM_DATA_BIT_TOTAL_LONG 2900
54
55 /*
56 * Total start bit time that is too short/long for a valid bit,
57 * used for error injection.
58 */
59 #define CEC_TIM_START_BIT_TOTAL_SHORT 4100
60 #define CEC_TIM_START_BIT_TOTAL_LONG 5000
61
62 /* Data bits are 0-7, EOM is bit 8 and ACK is bit 9 */
63 #define EOM_BIT 8
64 #define ACK_BIT 9
65
66 struct cec_state {
67 const char * const name;
68 unsigned int usecs;
69 };
70
71 static const struct cec_state states[CEC_PIN_STATES] = {
72 { "Off", 0 },
73 { "Idle", CEC_TIM_IDLE_SAMPLE },
74 { "Tx Wait", CEC_TIM_SAMPLE },
75 { "Tx Wait for High", CEC_TIM_IDLE_SAMPLE },
76 { "Tx Start Bit Low", CEC_TIM_START_BIT_LOW },
77 { "Tx Start Bit High", CEC_TIM_START_BIT_TOTAL - CEC_TIM_START_BIT_LOW },
78 { "Tx Start Bit High Short", CEC_TIM_START_BIT_TOTAL_SHORT - CEC_TIM_START_BIT_LOW },
79 { "Tx Start Bit High Long", CEC_TIM_START_BIT_TOTAL_LONG - CEC_TIM_START_BIT_LOW },
80 { "Tx Start Bit Low Custom", 0 },
81 { "Tx Start Bit High Custom", 0 },
82 { "Tx Data 0 Low", CEC_TIM_DATA_BIT_0_LOW },
83 { "Tx Data 0 High", CEC_TIM_DATA_BIT_TOTAL - CEC_TIM_DATA_BIT_0_LOW },
84 { "Tx Data 0 High Short", CEC_TIM_DATA_BIT_TOTAL_SHORT - CEC_TIM_DATA_BIT_0_LOW },
85 { "Tx Data 0 High Long", CEC_TIM_DATA_BIT_TOTAL_LONG - CEC_TIM_DATA_BIT_0_LOW },
86 { "Tx Data 1 Low", CEC_TIM_DATA_BIT_1_LOW },
87 { "Tx Data 1 High", CEC_TIM_DATA_BIT_TOTAL - CEC_TIM_DATA_BIT_1_LOW },
88 { "Tx Data 1 High Short", CEC_TIM_DATA_BIT_TOTAL_SHORT - CEC_TIM_DATA_BIT_1_LOW },
89 { "Tx Data 1 High Long", CEC_TIM_DATA_BIT_TOTAL_LONG - CEC_TIM_DATA_BIT_1_LOW },
90 { "Tx Data 1 High Pre Sample", CEC_TIM_DATA_BIT_SAMPLE - CEC_TIM_DATA_BIT_1_LOW },
91 { "Tx Data 1 High Post Sample", CEC_TIM_DATA_BIT_TOTAL - CEC_TIM_DATA_BIT_SAMPLE },
92 { "Tx Data 1 High Post Sample Short", CEC_TIM_DATA_BIT_TOTAL_SHORT - CEC_TIM_DATA_BIT_SAMPLE },
93 { "Tx Data 1 High Post Sample Long", CEC_TIM_DATA_BIT_TOTAL_LONG - CEC_TIM_DATA_BIT_SAMPLE },
94 { "Tx Data Bit Low Custom", 0 },
95 { "Tx Data Bit High Custom", 0 },
96 { "Tx Pulse Low Custom", 0 },
97 { "Tx Pulse High Custom", 0 },
98 { "Tx Low Drive", CEC_TIM_LOW_DRIVE_ERROR },
99 { "Rx Start Bit Low", CEC_TIM_SAMPLE },
100 { "Rx Start Bit High", CEC_TIM_SAMPLE },
101 { "Rx Data Sample", CEC_TIM_DATA_BIT_SAMPLE },
102 { "Rx Data Post Sample", CEC_TIM_DATA_BIT_HIGH - CEC_TIM_DATA_BIT_SAMPLE },
103 { "Rx Data Wait for Low", CEC_TIM_SAMPLE },
104 { "Rx Ack Low", CEC_TIM_DATA_BIT_0_LOW },
105 { "Rx Ack Low Post", CEC_TIM_DATA_BIT_HIGH - CEC_TIM_DATA_BIT_0_LOW },
106 { "Rx Ack High Post", CEC_TIM_DATA_BIT_HIGH },
107 { "Rx Ack Finish", CEC_TIM_DATA_BIT_TOTAL_MIN - CEC_TIM_DATA_BIT_HIGH },
108 { "Rx Low Drive", CEC_TIM_LOW_DRIVE_ERROR },
109 { "Rx Irq", 0 },
110 };
111
cec_pin_update(struct cec_pin * pin,bool v,bool force)112 static void cec_pin_update(struct cec_pin *pin, bool v, bool force)
113 {
114 if (!force && v == pin->adap->cec_pin_is_high)
115 return;
116
117 pin->adap->cec_pin_is_high = v;
118 if (atomic_read(&pin->work_pin_num_events) < CEC_NUM_PIN_EVENTS) {
119 u8 ev = v;
120
121 if (pin->work_pin_events_dropped) {
122 pin->work_pin_events_dropped = false;
123 ev |= CEC_PIN_EVENT_FL_DROPPED;
124 }
125 pin->work_pin_events[pin->work_pin_events_wr] = ev;
126 pin->work_pin_ts[pin->work_pin_events_wr] = ktime_get();
127 pin->work_pin_events_wr =
128 (pin->work_pin_events_wr + 1) % CEC_NUM_PIN_EVENTS;
129 atomic_inc(&pin->work_pin_num_events);
130 } else {
131 pin->work_pin_events_dropped = true;
132 pin->work_pin_events_dropped_cnt++;
133 }
134 wake_up_interruptible(&pin->kthread_waitq);
135 }
136
cec_pin_read(struct cec_pin * pin)137 static bool cec_pin_read(struct cec_pin *pin)
138 {
139 bool v = call_pin_op(pin, read);
140
141 cec_pin_update(pin, v, false);
142 return v;
143 }
144
cec_pin_insert_glitch(struct cec_pin * pin,bool rising_edge)145 static void cec_pin_insert_glitch(struct cec_pin *pin, bool rising_edge)
146 {
147 /*
148 * Insert a short glitch after the falling or rising edge to
149 * simulate reflections on the CEC line. This can be used to
150 * test deglitch filters, which should be present in CEC devices
151 * to deal with noise on the line.
152 */
153 if (!pin->tx_glitch_high_usecs || !pin->tx_glitch_low_usecs)
154 return;
155 if (rising_edge) {
156 udelay(pin->tx_glitch_high_usecs);
157 call_void_pin_op(pin, low);
158 udelay(pin->tx_glitch_low_usecs);
159 call_void_pin_op(pin, high);
160 } else {
161 udelay(pin->tx_glitch_low_usecs);
162 call_void_pin_op(pin, high);
163 udelay(pin->tx_glitch_high_usecs);
164 call_void_pin_op(pin, low);
165 }
166 }
167
cec_pin_low(struct cec_pin * pin)168 static void cec_pin_low(struct cec_pin *pin)
169 {
170 call_void_pin_op(pin, low);
171 if (pin->tx_glitch_falling_edge && pin->adap->cec_pin_is_high)
172 cec_pin_insert_glitch(pin, false);
173 cec_pin_update(pin, false, false);
174 }
175
cec_pin_high(struct cec_pin * pin)176 static bool cec_pin_high(struct cec_pin *pin)
177 {
178 call_void_pin_op(pin, high);
179 if (pin->tx_glitch_rising_edge && !pin->adap->cec_pin_is_high)
180 cec_pin_insert_glitch(pin, true);
181 return cec_pin_read(pin);
182 }
183
rx_error_inj(struct cec_pin * pin,unsigned int mode_offset,int arg_idx,u8 * arg)184 static bool rx_error_inj(struct cec_pin *pin, unsigned int mode_offset,
185 int arg_idx, u8 *arg)
186 {
187 #ifdef CONFIG_CEC_PIN_ERROR_INJ
188 u16 cmd = cec_pin_rx_error_inj(pin);
189 u64 e = pin->error_inj[cmd];
190 unsigned int mode = (e >> mode_offset) & CEC_ERROR_INJ_MODE_MASK;
191
192 if (arg_idx >= 0) {
193 u8 pos = pin->error_inj_args[cmd][arg_idx];
194
195 if (arg)
196 *arg = pos;
197 else if (pos != pin->rx_bit)
198 return false;
199 }
200
201 switch (mode) {
202 case CEC_ERROR_INJ_MODE_ONCE:
203 pin->error_inj[cmd] &=
204 ~(CEC_ERROR_INJ_MODE_MASK << mode_offset);
205 return true;
206 case CEC_ERROR_INJ_MODE_ALWAYS:
207 return true;
208 case CEC_ERROR_INJ_MODE_TOGGLE:
209 return pin->rx_toggle;
210 default:
211 return false;
212 }
213 #else
214 return false;
215 #endif
216 }
217
rx_nack(struct cec_pin * pin)218 static bool rx_nack(struct cec_pin *pin)
219 {
220 return rx_error_inj(pin, CEC_ERROR_INJ_RX_NACK_OFFSET, -1, NULL);
221 }
222
rx_low_drive(struct cec_pin * pin)223 static bool rx_low_drive(struct cec_pin *pin)
224 {
225 return rx_error_inj(pin, CEC_ERROR_INJ_RX_LOW_DRIVE_OFFSET,
226 CEC_ERROR_INJ_RX_LOW_DRIVE_ARG_IDX, NULL);
227 }
228
rx_add_byte(struct cec_pin * pin)229 static bool rx_add_byte(struct cec_pin *pin)
230 {
231 return rx_error_inj(pin, CEC_ERROR_INJ_RX_ADD_BYTE_OFFSET, -1, NULL);
232 }
233
rx_remove_byte(struct cec_pin * pin)234 static bool rx_remove_byte(struct cec_pin *pin)
235 {
236 return rx_error_inj(pin, CEC_ERROR_INJ_RX_REMOVE_BYTE_OFFSET, -1, NULL);
237 }
238
rx_arb_lost(struct cec_pin * pin,u8 * poll)239 static bool rx_arb_lost(struct cec_pin *pin, u8 *poll)
240 {
241 return pin->tx_msg.len == 0 &&
242 rx_error_inj(pin, CEC_ERROR_INJ_RX_ARB_LOST_OFFSET,
243 CEC_ERROR_INJ_RX_ARB_LOST_ARG_IDX, poll);
244 }
245
tx_error_inj(struct cec_pin * pin,unsigned int mode_offset,int arg_idx,u8 * arg)246 static bool tx_error_inj(struct cec_pin *pin, unsigned int mode_offset,
247 int arg_idx, u8 *arg)
248 {
249 #ifdef CONFIG_CEC_PIN_ERROR_INJ
250 u16 cmd = cec_pin_tx_error_inj(pin);
251 u64 e = pin->error_inj[cmd];
252 unsigned int mode = (e >> mode_offset) & CEC_ERROR_INJ_MODE_MASK;
253
254 if (arg_idx >= 0) {
255 u8 pos = pin->error_inj_args[cmd][arg_idx];
256
257 if (arg)
258 *arg = pos;
259 else if (pos != pin->tx_bit)
260 return false;
261 }
262
263 switch (mode) {
264 case CEC_ERROR_INJ_MODE_ONCE:
265 pin->error_inj[cmd] &=
266 ~(CEC_ERROR_INJ_MODE_MASK << mode_offset);
267 return true;
268 case CEC_ERROR_INJ_MODE_ALWAYS:
269 return true;
270 case CEC_ERROR_INJ_MODE_TOGGLE:
271 return pin->tx_toggle;
272 default:
273 return false;
274 }
275 #else
276 return false;
277 #endif
278 }
279
tx_no_eom(struct cec_pin * pin)280 static bool tx_no_eom(struct cec_pin *pin)
281 {
282 return tx_error_inj(pin, CEC_ERROR_INJ_TX_NO_EOM_OFFSET, -1, NULL);
283 }
284
tx_early_eom(struct cec_pin * pin)285 static bool tx_early_eom(struct cec_pin *pin)
286 {
287 return tx_error_inj(pin, CEC_ERROR_INJ_TX_EARLY_EOM_OFFSET, -1, NULL);
288 }
289
tx_short_bit(struct cec_pin * pin)290 static bool tx_short_bit(struct cec_pin *pin)
291 {
292 return tx_error_inj(pin, CEC_ERROR_INJ_TX_SHORT_BIT_OFFSET,
293 CEC_ERROR_INJ_TX_SHORT_BIT_ARG_IDX, NULL);
294 }
295
tx_long_bit(struct cec_pin * pin)296 static bool tx_long_bit(struct cec_pin *pin)
297 {
298 return tx_error_inj(pin, CEC_ERROR_INJ_TX_LONG_BIT_OFFSET,
299 CEC_ERROR_INJ_TX_LONG_BIT_ARG_IDX, NULL);
300 }
301
tx_custom_bit(struct cec_pin * pin)302 static bool tx_custom_bit(struct cec_pin *pin)
303 {
304 return tx_error_inj(pin, CEC_ERROR_INJ_TX_CUSTOM_BIT_OFFSET,
305 CEC_ERROR_INJ_TX_CUSTOM_BIT_ARG_IDX, NULL);
306 }
307
tx_short_start(struct cec_pin * pin)308 static bool tx_short_start(struct cec_pin *pin)
309 {
310 return tx_error_inj(pin, CEC_ERROR_INJ_TX_SHORT_START_OFFSET, -1, NULL);
311 }
312
tx_long_start(struct cec_pin * pin)313 static bool tx_long_start(struct cec_pin *pin)
314 {
315 return tx_error_inj(pin, CEC_ERROR_INJ_TX_LONG_START_OFFSET, -1, NULL);
316 }
317
tx_custom_start(struct cec_pin * pin)318 static bool tx_custom_start(struct cec_pin *pin)
319 {
320 return tx_error_inj(pin, CEC_ERROR_INJ_TX_CUSTOM_START_OFFSET,
321 -1, NULL);
322 }
323
tx_last_bit(struct cec_pin * pin)324 static bool tx_last_bit(struct cec_pin *pin)
325 {
326 return tx_error_inj(pin, CEC_ERROR_INJ_TX_LAST_BIT_OFFSET,
327 CEC_ERROR_INJ_TX_LAST_BIT_ARG_IDX, NULL);
328 }
329
tx_add_bytes(struct cec_pin * pin)330 static u8 tx_add_bytes(struct cec_pin *pin)
331 {
332 u8 bytes;
333
334 if (tx_error_inj(pin, CEC_ERROR_INJ_TX_ADD_BYTES_OFFSET,
335 CEC_ERROR_INJ_TX_ADD_BYTES_ARG_IDX, &bytes))
336 return bytes;
337 return 0;
338 }
339
tx_remove_byte(struct cec_pin * pin)340 static bool tx_remove_byte(struct cec_pin *pin)
341 {
342 return tx_error_inj(pin, CEC_ERROR_INJ_TX_REMOVE_BYTE_OFFSET, -1, NULL);
343 }
344
tx_low_drive(struct cec_pin * pin)345 static bool tx_low_drive(struct cec_pin *pin)
346 {
347 return tx_error_inj(pin, CEC_ERROR_INJ_TX_LOW_DRIVE_OFFSET,
348 CEC_ERROR_INJ_TX_LOW_DRIVE_ARG_IDX, NULL);
349 }
350
cec_pin_to_idle(struct cec_pin * pin)351 static void cec_pin_to_idle(struct cec_pin *pin)
352 {
353 /*
354 * Reset all status fields, release the bus and
355 * go to idle state.
356 */
357 pin->rx_bit = pin->tx_bit = 0;
358 pin->rx_msg.len = 0;
359 memset(pin->rx_msg.msg, 0, sizeof(pin->rx_msg.msg));
360 pin->ts = ns_to_ktime(0);
361 pin->tx_generated_poll = false;
362 pin->tx_post_eom = false;
363 if (pin->state >= CEC_ST_TX_WAIT &&
364 pin->state <= CEC_ST_TX_LOW_DRIVE)
365 pin->tx_toggle ^= 1;
366 if (pin->state >= CEC_ST_RX_START_BIT_LOW &&
367 pin->state <= CEC_ST_RX_LOW_DRIVE)
368 pin->rx_toggle ^= 1;
369 pin->state = CEC_ST_IDLE;
370 }
371
372 /*
373 * Handle Transmit-related states
374 *
375 * Basic state changes when transmitting:
376 *
377 * Idle -> Tx Wait (waiting for the end of signal free time) ->
378 * Tx Start Bit Low -> Tx Start Bit High ->
379 *
380 * Regular data bits + EOM:
381 * Tx Data 0 Low -> Tx Data 0 High ->
382 * or:
383 * Tx Data 1 Low -> Tx Data 1 High ->
384 *
385 * First 4 data bits or Ack bit:
386 * Tx Data 0 Low -> Tx Data 0 High ->
387 * or:
388 * Tx Data 1 Low -> Tx Data 1 High -> Tx Data 1 Pre Sample ->
389 * Tx Data 1 Post Sample ->
390 *
391 * After the last Ack go to Idle.
392 *
393 * If it detects a Low Drive condition then:
394 * Tx Wait For High -> Idle
395 *
396 * If it loses arbitration, then it switches to state Rx Data Post Sample.
397 */
cec_pin_tx_states(struct cec_pin * pin,ktime_t ts)398 static void cec_pin_tx_states(struct cec_pin *pin, ktime_t ts)
399 {
400 bool v;
401 bool is_ack_bit, ack;
402
403 switch (pin->state) {
404 case CEC_ST_TX_WAIT_FOR_HIGH:
405 if (cec_pin_read(pin))
406 cec_pin_to_idle(pin);
407 break;
408
409 case CEC_ST_TX_START_BIT_LOW:
410 if (tx_short_start(pin)) {
411 /*
412 * Error Injection: send an invalid (too short)
413 * start pulse.
414 */
415 pin->state = CEC_ST_TX_START_BIT_HIGH_SHORT;
416 } else if (tx_long_start(pin)) {
417 /*
418 * Error Injection: send an invalid (too long)
419 * start pulse.
420 */
421 pin->state = CEC_ST_TX_START_BIT_HIGH_LONG;
422 } else {
423 pin->state = CEC_ST_TX_START_BIT_HIGH;
424 }
425 /* Generate start bit */
426 cec_pin_high(pin);
427 break;
428
429 case CEC_ST_TX_START_BIT_LOW_CUSTOM:
430 pin->state = CEC_ST_TX_START_BIT_HIGH_CUSTOM;
431 /* Generate start bit */
432 cec_pin_high(pin);
433 break;
434
435 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE:
436 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_SHORT:
437 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_LONG:
438 if (pin->tx_nacked) {
439 cec_pin_to_idle(pin);
440 pin->tx_msg.len = 0;
441 if (pin->tx_generated_poll)
442 break;
443 pin->work_tx_ts = ts;
444 pin->work_tx_status = CEC_TX_STATUS_NACK;
445 wake_up_interruptible(&pin->kthread_waitq);
446 break;
447 }
448 fallthrough;
449 case CEC_ST_TX_DATA_BIT_0_HIGH:
450 case CEC_ST_TX_DATA_BIT_0_HIGH_SHORT:
451 case CEC_ST_TX_DATA_BIT_0_HIGH_LONG:
452 case CEC_ST_TX_DATA_BIT_1_HIGH:
453 case CEC_ST_TX_DATA_BIT_1_HIGH_SHORT:
454 case CEC_ST_TX_DATA_BIT_1_HIGH_LONG:
455 /*
456 * If the read value is 1, then all is OK, otherwise we have a
457 * low drive condition.
458 *
459 * Special case: when we generate a poll message due to an
460 * Arbitration Lost error injection, then ignore this since
461 * the pin can actually be low in that case.
462 */
463 if (!cec_pin_read(pin) && !pin->tx_generated_poll) {
464 /*
465 * It's 0, so someone detected an error and pulled the
466 * line low for 1.5 times the nominal bit period.
467 */
468 pin->tx_msg.len = 0;
469 pin->state = CEC_ST_TX_WAIT_FOR_HIGH;
470 pin->work_tx_ts = ts;
471 pin->work_tx_status = CEC_TX_STATUS_LOW_DRIVE;
472 pin->tx_low_drive_cnt++;
473 wake_up_interruptible(&pin->kthread_waitq);
474 break;
475 }
476 fallthrough;
477 case CEC_ST_TX_DATA_BIT_HIGH_CUSTOM:
478 if (tx_last_bit(pin)) {
479 /* Error Injection: just stop sending after this bit */
480 cec_pin_to_idle(pin);
481 pin->tx_msg.len = 0;
482 if (pin->tx_generated_poll)
483 break;
484 pin->work_tx_ts = ts;
485 pin->work_tx_status = CEC_TX_STATUS_OK;
486 wake_up_interruptible(&pin->kthread_waitq);
487 break;
488 }
489 pin->tx_bit++;
490 fallthrough;
491 case CEC_ST_TX_START_BIT_HIGH:
492 case CEC_ST_TX_START_BIT_HIGH_SHORT:
493 case CEC_ST_TX_START_BIT_HIGH_LONG:
494 case CEC_ST_TX_START_BIT_HIGH_CUSTOM:
495 if (tx_low_drive(pin)) {
496 /* Error injection: go to low drive */
497 cec_pin_low(pin);
498 pin->state = CEC_ST_TX_LOW_DRIVE;
499 pin->tx_msg.len = 0;
500 if (pin->tx_generated_poll)
501 break;
502 pin->work_tx_ts = ts;
503 pin->work_tx_status = CEC_TX_STATUS_LOW_DRIVE;
504 pin->tx_low_drive_cnt++;
505 wake_up_interruptible(&pin->kthread_waitq);
506 break;
507 }
508 if (pin->tx_bit / 10 >= pin->tx_msg.len + pin->tx_extra_bytes) {
509 cec_pin_to_idle(pin);
510 pin->tx_msg.len = 0;
511 if (pin->tx_generated_poll)
512 break;
513 pin->work_tx_ts = ts;
514 pin->work_tx_status = CEC_TX_STATUS_OK;
515 wake_up_interruptible(&pin->kthread_waitq);
516 break;
517 }
518
519 switch (pin->tx_bit % 10) {
520 default: {
521 /*
522 * In the CEC_ERROR_INJ_TX_ADD_BYTES case we transmit
523 * extra bytes, so pin->tx_bit / 10 can become >= 16.
524 * Generate bit values for those extra bytes instead
525 * of reading them from the transmit buffer.
526 */
527 unsigned int idx = (pin->tx_bit / 10);
528 u8 val = idx;
529
530 if (idx < pin->tx_msg.len)
531 val = pin->tx_msg.msg[idx];
532 v = val & (1 << (7 - (pin->tx_bit % 10)));
533
534 pin->state = v ? CEC_ST_TX_DATA_BIT_1_LOW :
535 CEC_ST_TX_DATA_BIT_0_LOW;
536 break;
537 }
538 case EOM_BIT: {
539 unsigned int tot_len = pin->tx_msg.len +
540 pin->tx_extra_bytes;
541 unsigned int tx_byte_idx = pin->tx_bit / 10;
542
543 v = !pin->tx_post_eom && tx_byte_idx == tot_len - 1;
544 if (tot_len > 1 && tx_byte_idx == tot_len - 2 &&
545 tx_early_eom(pin)) {
546 /* Error injection: set EOM one byte early */
547 v = true;
548 pin->tx_post_eom = true;
549 } else if (v && tx_no_eom(pin)) {
550 /* Error injection: no EOM */
551 v = false;
552 }
553 pin->state = v ? CEC_ST_TX_DATA_BIT_1_LOW :
554 CEC_ST_TX_DATA_BIT_0_LOW;
555 break;
556 }
557 case ACK_BIT:
558 pin->state = CEC_ST_TX_DATA_BIT_1_LOW;
559 break;
560 }
561 if (tx_custom_bit(pin))
562 pin->state = CEC_ST_TX_DATA_BIT_LOW_CUSTOM;
563 cec_pin_low(pin);
564 break;
565
566 case CEC_ST_TX_DATA_BIT_0_LOW:
567 case CEC_ST_TX_DATA_BIT_1_LOW:
568 v = pin->state == CEC_ST_TX_DATA_BIT_1_LOW;
569 is_ack_bit = pin->tx_bit % 10 == ACK_BIT;
570 if (v && (pin->tx_bit < 4 || is_ack_bit)) {
571 pin->state = CEC_ST_TX_DATA_BIT_1_HIGH_PRE_SAMPLE;
572 } else if (!is_ack_bit && tx_short_bit(pin)) {
573 /* Error Injection: send an invalid (too short) bit */
574 pin->state = v ? CEC_ST_TX_DATA_BIT_1_HIGH_SHORT :
575 CEC_ST_TX_DATA_BIT_0_HIGH_SHORT;
576 } else if (!is_ack_bit && tx_long_bit(pin)) {
577 /* Error Injection: send an invalid (too long) bit */
578 pin->state = v ? CEC_ST_TX_DATA_BIT_1_HIGH_LONG :
579 CEC_ST_TX_DATA_BIT_0_HIGH_LONG;
580 } else {
581 pin->state = v ? CEC_ST_TX_DATA_BIT_1_HIGH :
582 CEC_ST_TX_DATA_BIT_0_HIGH;
583 }
584 cec_pin_high(pin);
585 break;
586
587 case CEC_ST_TX_DATA_BIT_LOW_CUSTOM:
588 pin->state = CEC_ST_TX_DATA_BIT_HIGH_CUSTOM;
589 cec_pin_high(pin);
590 break;
591
592 case CEC_ST_TX_DATA_BIT_1_HIGH_PRE_SAMPLE:
593 /* Read the CEC value at the sample time */
594 v = cec_pin_read(pin);
595 is_ack_bit = pin->tx_bit % 10 == ACK_BIT;
596 /*
597 * If v == 0 and we're within the first 4 bits
598 * of the initiator, then someone else started
599 * transmitting and we lost the arbitration
600 * (i.e. the logical address of the other
601 * transmitter has more leading 0 bits in the
602 * initiator).
603 */
604 if (!v && !is_ack_bit && !pin->tx_generated_poll) {
605 pin->tx_msg.len = 0;
606 pin->work_tx_ts = ts;
607 pin->work_tx_status = CEC_TX_STATUS_ARB_LOST;
608 wake_up_interruptible(&pin->kthread_waitq);
609 pin->rx_bit = pin->tx_bit;
610 pin->tx_bit = 0;
611 memset(pin->rx_msg.msg, 0, sizeof(pin->rx_msg.msg));
612 pin->rx_msg.msg[0] = pin->tx_msg.msg[0];
613 pin->rx_msg.msg[0] &= (0xff << (8 - pin->rx_bit));
614 pin->rx_msg.len = 0;
615 pin->ts = ktime_sub_us(ts, CEC_TIM_DATA_BIT_SAMPLE);
616 pin->state = CEC_ST_RX_DATA_POST_SAMPLE;
617 pin->rx_bit++;
618 break;
619 }
620 pin->state = CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE;
621 if (!is_ack_bit && tx_short_bit(pin)) {
622 /* Error Injection: send an invalid (too short) bit */
623 pin->state = CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_SHORT;
624 } else if (!is_ack_bit && tx_long_bit(pin)) {
625 /* Error Injection: send an invalid (too long) bit */
626 pin->state = CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_LONG;
627 }
628 if (!is_ack_bit)
629 break;
630 /* Was the message ACKed? */
631 ack = cec_msg_is_broadcast(&pin->tx_msg) ? v : !v;
632 if (!ack && (!pin->tx_ignore_nack_until_eom ||
633 pin->tx_bit / 10 == pin->tx_msg.len - 1) &&
634 !pin->tx_post_eom) {
635 /*
636 * Note: the CEC spec is ambiguous regarding
637 * what action to take when a NACK appears
638 * before the last byte of the payload was
639 * transmitted: either stop transmitting
640 * immediately, or wait until the last byte
641 * was transmitted.
642 *
643 * Most CEC implementations appear to stop
644 * immediately, and that's what we do here
645 * as well.
646 */
647 pin->tx_nacked = true;
648 }
649 break;
650
651 case CEC_ST_TX_PULSE_LOW_CUSTOM:
652 cec_pin_high(pin);
653 pin->state = CEC_ST_TX_PULSE_HIGH_CUSTOM;
654 break;
655
656 case CEC_ST_TX_PULSE_HIGH_CUSTOM:
657 cec_pin_to_idle(pin);
658 break;
659
660 default:
661 break;
662 }
663 }
664
665 /*
666 * Handle Receive-related states
667 *
668 * Basic state changes when receiving:
669 *
670 * Rx Start Bit Low -> Rx Start Bit High ->
671 * Regular data bits + EOM:
672 * Rx Data Sample -> Rx Data Post Sample -> Rx Data High ->
673 * Ack bit 0:
674 * Rx Ack Low -> Rx Ack Low Post -> Rx Data High ->
675 * Ack bit 1:
676 * Rx Ack High Post -> Rx Data High ->
677 * Ack bit 0 && EOM:
678 * Rx Ack Low -> Rx Ack Low Post -> Rx Ack Finish -> Idle
679 */
cec_pin_rx_states(struct cec_pin * pin,ktime_t ts)680 static void cec_pin_rx_states(struct cec_pin *pin, ktime_t ts)
681 {
682 s32 delta;
683 bool v;
684 bool ack;
685 bool bcast, for_us;
686 u8 dest;
687 u8 poll;
688
689 switch (pin->state) {
690 /* Receive states */
691 case CEC_ST_RX_START_BIT_LOW:
692 v = cec_pin_read(pin);
693 if (!v)
694 break;
695 pin->state = CEC_ST_RX_START_BIT_HIGH;
696 delta = ktime_us_delta(ts, pin->ts);
697 /* Start bit low is too short, go back to idle */
698 if (delta < CEC_TIM_START_BIT_LOW_MIN - CEC_TIM_IDLE_SAMPLE) {
699 if (!pin->rx_start_bit_low_too_short_cnt++) {
700 pin->rx_start_bit_low_too_short_ts = ktime_to_ns(pin->ts);
701 pin->rx_start_bit_low_too_short_delta = delta;
702 }
703 cec_pin_to_idle(pin);
704 break;
705 }
706 if (rx_arb_lost(pin, &poll)) {
707 cec_msg_init(&pin->tx_msg, poll >> 4, poll & 0xf);
708 pin->tx_generated_poll = true;
709 pin->tx_extra_bytes = 0;
710 pin->state = CEC_ST_TX_START_BIT_HIGH;
711 pin->ts = ts;
712 }
713 break;
714
715 case CEC_ST_RX_START_BIT_HIGH:
716 v = cec_pin_read(pin);
717 delta = ktime_us_delta(ts, pin->ts);
718 /*
719 * Unfortunately the spec does not specify when to give up
720 * and go to idle. We just pick TOTAL_LONG.
721 */
722 if (v && delta > CEC_TIM_START_BIT_TOTAL_LONG) {
723 pin->rx_start_bit_too_long_cnt++;
724 cec_pin_to_idle(pin);
725 break;
726 }
727 if (v)
728 break;
729 /* Start bit is too short, go back to idle */
730 if (delta < CEC_TIM_START_BIT_TOTAL_MIN - CEC_TIM_IDLE_SAMPLE) {
731 if (!pin->rx_start_bit_too_short_cnt++) {
732 pin->rx_start_bit_too_short_ts = ktime_to_ns(pin->ts);
733 pin->rx_start_bit_too_short_delta = delta;
734 }
735 cec_pin_to_idle(pin);
736 break;
737 }
738 if (rx_low_drive(pin)) {
739 /* Error injection: go to low drive */
740 cec_pin_low(pin);
741 pin->state = CEC_ST_RX_LOW_DRIVE;
742 pin->rx_low_drive_cnt++;
743 break;
744 }
745 pin->state = CEC_ST_RX_DATA_SAMPLE;
746 pin->ts = ts;
747 pin->rx_eom = false;
748 break;
749
750 case CEC_ST_RX_DATA_SAMPLE:
751 v = cec_pin_read(pin);
752 pin->state = CEC_ST_RX_DATA_POST_SAMPLE;
753 switch (pin->rx_bit % 10) {
754 default:
755 if (pin->rx_bit / 10 < CEC_MAX_MSG_SIZE)
756 pin->rx_msg.msg[pin->rx_bit / 10] |=
757 v << (7 - (pin->rx_bit % 10));
758 break;
759 case EOM_BIT:
760 pin->rx_eom = v;
761 pin->rx_msg.len = pin->rx_bit / 10 + 1;
762 break;
763 case ACK_BIT:
764 break;
765 }
766 pin->rx_bit++;
767 break;
768
769 case CEC_ST_RX_DATA_POST_SAMPLE:
770 pin->state = CEC_ST_RX_DATA_WAIT_FOR_LOW;
771 break;
772
773 case CEC_ST_RX_DATA_WAIT_FOR_LOW:
774 v = cec_pin_read(pin);
775 delta = ktime_us_delta(ts, pin->ts);
776 /*
777 * Unfortunately the spec does not specify when to give up
778 * and go to idle. We just pick TOTAL_LONG.
779 */
780 if (v && delta > CEC_TIM_DATA_BIT_TOTAL_LONG) {
781 pin->rx_data_bit_too_long_cnt++;
782 cec_pin_to_idle(pin);
783 break;
784 }
785 if (v)
786 break;
787
788 if (rx_low_drive(pin)) {
789 /* Error injection: go to low drive */
790 cec_pin_low(pin);
791 pin->state = CEC_ST_RX_LOW_DRIVE;
792 pin->rx_low_drive_cnt++;
793 break;
794 }
795
796 /*
797 * Go to low drive state when the total bit time is
798 * too short.
799 */
800 if (delta < CEC_TIM_DATA_BIT_TOTAL_MIN && !pin->rx_no_low_drive) {
801 if (!pin->rx_data_bit_too_short_cnt++) {
802 pin->rx_data_bit_too_short_ts = ktime_to_ns(pin->ts);
803 pin->rx_data_bit_too_short_delta = delta;
804 }
805 cec_pin_low(pin);
806 pin->state = CEC_ST_RX_LOW_DRIVE;
807 pin->rx_low_drive_cnt++;
808 break;
809 }
810 pin->ts = ts;
811 if (pin->rx_bit % 10 != 9) {
812 pin->state = CEC_ST_RX_DATA_SAMPLE;
813 break;
814 }
815
816 dest = cec_msg_destination(&pin->rx_msg);
817 bcast = dest == CEC_LOG_ADDR_BROADCAST;
818 /* for_us == broadcast or directed to us */
819 for_us = bcast || (pin->la_mask & (1 << dest));
820 /* ACK bit value */
821 ack = bcast ? 1 : !for_us;
822
823 if (for_us && rx_nack(pin)) {
824 /* Error injection: toggle the ACK bit */
825 ack = !ack;
826 }
827
828 if (ack) {
829 /* No need to write to the bus, just wait */
830 pin->state = CEC_ST_RX_ACK_HIGH_POST;
831 break;
832 }
833 cec_pin_low(pin);
834 pin->state = CEC_ST_RX_ACK_LOW;
835 break;
836
837 case CEC_ST_RX_ACK_LOW:
838 cec_pin_high(pin);
839 pin->state = CEC_ST_RX_ACK_LOW_POST;
840 break;
841
842 case CEC_ST_RX_ACK_LOW_POST:
843 case CEC_ST_RX_ACK_HIGH_POST:
844 v = cec_pin_read(pin);
845 if (v && pin->rx_eom) {
846 pin->work_rx_msg = pin->rx_msg;
847 pin->work_rx_msg.rx_ts = ktime_to_ns(ts);
848 wake_up_interruptible(&pin->kthread_waitq);
849 pin->ts = ts;
850 pin->state = CEC_ST_RX_ACK_FINISH;
851 break;
852 }
853 pin->rx_bit++;
854 pin->state = CEC_ST_RX_DATA_WAIT_FOR_LOW;
855 break;
856
857 case CEC_ST_RX_ACK_FINISH:
858 cec_pin_to_idle(pin);
859 break;
860
861 default:
862 break;
863 }
864 }
865
866 /*
867 * Main timer function
868 *
869 */
cec_pin_timer(struct hrtimer * timer)870 static enum hrtimer_restart cec_pin_timer(struct hrtimer *timer)
871 {
872 struct cec_pin *pin = container_of(timer, struct cec_pin, timer);
873 struct cec_adapter *adap = pin->adap;
874 ktime_t ts;
875 s32 delta;
876 u32 usecs;
877
878 ts = ktime_get();
879 if (ktime_to_ns(pin->timer_ts)) {
880 delta = ktime_us_delta(ts, pin->timer_ts);
881 pin->timer_cnt++;
882 if (delta > 100 && pin->state != CEC_ST_IDLE) {
883 /* Keep track of timer overruns */
884 pin->timer_sum_overrun += delta;
885 pin->timer_100us_overruns++;
886 if (delta > 300)
887 pin->timer_300us_overruns++;
888 if (delta > pin->timer_max_overrun)
889 pin->timer_max_overrun = delta;
890 }
891 }
892 if (adap->monitor_pin_cnt)
893 cec_pin_read(pin);
894
895 if (pin->wait_usecs) {
896 /*
897 * If we are monitoring the pin, then we have to
898 * sample at regular intervals.
899 */
900 if (pin->wait_usecs > 150) {
901 pin->wait_usecs -= 100;
902 pin->timer_ts = ktime_add_us(ts, 100);
903 hrtimer_forward_now(timer, us_to_ktime(100));
904 return HRTIMER_RESTART;
905 }
906 if (pin->wait_usecs > 100) {
907 pin->wait_usecs /= 2;
908 pin->timer_ts = ktime_add_us(ts, pin->wait_usecs);
909 hrtimer_forward_now(timer,
910 us_to_ktime(pin->wait_usecs));
911 return HRTIMER_RESTART;
912 }
913 pin->timer_ts = ktime_add_us(ts, pin->wait_usecs);
914 hrtimer_forward_now(timer,
915 us_to_ktime(pin->wait_usecs));
916 pin->wait_usecs = 0;
917 return HRTIMER_RESTART;
918 }
919
920 switch (pin->state) {
921 /* Transmit states */
922 case CEC_ST_TX_WAIT_FOR_HIGH:
923 case CEC_ST_TX_START_BIT_LOW:
924 case CEC_ST_TX_START_BIT_HIGH:
925 case CEC_ST_TX_START_BIT_HIGH_SHORT:
926 case CEC_ST_TX_START_BIT_HIGH_LONG:
927 case CEC_ST_TX_START_BIT_LOW_CUSTOM:
928 case CEC_ST_TX_START_BIT_HIGH_CUSTOM:
929 case CEC_ST_TX_DATA_BIT_0_LOW:
930 case CEC_ST_TX_DATA_BIT_0_HIGH:
931 case CEC_ST_TX_DATA_BIT_0_HIGH_SHORT:
932 case CEC_ST_TX_DATA_BIT_0_HIGH_LONG:
933 case CEC_ST_TX_DATA_BIT_1_LOW:
934 case CEC_ST_TX_DATA_BIT_1_HIGH:
935 case CEC_ST_TX_DATA_BIT_1_HIGH_SHORT:
936 case CEC_ST_TX_DATA_BIT_1_HIGH_LONG:
937 case CEC_ST_TX_DATA_BIT_1_HIGH_PRE_SAMPLE:
938 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE:
939 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_SHORT:
940 case CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_LONG:
941 case CEC_ST_TX_DATA_BIT_LOW_CUSTOM:
942 case CEC_ST_TX_DATA_BIT_HIGH_CUSTOM:
943 case CEC_ST_TX_PULSE_LOW_CUSTOM:
944 case CEC_ST_TX_PULSE_HIGH_CUSTOM:
945 cec_pin_tx_states(pin, ts);
946 break;
947
948 /* Receive states */
949 case CEC_ST_RX_START_BIT_LOW:
950 case CEC_ST_RX_START_BIT_HIGH:
951 case CEC_ST_RX_DATA_SAMPLE:
952 case CEC_ST_RX_DATA_POST_SAMPLE:
953 case CEC_ST_RX_DATA_WAIT_FOR_LOW:
954 case CEC_ST_RX_ACK_LOW:
955 case CEC_ST_RX_ACK_LOW_POST:
956 case CEC_ST_RX_ACK_HIGH_POST:
957 case CEC_ST_RX_ACK_FINISH:
958 cec_pin_rx_states(pin, ts);
959 break;
960
961 case CEC_ST_IDLE:
962 case CEC_ST_TX_WAIT:
963 if (!cec_pin_high(pin)) {
964 /* Start bit, switch to receive state */
965 pin->ts = ts;
966 pin->state = CEC_ST_RX_START_BIT_LOW;
967 /*
968 * If a transmit is pending, then that transmit should
969 * use a signal free time of no more than
970 * CEC_SIGNAL_FREE_TIME_NEW_INITIATOR since it will
971 * have a new initiator due to the receive that is now
972 * starting.
973 */
974 if (pin->tx_msg.len && pin->tx_signal_free_time >
975 CEC_SIGNAL_FREE_TIME_NEW_INITIATOR)
976 pin->tx_signal_free_time =
977 CEC_SIGNAL_FREE_TIME_NEW_INITIATOR;
978 break;
979 }
980 if (ktime_to_ns(pin->ts) == 0)
981 pin->ts = ts;
982 if (pin->tx_msg.len) {
983 /*
984 * Check if the bus has been free for long enough
985 * so we can kick off the pending transmit.
986 */
987 delta = ktime_us_delta(ts, pin->ts);
988 if (delta / CEC_TIM_DATA_BIT_TOTAL >=
989 pin->tx_signal_free_time) {
990 pin->tx_nacked = false;
991 if (tx_custom_start(pin))
992 pin->state = CEC_ST_TX_START_BIT_LOW_CUSTOM;
993 else
994 pin->state = CEC_ST_TX_START_BIT_LOW;
995 /* Generate start bit */
996 cec_pin_low(pin);
997 break;
998 }
999 if (delta / CEC_TIM_DATA_BIT_TOTAL >=
1000 pin->tx_signal_free_time - 1)
1001 pin->state = CEC_ST_TX_WAIT;
1002 break;
1003 }
1004 if (pin->tx_custom_pulse && pin->state == CEC_ST_IDLE) {
1005 pin->tx_custom_pulse = false;
1006 /* Generate custom pulse */
1007 cec_pin_low(pin);
1008 pin->state = CEC_ST_TX_PULSE_LOW_CUSTOM;
1009 break;
1010 }
1011 if (pin->state != CEC_ST_IDLE || pin->ops->enable_irq == NULL ||
1012 pin->enable_irq_failed || adap->is_configuring ||
1013 adap->is_configured || adap->monitor_all_cnt || !adap->monitor_pin_cnt)
1014 break;
1015 /* Switch to interrupt mode */
1016 atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_ENABLE);
1017 pin->state = CEC_ST_RX_IRQ;
1018 wake_up_interruptible(&pin->kthread_waitq);
1019 return HRTIMER_NORESTART;
1020
1021 case CEC_ST_TX_LOW_DRIVE:
1022 case CEC_ST_RX_LOW_DRIVE:
1023 cec_pin_high(pin);
1024 cec_pin_to_idle(pin);
1025 break;
1026
1027 default:
1028 break;
1029 }
1030
1031 switch (pin->state) {
1032 case CEC_ST_TX_START_BIT_LOW_CUSTOM:
1033 case CEC_ST_TX_DATA_BIT_LOW_CUSTOM:
1034 case CEC_ST_TX_PULSE_LOW_CUSTOM:
1035 usecs = pin->tx_custom_low_usecs;
1036 break;
1037 case CEC_ST_TX_START_BIT_HIGH_CUSTOM:
1038 case CEC_ST_TX_DATA_BIT_HIGH_CUSTOM:
1039 case CEC_ST_TX_PULSE_HIGH_CUSTOM:
1040 usecs = pin->tx_custom_high_usecs;
1041 break;
1042 default:
1043 usecs = states[pin->state].usecs;
1044 break;
1045 }
1046
1047 if (!adap->monitor_pin_cnt || usecs <= 150) {
1048 pin->wait_usecs = 0;
1049 pin->timer_ts = ktime_add_us(ts, usecs);
1050 hrtimer_forward_now(timer, us_to_ktime(usecs));
1051 return HRTIMER_RESTART;
1052 }
1053 pin->wait_usecs = usecs - 100;
1054 pin->timer_ts = ktime_add_us(ts, 100);
1055 hrtimer_forward_now(timer, us_to_ktime(100));
1056 return HRTIMER_RESTART;
1057 }
1058
cec_pin_thread_func(void * _adap)1059 static int cec_pin_thread_func(void *_adap)
1060 {
1061 struct cec_adapter *adap = _adap;
1062 struct cec_pin *pin = adap->pin;
1063
1064 pin->enabled_irq = false;
1065 pin->enable_irq_failed = false;
1066 for (;;) {
1067 wait_event_interruptible(pin->kthread_waitq,
1068 kthread_should_stop() ||
1069 pin->work_rx_msg.len ||
1070 pin->work_tx_status ||
1071 atomic_read(&pin->work_irq_change) ||
1072 atomic_read(&pin->work_pin_num_events));
1073
1074 if (kthread_should_stop())
1075 break;
1076
1077 if (pin->work_rx_msg.len) {
1078 struct cec_msg *msg = &pin->work_rx_msg;
1079
1080 if (msg->len > 1 && msg->len < CEC_MAX_MSG_SIZE &&
1081 rx_add_byte(pin)) {
1082 /* Error injection: add byte to the message */
1083 msg->msg[msg->len++] = 0x55;
1084 }
1085 if (msg->len > 2 && rx_remove_byte(pin)) {
1086 /* Error injection: remove byte from message */
1087 msg->len--;
1088 }
1089 if (msg->len > CEC_MAX_MSG_SIZE)
1090 msg->len = CEC_MAX_MSG_SIZE;
1091 cec_received_msg_ts(adap, msg,
1092 ns_to_ktime(pin->work_rx_msg.rx_ts));
1093 msg->len = 0;
1094 }
1095
1096 if (pin->work_tx_status) {
1097 unsigned int tx_status = pin->work_tx_status;
1098
1099 pin->work_tx_status = 0;
1100 cec_transmit_attempt_done_ts(adap, tx_status,
1101 pin->work_tx_ts);
1102 }
1103
1104 while (atomic_read(&pin->work_pin_num_events)) {
1105 unsigned int idx = pin->work_pin_events_rd;
1106 u8 v = pin->work_pin_events[idx];
1107
1108 cec_queue_pin_cec_event(adap,
1109 v & CEC_PIN_EVENT_FL_IS_HIGH,
1110 v & CEC_PIN_EVENT_FL_DROPPED,
1111 pin->work_pin_ts[idx]);
1112 pin->work_pin_events_rd = (idx + 1) % CEC_NUM_PIN_EVENTS;
1113 atomic_dec(&pin->work_pin_num_events);
1114 }
1115
1116 switch (atomic_xchg(&pin->work_irq_change,
1117 CEC_PIN_IRQ_UNCHANGED)) {
1118 case CEC_PIN_IRQ_DISABLE:
1119 if (pin->enabled_irq) {
1120 pin->ops->disable_irq(adap);
1121 pin->enabled_irq = false;
1122 pin->enable_irq_failed = false;
1123 }
1124 cec_pin_high(pin);
1125 if (pin->state == CEC_ST_OFF)
1126 break;
1127 cec_pin_to_idle(pin);
1128 hrtimer_start(&pin->timer, ns_to_ktime(0),
1129 HRTIMER_MODE_REL);
1130 break;
1131 case CEC_PIN_IRQ_ENABLE:
1132 if (pin->enabled_irq || !pin->ops->enable_irq ||
1133 pin->adap->devnode.unregistered)
1134 break;
1135 pin->enable_irq_failed = !pin->ops->enable_irq(adap);
1136 if (pin->enable_irq_failed) {
1137 cec_pin_to_idle(pin);
1138 hrtimer_start(&pin->timer, ns_to_ktime(0),
1139 HRTIMER_MODE_REL);
1140 } else {
1141 pin->enabled_irq = true;
1142 }
1143 break;
1144 default:
1145 break;
1146 }
1147 }
1148
1149 if (pin->enabled_irq) {
1150 pin->ops->disable_irq(pin->adap);
1151 pin->enabled_irq = false;
1152 pin->enable_irq_failed = false;
1153 cec_pin_high(pin);
1154 }
1155 return 0;
1156 }
1157
cec_pin_adap_enable(struct cec_adapter * adap,bool enable)1158 static int cec_pin_adap_enable(struct cec_adapter *adap, bool enable)
1159 {
1160 struct cec_pin *pin = adap->pin;
1161
1162 if (enable) {
1163 cec_pin_read(pin);
1164 cec_pin_to_idle(pin);
1165 pin->tx_msg.len = 0;
1166 pin->timer_ts = ns_to_ktime(0);
1167 atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_UNCHANGED);
1168 if (!pin->kthread) {
1169 pin->kthread = kthread_run(cec_pin_thread_func, adap,
1170 "cec-pin");
1171 if (IS_ERR(pin->kthread)) {
1172 int err = PTR_ERR(pin->kthread);
1173
1174 pr_err("cec-pin: kernel_thread() failed\n");
1175 pin->kthread = NULL;
1176 return err;
1177 }
1178 }
1179 hrtimer_start(&pin->timer, ns_to_ktime(0),
1180 HRTIMER_MODE_REL);
1181 } else if (pin->kthread) {
1182 hrtimer_cancel(&pin->timer);
1183 cec_pin_high(pin);
1184 cec_pin_to_idle(pin);
1185 pin->state = CEC_ST_OFF;
1186 pin->work_tx_status = 0;
1187 atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_DISABLE);
1188 wake_up_interruptible(&pin->kthread_waitq);
1189 }
1190 return 0;
1191 }
1192
cec_pin_adap_log_addr(struct cec_adapter * adap,u8 log_addr)1193 static int cec_pin_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1194 {
1195 struct cec_pin *pin = adap->pin;
1196
1197 if (log_addr == CEC_LOG_ADDR_INVALID)
1198 pin->la_mask = 0;
1199 else
1200 pin->la_mask |= (1 << log_addr);
1201 return 0;
1202 }
1203
cec_pin_start_timer(struct cec_pin * pin)1204 void cec_pin_start_timer(struct cec_pin *pin)
1205 {
1206 if (pin->state != CEC_ST_RX_IRQ)
1207 return;
1208
1209 atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_DISABLE);
1210 wake_up_interruptible(&pin->kthread_waitq);
1211 }
1212
cec_pin_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)1213 static int cec_pin_adap_transmit(struct cec_adapter *adap, u8 attempts,
1214 u32 signal_free_time, struct cec_msg *msg)
1215 {
1216 struct cec_pin *pin = adap->pin;
1217
1218 /*
1219 * If a receive is in progress, then this transmit should use
1220 * a signal free time of max CEC_SIGNAL_FREE_TIME_NEW_INITIATOR
1221 * since when it starts transmitting it will have a new initiator.
1222 */
1223 if (pin->state != CEC_ST_IDLE &&
1224 signal_free_time > CEC_SIGNAL_FREE_TIME_NEW_INITIATOR)
1225 signal_free_time = CEC_SIGNAL_FREE_TIME_NEW_INITIATOR;
1226
1227 pin->tx_signal_free_time = signal_free_time;
1228 pin->tx_extra_bytes = 0;
1229 pin->tx_msg = *msg;
1230 if (msg->len > 1) {
1231 /* Error injection: add byte to the message */
1232 pin->tx_extra_bytes = tx_add_bytes(pin);
1233 }
1234 if (msg->len > 2 && tx_remove_byte(pin)) {
1235 /* Error injection: remove byte from the message */
1236 pin->tx_msg.len--;
1237 }
1238 pin->work_tx_status = 0;
1239 pin->tx_bit = 0;
1240 cec_pin_start_timer(pin);
1241 return 0;
1242 }
1243
cec_pin_adap_status(struct cec_adapter * adap,struct seq_file * file)1244 static void cec_pin_adap_status(struct cec_adapter *adap,
1245 struct seq_file *file)
1246 {
1247 struct cec_pin *pin = adap->pin;
1248
1249 seq_printf(file, "state: %s\n", states[pin->state].name);
1250 seq_printf(file, "tx_bit: %d\n", pin->tx_bit);
1251 seq_printf(file, "rx_bit: %d\n", pin->rx_bit);
1252 seq_printf(file, "cec pin: %d\n", call_pin_op(pin, read));
1253 seq_printf(file, "cec pin events dropped: %u\n",
1254 pin->work_pin_events_dropped_cnt);
1255 if (pin->ops->enable_irq)
1256 seq_printf(file, "irq %s\n", pin->enabled_irq ? "enabled" :
1257 (pin->enable_irq_failed ? "failed" : "disabled"));
1258 if (pin->timer_100us_overruns) {
1259 seq_printf(file, "timer overruns > 100us: %u of %u\n",
1260 pin->timer_100us_overruns, pin->timer_cnt);
1261 seq_printf(file, "timer overruns > 300us: %u of %u\n",
1262 pin->timer_300us_overruns, pin->timer_cnt);
1263 seq_printf(file, "max timer overrun: %u usecs\n",
1264 pin->timer_max_overrun);
1265 seq_printf(file, "avg timer overrun: %u usecs\n",
1266 pin->timer_sum_overrun / pin->timer_100us_overruns);
1267 }
1268 if (pin->rx_start_bit_low_too_short_cnt)
1269 seq_printf(file,
1270 "rx start bit low too short: %u (delta %u, ts %llu)\n",
1271 pin->rx_start_bit_low_too_short_cnt,
1272 pin->rx_start_bit_low_too_short_delta,
1273 pin->rx_start_bit_low_too_short_ts);
1274 if (pin->rx_start_bit_too_short_cnt)
1275 seq_printf(file,
1276 "rx start bit too short: %u (delta %u, ts %llu)\n",
1277 pin->rx_start_bit_too_short_cnt,
1278 pin->rx_start_bit_too_short_delta,
1279 pin->rx_start_bit_too_short_ts);
1280 if (pin->rx_start_bit_too_long_cnt)
1281 seq_printf(file, "rx start bit too long: %u\n",
1282 pin->rx_start_bit_too_long_cnt);
1283 if (pin->rx_data_bit_too_short_cnt)
1284 seq_printf(file,
1285 "rx data bit too short: %u (delta %u, ts %llu)\n",
1286 pin->rx_data_bit_too_short_cnt,
1287 pin->rx_data_bit_too_short_delta,
1288 pin->rx_data_bit_too_short_ts);
1289 if (pin->rx_data_bit_too_long_cnt)
1290 seq_printf(file, "rx data bit too long: %u\n",
1291 pin->rx_data_bit_too_long_cnt);
1292 seq_printf(file, "rx initiated low drive: %u\n", pin->rx_low_drive_cnt);
1293 seq_printf(file, "tx detected low drive: %u\n", pin->tx_low_drive_cnt);
1294 pin->work_pin_events_dropped_cnt = 0;
1295 pin->timer_cnt = 0;
1296 pin->timer_100us_overruns = 0;
1297 pin->timer_300us_overruns = 0;
1298 pin->timer_max_overrun = 0;
1299 pin->timer_sum_overrun = 0;
1300 pin->rx_start_bit_low_too_short_cnt = 0;
1301 pin->rx_start_bit_too_short_cnt = 0;
1302 pin->rx_start_bit_too_long_cnt = 0;
1303 pin->rx_data_bit_too_short_cnt = 0;
1304 pin->rx_data_bit_too_long_cnt = 0;
1305 pin->rx_low_drive_cnt = 0;
1306 pin->tx_low_drive_cnt = 0;
1307 call_void_pin_op(pin, status, file);
1308 }
1309
cec_pin_adap_monitor_all_enable(struct cec_adapter * adap,bool enable)1310 static int cec_pin_adap_monitor_all_enable(struct cec_adapter *adap,
1311 bool enable)
1312 {
1313 struct cec_pin *pin = adap->pin;
1314
1315 pin->monitor_all = enable;
1316 return 0;
1317 }
1318
cec_pin_adap_free(struct cec_adapter * adap)1319 static void cec_pin_adap_free(struct cec_adapter *adap)
1320 {
1321 struct cec_pin *pin = adap->pin;
1322
1323 if (pin->kthread)
1324 kthread_stop(pin->kthread);
1325 pin->kthread = NULL;
1326 if (pin->ops->free)
1327 pin->ops->free(adap);
1328 adap->pin = NULL;
1329 kfree(pin);
1330 }
1331
cec_pin_received(struct cec_adapter * adap,struct cec_msg * msg)1332 static int cec_pin_received(struct cec_adapter *adap, struct cec_msg *msg)
1333 {
1334 struct cec_pin *pin = adap->pin;
1335
1336 if (pin->ops->received && !adap->devnode.unregistered)
1337 return pin->ops->received(adap, msg);
1338 return -ENOMSG;
1339 }
1340
cec_pin_changed(struct cec_adapter * adap,bool value)1341 void cec_pin_changed(struct cec_adapter *adap, bool value)
1342 {
1343 struct cec_pin *pin = adap->pin;
1344
1345 cec_pin_update(pin, value, false);
1346 if (!value && (adap->is_configuring || adap->is_configured ||
1347 adap->monitor_all_cnt || !adap->monitor_pin_cnt))
1348 atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_DISABLE);
1349 }
1350 EXPORT_SYMBOL_GPL(cec_pin_changed);
1351
1352 static const struct cec_adap_ops cec_pin_adap_ops = {
1353 .adap_enable = cec_pin_adap_enable,
1354 .adap_monitor_all_enable = cec_pin_adap_monitor_all_enable,
1355 .adap_log_addr = cec_pin_adap_log_addr,
1356 .adap_transmit = cec_pin_adap_transmit,
1357 .adap_status = cec_pin_adap_status,
1358 .adap_free = cec_pin_adap_free,
1359 #ifdef CONFIG_CEC_PIN_ERROR_INJ
1360 .error_inj_parse_line = cec_pin_error_inj_parse_line,
1361 .error_inj_show = cec_pin_error_inj_show,
1362 #endif
1363 .received = cec_pin_received,
1364 };
1365
cec_pin_allocate_adapter(const struct cec_pin_ops * pin_ops,void * priv,const char * name,u32 caps)1366 struct cec_adapter *cec_pin_allocate_adapter(const struct cec_pin_ops *pin_ops,
1367 void *priv, const char *name, u32 caps)
1368 {
1369 struct cec_adapter *adap;
1370 struct cec_pin *pin = kzalloc_obj(*pin);
1371
1372 if (pin == NULL)
1373 return ERR_PTR(-ENOMEM);
1374 pin->ops = pin_ops;
1375 atomic_set(&pin->work_pin_num_events, 0);
1376 hrtimer_setup(&pin->timer, cec_pin_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1377 init_waitqueue_head(&pin->kthread_waitq);
1378 pin->tx_custom_low_usecs = CEC_TIM_CUSTOM_DEFAULT;
1379 pin->tx_custom_high_usecs = CEC_TIM_CUSTOM_DEFAULT;
1380 pin->tx_glitch_low_usecs = CEC_TIM_GLITCH_DEFAULT;
1381 pin->tx_glitch_high_usecs = CEC_TIM_GLITCH_DEFAULT;
1382
1383 adap = cec_allocate_adapter(&cec_pin_adap_ops, priv, name,
1384 caps | CEC_CAP_MONITOR_ALL | CEC_CAP_MONITOR_PIN,
1385 CEC_MAX_LOG_ADDRS);
1386
1387 if (IS_ERR(adap)) {
1388 kfree(pin);
1389 return adap;
1390 }
1391
1392 adap->pin = pin;
1393 pin->adap = adap;
1394 cec_pin_update(pin, cec_pin_high(pin), true);
1395 return adap;
1396 }
1397 EXPORT_SYMBOL_GPL(cec_pin_allocate_adapter);
1398