1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2016 Freescale Semiconductor, Inc.
4 // Copyright 2025 NXP
5
6 #include <linux/bitfield.h>
7 #include <linux/clk.h>
8 #include <linux/err.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/sizes.h>
15 #include <linux/thermal.h>
16 #include <linux/units.h>
17
18 #include "thermal_hwmon.h"
19
20 #define SITES_MAX 16
21 #define TMR_DISABLE 0x0
22 #define TMR_ME 0x80000000
23 #define TMR_CMD BIT(29)
24 #define TMR_ALPF 0x0c000000
25 #define TMR_ALPF_V2 0x03000000
26 #define TMTMIR_DEFAULT 0x0000000f
27 #define TIER_DISABLE 0x0
28 #define TEUMR0_V2 0x51009c00
29 #define TEUMR0_V21 0x55000c00
30 #define TMSARA_V2 0xe
31 #define TMU_VER1 0x1
32 #define TMU_VER2 0x2
33
34 /* errata ID info define */
35 #define TMU_ERR052243 BIT(0)
36
37 #define REGS_TMR 0x000 /* Mode Register */
38 #define TMR_DISABLE 0x0
39 #define TMR_ME 0x80000000
40 #define TMR_ALPF 0x0c000000
41
42 #define REGS_TMTMIR 0x008 /* Temperature measurement interval Register */
43 #define TMTMIR_DEFAULT 0x0000000f
44
45 #define REGS_V2_TMSR 0x008 /* monitor site register */
46
47 #define REGS_V2_TMTMIR 0x00c /* Temperature measurement interval Register */
48
49 #define REGS_TIER 0x020 /* Interrupt Enable Register */
50 #define TIER_DISABLE 0x0
51
52 #define REGS_TIDR 0x24
53 #define TEMP_RATE_IRQ_MASK GENMASK(25, 24)
54 #define TMRTRCTR 0x70
55 #define TMRTRCTR_EN BIT(31)
56 #define TMRTRCTR_TEMP_MASK GENMASK(7, 0)
57 #define TMFTRCTR 0x74
58 #define TMFTRCTR_EN BIT(31)
59 #define TMFTRCTR_TEMP_MASK GENMASK(7, 0)
60 #define TEMP_RATE_THR_LVL 0x7
61
62 #define REGS_TTCFGR 0x080 /* Temperature Configuration Register */
63 #define REGS_TSCFGR 0x084 /* Sensor Configuration Register */
64
65 #define REGS_TRITSR(n) (0x100 + 16 * (n)) /* Immediate Temperature
66 * Site Register
67 */
68 #define TRITSR_V BIT(31)
69 #define TRITSR_TP5 BIT(9)
70 #define REGS_V2_TMSAR(n) (0x304 + 16 * (n)) /* TMU monitoring
71 * site adjustment register
72 */
73 #define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n
74 * Control Register
75 */
76 #define NUM_TTRCR_V1 4
77 #define NUM_TTRCR_MAX 16
78
79 #define REGS_IPBRR(n) (0xbf8 + 4 * (n)) /* IP Block Revision
80 * Register n
81 */
82 #define REGS_V2_TEUMR(n) (0xf00 + 4 * (n))
83
84 /*
85 * Thermal zone data
86 */
87 struct qoriq_sensor {
88 int id;
89 };
90
91 struct tmu_drvdata {
92 u32 teumr0;
93 u32 tmu_errata;
94 };
95
96 struct qoriq_tmu_data {
97 int ver;
98 u32 ttrcr[NUM_TTRCR_MAX];
99 struct regmap *regmap;
100 struct clk *clk;
101 struct qoriq_sensor sensor[SITES_MAX];
102 const struct tmu_drvdata *drvdata;
103 };
104
qoriq_tmu_has_errata(const struct tmu_drvdata * drvdata,u32 flag)105 static inline bool qoriq_tmu_has_errata(const struct tmu_drvdata *drvdata,
106 u32 flag)
107 {
108 return drvdata->tmu_errata & flag;
109 }
110
qoriq_sensor_to_data(struct qoriq_sensor * s)111 static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s)
112 {
113 return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
114 }
115
tmu_get_temp(struct thermal_zone_device * tz,int * temp)116 static int tmu_get_temp(struct thermal_zone_device *tz, int *temp)
117 {
118 struct qoriq_sensor *qsensor = thermal_zone_device_priv(tz);
119 struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
120 u32 val, tidr;
121 /*
122 * REGS_TRITSR(id) has the following layout:
123 *
124 * For TMU Rev1:
125 * 31 ... 7 6 5 4 3 2 1 0
126 * V TEMP
127 *
128 * Where V bit signifies if the measurement is ready and is
129 * within sensor range. TEMP is an 8 bit value representing
130 * temperature in Celsius.
131
132 * For TMU Rev2:
133 * 31 ... 8 7 6 5 4 3 2 1 0
134 * V TEMP
135 *
136 * Where V bit signifies if the measurement is ready and is
137 * within sensor range. TEMP is an 9 bit value representing
138 * temperature in KelVin.
139 */
140
141 regmap_read(qdata->regmap, REGS_TMR, &val);
142 if (!(val & TMR_ME))
143 return -EAGAIN;
144
145 if (regmap_read_poll_timeout(qdata->regmap,
146 REGS_TRITSR(qsensor->id),
147 val,
148 val & TRITSR_V,
149 USEC_PER_MSEC,
150 10 * USEC_PER_MSEC))
151 return -ENODATA;
152
153 /*ERR052243: If a raising or falling edge happens, try later */
154 if (qoriq_tmu_has_errata(qdata->drvdata, TMU_ERR052243)) {
155 regmap_read(qdata->regmap, REGS_TIDR, &tidr);
156 if (tidr & TEMP_RATE_IRQ_MASK) {
157 regmap_write(qdata->regmap, REGS_TIDR, TEMP_RATE_IRQ_MASK);
158 return -EAGAIN;
159 }
160 }
161
162 if (qdata->ver == TMU_VER1) {
163 *temp = (val & GENMASK(7, 0)) * MILLIDEGREE_PER_DEGREE;
164 } else {
165 if (val & TRITSR_TP5)
166 *temp = milli_kelvin_to_millicelsius((val & GENMASK(8, 0)) *
167 MILLIDEGREE_PER_DEGREE + 500);
168 else
169 *temp = kelvin_to_millicelsius(val & GENMASK(8, 0));
170 }
171
172 return 0;
173 }
174
175 static const struct thermal_zone_device_ops tmu_tz_ops = {
176 .get_temp = tmu_get_temp,
177 };
178
qoriq_tmu_register_tmu_zone(struct device * dev,struct qoriq_tmu_data * qdata)179 static int qoriq_tmu_register_tmu_zone(struct device *dev,
180 struct qoriq_tmu_data *qdata)
181 {
182 int id, sites = 0;
183
184 for (id = 0; id < SITES_MAX; id++) {
185 struct thermal_zone_device *tzd;
186 struct qoriq_sensor *sensor = &qdata->sensor[id];
187 int ret;
188
189 sensor->id = id;
190
191 tzd = devm_thermal_of_zone_register(dev, id,
192 sensor,
193 &tmu_tz_ops);
194 ret = PTR_ERR_OR_ZERO(tzd);
195 if (ret) {
196 if (ret == -ENODEV)
197 continue;
198
199 return ret;
200 }
201
202 if (qdata->ver == TMU_VER1)
203 sites |= 0x1 << (15 - id);
204 else
205 sites |= 0x1 << id;
206
207 devm_thermal_add_hwmon_sysfs(dev, tzd);
208 }
209
210 if (sites) {
211 if (qdata->ver == TMU_VER1) {
212 regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF | sites);
213 } else {
214 regmap_write(qdata->regmap, REGS_V2_TMSR, sites);
215 regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF_V2);
216 }
217 }
218
219 return 0;
220 }
221
qoriq_tmu_calibration(struct device * dev,struct qoriq_tmu_data * data)222 static int qoriq_tmu_calibration(struct device *dev,
223 struct qoriq_tmu_data *data)
224 {
225 int i, val, len;
226 const u32 *calibration;
227 struct device_node *np = dev->of_node;
228
229 len = of_property_count_u32_elems(np, "fsl,tmu-range");
230 if (len < 0 || (data->ver == TMU_VER1 && len > NUM_TTRCR_V1) ||
231 (data->ver > TMU_VER1 && len > NUM_TTRCR_MAX)) {
232 dev_err(dev, "invalid range data.\n");
233 return len;
234 }
235
236 val = of_property_read_u32_array(np, "fsl,tmu-range", data->ttrcr, len);
237 if (val != 0) {
238 dev_err(dev, "failed to read range data.\n");
239 return val;
240 }
241
242 /* Init temperature range registers */
243 for (i = 0; i < len; i++)
244 regmap_write(data->regmap, REGS_TTRnCR(i), data->ttrcr[i]);
245
246 calibration = of_get_property(np, "fsl,tmu-calibration", &len);
247 if (calibration == NULL || len % 8) {
248 dev_err(dev, "invalid calibration data.\n");
249 return -ENODEV;
250 }
251
252 for (i = 0; i < len; i += 8, calibration += 2) {
253 val = of_read_number(calibration, 1);
254 regmap_write(data->regmap, REGS_TTCFGR, val);
255 val = of_read_number(calibration + 1, 1);
256 regmap_write(data->regmap, REGS_TSCFGR, val);
257 }
258
259 return 0;
260 }
261
qoriq_tmu_init_device(struct qoriq_tmu_data * data)262 static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
263 {
264 /* Disable interrupt, using polling instead */
265 regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
266
267 /* Set update_interval */
268
269 if (data->ver == TMU_VER1) {
270 regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
271 } else {
272 regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
273 regmap_write(data->regmap, REGS_V2_TEUMR(0),
274 data->drvdata->teumr0);
275 }
276
277 /* ERR052243: Set the raising & falling edge monitor */
278 if (qoriq_tmu_has_errata(data->drvdata, TMU_ERR052243)) {
279 regmap_write(data->regmap, TMRTRCTR, TMRTRCTR_EN |
280 FIELD_PREP(TMRTRCTR_TEMP_MASK, TEMP_RATE_THR_LVL));
281 regmap_write(data->regmap, TMFTRCTR, TMFTRCTR_EN |
282 FIELD_PREP(TMFTRCTR_TEMP_MASK, TEMP_RATE_THR_LVL));
283
284 }
285 /* Disable monitoring */
286 regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
287 }
288
289 static const struct regmap_range qoriq_yes_ranges[] = {
290 regmap_reg_range(REGS_TMR, REGS_TSCFGR),
291 regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(15)),
292 regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
293 regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)),
294 regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
295 /* Read only registers below */
296 regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
297 };
298
299 static const struct regmap_access_table qoriq_wr_table = {
300 .yes_ranges = qoriq_yes_ranges,
301 .n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges) - 1,
302 };
303
304 static const struct regmap_access_table qoriq_rd_table = {
305 .yes_ranges = qoriq_yes_ranges,
306 .n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges),
307 };
308
qoriq_tmu_action(void * p)309 static void qoriq_tmu_action(void *p)
310 {
311 struct qoriq_tmu_data *data = p;
312
313 regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
314 }
315
qoriq_tmu_probe(struct platform_device * pdev)316 static int qoriq_tmu_probe(struct platform_device *pdev)
317 {
318 int ret;
319 u32 ver;
320 struct qoriq_tmu_data *data;
321 struct device_node *np = pdev->dev.of_node;
322 struct device *dev = &pdev->dev;
323 const bool little_endian = of_property_read_bool(np, "little-endian");
324 const enum regmap_endian format_endian =
325 little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
326 const struct regmap_config regmap_config = {
327 .reg_bits = 32,
328 .val_bits = 32,
329 .reg_stride = 4,
330 .rd_table = &qoriq_rd_table,
331 .wr_table = &qoriq_wr_table,
332 .val_format_endian = format_endian,
333 .max_register = SZ_4K,
334 };
335 void __iomem *base;
336
337 data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
338 GFP_KERNEL);
339 if (!data)
340 return -ENOMEM;
341
342 base = devm_platform_ioremap_resource(pdev, 0);
343 ret = PTR_ERR_OR_ZERO(base);
344 if (ret)
345 return dev_err_probe(dev, ret, "Failed to get memory region\n");
346
347 data->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
348 ret = PTR_ERR_OR_ZERO(data->regmap);
349 if (ret)
350 return dev_err_probe(dev, ret, "Failed to init regmap\n");
351
352 data->clk = devm_clk_get_optional_enabled(dev, NULL);
353 if (IS_ERR(data->clk))
354 return PTR_ERR(data->clk);
355
356 ret = devm_add_action_or_reset(dev, qoriq_tmu_action, data);
357 if (ret)
358 return ret;
359
360 /* version register offset at: 0xbf8 on both v1 and v2 */
361 ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
362 if (ret)
363 return dev_err_probe(dev, ret, "Failed to read IP block version\n");
364
365 data->ver = (ver >> 8) & 0xff;
366
367 data->drvdata = of_device_get_match_data(&pdev->dev);
368 if (!data->drvdata)
369 return dev_err_probe(dev, -EINVAL, "Failed to get match data\n");
370
371 qoriq_tmu_init_device(data); /* TMU initialization */
372
373 ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */
374 if (ret < 0)
375 return ret;
376
377 ret = qoriq_tmu_register_tmu_zone(dev, data);
378 if (ret < 0)
379 return dev_err_probe(dev, ret, "Failed to register sensors\n");
380
381 platform_set_drvdata(pdev, data);
382
383 return 0;
384 }
385
qoriq_tmu_suspend(struct device * dev)386 static int qoriq_tmu_suspend(struct device *dev)
387 {
388 struct qoriq_tmu_data *data = dev_get_drvdata(dev);
389 int ret;
390
391 ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
392 if (ret)
393 return ret;
394
395 if (data->ver > TMU_VER1) {
396 ret = regmap_set_bits(data->regmap, REGS_TMR, TMR_CMD);
397 if (ret)
398 return ret;
399 }
400
401 clk_disable_unprepare(data->clk);
402
403 return 0;
404 }
405
qoriq_tmu_resume(struct device * dev)406 static int qoriq_tmu_resume(struct device *dev)
407 {
408 int ret;
409 struct qoriq_tmu_data *data = dev_get_drvdata(dev);
410
411 ret = clk_prepare_enable(data->clk);
412 if (ret)
413 return ret;
414
415 if (data->ver > TMU_VER1) {
416 ret = regmap_clear_bits(data->regmap, REGS_TMR, TMR_CMD);
417 if (ret)
418 goto disable_clk;
419 }
420
421 /* Enable monitoring */
422 ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
423 if (ret)
424 goto disable_clk;
425
426 return 0;
427
428 disable_clk:
429 clk_disable_unprepare(data->clk);
430
431 return ret;
432 }
433
434 static DEFINE_SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
435 qoriq_tmu_suspend, qoriq_tmu_resume);
436
437 static const struct tmu_drvdata qoriq_tmu_data = {
438 .teumr0 = TEUMR0_V2,
439 };
440
441 static const struct tmu_drvdata imx8mq_tmu_data = {
442 .teumr0 = TEUMR0_V2,
443 };
444
445 static const struct tmu_drvdata imx93_data = {
446 .teumr0 = TEUMR0_V21,
447 .tmu_errata = TMU_ERR052243,
448 };
449
450 static const struct of_device_id qoriq_tmu_match[] = {
451 { .compatible = "fsl,qoriq-tmu", .data = &qoriq_tmu_data },
452 { .compatible = "fsl,imx8mq-tmu", .data = &imx8mq_tmu_data },
453 { .compatible = "fsl,imx93-tmu", .data = &imx93_data },
454 {},
455 };
456 MODULE_DEVICE_TABLE(of, qoriq_tmu_match);
457
458 static struct platform_driver qoriq_tmu = {
459 .driver = {
460 .name = "qoriq_thermal",
461 .pm = pm_sleep_ptr(&qoriq_tmu_pm_ops),
462 .of_match_table = qoriq_tmu_match,
463 },
464 .probe = qoriq_tmu_probe,
465 };
466 module_platform_driver(qoriq_tmu);
467
468 MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
469 MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
470 MODULE_LICENSE("GPL v2");
471