1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 interrupt-parent = <&gic>; 16 17 audio_extal_clk: audio-clk { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by the board */ 21 clock-frequency = <0>; 22 }; 23 24 /* 25 * The default cluster table is based on the assumption that the PLLCA55 clock 26 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 27 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 28 * clocked to 1.8GHz as well). The table below should be overridden in the board 29 * DTS based on the PLLCA55 clock frequency. 30 */ 31 cluster0_opp: opp-table-0 { 32 compatible = "operating-points-v2"; 33 34 opp-1700000000 { 35 opp-hz = /bits/ 64 <1700000000>; 36 opp-microvolt = <900000>; 37 clock-latency-ns = <300000>; 38 }; 39 opp-850000000 { 40 opp-hz = /bits/ 64 <850000000>; 41 opp-microvolt = <800000>; 42 clock-latency-ns = <300000>; 43 }; 44 opp-425000000 { 45 opp-hz = /bits/ 64 <425000000>; 46 opp-microvolt = <800000>; 47 clock-latency-ns = <300000>; 48 }; 49 opp-212500000 { 50 opp-hz = /bits/ 64 <212500000>; 51 opp-microvolt = <800000>; 52 clock-latency-ns = <300000>; 53 opp-suspend; 54 }; 55 }; 56 57 cpus { 58 #address-cells = <1>; 59 #size-cells = <0>; 60 61 cpu0: cpu@0 { 62 compatible = "arm,cortex-a55"; 63 reg = <0>; 64 device_type = "cpu"; 65 next-level-cache = <&L3_CA55>; 66 enable-method = "psci"; 67 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; 68 #cooling-cells = <2>; 69 operating-points-v2 = <&cluster0_opp>; 70 }; 71 72 cpu1: cpu@100 { 73 compatible = "arm,cortex-a55"; 74 reg = <0x100>; 75 device_type = "cpu"; 76 next-level-cache = <&L3_CA55>; 77 enable-method = "psci"; 78 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; 79 #cooling-cells = <2>; 80 operating-points-v2 = <&cluster0_opp>; 81 }; 82 83 cpu2: cpu@200 { 84 compatible = "arm,cortex-a55"; 85 reg = <0x200>; 86 device_type = "cpu"; 87 next-level-cache = <&L3_CA55>; 88 enable-method = "psci"; 89 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; 90 #cooling-cells = <2>; 91 operating-points-v2 = <&cluster0_opp>; 92 }; 93 94 cpu3: cpu@300 { 95 compatible = "arm,cortex-a55"; 96 reg = <0x300>; 97 device_type = "cpu"; 98 next-level-cache = <&L3_CA55>; 99 enable-method = "psci"; 100 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; 101 #cooling-cells = <2>; 102 operating-points-v2 = <&cluster0_opp>; 103 }; 104 105 L3_CA55: cache-controller-0 { 106 compatible = "cache"; 107 cache-unified; 108 cache-size = <0x100000>; 109 cache-level = <3>; 110 }; 111 }; 112 113 gpu_opp_table: opp-table-1 { 114 compatible = "operating-points-v2"; 115 116 opp-630000000 { 117 opp-hz = /bits/ 64 <630000000>; 118 opp-microvolt = <800000>; 119 }; 120 121 opp-315000000 { 122 opp-hz = /bits/ 64 <315000000>; 123 opp-microvolt = <800000>; 124 }; 125 126 opp-157500000 { 127 opp-hz = /bits/ 64 <157500000>; 128 opp-microvolt = <800000>; 129 }; 130 131 opp-78750000 { 132 opp-hz = /bits/ 64 <78750000>; 133 opp-microvolt = <800000>; 134 }; 135 136 opp-19687500 { 137 opp-hz = /bits/ 64 <19687500>; 138 opp-microvolt = <800000>; 139 }; 140 }; 141 142 pmu { 143 compatible = "arm,cortex-a55-pmu"; 144 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 145 }; 146 147 psci { 148 compatible = "arm,psci-1.0", "arm,psci-0.2"; 149 method = "smc"; 150 }; 151 152 qextal_clk: qextal-clk { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 /* This value must be overridden by the board */ 156 clock-frequency = <0>; 157 }; 158 159 rtxin_clk: rtxin-clk { 160 compatible = "fixed-clock"; 161 #clock-cells = <0>; 162 /* This value must be overridden by the board */ 163 clock-frequency = <0>; 164 }; 165 166 soc: soc { 167 compatible = "simple-bus"; 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 icu: interrupt-controller@10400000 { 173 compatible = "renesas,r9a09g057-icu"; 174 reg = <0 0x10400000 0 0x10000>; 175 #interrupt-cells = <2>; 176 #address-cells = <0>; 177 interrupt-controller; 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 228 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 229 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 230 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 231 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 236 interrupt-names = "nmi", 237 "port_irq0", "port_irq1", "port_irq2", 238 "port_irq3", "port_irq4", "port_irq5", 239 "port_irq6", "port_irq7", "port_irq8", 240 "port_irq9", "port_irq10", "port_irq11", 241 "port_irq12", "port_irq13", "port_irq14", 242 "port_irq15", 243 "tint0", "tint1", "tint2", "tint3", 244 "tint4", "tint5", "tint6", "tint7", 245 "tint8", "tint9", "tint10", "tint11", 246 "tint12", "tint13", "tint14", "tint15", 247 "tint16", "tint17", "tint18", "tint19", 248 "tint20", "tint21", "tint22", "tint23", 249 "tint24", "tint25", "tint26", "tint27", 250 "tint28", "tint29", "tint30", "tint31", 251 "int-ca55-0", "int-ca55-1", 252 "int-ca55-2", "int-ca55-3", 253 "icu-error-ca55", 254 "gpt-u0-gtciada", "gpt-u0-gtciadb", 255 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 256 clocks = <&cpg CPG_MOD 0x5>; 257 power-domains = <&cpg>; 258 resets = <&cpg 0x36>; 259 }; 260 261 pinctrl: pinctrl@10410000 { 262 compatible = "renesas,r9a09g057-pinctrl"; 263 reg = <0 0x10410000 0 0x10000>; 264 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 265 gpio-controller; 266 #gpio-cells = <2>; 267 gpio-ranges = <&pinctrl 0 0 96>; 268 #interrupt-cells = <2>; 269 interrupt-controller; 270 interrupt-parent = <&icu>; 271 power-domains = <&cpg>; 272 resets = <&cpg 0xa5>, <&cpg 0xa6>; 273 }; 274 275 cpg: clock-controller@10420000 { 276 compatible = "renesas,r9a09g057-cpg"; 277 reg = <0 0x10420000 0 0x10000>; 278 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 279 clock-names = "audio_extal", "rtxin", "qextal"; 280 #clock-cells = <2>; 281 #reset-cells = <1>; 282 #power-domain-cells = <0>; 283 }; 284 285 sys: system-controller@10430000 { 286 compatible = "renesas,r9a09g057-sys"; 287 reg = <0 0x10430000 0 0x10000>; 288 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 289 resets = <&cpg 0x30>; 290 }; 291 292 tsu0: thermal@11000000 { 293 compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; 294 reg = <0 0x11000000 0 0x1000>; 295 interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 297 interrupt-names = "adi", "adcmpi"; 298 clocks = <&cpg CPG_MOD 0x109>; 299 resets = <&cpg 0xf7>; 300 power-domains = <&cpg>; 301 #thermal-sensor-cells = <0>; 302 renesas,tsu-trim = <&sys 0x320>; 303 }; 304 305 tsu1: thermal@14002000 { 306 compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; 307 reg = <0 0x14002000 0 0x1000>; 308 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 310 interrupt-names = "adi", "adcmpi"; 311 clocks = <&cpg CPG_MOD 0x10a>; 312 resets = <&cpg 0xf8>; 313 power-domains = <&cpg>; 314 #thermal-sensor-cells = <0>; 315 renesas,tsu-trim = <&sys 0x330>; 316 }; 317 318 xspi: spi@11030000 { 319 compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi"; 320 reg = <0 0x11030000 0 0x10000>, 321 <0 0x20000000 0 0x10000000>; 322 reg-names = "regs", "dirmap"; 323 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 325 interrupt-names = "pulse", "err_pulse"; 326 clocks = <&cpg CPG_MOD 0x9f>, 327 <&cpg CPG_MOD 0xa0>, 328 <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>, 329 <&cpg CPG_MOD 0xa1>; 330 clock-names = "ahb", "axi", "spi", "spix2"; 331 resets = <&cpg 0xa3>, <&cpg 0xa4>; 332 reset-names = "hresetn", "aresetn"; 333 power-domains = <&cpg>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 status = "disabled"; 337 }; 338 339 dmac0: dma-controller@11400000 { 340 compatible = "renesas,r9a09g057-dmac"; 341 reg = <0 0x11400000 0 0x10000>; 342 interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, 343 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 344 <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, 345 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, 346 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, 347 <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, 348 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, 349 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, 351 <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, 352 <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, 353 <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, 354 <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 355 <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, 356 <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, 357 <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, 358 <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; 359 interrupt-names = "error", 360 "ch0", "ch1", "ch2", "ch3", 361 "ch4", "ch5", "ch6", "ch7", 362 "ch8", "ch9", "ch10", "ch11", 363 "ch12", "ch13", "ch14", "ch15"; 364 clocks = <&cpg CPG_MOD 0x0>; 365 power-domains = <&cpg>; 366 resets = <&cpg 0x31>; 367 #dma-cells = <1>; 368 dma-channels = <16>; 369 renesas,icu = <&icu 4>; 370 }; 371 372 dmac1: dma-controller@14830000 { 373 compatible = "renesas,r9a09g057-dmac"; 374 reg = <0 0x14830000 0 0x10000>; 375 interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, 376 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 379 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 380 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 381 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 384 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 385 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 387 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 390 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 391 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; 392 interrupt-names = "error", 393 "ch0", "ch1", "ch2", "ch3", 394 "ch4", "ch5", "ch6", "ch7", 395 "ch8", "ch9", "ch10", "ch11", 396 "ch12", "ch13", "ch14", "ch15"; 397 clocks = <&cpg CPG_MOD 0x1>; 398 power-domains = <&cpg>; 399 resets = <&cpg 0x32>; 400 #dma-cells = <1>; 401 dma-channels = <16>; 402 renesas,icu = <&icu 0>; 403 }; 404 405 dmac2: dma-controller@14840000 { 406 compatible = "renesas,r9a09g057-dmac"; 407 reg = <0 0x14840000 0 0x10000>; 408 interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, 409 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 410 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 411 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 412 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 413 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 414 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 415 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 416 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 417 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 418 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 423 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 424 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 425 interrupt-names = "error", 426 "ch0", "ch1", "ch2", "ch3", 427 "ch4", "ch5", "ch6", "ch7", 428 "ch8", "ch9", "ch10", "ch11", 429 "ch12", "ch13", "ch14", "ch15"; 430 clocks = <&cpg CPG_MOD 0x2>; 431 power-domains = <&cpg>; 432 resets = <&cpg 0x33>; 433 #dma-cells = <1>; 434 dma-channels = <16>; 435 renesas,icu = <&icu 1>; 436 }; 437 438 dmac3: dma-controller@12000000 { 439 compatible = "renesas,r9a09g057-dmac"; 440 reg = <0 0x12000000 0 0x10000>; 441 interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, 442 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 443 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 444 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 445 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 446 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 447 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 456 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 457 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 458 interrupt-names = "error", 459 "ch0", "ch1", "ch2", "ch3", 460 "ch4", "ch5", "ch6", "ch7", 461 "ch8", "ch9", "ch10", "ch11", 462 "ch12", "ch13", "ch14", "ch15"; 463 clocks = <&cpg CPG_MOD 0x3>; 464 power-domains = <&cpg>; 465 resets = <&cpg 0x34>; 466 #dma-cells = <1>; 467 dma-channels = <16>; 468 renesas,icu = <&icu 2>; 469 }; 470 471 dmac4: dma-controller@12010000 { 472 compatible = "renesas,r9a09g057-dmac"; 473 reg = <0 0x12010000 0 0x10000>; 474 interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, 475 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 476 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 477 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 478 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 479 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 480 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 481 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 482 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 483 <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, 484 <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, 485 <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, 486 <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, 487 <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 488 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 489 <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, 490 <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 491 interrupt-names = "error", 492 "ch0", "ch1", "ch2", "ch3", 493 "ch4", "ch5", "ch6", "ch7", 494 "ch8", "ch9", "ch10", "ch11", 495 "ch12", "ch13", "ch14", "ch15"; 496 clocks = <&cpg CPG_MOD 0x4>; 497 power-domains = <&cpg>; 498 resets = <&cpg 0x35>; 499 #dma-cells = <1>; 500 dma-channels = <16>; 501 renesas,icu = <&icu 3>; 502 }; 503 504 ostm0: timer@11800000 { 505 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 506 reg = <0x0 0x11800000 0x0 0x1000>; 507 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 508 clocks = <&cpg CPG_MOD 0x43>; 509 resets = <&cpg 0x6d>; 510 power-domains = <&cpg>; 511 status = "disabled"; 512 }; 513 514 ostm1: timer@11801000 { 515 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 516 reg = <0x0 0x11801000 0x0 0x1000>; 517 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 518 clocks = <&cpg CPG_MOD 0x44>; 519 resets = <&cpg 0x6e>; 520 power-domains = <&cpg>; 521 status = "disabled"; 522 }; 523 524 ostm2: timer@14000000 { 525 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 526 reg = <0x0 0x14000000 0x0 0x1000>; 527 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 528 clocks = <&cpg CPG_MOD 0x45>; 529 resets = <&cpg 0x6f>; 530 power-domains = <&cpg>; 531 status = "disabled"; 532 }; 533 534 ostm3: timer@14001000 { 535 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 536 reg = <0x0 0x14001000 0x0 0x1000>; 537 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 538 clocks = <&cpg CPG_MOD 0x46>; 539 resets = <&cpg 0x70>; 540 power-domains = <&cpg>; 541 status = "disabled"; 542 }; 543 544 ostm4: timer@12c00000 { 545 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 546 reg = <0x0 0x12c00000 0x0 0x1000>; 547 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 548 clocks = <&cpg CPG_MOD 0x47>; 549 resets = <&cpg 0x71>; 550 power-domains = <&cpg>; 551 status = "disabled"; 552 }; 553 554 ostm5: timer@12c01000 { 555 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 556 reg = <0x0 0x12c01000 0x0 0x1000>; 557 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 558 clocks = <&cpg CPG_MOD 0x48>; 559 resets = <&cpg 0x72>; 560 power-domains = <&cpg>; 561 status = "disabled"; 562 }; 563 564 ostm6: timer@12c02000 { 565 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 566 reg = <0x0 0x12c02000 0x0 0x1000>; 567 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 568 clocks = <&cpg CPG_MOD 0x49>; 569 resets = <&cpg 0x73>; 570 power-domains = <&cpg>; 571 status = "disabled"; 572 }; 573 574 ostm7: timer@12c03000 { 575 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 576 reg = <0x0 0x12c03000 0x0 0x1000>; 577 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 578 clocks = <&cpg CPG_MOD 0x4a>; 579 resets = <&cpg 0x74>; 580 power-domains = <&cpg>; 581 status = "disabled"; 582 }; 583 584 wdt0: watchdog@11c00400 { 585 compatible = "renesas,r9a09g057-wdt"; 586 reg = <0 0x11c00400 0 0x400>; 587 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; 588 clock-names = "pclk", "oscclk"; 589 resets = <&cpg 0x75>; 590 power-domains = <&cpg>; 591 status = "disabled"; 592 }; 593 594 wdt1: watchdog@14400000 { 595 compatible = "renesas,r9a09g057-wdt"; 596 reg = <0 0x14400000 0 0x400>; 597 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 598 clock-names = "pclk", "oscclk"; 599 resets = <&cpg 0x76>; 600 power-domains = <&cpg>; 601 status = "disabled"; 602 }; 603 604 wdt2: watchdog@13000000 { 605 compatible = "renesas,r9a09g057-wdt"; 606 reg = <0 0x13000000 0 0x400>; 607 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 608 clock-names = "pclk", "oscclk"; 609 resets = <&cpg 0x77>; 610 power-domains = <&cpg>; 611 status = "disabled"; 612 }; 613 614 wdt3: watchdog@13000400 { 615 compatible = "renesas,r9a09g057-wdt"; 616 reg = <0 0x13000400 0 0x400>; 617 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 618 clock-names = "pclk", "oscclk"; 619 resets = <&cpg 0x78>; 620 power-domains = <&cpg>; 621 status = "disabled"; 622 }; 623 624 rtc: rtc@11c00800 { 625 compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3"; 626 reg = <0 0x11c00800 0 0x400>; 627 interrupts = <GIC_SPI 524 IRQ_TYPE_EDGE_RISING>, 628 <GIC_SPI 525 IRQ_TYPE_EDGE_RISING>, 629 <GIC_SPI 526 IRQ_TYPE_EDGE_RISING>; 630 interrupt-names = "alarm", "period", "carry"; 631 clocks = <&cpg CPG_MOD 0x53>, <&rtxin_clk>; 632 clock-names = "bus", "counter"; 633 power-domains = <&cpg>; 634 resets = <&cpg 0x79>, <&cpg 0x7a>; 635 reset-names = "rtc", "rtest"; 636 status = "disabled"; 637 }; 638 639 scif: serial@11c01400 { 640 compatible = "renesas,scif-r9a09g057"; 641 reg = <0 0x11c01400 0 0x400>; 642 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 650 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 651 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 652 "tei", "tei-dri", "rxi-edge", "txi-edge"; 653 clocks = <&cpg CPG_MOD 0x8f>; 654 clock-names = "fck"; 655 power-domains = <&cpg>; 656 resets = <&cpg 0x95>; 657 status = "disabled"; 658 }; 659 660 i3c: i3c@12400000 { 661 compatible = "renesas,r9a09g057-i3c", "renesas,r9a09g047-i3c"; 662 reg = <0 0x12400000 0 0x10000>; 663 clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>; 664 clock-names = "pclk", "tclk", "pclkrw"; 665 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, 669 <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, 670 <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, 671 <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, 672 <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, 673 <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, 674 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 681 interrupt-names = "ierr", "terr", "abort", "resp", 682 "cmd", "ibi", "rx", "tx", "rcv", 683 "st", "sp", "tend", "nack", 684 "al", "tmo", "wu"; 685 resets = <&cpg 0x96>, <&cpg 0x97>; 686 reset-names = "presetn", "tresetn"; 687 power-domains = <&cpg>; 688 #address-cells = <3>; 689 #size-cells = <0>; 690 status = "disabled"; 691 }; 692 693 rspi0: spi@12800000 { 694 compatible = "renesas,r9a09g057-rspi"; 695 reg = <0x0 0x12800000 0x0 0x400>; 696 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>, 699 <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, 700 <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>; 701 interrupt-names = "idle", "error", "end", "rx", "tx"; 702 clocks = <&cpg CPG_MOD 0x54>, 703 <&cpg CPG_MOD 0x55>, 704 <&cpg CPG_MOD 0x56>; 705 clock-names = "pclk", "pclk_sfr", "tclk"; 706 resets = <&cpg 0x7b>, <&cpg 0x7c>; 707 reset-names = "presetn", "tresetn"; 708 power-domains = <&cpg>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 status = "disabled"; 712 }; 713 714 rspi1: spi@12800400 { 715 compatible = "renesas,r9a09g057-rspi"; 716 reg = <0x0 0x12800400 0x0 0x400>; 717 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>, 720 <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>, 721 <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>; 722 interrupt-names = "idle", "error", "end", "rx", "tx"; 723 clocks = <&cpg CPG_MOD 0x57>, 724 <&cpg CPG_MOD 0x58>, 725 <&cpg CPG_MOD 0x59>; 726 clock-names = "pclk", "pclk_sfr", "tclk"; 727 resets = <&cpg 0x7d>, <&cpg 0x7e>; 728 reset-names = "presetn", "tresetn"; 729 power-domains = <&cpg>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 status = "disabled"; 733 }; 734 735 rspi2: spi@12800800 { 736 compatible = "renesas,r9a09g057-rspi"; 737 reg = <0x0 0x12800800 0x0 0x400>; 738 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 741 <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>, 742 <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>; 743 interrupt-names = "idle", "error", "end", "rx", "tx"; 744 clocks = <&cpg CPG_MOD 0x5a>, 745 <&cpg CPG_MOD 0x5b>, 746 <&cpg CPG_MOD 0x5c>; 747 clock-names = "pclk", "pclk_sfr", "tclk"; 748 resets = <&cpg 0x7f>, <&cpg 0x80>; 749 reset-names = "presetn", "tresetn"; 750 power-domains = <&cpg>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 status = "disabled"; 754 }; 755 756 i2c0: i2c@14400400 { 757 compatible = "renesas,riic-r9a09g057"; 758 reg = <0 0x14400400 0 0x400>; 759 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 761 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 762 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 767 interrupt-names = "tei", "ri", "ti", "spi", "sti", 768 "naki", "ali", "tmoi"; 769 clocks = <&cpg CPG_MOD 0x94>; 770 resets = <&cpg 0x98>; 771 power-domains = <&cpg>; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "disabled"; 775 }; 776 777 i2c1: i2c@14400800 { 778 compatible = "renesas,riic-r9a09g057"; 779 reg = <0 0x14400800 0 0x400>; 780 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 782 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 783 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 788 interrupt-names = "tei", "ri", "ti", "spi", "sti", 789 "naki", "ali", "tmoi"; 790 clocks = <&cpg CPG_MOD 0x95>; 791 resets = <&cpg 0x99>; 792 power-domains = <&cpg>; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 status = "disabled"; 796 }; 797 798 i2c2: i2c@14400c00 { 799 compatible = "renesas,riic-r9a09g057"; 800 reg = <0 0x14400c00 0 0x400>; 801 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 803 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 804 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 809 interrupt-names = "tei", "ri", "ti", "spi", "sti", 810 "naki", "ali", "tmoi"; 811 clocks = <&cpg CPG_MOD 0x96>; 812 resets = <&cpg 0x9a>; 813 power-domains = <&cpg>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 status = "disabled"; 817 }; 818 819 i2c3: i2c@14401000 { 820 compatible = "renesas,riic-r9a09g057"; 821 reg = <0 0x14401000 0 0x400>; 822 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 824 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 825 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 830 interrupt-names = "tei", "ri", "ti", "spi", "sti", 831 "naki", "ali", "tmoi"; 832 clocks = <&cpg CPG_MOD 0x97>; 833 resets = <&cpg 0x9b>; 834 power-domains = <&cpg>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 status = "disabled"; 838 }; 839 840 i2c4: i2c@14401400 { 841 compatible = "renesas,riic-r9a09g057"; 842 reg = <0 0x14401400 0 0x400>; 843 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 845 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 846 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 851 interrupt-names = "tei", "ri", "ti", "spi", "sti", 852 "naki", "ali", "tmoi"; 853 clocks = <&cpg CPG_MOD 0x98>; 854 resets = <&cpg 0x9c>; 855 power-domains = <&cpg>; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 status = "disabled"; 859 }; 860 861 i2c5: i2c@14401800 { 862 compatible = "renesas,riic-r9a09g057"; 863 reg = <0 0x14401800 0 0x400>; 864 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 866 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 867 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 872 interrupt-names = "tei", "ri", "ti", "spi", "sti", 873 "naki", "ali", "tmoi"; 874 clocks = <&cpg CPG_MOD 0x99>; 875 resets = <&cpg 0x9d>; 876 power-domains = <&cpg>; 877 #address-cells = <1>; 878 #size-cells = <0>; 879 status = "disabled"; 880 }; 881 882 i2c6: i2c@14401c00 { 883 compatible = "renesas,riic-r9a09g057"; 884 reg = <0 0x14401c00 0 0x400>; 885 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 887 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 888 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 893 interrupt-names = "tei", "ri", "ti", "spi", "sti", 894 "naki", "ali", "tmoi"; 895 clocks = <&cpg CPG_MOD 0x9a>; 896 resets = <&cpg 0x9e>; 897 power-domains = <&cpg>; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 status = "disabled"; 901 }; 902 903 i2c7: i2c@14402000 { 904 compatible = "renesas,riic-r9a09g057"; 905 reg = <0 0x14402000 0 0x400>; 906 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 908 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 909 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 914 interrupt-names = "tei", "ri", "ti", "spi", "sti", 915 "naki", "ali", "tmoi"; 916 clocks = <&cpg CPG_MOD 0x9b>; 917 resets = <&cpg 0x9f>; 918 power-domains = <&cpg>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 status = "disabled"; 922 }; 923 924 i2c8: i2c@11c01000 { 925 compatible = "renesas,riic-r9a09g057"; 926 reg = <0 0x11c01000 0 0x400>; 927 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 929 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 930 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 935 interrupt-names = "tei", "ri", "ti", "spi", "sti", 936 "naki", "ali", "tmoi"; 937 clocks = <&cpg CPG_MOD 0x93>; 938 resets = <&cpg 0xa0>; 939 power-domains = <&cpg>; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 status = "disabled"; 943 }; 944 945 gpu: gpu@14850000 { 946 compatible = "renesas,r9a09g057-mali", 947 "arm,mali-bifrost"; 948 reg = <0x0 0x14850000 0x0 0x10000>; 949 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-names = "job", "mmu", "gpu", "event"; 954 clocks = <&cpg CPG_MOD 0xf0>, 955 <&cpg CPG_MOD 0xf1>, 956 <&cpg CPG_MOD 0xf2>; 957 clock-names = "gpu", "bus", "bus_ace"; 958 power-domains = <&cpg>; 959 resets = <&cpg 0xdd>, 960 <&cpg 0xde>, 961 <&cpg 0xdf>; 962 reset-names = "rst", "axi_rst", "ace_rst"; 963 operating-points-v2 = <&gpu_opp_table>; 964 status = "disabled"; 965 }; 966 967 gic: interrupt-controller@14900000 { 968 compatible = "arm,gic-v3"; 969 reg = <0x0 0x14900000 0 0x20000>, 970 <0x0 0x14940000 0 0x80000>; 971 #interrupt-cells = <3>; 972 #address-cells = <0>; 973 interrupt-controller; 974 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 975 }; 976 977 ohci0: usb@15800000 { 978 compatible = "generic-ohci"; 979 reg = <0 0x15800000 0 0x100>; 980 interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 982 resets = <&usb20phyrst>, <&cpg 0xac>; 983 phys = <&usb2_phy0 1>; 984 phy-names = "usb"; 985 power-domains = <&cpg>; 986 status = "disabled"; 987 }; 988 989 ohci1: usb@15810000 { 990 compatible = "generic-ohci"; 991 reg = <0 0x15810000 0 0x100>; 992 interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 994 resets = <&usb21phyrst>, <&cpg 0xad>; 995 phys = <&usb2_phy1 1>; 996 phy-names = "usb"; 997 power-domains = <&cpg>; 998 status = "disabled"; 999 }; 1000 1001 ehci0: usb@15800100 { 1002 compatible = "generic-ehci"; 1003 reg = <0 0x15800100 0 0x100>; 1004 interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 1006 resets = <&usb20phyrst>, <&cpg 0xac>; 1007 phys = <&usb2_phy0 2>; 1008 phy-names = "usb"; 1009 companion = <&ohci0>; 1010 power-domains = <&cpg>; 1011 status = "disabled"; 1012 }; 1013 1014 ehci1: usb@15810100 { 1015 compatible = "generic-ehci"; 1016 reg = <0 0x15810100 0 0x100>; 1017 interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 1019 resets = <&usb21phyrst>, <&cpg 0xad>; 1020 phys = <&usb2_phy1 2>; 1021 phy-names = "usb"; 1022 companion = <&ohci1>; 1023 power-domains = <&cpg>; 1024 status = "disabled"; 1025 }; 1026 1027 usb2_phy0: usb-phy@15800200 { 1028 compatible = "renesas,usb2-phy-r9a09g057"; 1029 reg = <0 0x15800200 0 0x700>; 1030 interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&cpg CPG_MOD 0xb3>, 1032 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE0>; 1033 clock-names = "fck", "usb_x1"; 1034 resets = <&usb20phyrst>; 1035 #phy-cells = <1>; 1036 power-domains = <&cpg>; 1037 status = "disabled"; 1038 }; 1039 1040 usb2_phy1: usb-phy@15810200 { 1041 compatible = "renesas,usb2-phy-r9a09g057"; 1042 reg = <0 0x15810200 0 0x700>; 1043 interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&cpg CPG_MOD 0xb4>, 1045 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE1>; 1046 clock-names = "fck", "usb_x1"; 1047 resets = <&usb21phyrst>; 1048 #phy-cells = <1>; 1049 power-domains = <&cpg>; 1050 status = "disabled"; 1051 }; 1052 1053 hsusb: usb@15820000 { 1054 compatible = "renesas,usbhs-r9a09g057", 1055 "renesas,rzg2l-usbhs"; 1056 reg = <0 0x15820000 0 0x10000>; 1057 interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>, 1058 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>; 1062 resets = <&usb20phyrst>, 1063 <&cpg 0xae>; 1064 phys = <&usb2_phy0 3>; 1065 phy-names = "usb"; 1066 power-domains = <&cpg>; 1067 status = "disabled"; 1068 }; 1069 1070 usb20phyrst: usb20phy-reset@15830000 { 1071 compatible = "renesas,r9a09g057-usb2phy-reset"; 1072 reg = <0 0x15830000 0 0x10000>; 1073 clocks = <&cpg CPG_MOD 0xb6>; 1074 resets = <&cpg 0xaf>; 1075 power-domains = <&cpg>; 1076 #reset-cells = <0>; 1077 status = "disabled"; 1078 }; 1079 1080 usb21phyrst: usb21phy-reset@15840000 { 1081 compatible = "renesas,r9a09g057-usb2phy-reset"; 1082 reg = <0 0x15840000 0 0x10000>; 1083 clocks = <&cpg CPG_MOD 0xb7>; 1084 resets = <&cpg 0xaf>; 1085 power-domains = <&cpg>; 1086 #reset-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 sdhi0: mmc@15c00000 { 1091 compatible = "renesas,sdhi-r9a09g057"; 1092 reg = <0x0 0x15c00000 0 0x10000>; 1093 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 1096 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 1097 clock-names = "core", "clkh", "cd", "aclk"; 1098 resets = <&cpg 0xa7>; 1099 power-domains = <&cpg>; 1100 status = "disabled"; 1101 1102 sdhi0_vqmmc: vqmmc-regulator { 1103 regulator-name = "SDHI0-VQMMC"; 1104 regulator-min-microvolt = <1800000>; 1105 regulator-max-microvolt = <3300000>; 1106 status = "disabled"; 1107 }; 1108 }; 1109 1110 sdhi1: mmc@15c10000 { 1111 compatible = "renesas,sdhi-r9a09g057"; 1112 reg = <0x0 0x15c10000 0 0x10000>; 1113 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 1116 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 1117 clock-names = "core", "clkh", "cd", "aclk"; 1118 resets = <&cpg 0xa8>; 1119 power-domains = <&cpg>; 1120 status = "disabled"; 1121 1122 sdhi1_vqmmc: vqmmc-regulator { 1123 regulator-name = "SDHI1-VQMMC"; 1124 regulator-min-microvolt = <1800000>; 1125 regulator-max-microvolt = <3300000>; 1126 status = "disabled"; 1127 }; 1128 }; 1129 1130 sdhi2: mmc@15c20000 { 1131 compatible = "renesas,sdhi-r9a09g057"; 1132 reg = <0x0 0x15c20000 0 0x10000>; 1133 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 1136 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 1137 clock-names = "core", "clkh", "cd", "aclk"; 1138 resets = <&cpg 0xa9>; 1139 power-domains = <&cpg>; 1140 status = "disabled"; 1141 1142 sdhi2_vqmmc: vqmmc-regulator { 1143 regulator-name = "SDHI2-VQMMC"; 1144 regulator-min-microvolt = <1800000>; 1145 regulator-max-microvolt = <3300000>; 1146 status = "disabled"; 1147 }; 1148 }; 1149 1150 eth0: ethernet@15c30000 { 1151 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1152 "snps,dwmac-5.20"; 1153 reg = <0 0x15c30000 0 0x10000>; 1154 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 1165 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1166 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1167 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1168 "tx-queue-2", "tx-queue-3"; 1169 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 1170 <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, 1171 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 1172 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 1173 clock-names = "stmmaceth", "pclk", "ptp_ref", 1174 "tx", "rx", "tx-180", "rx-180"; 1175 resets = <&cpg 0xb0>; 1176 power-domains = <&cpg>; 1177 snps,multicast-filter-bins = <256>; 1178 snps,perfect-filter-entries = <128>; 1179 rx-fifo-depth = <8192>; 1180 tx-fifo-depth = <8192>; 1181 snps,fixed-burst; 1182 snps,no-pbl-x8; 1183 snps,force_thresh_dma_mode; 1184 snps,axi-config = <&stmmac_axi_setup>; 1185 snps,mtl-rx-config = <&mtl_rx_setup0>; 1186 snps,mtl-tx-config = <&mtl_tx_setup0>; 1187 snps,txpbl = <32>; 1188 snps,rxpbl = <32>; 1189 status = "disabled"; 1190 1191 mdio0: mdio { 1192 compatible = "snps,dwmac-mdio"; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 }; 1196 1197 mtl_rx_setup0: rx-queues-config { 1198 snps,rx-queues-to-use = <4>; 1199 snps,rx-sched-sp; 1200 1201 queue0 { 1202 snps,dcb-algorithm; 1203 snps,priority = <0x1>; 1204 snps,map-to-dma-channel = <0>; 1205 }; 1206 1207 queue1 { 1208 snps,dcb-algorithm; 1209 snps,priority = <0x2>; 1210 snps,map-to-dma-channel = <1>; 1211 }; 1212 1213 queue2 { 1214 snps,dcb-algorithm; 1215 snps,priority = <0x4>; 1216 snps,map-to-dma-channel = <2>; 1217 }; 1218 1219 queue3 { 1220 snps,dcb-algorithm; 1221 snps,priority = <0x8>; 1222 snps,map-to-dma-channel = <3>; 1223 }; 1224 }; 1225 1226 mtl_tx_setup0: tx-queues-config { 1227 snps,tx-queues-to-use = <4>; 1228 1229 queue0 { 1230 snps,dcb-algorithm; 1231 snps,priority = <0x1>; 1232 }; 1233 1234 queue1 { 1235 snps,dcb-algorithm; 1236 snps,priority = <0x2>; 1237 }; 1238 1239 queue2 { 1240 snps,dcb-algorithm; 1241 snps,priority = <0x4>; 1242 }; 1243 1244 queue3 { 1245 snps,dcb-algorithm; 1246 snps,priority = <0x8>; 1247 }; 1248 }; 1249 }; 1250 1251 eth1: ethernet@15c40000 { 1252 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1253 "snps,dwmac-5.20"; 1254 reg = <0 0x15c40000 0 0x10000>; 1255 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 1266 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1267 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1268 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1269 "tx-queue-2", "tx-queue-3"; 1270 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 1271 <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, 1272 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 1273 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 1274 clock-names = "stmmaceth", "pclk", "ptp_ref", 1275 "tx", "rx", "tx-180", "rx-180"; 1276 resets = <&cpg 0xb1>; 1277 power-domains = <&cpg>; 1278 snps,multicast-filter-bins = <256>; 1279 snps,perfect-filter-entries = <128>; 1280 rx-fifo-depth = <8192>; 1281 tx-fifo-depth = <8192>; 1282 snps,fixed-burst; 1283 snps,no-pbl-x8; 1284 snps,force_thresh_dma_mode; 1285 snps,axi-config = <&stmmac_axi_setup>; 1286 snps,mtl-rx-config = <&mtl_rx_setup1>; 1287 snps,mtl-tx-config = <&mtl_tx_setup1>; 1288 snps,txpbl = <32>; 1289 snps,rxpbl = <32>; 1290 status = "disabled"; 1291 1292 mdio1: mdio { 1293 compatible = "snps,dwmac-mdio"; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 }; 1297 1298 mtl_rx_setup1: rx-queues-config { 1299 snps,rx-queues-to-use = <4>; 1300 snps,rx-sched-sp; 1301 1302 queue0 { 1303 snps,dcb-algorithm; 1304 snps,priority = <0x1>; 1305 snps,map-to-dma-channel = <0>; 1306 }; 1307 1308 queue1 { 1309 snps,dcb-algorithm; 1310 snps,priority = <0x2>; 1311 snps,map-to-dma-channel = <1>; 1312 }; 1313 1314 queue2 { 1315 snps,dcb-algorithm; 1316 snps,priority = <0x4>; 1317 snps,map-to-dma-channel = <2>; 1318 }; 1319 1320 queue3 { 1321 snps,dcb-algorithm; 1322 snps,priority = <0x8>; 1323 snps,map-to-dma-channel = <3>; 1324 }; 1325 }; 1326 1327 mtl_tx_setup1: tx-queues-config { 1328 snps,tx-queues-to-use = <4>; 1329 1330 queue0 { 1331 snps,dcb-algorithm; 1332 snps,priority = <0x1>; 1333 }; 1334 1335 queue1 { 1336 snps,dcb-algorithm; 1337 snps,priority = <0x2>; 1338 }; 1339 1340 queue2 { 1341 snps,dcb-algorithm; 1342 snps,priority = <0x4>; 1343 }; 1344 1345 queue3 { 1346 snps,dcb-algorithm; 1347 snps,priority = <0x8>; 1348 }; 1349 }; 1350 }; 1351 }; 1352 1353 stmmac_axi_setup: stmmac-axi-config { 1354 snps,lpi_en; 1355 snps,wr_osr_lmt = <0xf>; 1356 snps,rd_osr_lmt = <0xf>; 1357 snps,blen = <16 8 4 0 0 0 0>; 1358 }; 1359 1360 thermal-zones { 1361 sensor1_thermal: sensor1-thermal { 1362 polling-delay = <1000>; 1363 polling-delay-passive = <250>; 1364 thermal-sensors = <&tsu0>; 1365 1366 trips { 1367 sensor1_crit: sensor1-crit { 1368 temperature = <120000>; 1369 hysteresis = <1000>; 1370 type = "critical"; 1371 }; 1372 }; 1373 }; 1374 1375 sensor2_thermal: sensor2-thermal { 1376 polling-delay = <1000>; 1377 polling-delay-passive = <250>; 1378 thermal-sensors = <&tsu1>; 1379 1380 cooling-maps { 1381 map0 { 1382 trip = <&sensor2_target>; 1383 cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, 1384 <&cpu2 0 3>, <&cpu3 0 3>; 1385 contribution = <1024>; 1386 }; 1387 }; 1388 1389 trips { 1390 sensor2_target: trip-point { 1391 temperature = <95000>; 1392 hysteresis = <1000>; 1393 type = "passive"; 1394 }; 1395 1396 sensor2_crit: sensor2-crit { 1397 temperature = <120000>; 1398 hysteresis = <1000>; 1399 type = "critical"; 1400 }; 1401 }; 1402 }; 1403 }; 1404 1405 timer { 1406 compatible = "arm,armv8-timer"; 1407 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1408 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1409 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1410 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1411 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1412 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 1413 }; 1414}; 1415