1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/V2H(P) ICU Driver
4 *
5 * Based on irq-renesas-rzg2l.c
6 *
7 * Copyright (C) 2024 Renesas Electronics Corporation.
8 *
9 * Author: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/cleanup.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/irqchip.h>
18 #include <linux/irqchip/irq-renesas-rzv2h.h>
19 #include <linux/irqdomain.h>
20 #include <linux/of_platform.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
23 #include <linux/spinlock.h>
24 #include <linux/syscore_ops.h>
25
26 /* DT "interrupts" indexes */
27 #define ICU_IRQ_START 1
28 #define ICU_IRQ_COUNT 16
29 #define ICU_IRQ_LAST (ICU_IRQ_START + ICU_IRQ_COUNT - 1)
30 #define ICU_TINT_START (ICU_IRQ_LAST + 1)
31 #define ICU_TINT_COUNT 32
32 #define ICU_TINT_LAST (ICU_TINT_START + ICU_TINT_COUNT - 1)
33 #define ICU_CA55_INT_START (ICU_TINT_LAST + 1)
34 #define ICU_CA55_INT_COUNT 4
35 #define ICU_CA55_INT_LAST (ICU_CA55_INT_START + ICU_CA55_INT_COUNT - 1)
36 #define ICU_ERR_INT_START (ICU_CA55_INT_LAST + 1)
37 #define ICU_ERR_INT_COUNT 1
38 #define ICU_ERR_INT_LAST (ICU_ERR_INT_START + ICU_ERR_INT_COUNT - 1)
39 #define ICU_NUM_IRQ (ICU_ERR_INT_LAST + 1)
40
41 /* Registers */
42 #define ICU_NSCNT 0x00
43 #define ICU_NSCLR 0x04
44 #define ICU_NITSR 0x08
45 #define ICU_ISCTR 0x10
46 #define ICU_ISCLR 0x14
47 #define ICU_IITSR 0x18
48 #define ICU_TSCTR 0x20
49 #define ICU_TSCLR 0x24
50 #define ICU_TITSR(k) (0x28 + (k) * 4)
51 #define ICU_TSSR(k) (0x30 + (k) * 4)
52 #define ICU_BEISR(k) (0x70 + (k) * 4)
53 #define ICU_BECLR(k) (0x80 + (k) * 4)
54 #define ICU_EREISR(k) (0x90 + (k) * 4)
55 #define ICU_ERCLR(k) (0xE0 + (k) * 4)
56 #define ICU_SWINT 0x130
57 #define ICU_ERINTA55CTL(k) (0x338 + (k) * 4)
58 #define ICU_ERINTA55CRL(k) (0x348 + (k) * 4)
59 #define ICU_ERINTA55MSK(k) (0x358 + (k) * 4)
60 #define ICU_SWPE 0x370
61 #define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4)
62 #define ICU_DMACKSELk(k) (0x500 + (k) * 4)
63
64 /* NMI */
65 #define ICU_NMI_EDGE_FALLING 0
66 #define ICU_NMI_EDGE_RISING 1
67
68 #define ICU_NSCLR_NCLR BIT(0)
69
70 /* IRQ */
71 #define ICU_IRQ_LEVEL_LOW 0
72 #define ICU_IRQ_EDGE_FALLING 1
73 #define ICU_IRQ_EDGE_RISING 2
74 #define ICU_IRQ_EDGE_BOTH 3
75
76 #define ICU_IITSR_IITSEL_PREP(iitsel, n) ((iitsel) << ((n) * 2))
77 #define ICU_IITSR_IITSEL_GET(iitsr, n) (((iitsr) >> ((n) * 2)) & 0x03)
78 #define ICU_IITSR_IITSEL_MASK(n) ICU_IITSR_IITSEL_PREP(0x03, n)
79
80 /* TINT */
81 #define ICU_TINT_EDGE_RISING 0
82 #define ICU_TINT_EDGE_FALLING 1
83 #define ICU_TINT_LEVEL_HIGH 2
84 #define ICU_TINT_LEVEL_LOW 3
85
86 #define ICU_TSSR_TSSEL_PREP(tssel, n, field_width) ((tssel) << ((n) * (field_width)))
87 #define ICU_TSSR_TSSEL_MASK(n, field_width) \
88 ({\
89 typeof(field_width) (_field_width) = (field_width); \
90 ICU_TSSR_TSSEL_PREP((GENMASK(((_field_width) - 2), 0)), (n), _field_width); \
91 })
92
93 #define ICU_TSSR_TIEN(n, field_width) \
94 ({\
95 typeof(field_width) (_field_width) = (field_width); \
96 BIT((_field_width) - 1) << ((n) * (_field_width)); \
97 })
98
99 #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16)
100 #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16)
101 #define ICU_TITSR_TITSEL_PREP(titsel, n) ICU_IITSR_IITSEL_PREP(titsel, n)
102 #define ICU_TITSR_TITSEL_MASK(n) ICU_IITSR_IITSEL_MASK(n)
103 #define ICU_TITSR_TITSEL_GET(titsr, n) ICU_IITSR_IITSEL_GET(titsr, n)
104
105 #define ICU_TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
106 #define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
107 #define ICU_RZG3E_TINT_OFFSET 0x800
108 #define ICU_RZG3E_TSSEL_MAX_VAL 0x8c
109 #define ICU_RZV2H_TSSEL_MAX_VAL 0x55
110
111 #define ICU_SWPE_NUM 16
112 #define ICU_NUM_BE 4
113 #define ICU_NUM_A55ERR 4
114
115 /**
116 * struct rzv2h_irqc_reg_cache - registers cache (necessary for suspend/resume)
117 * @nitsr: ICU_NITSR register
118 * @iitsr: ICU_IITSR register
119 * @titsr: ICU_TITSR registers
120 */
121 struct rzv2h_irqc_reg_cache {
122 u32 nitsr;
123 u32 iitsr;
124 u32 titsr[2];
125 };
126
127 /**
128 * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
129 * @tssel_lut: TINT lookup table
130 * @t_offs: TINT offset
131 * @max_tssel: TSSEL max value
132 * @field_width: TSSR field width
133 * @ecc_start: Start index of ECC RAM interrupts
134 * @ecc_end: End index of ECC RAM interrupts
135 */
136 struct rzv2h_hw_info {
137 const u8 *tssel_lut;
138 u16 t_offs;
139 u8 max_tssel;
140 u8 field_width;
141 u8 ecc_start;
142 u8 ecc_end;
143 };
144
145 /* DMAC */
146 #define ICU_DMAC_DkRQ_SEL_MASK GENMASK(9, 0)
147
148 #define ICU_DMAC_DMAREQ_SHIFT(up) ((up) * 16)
149 #define ICU_DMAC_DMAREQ_MASK(up) (ICU_DMAC_DkRQ_SEL_MASK \
150 << ICU_DMAC_DMAREQ_SHIFT(up))
151 #define ICU_DMAC_PREP_DMAREQ(sel, up) (FIELD_PREP(ICU_DMAC_DkRQ_SEL_MASK, (sel)) \
152 << ICU_DMAC_DMAREQ_SHIFT(up))
153
154 /**
155 * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
156 * @base: Controller's base address
157 * @fwspec: IRQ firmware specific data
158 * @lock: Lock to serialize access to hardware registers
159 * @info: Pointer to struct rzv2h_hw_info
160 * @cache: Registers cache for suspend/resume
161 */
162 static struct rzv2h_icu_priv {
163 void __iomem *base;
164 struct irq_fwspec fwspec[ICU_NUM_IRQ];
165 raw_spinlock_t lock;
166 const struct rzv2h_hw_info *info;
167 struct rzv2h_irqc_reg_cache cache;
168 } *rzv2h_icu_data;
169
rzv2h_icu_register_dma_req(struct platform_device * icu_dev,u8 dmac_index,u8 dmac_channel,u16 req_no)170 void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index, u8 dmac_channel,
171 u16 req_no)
172 {
173 struct rzv2h_icu_priv *priv = platform_get_drvdata(icu_dev);
174 u32 icu_dmksely, dmareq, dmareq_mask;
175 u8 y, upper;
176
177 y = dmac_channel / 2;
178 upper = dmac_channel % 2;
179
180 dmareq = ICU_DMAC_PREP_DMAREQ(req_no, upper);
181 dmareq_mask = ICU_DMAC_DMAREQ_MASK(upper);
182
183 guard(raw_spinlock_irqsave)(&priv->lock);
184
185 icu_dmksely = readl(priv->base + ICU_DMkSELy(dmac_index, y));
186 icu_dmksely = (icu_dmksely & ~dmareq_mask) | dmareq;
187 writel(icu_dmksely, priv->base + ICU_DMkSELy(dmac_index, y));
188 }
189 EXPORT_SYMBOL_GPL(rzv2h_icu_register_dma_req);
190
irq_data_to_priv(struct irq_data * data)191 static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *data)
192 {
193 return data->domain->host_data;
194 }
195
rzv2h_icu_tint_eoi(struct irq_data * d)196 static void rzv2h_icu_tint_eoi(struct irq_data *d)
197 {
198 struct rzv2h_icu_priv *priv = irq_data_to_priv(d);
199 unsigned int hw_irq = irqd_to_hwirq(d);
200 unsigned int tintirq_nr;
201 u32 bit;
202
203 if (!irqd_is_level_type(d)) {
204 tintirq_nr = hw_irq - ICU_TINT_START;
205 bit = BIT(tintirq_nr);
206 writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
207 }
208
209 irq_chip_eoi_parent(d);
210 }
211
rzv2h_icu_irq_eoi(struct irq_data * d)212 static void rzv2h_icu_irq_eoi(struct irq_data *d)
213 {
214 struct rzv2h_icu_priv *priv = irq_data_to_priv(d);
215 unsigned int hw_irq = irqd_to_hwirq(d);
216 unsigned int tintirq_nr;
217 u32 bit;
218
219 if (!irqd_is_level_type(d)) {
220 tintirq_nr = hw_irq - ICU_IRQ_START;
221 bit = BIT(tintirq_nr);
222 writel_relaxed(bit, priv->base + ICU_ISCLR);
223 }
224
225 irq_chip_eoi_parent(d);
226 }
227
rzv2h_icu_nmi_eoi(struct irq_data * d)228 static void rzv2h_icu_nmi_eoi(struct irq_data *d)
229 {
230 struct rzv2h_icu_priv *priv = irq_data_to_priv(d);
231
232 writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR);
233
234 irq_chip_eoi_parent(d);
235 }
236
rzv2h_tint_irq_endisable(struct irq_data * d,bool enable)237 static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
238 {
239 struct rzv2h_icu_priv *priv = irq_data_to_priv(d);
240 unsigned int hw_irq = irqd_to_hwirq(d);
241 u32 tint_nr, tssel_n, k, tssr;
242 u8 nr_tint;
243
244 tint_nr = hw_irq - ICU_TINT_START;
245 nr_tint = 32 / priv->info->field_width;
246 k = tint_nr / nr_tint;
247 tssel_n = tint_nr % nr_tint;
248
249 guard(raw_spinlock)(&priv->lock);
250 tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
251 if (enable)
252 tssr |= ICU_TSSR_TIEN(tssel_n, priv->info->field_width);
253 else
254 tssr &= ~ICU_TSSR_TIEN(tssel_n, priv->info->field_width);
255 writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
256
257 /*
258 * A glitch in the edge detection circuit can cause a spurious
259 * interrupt. Clear the status flag after setting the ICU_TSSRk
260 * registers, which is recommended by the hardware manual as a
261 * countermeasure.
262 */
263 writel_relaxed(BIT(tint_nr), priv->base + priv->info->t_offs + ICU_TSCLR);
264 }
265
rzv2h_icu_tint_disable(struct irq_data * d)266 static void rzv2h_icu_tint_disable(struct irq_data *d)
267 {
268 irq_chip_disable_parent(d);
269 rzv2h_tint_irq_endisable(d, false);
270 }
271
rzv2h_icu_tint_enable(struct irq_data * d)272 static void rzv2h_icu_tint_enable(struct irq_data *d)
273 {
274 rzv2h_tint_irq_endisable(d, true);
275 irq_chip_enable_parent(d);
276 }
277
rzv2h_nmi_set_type(struct irq_data * d,unsigned int type)278 static int rzv2h_nmi_set_type(struct irq_data *d, unsigned int type)
279 {
280 struct rzv2h_icu_priv *priv = irq_data_to_priv(d);
281 u32 sense;
282
283 switch (type & IRQ_TYPE_SENSE_MASK) {
284 case IRQ_TYPE_EDGE_FALLING:
285 sense = ICU_NMI_EDGE_FALLING;
286 break;
287
288 case IRQ_TYPE_EDGE_RISING:
289 sense = ICU_NMI_EDGE_RISING;
290 break;
291
292 default:
293 return -EINVAL;
294 }
295
296 writel_relaxed(sense, priv->base + ICU_NITSR);
297
298 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
299 }
300
rzv2h_clear_irq_int(struct rzv2h_icu_priv * priv,unsigned int hwirq)301 static void rzv2h_clear_irq_int(struct rzv2h_icu_priv *priv, unsigned int hwirq)
302 {
303 unsigned int irq_nr = hwirq - ICU_IRQ_START;
304 u32 isctr, iitsr, iitsel;
305 u32 bit = BIT(irq_nr);
306
307 isctr = readl_relaxed(priv->base + ICU_ISCTR);
308 iitsr = readl_relaxed(priv->base + ICU_IITSR);
309 iitsel = ICU_IITSR_IITSEL_GET(iitsr, irq_nr);
310
311 /*
312 * When level sensing is used, the interrupt flag gets automatically cleared when the
313 * interrupt signal is de-asserted by the source of the interrupt request, therefore clear
314 * the interrupt only for edge triggered interrupts.
315 */
316 if ((isctr & bit) && (iitsel != ICU_IRQ_LEVEL_LOW))
317 writel_relaxed(bit, priv->base + ICU_ISCLR);
318 }
319
rzv2h_irq_set_type(struct irq_data * d,unsigned int type)320 static int rzv2h_irq_set_type(struct irq_data *d, unsigned int type)
321 {
322 struct rzv2h_icu_priv *priv = irq_data_to_priv(d);
323 unsigned int hwirq = irqd_to_hwirq(d);
324 u32 irq_nr = hwirq - ICU_IRQ_START;
325 u32 iitsr, sense;
326
327 switch (type & IRQ_TYPE_SENSE_MASK) {
328 case IRQ_TYPE_LEVEL_LOW:
329 sense = ICU_IRQ_LEVEL_LOW;
330 break;
331
332 case IRQ_TYPE_EDGE_FALLING:
333 sense = ICU_IRQ_EDGE_FALLING;
334 break;
335
336 case IRQ_TYPE_EDGE_RISING:
337 sense = ICU_IRQ_EDGE_RISING;
338 break;
339
340 case IRQ_TYPE_EDGE_BOTH:
341 sense = ICU_IRQ_EDGE_BOTH;
342 break;
343
344 default:
345 return -EINVAL;
346 }
347
348 scoped_guard(raw_spinlock, &priv->lock) {
349 iitsr = readl_relaxed(priv->base + ICU_IITSR);
350 iitsr &= ~ICU_IITSR_IITSEL_MASK(irq_nr);
351 iitsr |= ICU_IITSR_IITSEL_PREP(sense, irq_nr);
352 rzv2h_clear_irq_int(priv, hwirq);
353 writel_relaxed(iitsr, priv->base + ICU_IITSR);
354 }
355
356 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
357 }
358
rzv2h_clear_tint_int(struct rzv2h_icu_priv * priv,unsigned int hwirq)359 static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq)
360 {
361 unsigned int tint_nr = hwirq - ICU_TINT_START;
362 int titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
363 u32 tsctr, titsr, titsel;
364 u32 bit = BIT(tint_nr);
365 int k = tint_nr / 16;
366
367 tsctr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSCTR);
368 titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(k));
369 titsel = ICU_TITSR_TITSEL_GET(titsr, titsel_n);
370
371 /*
372 * Writing 1 to the corresponding flag from register ICU_TSCTR only has effect if
373 * TSTATn = 1b and if it's a rising edge or a falling edge interrupt.
374 */
375 if ((tsctr & bit) && ((titsel == ICU_TINT_EDGE_RISING) ||
376 (titsel == ICU_TINT_EDGE_FALLING)))
377 writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
378 }
379
rzv2h_tint_set_type(struct irq_data * d,unsigned int type)380 static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
381 {
382 u32 titsr, titsr_k, titsel_n, tien;
383 struct rzv2h_icu_priv *priv;
384 u32 tssr, tssr_k, tssel_n;
385 u32 titsr_cur, tssr_cur;
386 unsigned int hwirq;
387 u32 tint, sense;
388 int tint_nr;
389 u8 nr_tint;
390
391 switch (type & IRQ_TYPE_SENSE_MASK) {
392 case IRQ_TYPE_LEVEL_LOW:
393 sense = ICU_TINT_LEVEL_LOW;
394 break;
395
396 case IRQ_TYPE_LEVEL_HIGH:
397 sense = ICU_TINT_LEVEL_HIGH;
398 break;
399
400 case IRQ_TYPE_EDGE_RISING:
401 sense = ICU_TINT_EDGE_RISING;
402 break;
403
404 case IRQ_TYPE_EDGE_FALLING:
405 sense = ICU_TINT_EDGE_FALLING;
406 break;
407
408 default:
409 return -EINVAL;
410 }
411
412 priv = irq_data_to_priv(d);
413 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
414 if (tint > priv->info->max_tssel)
415 return -EINVAL;
416
417 if (priv->info->tssel_lut)
418 tint = priv->info->tssel_lut[tint];
419
420 hwirq = irqd_to_hwirq(d);
421 tint_nr = hwirq - ICU_TINT_START;
422
423 nr_tint = 32 / priv->info->field_width;
424 tssr_k = tint_nr / nr_tint;
425 tssel_n = tint_nr % nr_tint;
426 tien = ICU_TSSR_TIEN(tssel_n, priv->info->field_width);
427
428 titsr_k = ICU_TITSR_K(tint_nr);
429 titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
430
431 scoped_guard(raw_spinlock, &priv->lock) {
432 tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
433 titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));
434
435 tssr_cur = field_get(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width), tssr);
436 titsr_cur = field_get(ICU_TITSR_TITSEL_MASK(titsel_n), titsr);
437 if (tssr_cur == tint && titsr_cur == sense)
438 goto set_parent_type;
439
440 tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien);
441 tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width);
442
443 writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
444
445 titsr &= ~ICU_TITSR_TITSEL_MASK(titsel_n);
446 titsr |= ICU_TITSR_TITSEL_PREP(sense, titsel_n);
447
448 writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));
449
450 rzv2h_clear_tint_int(priv, hwirq);
451
452 writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
453 }
454 set_parent_type:
455 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
456 }
457
rzv2h_icu_swint_set_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool state)458 static int rzv2h_icu_swint_set_irqchip_state(struct irq_data *d, enum irqchip_irq_state which,
459 bool state)
460 {
461 unsigned int hwirq = irqd_to_hwirq(d);
462 struct rzv2h_icu_priv *priv;
463 unsigned int bit;
464
465 if (which != IRQCHIP_STATE_PENDING)
466 return irq_chip_set_parent_state(d, which, state);
467
468 if (!state)
469 return 0;
470
471 priv = irq_data_to_priv(d);
472 bit = BIT(hwirq - ICU_CA55_INT_START);
473
474 /* Trigger the software interrupt */
475 writel_relaxed(bit, priv->base + ICU_SWINT);
476
477 return 0;
478 }
479
rzv2h_icu_swpe_set_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool state)480 static int rzv2h_icu_swpe_set_irqchip_state(struct irq_data *d, enum irqchip_irq_state which,
481 bool state)
482 {
483 struct rzv2h_icu_priv *priv;
484 unsigned int bit;
485 static u8 swpe;
486
487 if (which != IRQCHIP_STATE_PENDING)
488 return irq_chip_set_parent_state(d, which, state);
489
490 if (!state)
491 return 0;
492
493 priv = irq_data_to_priv(d);
494
495 bit = BIT(swpe);
496 /*
497 * SWPE has 16 bits; the bit position is rotated on each trigger
498 * and wraps around once all bits have been used.
499 */
500 if (++swpe >= ICU_SWPE_NUM)
501 swpe = 0;
502
503 /* Trigger the pseudo error interrupt */
504 writel_relaxed(bit, priv->base + ICU_SWPE);
505
506 return 0;
507 }
508
rzv2h_irqc_irq_suspend(void * data)509 static int rzv2h_irqc_irq_suspend(void *data)
510 {
511 struct rzv2h_irqc_reg_cache *cache = &rzv2h_icu_data->cache;
512 void __iomem *base = rzv2h_icu_data->base;
513
514 cache->nitsr = readl_relaxed(base + ICU_NITSR);
515 cache->iitsr = readl_relaxed(base + ICU_IITSR);
516 for (unsigned int i = 0; i < 2; i++)
517 cache->titsr[i] = readl_relaxed(base + rzv2h_icu_data->info->t_offs + ICU_TITSR(i));
518
519 return 0;
520 }
521
rzv2h_irqc_irq_resume(void * data)522 static void rzv2h_irqc_irq_resume(void *data)
523 {
524 struct rzv2h_irqc_reg_cache *cache = &rzv2h_icu_data->cache;
525 void __iomem *base = rzv2h_icu_data->base;
526
527 /*
528 * Restore only interrupt type. TSSRx will be restored at the
529 * request of pin controller to avoid spurious interrupts due
530 * to invalid PIN states.
531 */
532 for (unsigned int i = 0; i < 2; i++)
533 writel_relaxed(cache->titsr[i], base + rzv2h_icu_data->info->t_offs + ICU_TITSR(i));
534 writel_relaxed(cache->iitsr, base + ICU_IITSR);
535 writel_relaxed(cache->nitsr, base + ICU_NITSR);
536 }
537
538 static const struct syscore_ops rzv2h_irqc_syscore_ops = {
539 .suspend = rzv2h_irqc_irq_suspend,
540 .resume = rzv2h_irqc_irq_resume,
541 };
542
543 static struct syscore rzv2h_irqc_syscore = {
544 .ops = &rzv2h_irqc_syscore_ops,
545 };
546
547 static const struct irq_chip rzv2h_icu_tint_chip = {
548 .name = "rzv2h-icu",
549 .irq_eoi = rzv2h_icu_tint_eoi,
550 .irq_mask = irq_chip_mask_parent,
551 .irq_unmask = irq_chip_unmask_parent,
552 .irq_disable = rzv2h_icu_tint_disable,
553 .irq_enable = rzv2h_icu_tint_enable,
554 .irq_get_irqchip_state = irq_chip_get_parent_state,
555 .irq_set_irqchip_state = irq_chip_set_parent_state,
556 .irq_retrigger = irq_chip_retrigger_hierarchy,
557 .irq_set_type = rzv2h_tint_set_type,
558 .irq_set_affinity = irq_chip_set_affinity_parent,
559 .flags = IRQCHIP_MASK_ON_SUSPEND |
560 IRQCHIP_SET_TYPE_MASKED |
561 IRQCHIP_SKIP_SET_WAKE,
562 };
563
564 static const struct irq_chip rzv2h_icu_irq_chip = {
565 .name = "rzv2h-icu",
566 .irq_eoi = rzv2h_icu_irq_eoi,
567 .irq_mask = irq_chip_mask_parent,
568 .irq_unmask = irq_chip_unmask_parent,
569 .irq_disable = irq_chip_disable_parent,
570 .irq_enable = irq_chip_enable_parent,
571 .irq_get_irqchip_state = irq_chip_get_parent_state,
572 .irq_set_irqchip_state = irq_chip_set_parent_state,
573 .irq_retrigger = irq_chip_retrigger_hierarchy,
574 .irq_set_type = rzv2h_irq_set_type,
575 .irq_set_affinity = irq_chip_set_affinity_parent,
576 .flags = IRQCHIP_MASK_ON_SUSPEND |
577 IRQCHIP_SET_TYPE_MASKED |
578 IRQCHIP_SKIP_SET_WAKE,
579 };
580
581 static const struct irq_chip rzv2h_icu_nmi_chip = {
582 .name = "rzv2h-icu",
583 .irq_eoi = rzv2h_icu_nmi_eoi,
584 .irq_mask = irq_chip_mask_parent,
585 .irq_unmask = irq_chip_unmask_parent,
586 .irq_disable = irq_chip_disable_parent,
587 .irq_enable = irq_chip_enable_parent,
588 .irq_get_irqchip_state = irq_chip_get_parent_state,
589 .irq_set_irqchip_state = irq_chip_set_parent_state,
590 .irq_retrigger = irq_chip_retrigger_hierarchy,
591 .irq_set_type = rzv2h_nmi_set_type,
592 .irq_set_affinity = irq_chip_set_affinity_parent,
593 .flags = IRQCHIP_MASK_ON_SUSPEND |
594 IRQCHIP_SET_TYPE_MASKED |
595 IRQCHIP_SKIP_SET_WAKE,
596 };
597
598 static const struct irq_chip rzv2h_icu_swint_chip = {
599 .name = "rzv2h-icu",
600 .irq_eoi = irq_chip_eoi_parent,
601 .irq_mask = irq_chip_mask_parent,
602 .irq_unmask = irq_chip_unmask_parent,
603 .irq_disable = irq_chip_disable_parent,
604 .irq_enable = irq_chip_enable_parent,
605 .irq_get_irqchip_state = irq_chip_get_parent_state,
606 .irq_set_irqchip_state = rzv2h_icu_swint_set_irqchip_state,
607 .irq_retrigger = irq_chip_retrigger_hierarchy,
608 .irq_set_type = irq_chip_set_type_parent,
609 .irq_set_affinity = irq_chip_set_affinity_parent,
610 .flags = IRQCHIP_MASK_ON_SUSPEND |
611 IRQCHIP_SET_TYPE_MASKED |
612 IRQCHIP_SKIP_SET_WAKE,
613 };
614
615 static const struct irq_chip rzv2h_icu_swpe_err_chip = {
616 .name = "rzv2h-icu",
617 .irq_eoi = irq_chip_eoi_parent,
618 .irq_mask = irq_chip_mask_parent,
619 .irq_unmask = irq_chip_unmask_parent,
620 .irq_disable = irq_chip_disable_parent,
621 .irq_enable = irq_chip_enable_parent,
622 .irq_get_irqchip_state = irq_chip_get_parent_state,
623 .irq_set_irqchip_state = rzv2h_icu_swpe_set_irqchip_state,
624 .irq_retrigger = irq_chip_retrigger_hierarchy,
625 .irq_set_type = irq_chip_set_type_parent,
626 .irq_set_affinity = irq_chip_set_affinity_parent,
627 .flags = IRQCHIP_MASK_ON_SUSPEND |
628 IRQCHIP_SET_TYPE_MASKED |
629 IRQCHIP_SKIP_SET_WAKE,
630 };
631
632 #define hwirq_within(hwirq, which) ((hwirq) >= which##_START && (hwirq) <= which##_LAST)
633
rzv2h_icu_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)634 static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs,
635 void *arg)
636 {
637 struct rzv2h_icu_priv *priv = domain->host_data;
638 const struct irq_chip *chip;
639 unsigned long tint = 0;
640 irq_hw_number_t hwirq;
641 unsigned int type;
642 int ret;
643
644 ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
645 if (ret)
646 return ret;
647
648 /*
649 * For TINT interrupts the hwirq and TINT are encoded in
650 * fwspec->param[0].
651 * hwirq is embedded in bits 0-15.
652 * TINT is embedded in bits 16-31.
653 */
654 tint = ICU_TINT_EXTRACT_GPIOINT(hwirq);
655 if (tint || hwirq_within(hwirq, ICU_TINT)) {
656 hwirq = ICU_TINT_EXTRACT_HWIRQ(hwirq);
657
658 if (!hwirq_within(hwirq, ICU_TINT))
659 return -EINVAL;
660 chip = &rzv2h_icu_tint_chip;
661 } else if (hwirq_within(hwirq, ICU_IRQ)) {
662 chip = &rzv2h_icu_irq_chip;
663 } else if (hwirq_within(hwirq, ICU_CA55_INT)) {
664 chip = &rzv2h_icu_swint_chip;
665 } else if (hwirq_within(hwirq, ICU_ERR_INT)) {
666 chip = &rzv2h_icu_swpe_err_chip;
667 } else {
668 chip = &rzv2h_icu_nmi_chip;
669 }
670
671 if (hwirq > (ICU_NUM_IRQ - 1))
672 return -EINVAL;
673
674 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)(uintptr_t)tint);
675 if (ret)
676 return ret;
677
678 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
679 }
680
681 static const struct irq_domain_ops rzv2h_icu_domain_ops = {
682 .alloc = rzv2h_icu_alloc,
683 .free = irq_domain_free_irqs_common,
684 .translate = irq_domain_translate_twocell,
685 };
686
rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv * priv,struct device_node * np)687 static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, struct device_node *np)
688 {
689 struct of_phandle_args map;
690 unsigned int i;
691 int ret;
692
693 for (i = 0; i < ICU_NUM_IRQ; i++) {
694 ret = of_irq_parse_one(np, i, &map);
695 if (ret)
696 return ret;
697
698 of_phandle_args_to_fwspec(np, map.args, map.args_count, &priv->fwspec[i]);
699 }
700
701 return 0;
702 }
703
rzv2h_icu_error_irq(int irq,void * data)704 static irqreturn_t rzv2h_icu_error_irq(int irq, void *data)
705 {
706 struct rzv2h_icu_priv *priv = data;
707 const struct rzv2h_hw_info *hw_info = priv->info;
708 void __iomem *base = priv->base;
709 unsigned int k;
710 u32 st;
711
712 /* 1) Bus errors (BEISR0..3) */
713 for (k = 0; k < ICU_NUM_BE; k++) {
714 st = readl(base + ICU_BEISR(k));
715 if (!st)
716 continue;
717
718 writel_relaxed(st, base + ICU_BECLR(k));
719 pr_warn("rzv2h-icu: BUS error k=%u status=0x%08x\n", k, st);
720 }
721
722 /* 2) ECC RAM errors (EREISR0..X) */
723 for (k = hw_info->ecc_start; k <= hw_info->ecc_end; k++) {
724 st = readl(base + ICU_EREISR(k));
725 if (!st)
726 continue;
727
728 writel_relaxed(st, base + ICU_ERCLR(k));
729 pr_warn("rzv2h-icu: ECC error k=%u status=0x%08x\n", k, st);
730 }
731
732 /* 3) IP/CA55 error interrupt status (ERINTA55CTL0..3) */
733 for (k = 0; k < ICU_NUM_A55ERR; k++) {
734 st = readl(base + ICU_ERINTA55CTL(k));
735 if (!st)
736 continue;
737
738 /* there is no relation with status bits so clear all the interrupts */
739 writel_relaxed(0xffffffff, base + ICU_ERINTA55CRL(k));
740 pr_warn("rzv2h-icu: IP/CA55 error k=%u status=0x%08x\n", k, st);
741 }
742
743 return IRQ_HANDLED;
744 }
745
rzv2h_icu_swint_irq(int irq,void * data)746 static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data)
747 {
748 unsigned int cpu = (uintptr_t)data;
749
750 pr_info("SWINT interrupt for CA55 core %u\n", cpu);
751 return IRQ_HANDLED;
752 }
753
rzv2h_icu_setup_irqs(struct platform_device * pdev,struct irq_domain * irq_domain)754 static int rzv2h_icu_setup_irqs(struct platform_device *pdev, struct irq_domain *irq_domain)
755 {
756 const struct rzv2h_hw_info *hw_info = rzv2h_icu_data->info;
757 bool irq_inject = IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION);
758 void __iomem *base = rzv2h_icu_data->base;
759 struct device *dev = &pdev->dev;
760 struct irq_fwspec fwspec;
761 unsigned int i, virq;
762 int ret;
763
764 for (i = 0; i < ICU_CA55_INT_COUNT && irq_inject; i++) {
765 fwspec.fwnode = irq_domain->fwnode;
766 fwspec.param_count = 2;
767 fwspec.param[0] = ICU_CA55_INT_START + i;
768 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
769
770 virq = irq_create_fwspec_mapping(&fwspec);
771 if (!virq) {
772 return dev_err_probe(dev, -EINVAL,
773 "failed to create int-ca55-%u IRQ mapping\n", i);
774 }
775
776 ret = devm_request_irq(dev, virq, rzv2h_icu_swint_irq, 0, dev_name(dev),
777 (void *)(uintptr_t)i);
778 if (ret)
779 return dev_err_probe(dev, ret, "Failed to request int-ca55-%u IRQ\n", i);
780 }
781
782 /* Unmask and clear all IP/CA55 error interrupts */
783 for (i = 0; i < ICU_NUM_A55ERR; i++) {
784 writel_relaxed(0xffffff, base + ICU_ERINTA55CRL(i));
785 writel_relaxed(0x0, base + ICU_ERINTA55MSK(i));
786 }
787
788 /* Clear all Bus errors */
789 for (i = 0; i < ICU_NUM_BE; i++)
790 writel_relaxed(0xffffffff, base + ICU_BECLR(i));
791
792 /* Clear all ECCRAM errors */
793 for (i = hw_info->ecc_start; i <= hw_info->ecc_end; i++)
794 writel_relaxed(0xffffffff, base + ICU_ERCLR(i));
795
796 fwspec.fwnode = irq_domain->fwnode;
797 fwspec.param_count = 2;
798 fwspec.param[0] = ICU_ERR_INT_START;
799 fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
800
801 virq = irq_create_fwspec_mapping(&fwspec);
802 if (!virq)
803 return dev_err_probe(dev, -EINVAL, "failed to create icu-error-ca55 IRQ mapping\n");
804
805 ret = devm_request_irq(dev, virq, rzv2h_icu_error_irq, 0, dev_name(dev), rzv2h_icu_data);
806 if (ret)
807 return dev_err_probe(dev, ret, "Failed to request icu-error-ca55 IRQ\n");
808
809 return 0;
810 }
811
rzv2h_icu_probe_common(struct platform_device * pdev,struct device_node * parent,const struct rzv2h_hw_info * hw_info)812 static int rzv2h_icu_probe_common(struct platform_device *pdev, struct device_node *parent,
813 const struct rzv2h_hw_info *hw_info)
814 {
815 struct irq_domain *irq_domain, *parent_domain;
816 struct device_node *node = pdev->dev.of_node;
817 struct device *dev = &pdev->dev;
818 struct reset_control *resetn;
819 int ret;
820
821 parent_domain = irq_find_host(parent);
822 if (!parent_domain)
823 return dev_err_probe(dev, -ENODEV, "cannot find parent domain\n");
824
825 rzv2h_icu_data = devm_kzalloc(dev, sizeof(*rzv2h_icu_data), GFP_KERNEL);
826 if (!rzv2h_icu_data)
827 return -ENOMEM;
828
829 platform_set_drvdata(pdev, rzv2h_icu_data);
830
831 rzv2h_icu_data->base = devm_of_iomap(dev, node, 0, NULL);
832 if (IS_ERR(rzv2h_icu_data->base))
833 return PTR_ERR(rzv2h_icu_data->base);
834
835 ret = rzv2h_icu_parse_interrupts(rzv2h_icu_data, node);
836 if (ret)
837 return dev_err_probe(dev, ret, "cannot parse interrupts\n");
838
839 resetn = devm_reset_control_get_exclusive_deasserted(dev, NULL);
840 if (IS_ERR(resetn))
841 return dev_err_probe(dev, PTR_ERR(resetn), "failed to acquire deasserted reset\n");
842
843 ret = devm_pm_runtime_enable(dev);
844 if (ret < 0)
845 return dev_err_probe(dev, ret, "devm_pm_runtime_enable failed\n");
846
847 ret = pm_runtime_resume_and_get(dev);
848 if (ret < 0)
849 return dev_err_probe(dev, ret, "pm_runtime_resume_and_get failed\n");
850
851 raw_spin_lock_init(&rzv2h_icu_data->lock);
852
853 irq_domain = irq_domain_create_hierarchy(parent_domain, 0, ICU_NUM_IRQ,
854 dev_fwnode(dev), &rzv2h_icu_domain_ops,
855 rzv2h_icu_data);
856 if (!irq_domain) {
857 dev_err(dev, "failed to add irq domain\n");
858 ret = -ENOMEM;
859 goto pm_put;
860 }
861
862 rzv2h_icu_data->info = hw_info;
863
864 register_syscore(&rzv2h_irqc_syscore);
865
866 ret = rzv2h_icu_setup_irqs(pdev, irq_domain);
867 if (ret)
868 goto pm_put;
869
870 /*
871 * coccicheck complains about a missing put_device call before returning, but it's a false
872 * positive. We still need dev after successfully returning from this function.
873 */
874 return 0;
875
876 pm_put:
877 pm_runtime_put_sync(dev);
878 return ret;
879 }
880
881 /* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */
882 static const u8 rzg3e_tssel_lut[] = {
883 81, 82, 83, 84, 85, 86, 87, 88, /* P00-P07 */
884 89, 90, 91, 92, 93, 94, 95, 96, /* P10-P17 */
885 111, 112, /* P20-P21 */
886 97, 98, 99, 100, 101, 102, 103, 104, /* P30-P37 */
887 105, 106, 107, 108, 109, 110, /* P40-P45 */
888 113, 114, 115, 116, 117, 118, 119, /* P50-P56 */
889 120, 121, 122, 123, 124, 125, 126, /* P60-P66 */
890 127, 128, 129, 130, 131, 132, 133, 134, /* P70-P77 */
891 135, 136, 137, 138, 139, 140, /* P80-P85 */
892 43, 44, 45, 46, 47, 48, 49, 50, /* PA0-PA7 */
893 51, 52, 53, 54, 55, 56, 57, 58, /* PB0-PB7 */
894 59, 60, 61, /* PC0-PC2 */
895 62, 63, 64, 65, 66, 67, 68, 69, /* PD0-PD7 */
896 70, 71, 72, 73, 74, 75, 76, 77, /* PE0-PE7 */
897 78, 79, 80, /* PF0-PF2 */
898 25, 26, 27, 28, 29, 30, 31, 32, /* PG0-PG7 */
899 33, 34, 35, 36, 37, 38, /* PH0-PH5 */
900 4, 5, 6, 7, 8, /* PJ0-PJ4 */
901 39, 40, 41, 42, /* PK0-PK3 */
902 9, 10, 11, 12, 21, 22, 23, 24, /* PL0-PL7 */
903 13, 14, 15, 16, 17, 18, 19, 20, /* PM0-PM7 */
904 0, 1, 2, 3 /* PS0-PS3 */
905 };
906
907 static const struct rzv2h_hw_info rzg3e_hw_params = {
908 .tssel_lut = rzg3e_tssel_lut,
909 .t_offs = ICU_RZG3E_TINT_OFFSET,
910 .max_tssel = ICU_RZG3E_TSSEL_MAX_VAL,
911 .field_width = 16,
912 .ecc_start = 1,
913 .ecc_end = 4,
914 };
915
916 static const struct rzv2h_hw_info rzv2n_hw_params = {
917 .t_offs = 0,
918 .max_tssel = ICU_RZV2H_TSSEL_MAX_VAL,
919 .field_width = 8,
920 .ecc_start = 0,
921 .ecc_end = 2,
922 };
923
924 static const struct rzv2h_hw_info rzv2h_hw_params = {
925 .t_offs = 0,
926 .max_tssel = ICU_RZV2H_TSSEL_MAX_VAL,
927 .field_width = 8,
928 .ecc_start = 0,
929 .ecc_end = 11,
930 };
931
rzg3e_icu_probe(struct platform_device * pdev,struct device_node * parent)932 static int rzg3e_icu_probe(struct platform_device *pdev, struct device_node *parent)
933 {
934 return rzv2h_icu_probe_common(pdev, parent, &rzg3e_hw_params);
935 }
936
rzv2n_icu_probe(struct platform_device * pdev,struct device_node * parent)937 static int rzv2n_icu_probe(struct platform_device *pdev, struct device_node *parent)
938 {
939 return rzv2h_icu_probe_common(pdev, parent, &rzv2n_hw_params);
940 }
941
rzv2h_icu_probe(struct platform_device * pdev,struct device_node * parent)942 static int rzv2h_icu_probe(struct platform_device *pdev, struct device_node *parent)
943 {
944 return rzv2h_icu_probe_common(pdev, parent, &rzv2h_hw_params);
945 }
946
947 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
948 IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_probe)
949 IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2n_icu_probe)
950 IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_probe)
951 IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
952 MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
953 MODULE_DESCRIPTION("Renesas RZ/V2H(P) ICU Driver");
954