1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2021-2023 Samuel Holland <samuel@sholland.org>
4 *
5 * Partly based on drivers/leds/leds-turris-omnia.c, which is:
6 * Copyright (c) 2020 by Marek Behún <kabel@kernel.org>
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/led-class-multicolor.h>
17 #include <linux/leds.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm.h>
21 #include <linux/property.h>
22 #include <linux/reset.h>
23 #include <linux/spinlock.h>
24
25 #define LEDC_CTRL_REG 0x0000
26 #define LEDC_CTRL_REG_DATA_LENGTH GENMASK(28, 16)
27 #define LEDC_CTRL_REG_RGB_MODE GENMASK(8, 6)
28 #define LEDC_CTRL_REG_LEDC_EN BIT(0)
29 #define LEDC_T01_TIMING_CTRL_REG 0x0004
30 #define LEDC_T01_TIMING_CTRL_REG_T1H GENMASK(26, 21)
31 #define LEDC_T01_TIMING_CTRL_REG_T1L GENMASK(20, 16)
32 #define LEDC_T01_TIMING_CTRL_REG_T0H GENMASK(10, 6)
33 #define LEDC_T01_TIMING_CTRL_REG_T0L GENMASK(5, 0)
34 #define LEDC_RESET_TIMING_CTRL_REG 0x000c
35 #define LEDC_RESET_TIMING_CTRL_REG_TR GENMASK(28, 16)
36 #define LEDC_RESET_TIMING_CTRL_REG_LED_NUM GENMASK(9, 0)
37 #define LEDC_DATA_REG 0x0014
38 #define LEDC_DMA_CTRL_REG 0x0018
39 #define LEDC_DMA_CTRL_REG_DMA_EN BIT(5)
40 #define LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL GENMASK(4, 0)
41 #define LEDC_INT_CTRL_REG 0x001c
42 #define LEDC_INT_CTRL_REG_GLOBAL_INT_EN BIT(5)
43 #define LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN BIT(1)
44 #define LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN BIT(0)
45 #define LEDC_INT_STS_REG 0x0020
46 #define LEDC_INT_STS_REG_FIFO_WLW GENMASK(15, 10)
47 #define LEDC_INT_STS_REG_FIFO_CPUREQ_INT BIT(1)
48 #define LEDC_INT_STS_REG_TRANS_FINISH_INT BIT(0)
49
50 #define LEDC_FIFO_DEPTH 32U
51 #define LEDC_MAX_LEDS 1024
52 #define LEDC_CHANNELS_PER_LED 3 /* RGB */
53
54 #define LEDS_TO_BYTES(n) ((n) * sizeof(u32))
55
56 struct sun50i_a100_ledc_led {
57 struct led_classdev_mc mc_cdev;
58 struct mc_subled subled_info[LEDC_CHANNELS_PER_LED];
59 u32 addr;
60 };
61
62 #define to_ledc_led(mc) container_of(mc, struct sun50i_a100_ledc_led, mc_cdev)
63
64 struct sun50i_a100_ledc_timing {
65 u32 t0h_ns;
66 u32 t0l_ns;
67 u32 t1h_ns;
68 u32 t1l_ns;
69 u32 treset_ns;
70 };
71
72 struct sun50i_a100_ledc {
73 struct device *dev;
74 void __iomem *base;
75 struct clk *bus_clk;
76 struct clk *mod_clk;
77 struct reset_control *reset;
78
79 u32 *buffer;
80 struct dma_chan *dma_chan;
81 dma_addr_t dma_handle;
82 unsigned int pio_length;
83 unsigned int pio_offset;
84
85 spinlock_t lock;
86 unsigned int next_length;
87 bool xfer_active;
88
89 u32 format;
90 struct sun50i_a100_ledc_timing timing;
91
92 u32 max_addr;
93 u32 num_leds;
94 struct sun50i_a100_ledc_led leds[] __counted_by(num_leds);
95 };
96
sun50i_a100_ledc_dma_xfer(struct sun50i_a100_ledc * priv,unsigned int length)97 static int sun50i_a100_ledc_dma_xfer(struct sun50i_a100_ledc *priv, unsigned int length)
98 {
99 struct dma_async_tx_descriptor *desc;
100 dma_cookie_t cookie;
101
102 desc = dmaengine_prep_slave_single(priv->dma_chan, priv->dma_handle,
103 LEDS_TO_BYTES(length), DMA_MEM_TO_DEV, 0);
104 if (!desc)
105 return -ENOMEM;
106
107 cookie = dmaengine_submit(desc);
108 if (dma_submit_error(cookie))
109 return -EIO;
110
111 dma_async_issue_pending(priv->dma_chan);
112
113 return 0;
114 }
115
sun50i_a100_ledc_pio_xfer(struct sun50i_a100_ledc * priv,unsigned int fifo_used)116 static void sun50i_a100_ledc_pio_xfer(struct sun50i_a100_ledc *priv, unsigned int fifo_used)
117 {
118 unsigned int burst, length, offset;
119 u32 control;
120
121 length = priv->pio_length;
122 offset = priv->pio_offset;
123 burst = min(length, LEDC_FIFO_DEPTH - fifo_used);
124
125 iowrite32_rep(priv->base + LEDC_DATA_REG, priv->buffer + offset, burst);
126
127 if (burst < length) {
128 priv->pio_length = length - burst;
129 priv->pio_offset = offset + burst;
130
131 if (!offset) {
132 control = readl(priv->base + LEDC_INT_CTRL_REG);
133 control |= LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;
134 writel(control, priv->base + LEDC_INT_CTRL_REG);
135 }
136 } else {
137 /* Disable the request IRQ once all data is written. */
138 control = readl(priv->base + LEDC_INT_CTRL_REG);
139 control &= ~LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;
140 writel(control, priv->base + LEDC_INT_CTRL_REG);
141 }
142 }
143
sun50i_a100_ledc_start_xfer(struct sun50i_a100_ledc * priv,unsigned int length)144 static void sun50i_a100_ledc_start_xfer(struct sun50i_a100_ledc *priv, unsigned int length)
145 {
146 bool use_dma = false;
147 u32 control;
148
149 if (priv->dma_chan && length > LEDC_FIFO_DEPTH) {
150 int ret;
151
152 ret = sun50i_a100_ledc_dma_xfer(priv, length);
153 if (ret)
154 dev_warn(priv->dev, "Failed to set up DMA (%d), using PIO\n", ret);
155 else
156 use_dma = true;
157 }
158
159 /* The DMA trigger level must be at least the burst length. */
160 control = FIELD_PREP(LEDC_DMA_CTRL_REG_DMA_EN, use_dma) |
161 FIELD_PREP_CONST(LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL, LEDC_FIFO_DEPTH / 2);
162 writel(control, priv->base + LEDC_DMA_CTRL_REG);
163
164 control = readl(priv->base + LEDC_CTRL_REG);
165 control &= ~LEDC_CTRL_REG_DATA_LENGTH;
166 control |= FIELD_PREP(LEDC_CTRL_REG_DATA_LENGTH, length) | LEDC_CTRL_REG_LEDC_EN;
167 writel(control, priv->base + LEDC_CTRL_REG);
168
169 if (!use_dma) {
170 /* The FIFO is empty when starting a new transfer. */
171 unsigned int fifo_used = 0;
172
173 priv->pio_length = length;
174 priv->pio_offset = 0;
175
176 sun50i_a100_ledc_pio_xfer(priv, fifo_used);
177 }
178 }
179
sun50i_a100_ledc_irq(int irq,void * data)180 static irqreturn_t sun50i_a100_ledc_irq(int irq, void *data)
181 {
182 struct sun50i_a100_ledc *priv = data;
183 u32 status;
184
185 status = readl(priv->base + LEDC_INT_STS_REG);
186
187 if (status & LEDC_INT_STS_REG_TRANS_FINISH_INT) {
188 unsigned int next_length;
189
190 spin_lock(&priv->lock);
191
192 /* If another transfer is queued, dequeue and start it. */
193 next_length = priv->next_length;
194 if (next_length)
195 priv->next_length = 0;
196 else
197 priv->xfer_active = false;
198
199 spin_unlock(&priv->lock);
200
201 if (next_length)
202 sun50i_a100_ledc_start_xfer(priv, next_length);
203 } else if (status & LEDC_INT_STS_REG_FIFO_CPUREQ_INT) {
204 /* Continue the current transfer. */
205 sun50i_a100_ledc_pio_xfer(priv, FIELD_GET(LEDC_INT_STS_REG_FIFO_WLW, status));
206 }
207
208 /* Clear the W1C status bits. */
209 writel(status, priv->base + LEDC_INT_STS_REG);
210
211 return IRQ_HANDLED;
212 }
213
sun50i_a100_ledc_brightness_set(struct led_classdev * cdev,enum led_brightness brightness)214 static void sun50i_a100_ledc_brightness_set(struct led_classdev *cdev,
215 enum led_brightness brightness)
216 {
217 struct sun50i_a100_ledc *priv = dev_get_drvdata(cdev->dev->parent);
218 struct led_classdev_mc *mc_cdev = lcdev_to_mccdev(cdev);
219 struct sun50i_a100_ledc_led *led = to_ledc_led(mc_cdev);
220 unsigned int next_length;
221 unsigned long flags;
222 bool xfer_active;
223
224 led_mc_calc_color_components(mc_cdev, brightness);
225
226 priv->buffer[led->addr] = led->subled_info[0].brightness << 16 |
227 led->subled_info[1].brightness << 8 |
228 led->subled_info[2].brightness;
229
230 spin_lock_irqsave(&priv->lock, flags);
231
232 /* Start, enqueue, or extend an enqueued transfer, as appropriate. */
233 next_length = max(priv->next_length, led->addr + 1);
234 xfer_active = priv->xfer_active;
235 if (xfer_active)
236 priv->next_length = next_length;
237 else
238 priv->xfer_active = true;
239
240 spin_unlock_irqrestore(&priv->lock, flags);
241
242 if (!xfer_active)
243 sun50i_a100_ledc_start_xfer(priv, next_length);
244 }
245
246 static const char *const sun50i_a100_ledc_formats[] = {
247 "rgb", "rbg", "grb", "gbr", "brg", "bgr",
248 };
249
sun50i_a100_ledc_parse_format(struct device * dev,struct sun50i_a100_ledc * priv)250 static int sun50i_a100_ledc_parse_format(struct device *dev,
251 struct sun50i_a100_ledc *priv)
252 {
253 const char *format = "grb";
254 int i;
255
256 device_property_read_string(dev, "allwinner,pixel-format", &format);
257
258 i = match_string(sun50i_a100_ledc_formats, ARRAY_SIZE(sun50i_a100_ledc_formats), format);
259 if (i < 0)
260 return dev_err_probe(dev, i, "Bad pixel format '%s'\n", format);
261
262 priv->format = i;
263 return 0;
264 }
265
sun50i_a100_ledc_set_format(struct sun50i_a100_ledc * priv)266 static void sun50i_a100_ledc_set_format(struct sun50i_a100_ledc *priv)
267 {
268 u32 control;
269
270 control = readl(priv->base + LEDC_CTRL_REG);
271 control &= ~LEDC_CTRL_REG_RGB_MODE;
272 control |= FIELD_PREP(LEDC_CTRL_REG_RGB_MODE, priv->format);
273 writel(control, priv->base + LEDC_CTRL_REG);
274 }
275
276 static const struct sun50i_a100_ledc_timing sun50i_a100_ledc_default_timing = {
277 .t0h_ns = 336,
278 .t0l_ns = 840,
279 .t1h_ns = 882,
280 .t1l_ns = 294,
281 .treset_ns = 300000,
282 };
283
sun50i_a100_ledc_parse_timing(struct device * dev,struct sun50i_a100_ledc * priv)284 static int sun50i_a100_ledc_parse_timing(struct device *dev,
285 struct sun50i_a100_ledc *priv)
286 {
287 struct sun50i_a100_ledc_timing *timing = &priv->timing;
288
289 *timing = sun50i_a100_ledc_default_timing;
290
291 device_property_read_u32(dev, "allwinner,t0h-ns", &timing->t0h_ns);
292 device_property_read_u32(dev, "allwinner,t0l-ns", &timing->t0l_ns);
293 device_property_read_u32(dev, "allwinner,t1h-ns", &timing->t1h_ns);
294 device_property_read_u32(dev, "allwinner,t1l-ns", &timing->t1l_ns);
295 device_property_read_u32(dev, "allwinner,treset-ns", &timing->treset_ns);
296
297 return 0;
298 }
299
sun50i_a100_ledc_set_timing(struct sun50i_a100_ledc * priv)300 static void sun50i_a100_ledc_set_timing(struct sun50i_a100_ledc *priv)
301 {
302 const struct sun50i_a100_ledc_timing *timing = &priv->timing;
303 unsigned long mod_freq = clk_get_rate(priv->mod_clk);
304 u32 cycle_ns;
305 u32 control;
306
307 if (!mod_freq)
308 return;
309
310 cycle_ns = NSEC_PER_SEC / mod_freq;
311 control = FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T1H, timing->t1h_ns / cycle_ns) |
312 FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T1L, timing->t1l_ns / cycle_ns) |
313 FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T0H, timing->t0h_ns / cycle_ns) |
314 FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T0L, timing->t0l_ns / cycle_ns);
315 writel(control, priv->base + LEDC_T01_TIMING_CTRL_REG);
316
317 control = FIELD_PREP(LEDC_RESET_TIMING_CTRL_REG_TR, timing->treset_ns / cycle_ns) |
318 FIELD_PREP(LEDC_RESET_TIMING_CTRL_REG_LED_NUM, priv->max_addr);
319 writel(control, priv->base + LEDC_RESET_TIMING_CTRL_REG);
320 }
321
sun50i_a100_ledc_resume(struct device * dev)322 static int sun50i_a100_ledc_resume(struct device *dev)
323 {
324 struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);
325 int ret;
326
327 ret = reset_control_deassert(priv->reset);
328 if (ret)
329 return ret;
330
331 ret = clk_prepare_enable(priv->bus_clk);
332 if (ret)
333 goto err_assert_reset;
334
335 ret = clk_prepare_enable(priv->mod_clk);
336 if (ret)
337 goto err_disable_bus_clk;
338
339 sun50i_a100_ledc_set_format(priv);
340 sun50i_a100_ledc_set_timing(priv);
341
342 writel(LEDC_INT_CTRL_REG_GLOBAL_INT_EN | LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN,
343 priv->base + LEDC_INT_CTRL_REG);
344
345 return 0;
346
347 err_disable_bus_clk:
348 clk_disable_unprepare(priv->bus_clk);
349 err_assert_reset:
350 reset_control_assert(priv->reset);
351
352 return ret;
353 }
354
sun50i_a100_ledc_suspend(struct device * dev)355 static int sun50i_a100_ledc_suspend(struct device *dev)
356 {
357 struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);
358
359 /* Wait for all transfers to complete. */
360 for (;;) {
361 unsigned long flags;
362 bool xfer_active;
363
364 spin_lock_irqsave(&priv->lock, flags);
365 xfer_active = priv->xfer_active;
366 spin_unlock_irqrestore(&priv->lock, flags);
367 if (!xfer_active)
368 break;
369
370 usleep_range(1000, 1100);
371 }
372
373 clk_disable_unprepare(priv->mod_clk);
374 clk_disable_unprepare(priv->bus_clk);
375 reset_control_assert(priv->reset);
376
377 return 0;
378 }
379
sun50i_a100_ledc_dma_cleanup(void * data)380 static void sun50i_a100_ledc_dma_cleanup(void *data)
381 {
382 struct sun50i_a100_ledc *priv = data;
383
384 dma_release_channel(priv->dma_chan);
385 }
386
sun50i_a100_ledc_probe(struct platform_device * pdev)387 static int sun50i_a100_ledc_probe(struct platform_device *pdev)
388 {
389 struct dma_slave_config dma_cfg = {};
390 struct led_init_data init_data = {};
391 struct sun50i_a100_ledc_led *led;
392 struct device *dev = &pdev->dev;
393 struct sun50i_a100_ledc *priv;
394 struct resource *mem;
395 u32 max_addr = 0;
396 u32 num_leds = 0;
397 int irq, ret;
398
399 /*
400 * The maximum LED address must be known in sun50i_a100_ledc_resume() before
401 * class device registration, so parse and validate the subnodes up front.
402 */
403 device_for_each_child_node_scoped(dev, child) {
404 u32 addr, color;
405
406 ret = fwnode_property_read_u32(child, "reg", &addr);
407 if (ret || addr >= LEDC_MAX_LEDS)
408 return dev_err_probe(dev, -EINVAL, "'reg' must be between 0 and %d\n",
409 LEDC_MAX_LEDS - 1);
410
411 ret = fwnode_property_read_u32(child, "color", &color);
412 if (ret || color != LED_COLOR_ID_RGB)
413 return dev_err_probe(dev, -EINVAL, "'color' must be LED_COLOR_ID_RGB\n");
414
415 max_addr = max(max_addr, addr);
416 num_leds++;
417 }
418
419 if (!num_leds)
420 return -ENODEV;
421
422 priv = devm_kzalloc(dev, struct_size(priv, leds, num_leds), GFP_KERNEL);
423 if (!priv)
424 return -ENOMEM;
425
426 priv->dev = dev;
427 priv->max_addr = max_addr;
428 priv->num_leds = num_leds;
429 spin_lock_init(&priv->lock);
430 dev_set_drvdata(dev, priv);
431
432 ret = sun50i_a100_ledc_parse_format(dev, priv);
433 if (ret)
434 return ret;
435
436 ret = sun50i_a100_ledc_parse_timing(dev, priv);
437 if (ret)
438 return ret;
439
440 priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
441 if (IS_ERR(priv->base))
442 return PTR_ERR(priv->base);
443
444 priv->bus_clk = devm_clk_get(dev, "bus");
445 if (IS_ERR(priv->bus_clk))
446 return PTR_ERR(priv->bus_clk);
447
448 priv->mod_clk = devm_clk_get(dev, "mod");
449 if (IS_ERR(priv->mod_clk))
450 return PTR_ERR(priv->mod_clk);
451
452 priv->reset = devm_reset_control_get_exclusive(dev, NULL);
453 if (IS_ERR(priv->reset))
454 return PTR_ERR(priv->reset);
455
456 priv->dma_chan = dma_request_chan(dev, "tx");
457 if (IS_ERR(priv->dma_chan)) {
458 if (PTR_ERR(priv->dma_chan) != -ENODEV)
459 return PTR_ERR(priv->dma_chan);
460
461 priv->dma_chan = NULL;
462
463 priv->buffer = devm_kzalloc(dev, LEDS_TO_BYTES(LEDC_MAX_LEDS), GFP_KERNEL);
464 if (!priv->buffer)
465 return -ENOMEM;
466 } else {
467 ret = devm_add_action_or_reset(dev, sun50i_a100_ledc_dma_cleanup, priv);
468 if (ret)
469 return ret;
470
471 dma_cfg.dst_addr = mem->start + LEDC_DATA_REG;
472 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
473 dma_cfg.dst_maxburst = LEDC_FIFO_DEPTH / 2;
474
475 ret = dmaengine_slave_config(priv->dma_chan, &dma_cfg);
476 if (ret)
477 return ret;
478
479 priv->buffer = dmam_alloc_attrs(dmaengine_get_dma_device(priv->dma_chan),
480 LEDS_TO_BYTES(LEDC_MAX_LEDS), &priv->dma_handle,
481 GFP_KERNEL, DMA_ATTR_WRITE_COMBINE);
482 if (!priv->buffer)
483 return -ENOMEM;
484 }
485
486 irq = platform_get_irq(pdev, 0);
487 if (irq < 0)
488 return irq;
489
490 ret = devm_request_irq(dev, irq, sun50i_a100_ledc_irq, 0, dev_name(dev), priv);
491 if (ret)
492 return ret;
493
494 ret = sun50i_a100_ledc_resume(dev);
495 if (ret)
496 return ret;
497
498 led = priv->leds;
499 device_for_each_child_node_scoped(dev, child) {
500 struct led_classdev *cdev;
501
502 /* The node was already validated above. */
503 fwnode_property_read_u32(child, "reg", &led->addr);
504
505 led->subled_info[0].color_index = LED_COLOR_ID_RED;
506 led->subled_info[0].channel = 0;
507 led->subled_info[1].color_index = LED_COLOR_ID_GREEN;
508 led->subled_info[1].channel = 1;
509 led->subled_info[2].color_index = LED_COLOR_ID_BLUE;
510 led->subled_info[2].channel = 2;
511
512 led->mc_cdev.num_colors = ARRAY_SIZE(led->subled_info);
513 led->mc_cdev.subled_info = led->subled_info;
514
515 cdev = &led->mc_cdev.led_cdev;
516 cdev->max_brightness = U8_MAX;
517 cdev->brightness_set = sun50i_a100_ledc_brightness_set;
518
519 init_data.fwnode = child;
520
521 ret = led_classdev_multicolor_register_ext(dev, &led->mc_cdev, &init_data);
522 if (ret) {
523 dev_err_probe(dev, ret, "Failed to register multicolor LED %u", led->addr);
524 while (led-- > priv->leds)
525 led_classdev_multicolor_unregister(&led->mc_cdev);
526 sun50i_a100_ledc_suspend(&pdev->dev);
527
528 return ret;
529 }
530
531 led++;
532 }
533
534 dev_info(dev, "Registered %u LEDs\n", num_leds);
535
536 return 0;
537 }
538
sun50i_a100_ledc_remove(struct platform_device * pdev)539 static void sun50i_a100_ledc_remove(struct platform_device *pdev)
540 {
541 struct sun50i_a100_ledc *priv = platform_get_drvdata(pdev);
542
543 for (u32 i = 0; i < priv->num_leds; i++)
544 led_classdev_multicolor_unregister(&priv->leds[i].mc_cdev);
545 sun50i_a100_ledc_suspend(&pdev->dev);
546 }
547
548 static const struct of_device_id sun50i_a100_ledc_of_match[] = {
549 { .compatible = "allwinner,sun50i-a100-ledc" },
550 {}
551 };
552 MODULE_DEVICE_TABLE(of, sun50i_a100_ledc_of_match);
553
554 static DEFINE_SIMPLE_DEV_PM_OPS(sun50i_a100_ledc_pm,
555 sun50i_a100_ledc_suspend,
556 sun50i_a100_ledc_resume);
557
558 static struct platform_driver sun50i_a100_ledc_driver = {
559 .probe = sun50i_a100_ledc_probe,
560 .remove = sun50i_a100_ledc_remove,
561 .shutdown = sun50i_a100_ledc_remove,
562 .driver = {
563 .name = "sun50i-a100-ledc",
564 .of_match_table = sun50i_a100_ledc_of_match,
565 .pm = pm_ptr(&sun50i_a100_ledc_pm),
566 },
567 };
568 module_platform_driver(sun50i_a100_ledc_driver);
569
570 MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
571 MODULE_DESCRIPTION("Allwinner A100 LED controller driver");
572 MODULE_LICENSE("GPL");
573