1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * TQ-Systems TQMx86 PLD GPIO driver
4 *
5 * Based on vendor driver by:
6 * Vadim V.Vlasov <vvlasov@dev.rtsoft.ru>
7 */
8
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/errno.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/seq_file.h>
20 #include <linux/slab.h>
21
22 #define TQMX86_NGPIO 8
23 #define TQMX86_NGPO 4 /* 0-3 - output */
24 #define TQMX86_NGPI 4 /* 4-7 - input */
25 #define TQMX86_DIR_INPUT_MASK 0xf0 /* 0-3 - output, 4-7 - input */
26
27 #define TQMX86_GPIODD 0 /* GPIO Data Direction Register */
28 #define TQMX86_GPIOD 1 /* GPIO Data Register */
29 #define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */
30 #define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */
31
32 /*
33 * NONE, FALLING and RISING use the same bit patterns that can be programmed to
34 * the GPII register (after passing them to the TQMX86_GPII_ macros to shift
35 * them to the right position)
36 */
37 #define TQMX86_INT_TRIG_NONE 0
38 #define TQMX86_INT_TRIG_FALLING BIT(0)
39 #define TQMX86_INT_TRIG_RISING BIT(1)
40 #define TQMX86_INT_TRIG_BOTH (BIT(0) | BIT(1))
41 #define TQMX86_INT_TRIG_MASK (BIT(0) | BIT(1))
42 /* Stored in irq_type with GPII bits */
43 #define TQMX86_INT_UNMASKED BIT(2)
44
45 #define TQMX86_GPIIC_CONFIG(i, v) ((v) << (2 * (i)))
46 #define TQMX86_GPIIC_MASK(i) TQMX86_GPIIC_CONFIG(i, TQMX86_INT_TRIG_MASK)
47
48 struct tqmx86_gpio_data {
49 struct gpio_chip chip;
50 void __iomem *io_base;
51 int irq;
52 /* Lock must be held for accessing output and irq_type fields */
53 raw_spinlock_t spinlock;
54 DECLARE_BITMAP(output, TQMX86_NGPIO);
55 u8 irq_type[TQMX86_NGPIO];
56 };
57
tqmx86_gpio_read(struct tqmx86_gpio_data * gd,unsigned int reg)58 static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg)
59 {
60 return ioread8(gd->io_base + reg);
61 }
62
tqmx86_gpio_write(struct tqmx86_gpio_data * gd,u8 val,unsigned int reg)63 static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val,
64 unsigned int reg)
65 {
66 iowrite8(val, gd->io_base + reg);
67 }
68
tqmx86_gpio_clrsetbits(struct tqmx86_gpio_data * gpio,u8 clr,u8 set,unsigned int reg)69 static void tqmx86_gpio_clrsetbits(struct tqmx86_gpio_data *gpio,
70 u8 clr, u8 set, unsigned int reg)
71 __must_hold(&gpio->spinlock)
72 {
73 u8 val = tqmx86_gpio_read(gpio, reg);
74
75 val &= ~clr;
76 val |= set;
77
78 tqmx86_gpio_write(gpio, val, reg);
79 }
80
tqmx86_gpio_get(struct gpio_chip * chip,unsigned int offset)81 static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset)
82 {
83 struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
84
85 return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & BIT(offset));
86 }
87
_tqmx86_gpio_set(struct tqmx86_gpio_data * gpio,unsigned int offset,int value)88 static void _tqmx86_gpio_set(struct tqmx86_gpio_data *gpio, unsigned int offset,
89 int value)
90 __must_hold(&gpio->spinlock)
91 {
92 __assign_bit(offset, gpio->output, value);
93 tqmx86_gpio_write(gpio, bitmap_get_value8(gpio->output, 0), TQMX86_GPIOD);
94 }
95
tqmx86_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)96 static int tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset,
97 int value)
98 {
99 struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
100
101 guard(raw_spinlock_irqsave)(&gpio->spinlock);
102
103 _tqmx86_gpio_set(gpio, offset, value);
104
105 return 0;
106 }
107
tqmx86_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)108 static int tqmx86_gpio_direction_input(struct gpio_chip *chip,
109 unsigned int offset)
110 {
111 struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
112
113 guard(raw_spinlock_irqsave)(&gpio->spinlock);
114
115 tqmx86_gpio_clrsetbits(gpio, BIT(offset), 0, TQMX86_GPIODD);
116
117 return 0;
118 }
119
tqmx86_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)120 static int tqmx86_gpio_direction_output(struct gpio_chip *chip,
121 unsigned int offset,
122 int value)
123 {
124 struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
125
126 guard(raw_spinlock_irqsave)(&gpio->spinlock);
127
128 _tqmx86_gpio_set(gpio, offset, value);
129 tqmx86_gpio_clrsetbits(gpio, 0, BIT(offset), TQMX86_GPIODD);
130
131 return 0;
132 }
133
tqmx86_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)134 static int tqmx86_gpio_get_direction(struct gpio_chip *chip,
135 unsigned int offset)
136 {
137 struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
138 u8 val;
139
140 val = tqmx86_gpio_read(gpio, TQMX86_GPIODD);
141
142 if (val & BIT(offset))
143 return GPIO_LINE_DIRECTION_OUT;
144
145 return GPIO_LINE_DIRECTION_IN;
146 }
147
tqmx86_gpio_irq_config(struct tqmx86_gpio_data * gpio,int hwirq)148 static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int hwirq)
149 __must_hold(&gpio->spinlock)
150 {
151 u8 type = TQMX86_INT_TRIG_NONE;
152 int gpiic_irq = hwirq - TQMX86_NGPO;
153
154 if (gpio->irq_type[hwirq] & TQMX86_INT_UNMASKED) {
155 type = gpio->irq_type[hwirq] & TQMX86_INT_TRIG_MASK;
156
157 if (type == TQMX86_INT_TRIG_BOTH)
158 type = tqmx86_gpio_get(&gpio->chip, hwirq)
159 ? TQMX86_INT_TRIG_FALLING
160 : TQMX86_INT_TRIG_RISING;
161 }
162
163 tqmx86_gpio_clrsetbits(gpio,
164 TQMX86_GPIIC_MASK(gpiic_irq),
165 TQMX86_GPIIC_CONFIG(gpiic_irq, type),
166 TQMX86_GPIIC);
167 }
168
tqmx86_gpio_irq_mask(struct irq_data * data)169 static void tqmx86_gpio_irq_mask(struct irq_data *data)
170 {
171 struct tqmx86_gpio_data *gpio = gpiochip_get_data(
172 irq_data_get_irq_chip_data(data));
173
174 scoped_guard(raw_spinlock_irqsave, &gpio->spinlock) {
175 gpio->irq_type[data->hwirq] &= ~TQMX86_INT_UNMASKED;
176 tqmx86_gpio_irq_config(gpio, data->hwirq);
177 }
178
179 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(data));
180 }
181
tqmx86_gpio_irq_unmask(struct irq_data * data)182 static void tqmx86_gpio_irq_unmask(struct irq_data *data)
183 {
184 struct tqmx86_gpio_data *gpio = gpiochip_get_data(
185 irq_data_get_irq_chip_data(data));
186
187 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(data));
188
189 guard(raw_spinlock_irqsave)(&gpio->spinlock);
190
191 gpio->irq_type[data->hwirq] |= TQMX86_INT_UNMASKED;
192 tqmx86_gpio_irq_config(gpio, data->hwirq);
193 }
194
tqmx86_gpio_irq_set_type(struct irq_data * data,unsigned int type)195 static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type)
196 {
197 struct tqmx86_gpio_data *gpio = gpiochip_get_data(
198 irq_data_get_irq_chip_data(data));
199 unsigned int edge_type = type & IRQF_TRIGGER_MASK;
200 u8 new_type;
201
202 switch (edge_type) {
203 case IRQ_TYPE_EDGE_RISING:
204 new_type = TQMX86_INT_TRIG_RISING;
205 break;
206 case IRQ_TYPE_EDGE_FALLING:
207 new_type = TQMX86_INT_TRIG_FALLING;
208 break;
209 case IRQ_TYPE_EDGE_BOTH:
210 new_type = TQMX86_INT_TRIG_BOTH;
211 break;
212 default:
213 return -EINVAL; /* not supported */
214 }
215
216 guard(raw_spinlock_irqsave)(&gpio->spinlock);
217
218 gpio->irq_type[data->hwirq] &= ~TQMX86_INT_TRIG_MASK;
219 gpio->irq_type[data->hwirq] |= new_type;
220 tqmx86_gpio_irq_config(gpio, data->hwirq);
221
222 return 0;
223 }
224
tqmx86_gpio_irq_handler(struct irq_desc * desc)225 static void tqmx86_gpio_irq_handler(struct irq_desc *desc)
226 {
227 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
228 struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
229 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
230 unsigned long irq_bits;
231 int i, hwirq;
232 u8 irq_status;
233
234 chained_irq_enter(irq_chip, desc);
235
236 irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
237 tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
238
239 irq_bits = irq_status;
240
241 scoped_guard(raw_spinlock_irqsave, &gpio->spinlock) {
242 for_each_set_bit(i, &irq_bits, TQMX86_NGPI) {
243 hwirq = i + TQMX86_NGPO;
244
245 /*
246 * Edge-both triggers are implemented by flipping the
247 * edge trigger after each interrupt, as the controller
248 * only supports either rising or falling edge triggers,
249 * but not both.
250 *
251 * Internally, the TQMx86 GPIO controller has separate
252 * status registers for rising and falling edge
253 * interrupts. GPIIC configures which bits from which
254 * register are visible in the interrupt status register
255 * GPIIS and defines what triggers the parent IRQ line.
256 * Writing to GPIIS always clears both rising and
257 * falling interrupt flags internally, regardless of the
258 * currently configured trigger.
259 *
260 * In consequence, we can cleanly implement the
261 * edge-both trigger in software by first clearing the
262 * interrupt and then setting the new trigger based on
263 * the current GPIO input in tqmx86_gpio_irq_config() -
264 * even if an edge arrives between reading the input and
265 * setting the trigger, we will have a new interrupt
266 * pending.
267 */
268 if ((gpio->irq_type[hwirq] & TQMX86_INT_TRIG_MASK) ==
269 TQMX86_INT_TRIG_BOTH)
270 tqmx86_gpio_irq_config(gpio, hwirq);
271 }
272 }
273
274 for_each_set_bit(i, &irq_bits, TQMX86_NGPI)
275 generic_handle_domain_irq(gpio->chip.irq.domain,
276 i + TQMX86_NGPO);
277
278 chained_irq_exit(irq_chip, desc);
279 }
280
281 /* Minimal runtime PM is needed by the IRQ subsystem */
tqmx86_gpio_runtime_suspend(struct device * dev)282 static int __maybe_unused tqmx86_gpio_runtime_suspend(struct device *dev)
283 {
284 return 0;
285 }
286
tqmx86_gpio_runtime_resume(struct device * dev)287 static int __maybe_unused tqmx86_gpio_runtime_resume(struct device *dev)
288 {
289 return 0;
290 }
291
292 static const struct dev_pm_ops tqmx86_gpio_dev_pm_ops = {
293 SET_RUNTIME_PM_OPS(tqmx86_gpio_runtime_suspend,
294 tqmx86_gpio_runtime_resume, NULL)
295 };
296
tqmx86_init_irq_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)297 static void tqmx86_init_irq_valid_mask(struct gpio_chip *chip,
298 unsigned long *valid_mask,
299 unsigned int ngpios)
300 {
301 /* Only GPIOs 4-7 are valid for interrupts. Clear the others */
302 clear_bit(0, valid_mask);
303 clear_bit(1, valid_mask);
304 clear_bit(2, valid_mask);
305 clear_bit(3, valid_mask);
306 }
307
tqmx86_gpio_irq_print_chip(struct irq_data * d,struct seq_file * p)308 static void tqmx86_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
309 {
310 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
311
312 seq_puts(p, gc->label);
313 }
314
315 static const struct irq_chip tqmx86_gpio_irq_chip = {
316 .irq_mask = tqmx86_gpio_irq_mask,
317 .irq_unmask = tqmx86_gpio_irq_unmask,
318 .irq_set_type = tqmx86_gpio_irq_set_type,
319 .irq_print_chip = tqmx86_gpio_irq_print_chip,
320 .flags = IRQCHIP_IMMUTABLE,
321 GPIOCHIP_IRQ_RESOURCE_HELPERS,
322 };
323
tqmx86_gpio_probe(struct platform_device * pdev)324 static int tqmx86_gpio_probe(struct platform_device *pdev)
325 {
326 struct device *dev = &pdev->dev;
327 struct tqmx86_gpio_data *gpio;
328 struct gpio_chip *chip;
329 struct gpio_irq_chip *girq;
330 void __iomem *io_base;
331 struct resource *res;
332 int ret, irq;
333
334 irq = platform_get_irq_optional(pdev, 0);
335 if (irq < 0 && irq != -ENXIO)
336 return irq;
337
338 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
339 if (!res) {
340 dev_err(&pdev->dev, "Cannot get I/O\n");
341 return -ENODEV;
342 }
343
344 io_base = devm_ioport_map(&pdev->dev, res->start, resource_size(res));
345 if (!io_base)
346 return -ENOMEM;
347
348 gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
349 if (!gpio)
350 return -ENOMEM;
351
352 raw_spin_lock_init(&gpio->spinlock);
353 gpio->io_base = io_base;
354
355 tqmx86_gpio_write(gpio, (u8)~TQMX86_DIR_INPUT_MASK, TQMX86_GPIODD);
356
357 /*
358 * Reading the previous output state is not possible with TQMx86 hardware.
359 * Initialize all outputs to 0 to have a defined state that matches the
360 * shadow register.
361 */
362 tqmx86_gpio_write(gpio, 0, TQMX86_GPIOD);
363
364 chip = &gpio->chip;
365 chip->label = "gpio-tqmx86";
366 chip->owner = THIS_MODULE;
367 chip->can_sleep = false;
368 chip->base = -1;
369 chip->direction_input = tqmx86_gpio_direction_input;
370 chip->direction_output = tqmx86_gpio_direction_output;
371 chip->get_direction = tqmx86_gpio_get_direction;
372 chip->get = tqmx86_gpio_get;
373 chip->set_rv = tqmx86_gpio_set;
374 chip->ngpio = TQMX86_NGPIO;
375 chip->parent = pdev->dev.parent;
376
377 pm_runtime_enable(&pdev->dev);
378
379 if (irq > 0) {
380 u8 irq_status;
381
382 /* Mask all interrupts */
383 tqmx86_gpio_write(gpio, 0, TQMX86_GPIIC);
384
385 /* Clear all pending interrupts */
386 irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
387 tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
388
389 girq = &chip->irq;
390 gpio_irq_chip_set_chip(girq, &tqmx86_gpio_irq_chip);
391 girq->parent_handler = tqmx86_gpio_irq_handler;
392 girq->num_parents = 1;
393 girq->parents = devm_kcalloc(&pdev->dev, 1,
394 sizeof(*girq->parents),
395 GFP_KERNEL);
396 if (!girq->parents) {
397 ret = -ENOMEM;
398 goto out_pm_dis;
399 }
400 girq->parents[0] = irq;
401 girq->default_type = IRQ_TYPE_NONE;
402 girq->handler = handle_simple_irq;
403 girq->init_valid_mask = tqmx86_init_irq_valid_mask;
404
405 irq_domain_set_pm_device(girq->domain, dev);
406 }
407
408 ret = devm_gpiochip_add_data(dev, chip, gpio);
409 if (ret) {
410 dev_err(dev, "Could not register GPIO chip\n");
411 goto out_pm_dis;
412 }
413
414 dev_info(dev, "GPIO functionality initialized with %d pins\n",
415 chip->ngpio);
416
417 return 0;
418
419 out_pm_dis:
420 pm_runtime_disable(&pdev->dev);
421
422 return ret;
423 }
424
425 static struct platform_driver tqmx86_gpio_driver = {
426 .driver = {
427 .name = "tqmx86-gpio",
428 .pm = &tqmx86_gpio_dev_pm_ops,
429 },
430 .probe = tqmx86_gpio_probe,
431 };
432
433 module_platform_driver(tqmx86_gpio_driver);
434
435 MODULE_DESCRIPTION("TQMx86 PLD GPIO Driver");
436 MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
437 MODULE_LICENSE("GPL");
438 MODULE_ALIAS("platform:tqmx86-gpio");
439