1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 Samsung Electronics Co., Ltd.
4 * Author: Sunyeal Hong <sunyeal.hong@samsung.com>
5 *
6 * Common Clock Framework support for ExynosAuto v920 SoC.
7 */
8
9 #include <linux/clk-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13
14 #include <dt-bindings/clock/samsung,exynosautov920.h>
15
16 #include "clk.h"
17 #include "clk-exynos-arm64.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
21 #define CLKS_NR_CPUCL0 (CLK_DOUT_CPUCL0_NOCP + 1)
22 #define CLKS_NR_CPUCL1 (CLK_DOUT_CPUCL1_NOCP + 1)
23 #define CLKS_NR_CPUCL2 (CLK_DOUT_CPUCL2_NOCP + 1)
24 #define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
25 #define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
26 #define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
27 #define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
28 #define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
29 #define CLKS_NR_HSI2 (CLK_DOUT_HSI2_ETHERNET_PTP + 1)
30 #define CLKS_NR_M2M (CLK_DOUT_M2M_NOCP + 1)
31 #define CLKS_NR_MFC (CLK_DOUT_MFC_NOCP + 1)
32
33 /* ---- CMU_TOP ------------------------------------------------------------ */
34
35 /* Register Offset definitions for CMU_TOP (0x11000000) */
36 #define PLL_LOCKTIME_PLL_MMC 0x0004
37 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
38 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
39 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
40 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
41 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
42 #define PLL_LOCKTIME_PLL_SHARED5 0x0018
43 #define PLL_CON0_PLL_MMC 0x0140
44 #define PLL_CON3_PLL_MMC 0x014c
45 #define PLL_CON0_PLL_SHARED0 0x0180
46 #define PLL_CON3_PLL_SHARED0 0x018c
47 #define PLL_CON0_PLL_SHARED1 0x01c0
48 #define PLL_CON3_PLL_SHARED1 0x01cc
49 #define PLL_CON0_PLL_SHARED2 0x0200
50 #define PLL_CON3_PLL_SHARED2 0x020c
51 #define PLL_CON0_PLL_SHARED3 0x0240
52 #define PLL_CON3_PLL_SHARED3 0x024c
53 #define PLL_CON0_PLL_SHARED4 0x0280
54 #define PLL_CON3_PLL_SHARED4 0x028c
55 #define PLL_CON0_PLL_SHARED5 0x02c0
56 #define PLL_CON3_PLL_SHARED5 0x02cc
57
58 /* MUX */
59 #define CLK_CON_MUX_MUX_CLKCMU_ACC_NOC 0x1000
60 #define CLK_CON_MUX_MUX_CLKCMU_APM_NOC 0x1004
61 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
62 #define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC 0x100c
63 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0 0x1010
64 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1 0x1014
65 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2 0x1018
66 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3 0x101c
67 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1020
68 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
69 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1028
70 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
71 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
72 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
73 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER 0x1038
74 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x103c
75 #define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC 0x1040
76 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
77 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC 0x1048
78 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC 0x104c
79 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM 0x1050
80 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC 0x1054
81 #define CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC 0x1058
82 #define CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC 0x105c
83 #define CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC 0x1060
84 #define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC 0x1064
85 #define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP 0x1068
86 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x106c
87 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC 0x1070
88 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC 0x1074
89 #define CLK_CON_MUX_MUX_CLKCMU_ACC_ORB 0x1078
90 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA 0x107c
91 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x1080
92 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC 0x1084
93 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD 0x1088
94 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET 0x108c
95 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC 0x1090
96 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS 0x1094
97 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x1098
98 #define CLK_CON_MUX_MUX_CLKCMU_ISP_NOC 0x109c
99 #define CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG 0x10a0
100 #define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC 0x10a4
101 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10a8
102 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x10ac
103 #define CLK_CON_MUX_MUX_CLKCMU_MFD_NOC 0x10b0
104 #define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP 0x10b4
105 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10b8
106 #define CLK_CON_MUX_MUX_CLKCMU_MISC_NOC 0x10bc
107 #define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC 0x10c0
108 #define CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC 0x10c4
109 #define CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC 0x10c8
110 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10cc
111 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC 0x10d0
112 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d4
113 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC 0x10d8
114 #define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC 0x10dc
115 #define CLK_CON_MUX_MUX_CLKCMU_SNW_NOC 0x10e0
116 #define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC 0x10e4
117 #define CLK_CON_MUX_MUX_CLKCMU_TAA_NOC 0x10e8
118 #define CLK_CON_MUX_MUX_CLK_CMU_NOCP 0x10ec
119 #define CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT 0x10f0
120 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
121
122 /* DIV */
123 #define CLK_CON_DIV_CLKCMU_ACC_NOC 0x1800
124 #define CLK_CON_DIV_CLKCMU_APM_NOC 0x1804
125 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1808
126 #define CLK_CON_DIV_CLKCMU_AUD_NOC 0x180c
127 #define CLK_CON_DIV_CLKCMU_CIS_MCLK0 0x1810
128 #define CLK_CON_DIV_CLKCMU_CIS_MCLK1 0x1814
129 #define CLK_CON_DIV_CLKCMU_CIS_MCLK2 0x1818
130 #define CLK_CON_DIV_CLKCMU_CIS_MCLK3 0x181c
131 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
132 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1824
133 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
134 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
135 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
136 #define CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER 0x1834
137 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1838
138 #define CLK_CON_DIV_CLKCMU_DNC_NOC 0x183c
139 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
140 #define CLK_CON_DIV_CLKCMU_DPTX_DPOSC 0x1844
141 #define CLK_CON_DIV_CLKCMU_DPTX_NOC 0x1848
142 #define CLK_CON_DIV_CLKCMU_DPUB_DSIM 0x184c
143 #define CLK_CON_DIV_CLKCMU_DPUB_NOC 0x1850
144 #define CLK_CON_DIV_CLKCMU_DPUF0_NOC 0x1854
145 #define CLK_CON_DIV_CLKCMU_DPUF1_NOC 0x1858
146 #define CLK_CON_DIV_CLKCMU_DPUF2_NOC 0x185c
147 #define CLK_CON_DIV_CLKCMU_DSP_NOC 0x1860
148 #define CLK_CON_DIV_CLKCMU_G3D_NOCP 0x1864
149 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868
150 #define CLK_CON_DIV_CLKCMU_GNPU_NOC 0x186c
151 #define CLK_CON_DIV_CLKCMU_HSI0_NOC 0x1870
152 #define CLK_CON_DIV_CLKCMU_ACC_ORB 0x1874
153 #define CLK_CON_DIV_CLKCMU_GNPU_XMAA 0x1878
154 #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x187c
155 #define CLK_CON_DIV_CLKCMU_HSI1_NOC 0x1880
156 #define CLK_CON_DIV_CLKCMU_HSI1_USBDRD 0x1884
157 #define CLK_CON_DIV_CLKCMU_HSI2_ETHERNET 0x1888
158 #define CLK_CON_DIV_CLKCMU_HSI2_NOC 0x188c
159 #define CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS 0x1890
160 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x1894
161 #define CLK_CON_DIV_CLKCMU_ISP_NOC 0x1898
162 #define CLK_CON_DIV_CLKCMU_M2M_JPEG 0x189c
163 #define CLK_CON_DIV_CLKCMU_M2M_NOC 0x18a0
164 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18a4
165 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x18a8
166 #define CLK_CON_DIV_CLKCMU_MFD_NOC 0x18ac
167 #define CLK_CON_DIV_CLKCMU_MIF_NOCP 0x18b0
168 #define CLK_CON_DIV_CLKCMU_MISC_NOC 0x18b4
169 #define CLK_CON_DIV_CLKCMU_NOCL0_NOC 0x18b8
170 #define CLK_CON_DIV_CLKCMU_NOCL1_NOC 0x18bc
171 #define CLK_CON_DIV_CLKCMU_NOCL2_NOC 0x18c0
172 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c4
173 #define CLK_CON_DIV_CLKCMU_PERIC0_NOC 0x18c8
174 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18cc
175 #define CLK_CON_DIV_CLKCMU_PERIC1_NOC 0x18d0
176 #define CLK_CON_DIV_CLKCMU_SDMA_NOC 0x18d4
177 #define CLK_CON_DIV_CLKCMU_SNW_NOC 0x18d8
178 #define CLK_CON_DIV_CLKCMU_SSP_NOC 0x18dc
179 #define CLK_CON_DIV_CLKCMU_TAA_NOC 0x18e0
180 #define CLK_CON_DIV_CLK_ADD_CH_CLK 0x18e4
181 #define CLK_CON_DIV_CLK_CMU_PLLCLKOUT 0x18e8
182 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18ec
183 #define CLK_CON_DIV_DIV_CLK_CMU_NOCP 0x18f0
184
185 static const unsigned long top_clk_regs[] __initconst = {
186 PLL_LOCKTIME_PLL_MMC,
187 PLL_LOCKTIME_PLL_SHARED0,
188 PLL_LOCKTIME_PLL_SHARED1,
189 PLL_LOCKTIME_PLL_SHARED2,
190 PLL_LOCKTIME_PLL_SHARED3,
191 PLL_LOCKTIME_PLL_SHARED4,
192 PLL_LOCKTIME_PLL_SHARED5,
193 PLL_CON0_PLL_MMC,
194 PLL_CON3_PLL_MMC,
195 PLL_CON0_PLL_SHARED0,
196 PLL_CON3_PLL_SHARED0,
197 PLL_CON0_PLL_SHARED1,
198 PLL_CON3_PLL_SHARED1,
199 PLL_CON0_PLL_SHARED2,
200 PLL_CON3_PLL_SHARED2,
201 PLL_CON0_PLL_SHARED3,
202 PLL_CON3_PLL_SHARED3,
203 PLL_CON0_PLL_SHARED4,
204 PLL_CON3_PLL_SHARED4,
205 PLL_CON0_PLL_SHARED5,
206 PLL_CON3_PLL_SHARED5,
207 CLK_CON_MUX_MUX_CLKCMU_ACC_NOC,
208 CLK_CON_MUX_MUX_CLKCMU_APM_NOC,
209 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
210 CLK_CON_MUX_MUX_CLKCMU_AUD_NOC,
211 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0,
212 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1,
213 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2,
214 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3,
215 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
216 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
217 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
218 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
219 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
220 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
221 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER,
222 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
223 CLK_CON_MUX_MUX_CLKCMU_DNC_NOC,
224 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC,
225 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC,
226 CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC,
227 CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM,
228 CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC,
229 CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC,
230 CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC,
231 CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC,
232 CLK_CON_MUX_MUX_CLKCMU_DSP_NOC,
233 CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP,
234 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
235 CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC,
236 CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC,
237 CLK_CON_MUX_MUX_CLKCMU_ACC_ORB,
238 CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA,
239 CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
240 CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC,
241 CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD,
242 CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET,
243 CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC,
244 CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS,
245 CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
246 CLK_CON_MUX_MUX_CLKCMU_ISP_NOC,
247 CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG,
248 CLK_CON_MUX_MUX_CLKCMU_M2M_NOC,
249 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
250 CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
251 CLK_CON_MUX_MUX_CLKCMU_MFD_NOC,
252 CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP,
253 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
254 CLK_CON_MUX_MUX_CLKCMU_MISC_NOC,
255 CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC,
256 CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC,
257 CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC,
258 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
259 CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC,
260 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
261 CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC,
262 CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC,
263 CLK_CON_MUX_MUX_CLKCMU_SNW_NOC,
264 CLK_CON_MUX_MUX_CLKCMU_SSP_NOC,
265 CLK_CON_MUX_MUX_CLKCMU_TAA_NOC,
266 CLK_CON_MUX_MUX_CLK_CMU_NOCP,
267 CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT,
268 CLK_CON_MUX_MUX_CMU_CMUREF,
269 CLK_CON_DIV_CLKCMU_ACC_NOC,
270 CLK_CON_DIV_CLKCMU_APM_NOC,
271 CLK_CON_DIV_CLKCMU_AUD_CPU,
272 CLK_CON_DIV_CLKCMU_AUD_NOC,
273 CLK_CON_DIV_CLKCMU_CIS_MCLK0,
274 CLK_CON_DIV_CLKCMU_CIS_MCLK1,
275 CLK_CON_DIV_CLKCMU_CIS_MCLK2,
276 CLK_CON_DIV_CLKCMU_CIS_MCLK3,
277 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
278 CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
279 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
280 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
281 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
282 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER,
283 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
284 CLK_CON_DIV_CLKCMU_DNC_NOC,
285 CLK_CON_DIV_CLKCMU_DPTX_DPGTC,
286 CLK_CON_DIV_CLKCMU_DPTX_DPOSC,
287 CLK_CON_DIV_CLKCMU_DPTX_NOC,
288 CLK_CON_DIV_CLKCMU_DPUB_DSIM,
289 CLK_CON_DIV_CLKCMU_DPUB_NOC,
290 CLK_CON_DIV_CLKCMU_DPUF0_NOC,
291 CLK_CON_DIV_CLKCMU_DPUF1_NOC,
292 CLK_CON_DIV_CLKCMU_DPUF2_NOC,
293 CLK_CON_DIV_CLKCMU_DSP_NOC,
294 CLK_CON_DIV_CLKCMU_G3D_NOCP,
295 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
296 CLK_CON_DIV_CLKCMU_GNPU_NOC,
297 CLK_CON_DIV_CLKCMU_HSI0_NOC,
298 CLK_CON_DIV_CLKCMU_ACC_ORB,
299 CLK_CON_DIV_CLKCMU_GNPU_XMAA,
300 CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
301 CLK_CON_DIV_CLKCMU_HSI1_NOC,
302 CLK_CON_DIV_CLKCMU_HSI1_USBDRD,
303 CLK_CON_DIV_CLKCMU_HSI2_ETHERNET,
304 CLK_CON_DIV_CLKCMU_HSI2_NOC,
305 CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS,
306 CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
307 CLK_CON_DIV_CLKCMU_ISP_NOC,
308 CLK_CON_DIV_CLKCMU_M2M_JPEG,
309 CLK_CON_DIV_CLKCMU_M2M_NOC,
310 CLK_CON_DIV_CLKCMU_MFC_MFC,
311 CLK_CON_DIV_CLKCMU_MFC_WFD,
312 CLK_CON_DIV_CLKCMU_MFD_NOC,
313 CLK_CON_DIV_CLKCMU_MIF_NOCP,
314 CLK_CON_DIV_CLKCMU_MISC_NOC,
315 CLK_CON_DIV_CLKCMU_NOCL0_NOC,
316 CLK_CON_DIV_CLKCMU_NOCL1_NOC,
317 CLK_CON_DIV_CLKCMU_NOCL2_NOC,
318 CLK_CON_DIV_CLKCMU_PERIC0_IP,
319 CLK_CON_DIV_CLKCMU_PERIC0_NOC,
320 CLK_CON_DIV_CLKCMU_PERIC1_IP,
321 CLK_CON_DIV_CLKCMU_PERIC1_NOC,
322 CLK_CON_DIV_CLKCMU_SDMA_NOC,
323 CLK_CON_DIV_CLKCMU_SNW_NOC,
324 CLK_CON_DIV_CLKCMU_SSP_NOC,
325 CLK_CON_DIV_CLKCMU_TAA_NOC,
326 CLK_CON_DIV_CLK_ADD_CH_CLK,
327 CLK_CON_DIV_CLK_CMU_PLLCLKOUT,
328 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
329 CLK_CON_DIV_DIV_CLK_CMU_NOCP,
330 };
331
332 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
333 /* CMU_TOP_PURECLKCOMP */
334 PLL(pll_531x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
335 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
336 PLL(pll_531x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
337 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
338 PLL(pll_531x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
339 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
340 PLL(pll_531x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
341 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
342 PLL(pll_531x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
343 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
344 PLL(pll_531x, FOUT_SHARED5_PLL, "fout_shared5_pll", "oscclk",
345 PLL_LOCKTIME_PLL_SHARED5, PLL_CON3_PLL_SHARED5, NULL),
346 PLL(pll_531x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
347 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
348 };
349
350 /* List of parent clocks for Muxes in CMU_TOP */
351 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
352 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
353 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
354 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
355 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
356 PNAME(mout_shared5_pll_p) = { "oscclk", "fout_shared5_pll" };
357 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
358
359 PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
360 "dout_shared2_div4", "dout_shared4_div4" };
361
362 PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
363
364 PNAME(mout_clkcmu_acc_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
365 "dout_shared4_div2", "dout_shared1_div3",
366 "dout_shared2_div3", "dout_shared5_div1",
367 "dout_shared3_div1", "oscclk" };
368
369 PNAME(mout_clkcmu_acc_orb_p) = { "dout_shared2_div2", "dout_shared0_div3",
370 "dout_shared1_div2", "dout_shared1_div3",
371 "dout_shared2_div3", "fout_shared5_pll",
372 "fout_shared3_pll", "oscclk" };
373
374 PNAME(mout_clkcmu_apm_noc_p) = { "dout_shared2_div2", "dout_shared1_div4",
375 "dout_shared2_div4", "dout_shared4_div4" };
376
377 PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
378 "dout_shared2_div2", "dout_shared0_div3",
379 "dout_shared4_div2", "dout_shared1_div3",
380 "dout_shared2_div3", "dout_shared4_div3" };
381
382 PNAME(mout_clkcmu_aud_noc_p) = { "dout_shared2_div2", "dout_shared4_div2",
383 "dout_shared1_div2", "dout_shared2_div3" };
384
385 PNAME(mout_clkcmu_cpucl0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
386 "dout_shared2_div2", "dout_shared4_div2" };
387
388 PNAME(mout_clkcmu_cpucl0_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
389 "dout_shared0_div2", "dout_shared1_div2",
390 "dout_shared2_div2", "dout_shared4_div2",
391 "dout_shared2_div3", "fout_shared3_pll" };
392
393 PNAME(mout_clkcmu_cpucl0_dbg_p) = { "dout_shared2_div2", "dout_shared0_div3",
394 "dout_shared4_div2", "dout_shared0_div4" };
395
396 PNAME(mout_clkcmu_cpucl1_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
397 "dout_shared2_div2", "dout_shared4_div2" };
398
399 PNAME(mout_clkcmu_cpucl1_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
400 "dout_shared0_div2", "dout_shared1_div2",
401 "dout_shared2_div2", "dout_shared4_div2",
402 "dout_shared2_div3", "fout_shared3_pll" };
403
404 PNAME(mout_clkcmu_cpucl2_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
405 "dout_shared2_div2", "dout_shared4_div2" };
406
407 PNAME(mout_clkcmu_cpucl2_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
408 "dout_shared0_div2", "dout_shared1_div2",
409 "dout_shared2_div2", "dout_shared4_div2",
410 "dout_shared2_div3", "fout_shared3_pll" };
411
412 PNAME(mout_clkcmu_dnc_noc_p) = { "dout_shared1_div2", "dout_shared2_div2",
413 "dout_shared0_div3", "dout_shared4_div2",
414 "dout_shared1_div3", "dout_shared2_div3",
415 "dout_shared1_div4", "fout_shared3_pll" };
416
417 PNAME(mout_clkcmu_dptx_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
418 "dout_shared1_div4", "dout_shared2_div4" };
419
420 PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3",
421 "dout_shared2_div4", "dout_shared4_div4" };
422
423 PNAME(mout_clkcmu_dptx_dposc_p) = { "oscclk", "dout_shared2_div4" };
424
425 PNAME(mout_clkcmu_dpub_noc_p) = { "dout_shared4_div2", "dout_shared1_div3",
426 "dout_shared2_div3", "dout_shared1_div4",
427 "dout_shared2_div4", "dout_shared4_div4",
428 "fout_shared3_pll" };
429
430 PNAME(mout_clkcmu_dpub_dsim_p) = { "dout_shared2_div3", "dout_shared2_div4" };
431
432 PNAME(mout_clkcmu_dpuf_noc_p) = { "dout_shared4_div2", "dout_shared1_div3",
433 "dout_shared2_div3", "dout_shared1_div4",
434 "dout_shared2_div4", "dout_shared4_div4",
435 "fout_shared3_pll" };
436
437 PNAME(mout_clkcmu_dsp_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
438 "dout_shared2_div2", "dout_shared0_div3",
439 "dout_shared4_div2", "dout_shared1_div3",
440 "fout_shared5_pll", "fout_shared3_pll" };
441
442 PNAME(mout_clkcmu_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
443 "dout_shared2_div2", "dout_shared4_div2" };
444
445 PNAME(mout_clkcmu_g3d_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4",
446 "dout_shared2_div4", "dout_shared4_div4" };
447
448 PNAME(mout_clkcmu_gnpu_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
449 "dout_shared2_div2", "dout_shared0_div3",
450 "dout_shared4_div2", "dout_shared2_div3",
451 "fout_shared5_pll", "fout_shared3_pll" };
452
453 PNAME(mout_clkcmu_hsi0_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
454 "dout_shared1_div4", "dout_shared2_div4" };
455
456 PNAME(mout_clkcmu_hsi1_noc_p) = { "dout_shared2_div3", "dout_shared1_div4",
457 "dout_shared2_div4", "dout_shared4_div4" };
458
459 PNAME(mout_clkcmu_hsi1_usbdrd_p) = { "oscclk", "dout_shared2_div3",
460 "dout_shared2_div4", "dout_shared4_div4" };
461
462 PNAME(mout_clkcmu_hsi1_mmc_card_p) = { "oscclk", "dout_shared2_div2",
463 "dout_shared4_div2", "fout_mmc_pll" };
464
465 PNAME(mout_clkcmu_hsi2_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
466 "dout_shared1_div4", "dout_shared2_div4" };
467
468 PNAME(mout_clkcmu_hsi2_noc_ufs_p) = { "dout_shared4_div2", "dout_shared2_div3",
469 "dout_shared1_div4", "dout_shared2_div2" };
470
471 PNAME(mout_clkcmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared2_div3",
472 "dout_shared2_div4", "dout_shared4_div4" };
473
474 PNAME(mout_clkcmu_hsi2_ethernet_p) = { "oscclk", "dout_shared2_div2",
475 "dout_shared0_div3", "dout_shared1_div3" };
476
477 PNAME(mout_clkcmu_isp_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
478 "dout_shared4_div2", "dout_shared1_div3",
479 "dout_shared2_div3", "fout_shared5_pll",
480 "fout_shared3_pll", "oscclk" };
481
482 PNAME(mout_clkcmu_m2m_noc_p) = { "dout_shared0_div3", "dout_shared4_div2",
483 "dout_shared2_div3", "dout_shared1_div4" };
484
485 PNAME(mout_clkcmu_m2m_jpeg_p) = { "dout_shared0_div3", "dout_shared4_div2",
486 "dout_shared2_div3", "dout_shared1_div4" };
487
488 PNAME(mout_clkcmu_mfc_mfc_p) = { "dout_shared0_div3", "dout_shared4_div2",
489 "dout_shared2_div3", "dout_shared1_div4" };
490
491 PNAME(mout_clkcmu_mfc_wfd_p) = { "dout_shared0_div3", "dout_shared4_div2",
492 "dout_shared2_div3", "dout_shared1_div4" };
493
494 PNAME(mout_clkcmu_mfd_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
495 "dout_shared4_div2", "dout_shared1_div3",
496 "dout_shared2_div3", "fout_shared5_pll",
497 "fout_shared3_pll", "oscclk" };
498
499 PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
500 "fout_shared2_pll", "fout_shared4_pll",
501 "dout_shared0_div2", "dout_shared1_div2",
502 "dout_shared2_div2", "fout_shared5_pll" };
503
504 PNAME(mout_clkcmu_mif_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4",
505 "dout_shared2_div4", "dout_shared4_div4" };
506
507 PNAME(mout_clkcmu_misc_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
508 "dout_shared1_div4", "dout_shared2_div4" };
509
510 PNAME(mout_clkcmu_nocl0_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
511 "dout_shared2_div2", "dout_shared0_div3",
512 "dout_shared4_div2", "dout_shared1_div3",
513 "dout_shared2_div3", "fout_shared3_pll" };
514
515 PNAME(mout_clkcmu_nocl1_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
516 "dout_shared4_div2", "dout_shared1_div3",
517 "dout_shared2_div3", "fout_shared5_pll",
518 "fout_shared3_pll", "oscclk" };
519
520 PNAME(mout_clkcmu_nocl2_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
521 "dout_shared4_div2", "dout_shared1_div3",
522 "dout_shared2_div3", "fout_shared5_pll",
523 "fout_shared3_pll", "oscclk" };
524
525 PNAME(mout_clkcmu_peric0_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" };
526
527 PNAME(mout_clkcmu_peric0_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" };
528
529 PNAME(mout_clkcmu_peric1_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" };
530
531 PNAME(mout_clkcmu_peric1_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" };
532
533 PNAME(mout_clkcmu_sdma_noc_p) = { "dout_shared1_div2", "dout_shared2_div2",
534 "dout_shared0_div3", "dout_shared4_div2",
535 "dout_shared1_div3", "dout_shared2_div3",
536 "dout_shared1_div4", "fout_shared3_pll" };
537
538 PNAME(mout_clkcmu_snw_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
539 "dout_shared4_div2", "dout_shared1_div3",
540 "dout_shared2_div3", "fout_shared5_pll",
541 "fout_shared3_pll", "oscclk" };
542
543 PNAME(mout_clkcmu_ssp_noc_p) = { "dout_shared2_div3", "dout_shared1_div4",
544 "dout_shared2_div2", "dout_shared4_div4" };
545
546 PNAME(mout_clkcmu_taa_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
547 "dout_shared4_div2", "dout_shared1_div3",
548 "dout_shared2_div3", "fout_shared5_pll",
549 "fout_shared3_pll", "oscclk" };
550
551 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
552 /* CMU_TOP_PURECLKCOMP */
553 MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
554 PLL_CON0_PLL_SHARED0, 4, 1),
555 MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
556 PLL_CON0_PLL_SHARED1, 4, 1),
557 MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
558 PLL_CON0_PLL_SHARED2, 4, 1),
559 MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
560 PLL_CON0_PLL_SHARED3, 4, 1),
561 MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
562 PLL_CON0_PLL_SHARED4, 4, 1),
563 MUX(MOUT_SHARED5_PLL, "mout_shared5_pll", mout_shared5_pll_p,
564 PLL_CON0_PLL_SHARED5, 4, 1),
565 MUX(MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
566 PLL_CON0_PLL_MMC, 4, 1),
567
568 /* BOOST */
569 MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
570 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
571 MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref",
572 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
573
574 /* ACC */
575 MUX(MOUT_CLKCMU_ACC_NOC, "mout_clkcmu_acc_noc",
576 mout_clkcmu_acc_noc_p, CLK_CON_MUX_MUX_CLKCMU_ACC_NOC, 0, 3),
577 MUX(MOUT_CLKCMU_ACC_ORB, "mout_clkcmu_acc_orb",
578 mout_clkcmu_acc_orb_p, CLK_CON_MUX_MUX_CLKCMU_ACC_ORB, 0, 3),
579
580 /* APM */
581 MUX(MOUT_CLKCMU_APM_NOC, "mout_clkcmu_apm_noc",
582 mout_clkcmu_apm_noc_p, CLK_CON_MUX_MUX_CLKCMU_APM_NOC, 0, 2),
583
584 /* AUD */
585 MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu",
586 mout_clkcmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
587 MUX(MOUT_CLKCMU_AUD_NOC, "mout_clkcmu_aud_noc",
588 mout_clkcmu_aud_noc_p, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0, 2),
589
590 /* CPUCL0 */
591 MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch",
592 mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
593 0, 2),
594 MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster",
595 mout_clkcmu_cpucl0_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
596 0, 3),
597 MUX(MOUT_CLKCMU_CPUCL0_DBG, "mout_clkcmu_cpucl0_dbg",
598 mout_clkcmu_cpucl0_dbg_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
599 0, 2),
600
601 /* CPUCL1 */
602 MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch",
603 mout_clkcmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
604 0, 2),
605 MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster",
606 mout_clkcmu_cpucl1_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
607 0, 3),
608
609 /* CPUCL2 */
610 MUX(MOUT_CLKCMU_CPUCL2_SWITCH, "mout_clkcmu_cpucl2_switch",
611 mout_clkcmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
612 0, 2),
613 MUX(MOUT_CLKCMU_CPUCL2_CLUSTER, "mout_clkcmu_cpucl2_cluster",
614 mout_clkcmu_cpucl2_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER,
615 0, 3),
616
617 /* DNC */
618 MUX(MOUT_CLKCMU_DNC_NOC, "mout_clkcmu_dnc_noc",
619 mout_clkcmu_dnc_noc_p, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0, 3),
620
621 /* DPTX */
622 MUX(MOUT_CLKCMU_DPTX_NOC, "mout_clkcmu_dptx_noc",
623 mout_clkcmu_dptx_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC, 0, 2),
624 MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc",
625 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
626 MUX(MOUT_CLKCMU_DPTX_DPOSC, "mout_clkcmu_dptx_dposc",
627 mout_clkcmu_dptx_dposc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC, 0, 1),
628
629 /* DPUB */
630 MUX(MOUT_CLKCMU_DPUB_NOC, "mout_clkcmu_dpub_noc",
631 mout_clkcmu_dpub_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC, 0, 3),
632 MUX(MOUT_CLKCMU_DPUB_DSIM, "mout_clkcmu_dpub_dsim",
633 mout_clkcmu_dpub_dsim_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0, 1),
634
635 /* DPUF */
636 MUX(MOUT_CLKCMU_DPUF0_NOC, "mout_clkcmu_dpuf0_noc",
637 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC, 0, 3),
638 MUX(MOUT_CLKCMU_DPUF1_NOC, "mout_clkcmu_dpuf1_noc",
639 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC, 0, 3),
640 MUX(MOUT_CLKCMU_DPUF2_NOC, "mout_clkcmu_dpuf2_noc",
641 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC, 0, 3),
642
643 /* DSP */
644 MUX(MOUT_CLKCMU_DSP_NOC, "mout_clkcmu_dsp_noc",
645 mout_clkcmu_dsp_noc_p, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0, 3),
646
647 /* G3D */
648 MUX(MOUT_CLKCMU_G3D_SWITCH, "mout_clkcmu_g3d_switch",
649 mout_clkcmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
650 MUX(MOUT_CLKCMU_G3D_NOCP, "mout_clkcmu_g3d_nocp",
651 mout_clkcmu_g3d_nocp_p, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0, 2),
652
653 /* GNPU */
654 MUX(MOUT_CLKCMU_GNPU_NOC, "mout_clkcmu_gnpu_noc",
655 mout_clkcmu_gnpu_noc_p, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0, 3),
656
657 /* HSI0 */
658 MUX(MOUT_CLKCMU_HSI0_NOC, "mout_clkcmu_hsi0_noc",
659 mout_clkcmu_hsi0_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0, 2),
660
661 /* HSI1 */
662 MUX(MOUT_CLKCMU_HSI1_NOC, "mout_clkcmu_hsi1_noc",
663 mout_clkcmu_hsi1_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC,
664 0, 2),
665 MUX(MOUT_CLKCMU_HSI1_USBDRD, "mout_clkcmu_hsi1_usbdrd",
666 mout_clkcmu_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD,
667 0, 2),
668 MUX(MOUT_CLKCMU_HSI1_MMC_CARD, "mout_clkcmu_hsi1_mmc_card",
669 mout_clkcmu_hsi1_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
670 0, 2),
671
672 /* HSI2 */
673 MUX(MOUT_CLKCMU_HSI2_NOC, "mout_clkcmu_hsi2_noc",
674 mout_clkcmu_hsi2_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC,
675 0, 2),
676 MUX(MOUT_CLKCMU_HSI2_NOC_UFS, "mout_clkcmu_hsi2_noc_ufs",
677 mout_clkcmu_hsi2_noc_ufs_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS,
678 0, 2),
679 MUX(MOUT_CLKCMU_HSI2_UFS_EMBD, "mout_clkcmu_hsi2_ufs_embd",
680 mout_clkcmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
681 0, 2),
682 MUX(MOUT_CLKCMU_HSI2_ETHERNET, "mout_clkcmu_hsi2_ethernet",
683 mout_clkcmu_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET,
684 0, 2),
685
686 /* ISP */
687 MUX(MOUT_CLKCMU_ISP_NOC, "mout_clkcmu_isp_noc",
688 mout_clkcmu_isp_noc_p, CLK_CON_MUX_MUX_CLKCMU_ISP_NOC, 0, 3),
689
690 /* M2M */
691 MUX(MOUT_CLKCMU_M2M_NOC, "mout_clkcmu_m2m_noc",
692 mout_clkcmu_m2m_noc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0, 2),
693 MUX(MOUT_CLKCMU_M2M_JPEG, "mout_clkcmu_m2m_jpeg",
694 mout_clkcmu_m2m_jpeg_p, CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG, 0, 2),
695
696 /* MFC */
697 MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
698 mout_clkcmu_mfc_mfc_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
699 MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd",
700 mout_clkcmu_mfc_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
701
702 /* MFD */
703 MUX(MOUT_CLKCMU_MFD_NOC, "mout_clkcmu_mfd_noc",
704 mout_clkcmu_mfd_noc_p, CLK_CON_MUX_MUX_CLKCMU_MFD_NOC, 0, 3),
705
706 /* MIF */
707 MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch",
708 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
709 MUX(MOUT_CLKCMU_MIF_NOCP, "mout_clkcmu_mif_nocp",
710 mout_clkcmu_mif_nocp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0, 2),
711
712 /* MISC */
713 MUX(MOUT_CLKCMU_MISC_NOC, "mout_clkcmu_misc_noc",
714 mout_clkcmu_misc_noc_p, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, 0, 2),
715
716 /* NOCL0 */
717 MUX(MOUT_CLKCMU_NOCL0_NOC, "mout_clkcmu_nocl0_noc",
718 mout_clkcmu_nocl0_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0, 3),
719
720 /* NOCL1 */
721 MUX(MOUT_CLKCMU_NOCL1_NOC, "mout_clkcmu_nocl1_noc",
722 mout_clkcmu_nocl1_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC, 0, 3),
723
724 /* NOCL2 */
725 MUX(MOUT_CLKCMU_NOCL2_NOC, "mout_clkcmu_nocl2_noc",
726 mout_clkcmu_nocl2_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC, 0, 3),
727
728 /* PERIC0 */
729 MUX(MOUT_CLKCMU_PERIC0_NOC, "mout_clkcmu_peric0_noc",
730 mout_clkcmu_peric0_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, 0, 1),
731 MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip",
732 mout_clkcmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
733
734 /* PERIC1 */
735 MUX(MOUT_CLKCMU_PERIC1_NOC, "mout_clkcmu_peric1_noc",
736 mout_clkcmu_peric1_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, 0, 1),
737 MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip",
738 mout_clkcmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
739
740 /* SDMA */
741 MUX(MOUT_CLKCMU_SDMA_NOC, "mout_clkcmu_sdma_noc",
742 mout_clkcmu_sdma_noc_p, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 0, 3),
743
744 /* SNW */
745 MUX(MOUT_CLKCMU_SNW_NOC, "mout_clkcmu_snw_noc",
746 mout_clkcmu_snw_noc_p, CLK_CON_MUX_MUX_CLKCMU_SNW_NOC, 0, 3),
747
748 /* SSP */
749 MUX(MOUT_CLKCMU_SSP_NOC, "mout_clkcmu_ssp_noc",
750 mout_clkcmu_ssp_noc_p, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 0, 2),
751
752 /* TAA */
753 MUX(MOUT_CLKCMU_TAA_NOC, "mout_clkcmu_taa_noc",
754 mout_clkcmu_taa_noc_p, CLK_CON_MUX_MUX_CLKCMU_TAA_NOC, 0, 3),
755 };
756
757 static const struct samsung_div_clock top_div_clks[] __initconst = {
758 /* CMU_TOP_PURECLKCOMP */
759
760 /* BOOST */
761 DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost",
762 "mout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
763
764 /* ACC */
765 DIV(DOUT_CLKCMU_ACC_NOC, "dout_clkcmu_acc_noc",
766 "mout_clkcmu_acc_noc", CLK_CON_DIV_CLKCMU_ACC_NOC, 0, 4),
767 DIV(DOUT_CLKCMU_ACC_ORB, "dout_clkcmu_acc_orb",
768 "mout_clkcmu_acc_orb", CLK_CON_DIV_CLKCMU_ACC_ORB, 0, 4),
769
770 /* APM */
771 DIV(DOUT_CLKCMU_APM_NOC, "dout_clkcmu_apm_noc",
772 "mout_clkcmu_apm_noc", CLK_CON_DIV_CLKCMU_APM_NOC, 0, 3),
773
774 /* AUD */
775 DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu",
776 "mout_clkcmu_aud_cpu", CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
777 DIV(DOUT_CLKCMU_AUD_NOC, "dout_clkcmu_aud_noc",
778 "mout_clkcmu_aud_noc", CLK_CON_DIV_CLKCMU_AUD_NOC, 0, 4),
779
780 /* CPUCL0 */
781 DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch",
782 "mout_clkcmu_cpucl0_switch",
783 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
784 DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster",
785 "mout_clkcmu_cpucl0_cluster",
786 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, 0, 3),
787 DIV(DOUT_CLKCMU_CPUCL0_DBG, "dout_clkcmu_cpucl0_dbg",
788 "mout_clkcmu_cpucl0_dbg",
789 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
790
791 /* CPUCL1 */
792 DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch",
793 "mout_clkcmu_cpucl1_switch",
794 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
795 DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster",
796 "mout_clkcmu_cpucl1_cluster",
797 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, 0, 3),
798
799 /* CPUCL2 */
800 DIV(DOUT_CLKCMU_CPUCL2_SWITCH, "dout_clkcmu_cpucl2_switch",
801 "mout_clkcmu_cpucl2_switch",
802 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
803 DIV(DOUT_CLKCMU_CPUCL2_CLUSTER, "dout_clkcmu_cpucl2_cluster",
804 "mout_clkcmu_cpucl2_cluster",
805 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER, 0, 3),
806
807 /* DNC */
808 DIV(DOUT_CLKCMU_DNC_NOC, "dout_clkcmu_dnc_noc",
809 "mout_clkcmu_dnc_noc", CLK_CON_DIV_CLKCMU_DNC_NOC, 0, 4),
810
811 /* DPTX */
812 DIV(DOUT_CLKCMU_DPTX_NOC, "dout_clkcmu_dptx_noc",
813 "mout_clkcmu_dptx_noc", CLK_CON_DIV_CLKCMU_DPTX_NOC, 0, 4),
814 DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc",
815 "mout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
816 DIV(DOUT_CLKCMU_DPTX_DPOSC, "dout_clkcmu_dptx_dposc",
817 "mout_clkcmu_dptx_dposc", CLK_CON_DIV_CLKCMU_DPTX_DPOSC, 0, 5),
818
819 /* DPUB */
820 DIV(DOUT_CLKCMU_DPUB_NOC, "dout_clkcmu_dpub_noc",
821 "mout_clkcmu_dpub_noc", CLK_CON_DIV_CLKCMU_DPUB_NOC, 0, 4),
822 DIV(DOUT_CLKCMU_DPUB_DSIM, "dout_clkcmu_dpub_dsim",
823 "mout_clkcmu_dpub_dsim", CLK_CON_DIV_CLKCMU_DPUB_DSIM, 0, 4),
824
825 /* DPUF */
826 DIV(DOUT_CLKCMU_DPUF0_NOC, "dout_clkcmu_dpuf0_noc",
827 "mout_clkcmu_dpuf0_noc", CLK_CON_DIV_CLKCMU_DPUF0_NOC, 0, 4),
828 DIV(DOUT_CLKCMU_DPUF1_NOC, "dout_clkcmu_dpuf1_noc",
829 "mout_clkcmu_dpuf1_noc", CLK_CON_DIV_CLKCMU_DPUF1_NOC, 0, 4),
830 DIV(DOUT_CLKCMU_DPUF2_NOC, "dout_clkcmu_dpuf2_noc",
831 "mout_clkcmu_dpuf2_noc", CLK_CON_DIV_CLKCMU_DPUF2_NOC, 0, 4),
832
833 /* DSP */
834 DIV(DOUT_CLKCMU_DSP_NOC, "dout_clkcmu_dsp_noc",
835 "mout_clkcmu_dsp_noc", CLK_CON_DIV_CLKCMU_DSP_NOC, 0, 4),
836
837 /* G3D */
838 DIV(DOUT_CLKCMU_G3D_SWITCH, "dout_clkcmu_g3d_switch",
839 "mout_clkcmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
840 DIV(DOUT_CLKCMU_G3D_NOCP, "dout_clkcmu_g3d_nocp",
841 "mout_clkcmu_g3d_nocp", CLK_CON_DIV_CLKCMU_G3D_NOCP, 0, 3),
842
843 /* GNPU */
844 DIV(DOUT_CLKCMU_GNPU_NOC, "dout_clkcmu_gnpu_noc",
845 "mout_clkcmu_gnpu_noc", CLK_CON_DIV_CLKCMU_GNPU_NOC, 0, 4),
846
847 /* HSI0 */
848 DIV(DOUT_CLKCMU_HSI0_NOC, "dout_clkcmu_hsi0_noc",
849 "mout_clkcmu_hsi0_noc", CLK_CON_DIV_CLKCMU_HSI0_NOC, 0, 4),
850
851 /* HSI1 */
852 DIV(DOUT_CLKCMU_HSI1_NOC, "dout_clkcmu_hsi1_noc",
853 "mout_clkcmu_hsi1_noc", CLK_CON_DIV_CLKCMU_HSI1_NOC, 0, 4),
854 DIV(DOUT_CLKCMU_HSI1_USBDRD, "dout_clkcmu_hsi1_usbdrd",
855 "mout_clkcmu_hsi1_usbdrd", CLK_CON_DIV_CLKCMU_HSI1_USBDRD, 0, 4),
856 DIV(DOUT_CLKCMU_HSI1_MMC_CARD, "dout_clkcmu_hsi1_mmc_card",
857 "mout_clkcmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 0, 9),
858
859 /* HSI2 */
860 DIV(DOUT_CLKCMU_HSI2_NOC, "dout_clkcmu_hsi2_noc",
861 "mout_clkcmu_hsi2_noc", CLK_CON_DIV_CLKCMU_HSI2_NOC, 0, 4),
862 DIV(DOUT_CLKCMU_HSI2_NOC_UFS, "dout_clkcmu_hsi2_noc_ufs",
863 "mout_clkcmu_hsi2_noc_ufs", CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS, 0, 4),
864 DIV(DOUT_CLKCMU_HSI2_UFS_EMBD, "dout_clkcmu_hsi2_ufs_embd",
865 "mout_clkcmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 3),
866 DIV(DOUT_CLKCMU_HSI2_ETHERNET, "dout_clkcmu_hsi2_ethernet",
867 "mout_clkcmu_hsi2_ethernet", CLK_CON_DIV_CLKCMU_HSI2_ETHERNET, 0, 3),
868
869 /* ISP */
870 DIV(DOUT_CLKCMU_ISP_NOC, "dout_clkcmu_isp_noc",
871 "mout_clkcmu_isp_noc", CLK_CON_DIV_CLKCMU_ISP_NOC, 0, 4),
872
873 /* M2M */
874 DIV(DOUT_CLKCMU_M2M_NOC, "dout_clkcmu_m2m_noc",
875 "mout_clkcmu_m2m_noc", CLK_CON_DIV_CLKCMU_M2M_NOC, 0, 4),
876 DIV(DOUT_CLKCMU_M2M_JPEG, "dout_clkcmu_m2m_jpeg",
877 "mout_clkcmu_m2m_jpeg", CLK_CON_DIV_CLKCMU_M2M_JPEG, 0, 4),
878
879 /* MFC */
880 DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc",
881 "mout_clkcmu_mfc_mfc", CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
882 DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd",
883 "mout_clkcmu_mfc_wfd", CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
884
885 /* MFD */
886 DIV(DOUT_CLKCMU_MFD_NOC, "dout_clkcmu_mfd_noc",
887 "mout_clkcmu_mfd_noc", CLK_CON_DIV_CLKCMU_MFD_NOC, 0, 4),
888
889 /* MIF */
890 DIV(DOUT_CLKCMU_MIF_NOCP, "dout_clkcmu_mif_nocp",
891 "mout_clkcmu_mif_nocp", CLK_CON_DIV_CLKCMU_MIF_NOCP, 0, 4),
892
893 /* MISC */
894 DIV(DOUT_CLKCMU_MISC_NOC, "dout_clkcmu_misc_noc",
895 "mout_clkcmu_misc_noc", CLK_CON_DIV_CLKCMU_MISC_NOC, 0, 4),
896
897 /* NOCL0 */
898 DIV(DOUT_CLKCMU_NOCL0_NOC, "dout_clkcmu_nocl0_noc",
899 "mout_clkcmu_nocl0_noc", CLK_CON_DIV_CLKCMU_NOCL0_NOC, 0, 4),
900
901 /* NOCL1 */
902 DIV(DOUT_CLKCMU_NOCL1_NOC, "dout_clkcmu_nocl1_noc",
903 "mout_clkcmu_nocl1_noc", CLK_CON_DIV_CLKCMU_NOCL1_NOC, 0, 4),
904
905 /* NOCL2 */
906 DIV(DOUT_CLKCMU_NOCL2_NOC, "dout_clkcmu_nocl2_noc",
907 "mout_clkcmu_nocl2_noc", CLK_CON_DIV_CLKCMU_NOCL2_NOC, 0, 4),
908
909 /* PERIC0 */
910 DIV(DOUT_CLKCMU_PERIC0_NOC, "dout_clkcmu_peric0_noc",
911 "mout_clkcmu_peric0_noc", CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0, 4),
912 DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip",
913 "mout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
914
915 /* PERIC1 */
916 DIV(DOUT_CLKCMU_PERIC1_NOC, "dout_clkcmu_peric1_noc",
917 "mout_clkcmu_peric1_noc", CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0, 4),
918 DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip",
919 "mout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
920
921 /* SDMA */
922 DIV(DOUT_CLKCMU_SDMA_NOC, "dout_clkcmu_sdma_noc",
923 "mout_clkcmu_sdma_noc", CLK_CON_DIV_CLKCMU_SDMA_NOC, 0, 4),
924
925 /* SNW */
926 DIV(DOUT_CLKCMU_SNW_NOC, "dout_clkcmu_snw_noc",
927 "mout_clkcmu_snw_noc", CLK_CON_DIV_CLKCMU_SNW_NOC, 0, 4),
928
929 /* SSP */
930 DIV(DOUT_CLKCMU_SSP_NOC, "dout_clkcmu_ssp_noc",
931 "mout_clkcmu_ssp_noc", CLK_CON_DIV_CLKCMU_SSP_NOC, 0, 4),
932
933 /* TAA */
934 DIV(DOUT_CLKCMU_TAA_NOC, "dout_clkcmu_taa_noc",
935 "mout_clkcmu_taa_noc", CLK_CON_DIV_CLKCMU_TAA_NOC, 0, 4),
936 };
937
938 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
939 FFACTOR(DOUT_SHARED0_DIV1, "dout_shared0_div1",
940 "mout_shared0_pll", 1, 1, 0),
941 FFACTOR(DOUT_SHARED0_DIV2, "dout_shared0_div2",
942 "mout_shared0_pll", 1, 2, 0),
943 FFACTOR(DOUT_SHARED0_DIV3, "dout_shared0_div3",
944 "mout_shared0_pll", 1, 3, 0),
945 FFACTOR(DOUT_SHARED0_DIV4, "dout_shared0_div4",
946 "mout_shared0_pll", 1, 4, 0),
947 FFACTOR(DOUT_SHARED1_DIV1, "dout_shared1_div1",
948 "mout_shared1_pll", 1, 1, 0),
949 FFACTOR(DOUT_SHARED1_DIV2, "dout_shared1_div2",
950 "mout_shared1_pll", 1, 2, 0),
951 FFACTOR(DOUT_SHARED1_DIV3, "dout_shared1_div3",
952 "mout_shared1_pll", 1, 3, 0),
953 FFACTOR(DOUT_SHARED1_DIV4, "dout_shared1_div4",
954 "mout_shared1_pll", 1, 4, 0),
955 FFACTOR(DOUT_SHARED2_DIV1, "dout_shared2_div1",
956 "mout_shared2_pll", 1, 1, 0),
957 FFACTOR(DOUT_SHARED2_DIV2, "dout_shared2_div2",
958 "mout_shared2_pll", 1, 2, 0),
959 FFACTOR(DOUT_SHARED2_DIV3, "dout_shared2_div3",
960 "mout_shared2_pll", 1, 3, 0),
961 FFACTOR(DOUT_SHARED2_DIV4, "dout_shared2_div4",
962 "mout_shared2_pll", 1, 4, 0),
963 FFACTOR(DOUT_SHARED3_DIV1, "dout_shared3_div1",
964 "mout_shared3_pll", 1, 1, 0),
965 FFACTOR(DOUT_SHARED3_DIV2, "dout_shared3_div2",
966 "mout_shared3_pll", 1, 2, 0),
967 FFACTOR(DOUT_SHARED3_DIV3, "dout_shared3_div3",
968 "mout_shared3_pll", 1, 3, 0),
969 FFACTOR(DOUT_SHARED3_DIV4, "dout_shared3_div4",
970 "mout_shared3_pll", 1, 4, 0),
971 FFACTOR(DOUT_SHARED4_DIV1, "dout_shared4_div1",
972 "mout_shared4_pll", 1, 1, 0),
973 FFACTOR(DOUT_SHARED4_DIV2, "dout_shared4_div2",
974 "mout_shared4_pll", 1, 2, 0),
975 FFACTOR(DOUT_SHARED4_DIV3, "dout_shared4_div3",
976 "mout_shared4_pll", 1, 3, 0),
977 FFACTOR(DOUT_SHARED4_DIV4, "dout_shared4_div4",
978 "mout_shared4_pll", 1, 4, 0),
979 FFACTOR(DOUT_SHARED5_DIV1, "dout_shared5_div1",
980 "mout_shared5_pll", 1, 1, 0),
981 FFACTOR(DOUT_SHARED5_DIV2, "dout_shared5_div2",
982 "mout_shared5_pll", 1, 2, 0),
983 FFACTOR(DOUT_SHARED5_DIV3, "dout_shared5_div3",
984 "mout_shared5_pll", 1, 3, 0),
985 FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4",
986 "mout_shared5_pll", 1, 4, 0),
987 FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2",
988 "oscclk", 1, 2, 0),
989 };
990
991 static const struct samsung_cmu_info top_cmu_info __initconst = {
992 .pll_clks = top_pll_clks,
993 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
994 .mux_clks = top_mux_clks,
995 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
996 .div_clks = top_div_clks,
997 .nr_div_clks = ARRAY_SIZE(top_div_clks),
998 .fixed_factor_clks = top_fixed_factor_clks,
999 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
1000 .nr_clk_ids = CLKS_NR_TOP,
1001 .clk_regs = top_clk_regs,
1002 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
1003 };
1004
exynosautov920_cmu_top_init(struct device_node * np)1005 static void __init exynosautov920_cmu_top_init(struct device_node *np)
1006 {
1007 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
1008 }
1009
1010 /* Register CMU_TOP early, as it's a dependency for other early domains */
1011 CLK_OF_DECLARE(exynosautov920_cmu_top, "samsung,exynosautov920-cmu-top",
1012 exynosautov920_cmu_top_init);
1013
1014 /* ---- CMU_CPUCL0 --------------------------------------------------------- */
1015
1016 /* Register Offset definitions for CMU_CPUCL0 (0x1EC00000) */
1017 #define PLL_LOCKTIME_PLL_CPUCL0 0x0000
1018 #define PLL_CON0_PLL_CPUCL0 0x0100
1019 #define PLL_CON1_PLL_CPUCL0 0x0104
1020 #define PLL_CON3_PLL_CPUCL0 0x010c
1021 #define PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER 0x0600
1022 #define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0610
1023 #define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0620
1024
1025 #define CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER 0x1000
1026 #define CLK_CON_MUX_MUX_CLK_CPUCL0_CORE 0x1004
1027
1028 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
1029 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1804
1030 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK 0x1808
1031 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK 0x180c
1032 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
1033 #define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC 0x181c
1034 #define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG 0x1820
1035 #define CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP 0x1824
1036
1037 static const unsigned long cpucl0_clk_regs[] __initconst = {
1038 PLL_LOCKTIME_PLL_CPUCL0,
1039 PLL_CON0_PLL_CPUCL0,
1040 PLL_CON1_PLL_CPUCL0,
1041 PLL_CON3_PLL_CPUCL0,
1042 PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER,
1043 PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
1044 PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
1045 CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER,
1046 CLK_CON_MUX_MUX_CLK_CPUCL0_CORE,
1047 CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
1048 CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
1049 CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK,
1050 CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK,
1051 CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
1052 CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC,
1053 CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG,
1054 CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP,
1055 };
1056
1057 /* List of parent clocks for Muxes in CMU_CPUCL0 */
1058 PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
1059 PNAME(mout_cpucl0_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl0_cluster" };
1060 PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_clkcmu_cpucl0_dbg" };
1061 PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl0_switch" };
1062 PNAME(mout_cpucl0_cluster_p) = { "oscclk", "mout_cpucl0_cluster_user",
1063 "mout_cpucl0_switch_user"};
1064 PNAME(mout_cpucl0_core_p) = { "oscclk", "mout_pll_cpucl0",
1065 "mout_cpucl0_switch_user"};
1066
1067 static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
1068 PLL_35XX_RATE(38400000U, 2400000000U, 250, 4, 0),
1069 PLL_35XX_RATE(38400000U, 2304000000U, 240, 4, 0),
1070 PLL_35XX_RATE(38400000U, 2208000000U, 230, 4, 0),
1071 PLL_35XX_RATE(38400000U, 2112000000U, 220, 4, 0),
1072 PLL_35XX_RATE(38400000U, 2016000000U, 210, 4, 0),
1073 PLL_35XX_RATE(38400000U, 1824000000U, 190, 4, 0),
1074 PLL_35XX_RATE(38400000U, 1680000000U, 175, 4, 0),
1075 PLL_35XX_RATE(38400000U, 1344000000U, 140, 4, 0),
1076 PLL_35XX_RATE(38400000U, 1152000000U, 120, 4, 0),
1077 PLL_35XX_RATE(38400000U, 576000000U, 120, 4, 1),
1078 PLL_35XX_RATE(38400000U, 288000000U, 120, 4, 2),
1079 };
1080
1081 static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
1082 /* CMU_CPUCL0_PURECLKCOMP */
1083 PLL(pll_531x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
1084 PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
1085 };
1086
1087 static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
1088 MUX(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
1089 PLL_CON0_PLL_CPUCL0, 4, 1),
1090 MUX(CLK_MOUT_CPUCL0_CLUSTER_USER, "mout_cpucl0_cluster_user", mout_cpucl0_cluster_user_p,
1091 PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER, 4, 1),
1092 MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user", mout_cpucl0_dbg_user_p,
1093 PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
1094 MUX(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user", mout_cpucl0_switch_user_p,
1095 PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1),
1096 MUX(CLK_MOUT_CPUCL0_CLUSTER, "mout_cpucl0_cluster", mout_cpucl0_cluster_p,
1097 CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER, 0, 2),
1098 MUX(CLK_MOUT_CPUCL0_CORE, "mout_cpucl0_core", mout_cpucl0_core_p,
1099 CLK_CON_MUX_MUX_CLK_CPUCL0_CORE, 0, 2),
1100 };
1101
1102 static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
1103 DIV(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk",
1104 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4),
1105 DIV(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
1106 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4),
1107 DIV(CLK_DOUT_CLUSTER0_MPCLK, "dout_cluster0_mpclk",
1108 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK, 0, 4),
1109 DIV(CLK_DOUT_CLUSTER0_PCLK, "dout_cluster0_pclk",
1110 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK, 0, 4),
1111 DIV(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
1112 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4),
1113 DIV(CLK_DOUT_CPUCL0_DBG_NOC, "dout_cpucl0_dbg_noc",
1114 "mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC, 0, 3),
1115 DIV(CLK_DOUT_CPUCL0_DBG_PCLKDBG, "dout_cpucl0_dbg_pclkdbg",
1116 "mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0, 3),
1117 DIV(CLK_DOUT_CPUCL0_NOCP, "dout_cpucl0_nocp",
1118 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP, 0, 4),
1119 };
1120
1121 static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
1122 .pll_clks = cpucl0_pll_clks,
1123 .nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
1124 .mux_clks = cpucl0_mux_clks,
1125 .nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
1126 .div_clks = cpucl0_div_clks,
1127 .nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
1128 .nr_clk_ids = CLKS_NR_CPUCL0,
1129 .clk_regs = cpucl0_clk_regs,
1130 .nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
1131 .clk_name = "cpucl0",
1132 };
1133
exynosautov920_cmu_cpucl0_init(struct device_node * np)1134 static void __init exynosautov920_cmu_cpucl0_init(struct device_node *np)
1135 {
1136 exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
1137 }
1138
1139 /* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */
1140 CLK_OF_DECLARE(exynosautov920_cmu_cpucl0, "samsung,exynosautov920-cmu-cpucl0",
1141 exynosautov920_cmu_cpucl0_init);
1142
1143 /* ---- CMU_CPUCL1 --------------------------------------------------------- */
1144
1145 /* Register Offset definitions for CMU_CPUCL1 (0x1ED00000) */
1146 #define PLL_LOCKTIME_PLL_CPUCL1 0x0000
1147 #define PLL_CON0_PLL_CPUCL1 0x0100
1148 #define PLL_CON1_PLL_CPUCL1 0x0104
1149 #define PLL_CON3_PLL_CPUCL1 0x010c
1150 #define PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER 0x0600
1151 #define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
1152
1153 #define CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER 0x1000
1154 #define CLK_CON_MUX_MUX_CLK_CPUCL1_CORE 0x1004
1155
1156 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
1157 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1804
1158 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK 0x1808
1159 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK 0x180c
1160 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
1161 #define CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP 0x181c
1162
1163 static const unsigned long cpucl1_clk_regs[] __initconst = {
1164 PLL_LOCKTIME_PLL_CPUCL1,
1165 PLL_CON0_PLL_CPUCL1,
1166 PLL_CON1_PLL_CPUCL1,
1167 PLL_CON3_PLL_CPUCL1,
1168 PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER,
1169 PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
1170 CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER,
1171 CLK_CON_MUX_MUX_CLK_CPUCL1_CORE,
1172 CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
1173 CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
1174 CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK,
1175 CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK,
1176 CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
1177 CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP,
1178 };
1179
1180 /* List of parent clocks for Muxes in CMU_CPUCL1 */
1181 PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
1182 PNAME(mout_cpucl1_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl1_cluster" };
1183 PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl1_switch" };
1184 PNAME(mout_cpucl1_cluster_p) = { "oscclk", "mout_cpucl1_cluster_user",
1185 "mout_cpucl1_switch_user"};
1186 PNAME(mout_cpucl1_core_p) = { "oscclk", "mout_pll_cpucl1",
1187 "mout_cpucl1_switch_user"};
1188
1189 static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
1190 /* CMU_CPUCL1_PURECLKCOMP */
1191 PLL(pll_531x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
1192 PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
1193 };
1194
1195 static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
1196 MUX(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
1197 PLL_CON0_PLL_CPUCL1, 4, 1),
1198 MUX(CLK_MOUT_CPUCL1_CLUSTER_USER, "mout_cpucl1_cluster_user", mout_cpucl1_cluster_user_p,
1199 PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER, 4, 1),
1200 MUX(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user", mout_cpucl1_switch_user_p,
1201 PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1),
1202 MUX(CLK_MOUT_CPUCL1_CLUSTER, "mout_cpucl1_cluster", mout_cpucl1_cluster_p,
1203 CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER, 0, 2),
1204 MUX(CLK_MOUT_CPUCL1_CORE, "mout_cpucl1_core", mout_cpucl1_core_p,
1205 CLK_CON_MUX_MUX_CLK_CPUCL1_CORE, 0, 2),
1206 };
1207
1208 static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
1209 DIV(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk",
1210 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4),
1211 DIV(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
1212 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4),
1213 DIV(CLK_DOUT_CLUSTER1_MPCLK, "dout_cluster1_mpclk",
1214 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK, 0, 4),
1215 DIV(CLK_DOUT_CLUSTER1_PCLK, "dout_cluster1_pclk",
1216 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK, 0, 4),
1217 DIV(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
1218 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4),
1219 DIV(CLK_DOUT_CPUCL1_NOCP, "dout_cpucl1_nocp",
1220 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP, 0, 4),
1221 };
1222
1223 static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
1224 .pll_clks = cpucl1_pll_clks,
1225 .nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
1226 .mux_clks = cpucl1_mux_clks,
1227 .nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
1228 .div_clks = cpucl1_div_clks,
1229 .nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
1230 .nr_clk_ids = CLKS_NR_CPUCL1,
1231 .clk_regs = cpucl1_clk_regs,
1232 .nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
1233 .clk_name = "cpucl1",
1234 };
1235
exynosautov920_cmu_cpucl1_init(struct device_node * np)1236 static void __init exynosautov920_cmu_cpucl1_init(struct device_node *np)
1237 {
1238 exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
1239 }
1240
1241 /* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
1242 CLK_OF_DECLARE(exynosautov920_cmu_cpucl1, "samsung,exynosautov920-cmu-cpucl1",
1243 exynosautov920_cmu_cpucl1_init);
1244
1245 /* ---- CMU_CPUCL2 --------------------------------------------------------- */
1246
1247 /* Register Offset definitions for CMU_CPUCL2 (0x1EE00000) */
1248 #define PLL_LOCKTIME_PLL_CPUCL2 0x0000
1249 #define PLL_CON0_PLL_CPUCL2 0x0100
1250 #define PLL_CON1_PLL_CPUCL2 0x0104
1251 #define PLL_CON3_PLL_CPUCL2 0x010c
1252 #define PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER 0x0600
1253 #define PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER 0x0610
1254
1255 #define CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER 0x1000
1256 #define CLK_CON_MUX_MUX_CLK_CPUCL2_CORE 0x1004
1257
1258 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK 0x1800
1259 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK 0x1804
1260 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK 0x1808
1261 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK 0x180c
1262 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK 0x1810
1263 #define CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP 0x181c
1264
1265 static const unsigned long cpucl2_clk_regs[] __initconst = {
1266 PLL_LOCKTIME_PLL_CPUCL2,
1267 PLL_CON0_PLL_CPUCL2,
1268 PLL_CON1_PLL_CPUCL2,
1269 PLL_CON3_PLL_CPUCL2,
1270 PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER,
1271 PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER,
1272 CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER,
1273 CLK_CON_MUX_MUX_CLK_CPUCL2_CORE,
1274 CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK,
1275 CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK,
1276 CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK,
1277 CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK,
1278 CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK,
1279 CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP,
1280 };
1281
1282 /* List of parent clocks for Muxes in CMU_CPUCL2 */
1283 PNAME(mout_pll_cpucl2_p) = { "oscclk", "fout_cpucl2_pll" };
1284 PNAME(mout_cpucl2_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl2_cluster" };
1285 PNAME(mout_cpucl2_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl2_switch" };
1286 PNAME(mout_cpucl2_cluster_p) = { "oscclk", "mout_cpucl2_cluster_user",
1287 "mout_cpucl2_switch_user"};
1288 PNAME(mout_cpucl2_core_p) = { "oscclk", "mout_pll_cpucl2",
1289 "mout_cpucl2_switch_user"};
1290
1291 static const struct samsung_pll_clock cpucl2_pll_clks[] __initconst = {
1292 /* CMU_CPUCL2_PURECLKCOMP */
1293 PLL(pll_531x, CLK_FOUT_CPUCL2_PLL, "fout_cpucl2_pll", "oscclk",
1294 PLL_LOCKTIME_PLL_CPUCL2, PLL_CON3_PLL_CPUCL2, cpu_pll_rates),
1295 };
1296
1297 static const struct samsung_mux_clock cpucl2_mux_clks[] __initconst = {
1298 MUX(CLK_MOUT_PLL_CPUCL2, "mout_pll_cpucl2", mout_pll_cpucl2_p,
1299 PLL_CON0_PLL_CPUCL2, 4, 1),
1300 MUX(CLK_MOUT_CPUCL2_CLUSTER_USER, "mout_cpucl2_cluster_user", mout_cpucl2_cluster_user_p,
1301 PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER, 4, 1),
1302 MUX(CLK_MOUT_CPUCL2_SWITCH_USER, "mout_cpucl2_switch_user", mout_cpucl2_switch_user_p,
1303 PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 4, 1),
1304 MUX(CLK_MOUT_CPUCL2_CLUSTER, "mout_cpucl2_cluster", mout_cpucl2_cluster_p,
1305 CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER, 0, 2),
1306 MUX(CLK_MOUT_CPUCL2_CORE, "mout_cpucl2_core", mout_cpucl2_core_p,
1307 CLK_CON_MUX_MUX_CLK_CPUCL2_CORE, 0, 2),
1308 };
1309
1310 static const struct samsung_div_clock cpucl2_div_clks[] __initconst = {
1311 DIV(CLK_DOUT_CLUSTER2_ACLK, "dout_cluster2_aclk",
1312 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK, 0, 4),
1313 DIV(CLK_DOUT_CLUSTER2_ATCLK, "dout_cluster2_atclk",
1314 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK, 0, 4),
1315 DIV(CLK_DOUT_CLUSTER2_MPCLK, "dout_cluster2_mpclk",
1316 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK, 0, 4),
1317 DIV(CLK_DOUT_CLUSTER2_PCLK, "dout_cluster2_pclk",
1318 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK, 0, 4),
1319 DIV(CLK_DOUT_CLUSTER2_PERIPHCLK, "dout_cluster2_periphclk",
1320 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK, 0, 4),
1321 DIV(CLK_DOUT_CPUCL2_NOCP, "dout_cpucl2_nocp",
1322 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP, 0, 4),
1323 };
1324
1325 static const struct samsung_cmu_info cpucl2_cmu_info __initconst = {
1326 .pll_clks = cpucl2_pll_clks,
1327 .nr_pll_clks = ARRAY_SIZE(cpucl2_pll_clks),
1328 .mux_clks = cpucl2_mux_clks,
1329 .nr_mux_clks = ARRAY_SIZE(cpucl2_mux_clks),
1330 .div_clks = cpucl2_div_clks,
1331 .nr_div_clks = ARRAY_SIZE(cpucl2_div_clks),
1332 .nr_clk_ids = CLKS_NR_CPUCL2,
1333 .clk_regs = cpucl2_clk_regs,
1334 .nr_clk_regs = ARRAY_SIZE(cpucl2_clk_regs),
1335 .clk_name = "cpucl2",
1336 };
1337
exynosautov920_cmu_cpucl2_init(struct device_node * np)1338 static void __init exynosautov920_cmu_cpucl2_init(struct device_node *np)
1339 {
1340 exynos_arm64_register_cmu(NULL, np, &cpucl2_cmu_info);
1341 }
1342
1343 /* Register CMU_CPUCL2 early, as CPU clocks should be available ASAP */
1344 CLK_OF_DECLARE(exynosautov920_cmu_cpucl2, "samsung,exynosautov920-cmu-cpucl2",
1345 exynosautov920_cmu_cpucl2_init);
1346
1347 /* ---- CMU_PERIC0 --------------------------------------------------------- */
1348
1349 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */
1350 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0600
1351 #define PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER 0x0610
1352 #define CLK_CON_MUX_MUX_CLK_PERIC0_I3C 0x1000
1353 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1004
1354 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1008
1355 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x100c
1356 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x1010
1357 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1014
1358 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1018
1359 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI 0x101c
1360 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI 0x1020
1361 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI 0x1024
1362 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1028
1363 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
1364 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804
1365 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808
1366 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c
1367 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810
1368 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814
1369 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818
1370 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI 0x181c
1371 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI 0x1820
1372 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI 0x1824
1373 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828
1374
1375 static const unsigned long peric0_clk_regs[] __initconst = {
1376 PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
1377 PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER,
1378 CLK_CON_MUX_MUX_CLK_PERIC0_I3C,
1379 CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
1380 CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
1381 CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
1382 CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
1383 CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
1384 CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
1385 CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI,
1386 CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI,
1387 CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI,
1388 CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
1389 CLK_CON_DIV_DIV_CLK_PERIC0_I3C,
1390 CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1391 CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1392 CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1393 CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1394 CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1395 CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1396 CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI,
1397 CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI,
1398 CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI,
1399 CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1400 };
1401
1402 /* List of parent clocks for Muxes in CMU_PERIC0 */
1403 PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };
1404 PNAME(mout_peric0_noc_user_p) = { "oscclk", "dout_clkcmu_peric0_noc" };
1405 PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };
1406
1407 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
1408 MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",
1409 mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),
1410 MUX(CLK_MOUT_PERIC0_NOC_USER, "mout_peric0_noc_user",
1411 mout_peric0_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, 4, 1),
1412 /* USI00 ~ USI08 */
1413 MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",
1414 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1415 MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",
1416 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1417 MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",
1418 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1419 MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",
1420 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1421 MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",
1422 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1423 MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",
1424 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1425 MUX(CLK_MOUT_PERIC0_USI06_USI, "mout_peric0_usi06_usi",
1426 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI, 0, 1),
1427 MUX(CLK_MOUT_PERIC0_USI07_USI, "mout_peric0_usi07_usi",
1428 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI, 0, 1),
1429 MUX(CLK_MOUT_PERIC0_USI08_USI, "mout_peric0_usi08_usi",
1430 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI, 0, 1),
1431 /* USI_I2C */
1432 MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",
1433 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1434 /* USI_I3C */
1435 MUX(CLK_MOUT_PERIC0_I3C, "mout_peric0_i3c",
1436 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_I3C, 0, 1),
1437 };
1438
1439 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
1440 /* USI00 ~ USI08 */
1441 DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
1442 "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1443 0, 4),
1444 DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
1445 "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1446 0, 4),
1447 DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
1448 "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1449 0, 4),
1450 DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
1451 "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1452 0, 4),
1453 DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
1454 "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1455 0, 4),
1456 DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
1457 "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1458 0, 4),
1459 DIV(CLK_DOUT_PERIC0_USI06_USI, "dout_peric0_usi06_usi",
1460 "mout_peric0_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI,
1461 0, 4),
1462 DIV(CLK_DOUT_PERIC0_USI07_USI, "dout_peric0_usi07_usi",
1463 "mout_peric0_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI,
1464 0, 4),
1465 DIV(CLK_DOUT_PERIC0_USI08_USI, "dout_peric0_usi08_usi",
1466 "mout_peric0_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI,
1467 0, 4),
1468 /* USI_I2C */
1469 DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
1470 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1471 /* USI_I3C */
1472 DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c",
1473 "mout_peric0_i3c", CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4),
1474 };
1475
1476 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
1477 .mux_clks = peric0_mux_clks,
1478 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
1479 .div_clks = peric0_div_clks,
1480 .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
1481 .nr_clk_ids = CLKS_NR_PERIC0,
1482 .clk_regs = peric0_clk_regs,
1483 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
1484 .clk_name = "noc",
1485 };
1486
1487 /* ---- CMU_PERIC1 --------------------------------------------------------- */
1488
1489 /* Register Offset definitions for CMU_PERIC1 (0x10C00000) */
1490 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x600
1491 #define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x610
1492 #define CLK_CON_MUX_MUX_CLK_PERIC1_I3C 0x1000
1493 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x1004
1494 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1008
1495 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x100c
1496 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI 0x1010
1497 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI 0x1014
1498 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI 0x1018
1499 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI 0x101c
1500 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI 0x1020
1501 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI 0x1024
1502 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1028
1503 #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
1504 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1804
1505 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
1506 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
1507 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
1508 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
1509 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI 0x1818
1510 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI 0x181c
1511 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820
1512 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824
1513 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1828
1514
1515 static const unsigned long peric1_clk_regs[] __initconst = {
1516 PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
1517 PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER,
1518 CLK_CON_MUX_MUX_CLK_PERIC1_I3C,
1519 CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
1520 CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
1521 CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
1522 CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI,
1523 CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI,
1524 CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI,
1525 CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI,
1526 CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI,
1527 CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI,
1528 CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
1529 CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
1530 CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1531 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1532 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1533 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
1534 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
1535 CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
1536 CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
1537 CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
1538 CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
1539 CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
1540 };
1541
1542 /* List of parent clocks for Muxes in CMU_PERIC1 */
1543 PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
1544 PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" };
1545 PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
1546
1547 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
1548 MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
1549 mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
1550 MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user",
1551 mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1),
1552 /* USI09 ~ USI17 */
1553 MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
1554 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1555 MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
1556 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1557 MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
1558 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1559 MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi",
1560 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1),
1561 MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi",
1562 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1),
1563 MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi",
1564 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1),
1565 MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi",
1566 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1),
1567 MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi",
1568 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1),
1569 MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi",
1570 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1),
1571 /* USI_I2C */
1572 MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
1573 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1574 /* USI_I3C */
1575 MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c",
1576 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1),
1577 };
1578
1579 static const struct samsung_div_clock peric1_div_clks[] __initconst = {
1580 /* USI09 ~ USI17 */
1581 DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
1582 "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1583 0, 4),
1584 DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
1585 "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1586 0, 4),
1587 DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
1588 "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1589 0, 4),
1590 DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
1591 "mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
1592 0, 4),
1593 DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi",
1594 "mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
1595 0, 4),
1596 DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi",
1597 "mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
1598 0, 4),
1599 DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi",
1600 "mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
1601 0, 4),
1602 DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
1603 "mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
1604 0, 4),
1605 DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
1606 "mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
1607 0, 4),
1608 /* USI_I2C */
1609 DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
1610 "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1611 /* USI_I3C */
1612 DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c",
1613 "mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
1614 };
1615
1616 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
1617 .mux_clks = peric1_mux_clks,
1618 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
1619 .div_clks = peric1_div_clks,
1620 .nr_div_clks = ARRAY_SIZE(peric1_div_clks),
1621 .nr_clk_ids = CLKS_NR_PERIC1,
1622 .clk_regs = peric1_clk_regs,
1623 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
1624 .clk_name = "noc",
1625 };
1626
1627 /* ---- CMU_MISC --------------------------------------------------------- */
1628
1629 /* Register Offset definitions for CMU_MISC (0x10020000) */
1630 #define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER 0x600
1631 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
1632 #define CLK_CON_DIV_CLKCMU_OTP 0x1800
1633 #define CLK_CON_DIV_DIV_CLK_MISC_NOCP 0x1804
1634 #define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2 0x1808
1635
1636 static const unsigned long misc_clk_regs[] __initconst = {
1637 PLL_CON0_MUX_CLKCMU_MISC_NOC_USER,
1638 CLK_CON_MUX_MUX_CLK_MISC_GIC,
1639 CLK_CON_DIV_CLKCMU_OTP,
1640 CLK_CON_DIV_DIV_CLK_MISC_NOCP,
1641 CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2,
1642 };
1643
1644 /* List of parent clocks for Muxes in CMU_MISC */
1645 PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" };
1646 PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" };
1647
1648 static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
1649 MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user",
1650 mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1),
1651 MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic",
1652 mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1),
1653 };
1654
1655 static const struct samsung_div_clock misc_div_clks[] __initconst = {
1656 DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp",
1657 "mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP,
1658 0, 3),
1659 };
1660
1661 static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = {
1662 FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp",
1663 "oscclk", 1, 10, 0),
1664 FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2",
1665 "oscclk", 1, 2, 0),
1666 };
1667
1668 static const struct samsung_cmu_info misc_cmu_info __initconst = {
1669 .mux_clks = misc_mux_clks,
1670 .nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
1671 .div_clks = misc_div_clks,
1672 .nr_div_clks = ARRAY_SIZE(misc_div_clks),
1673 .fixed_factor_clks = misc_fixed_factor_clks,
1674 .nr_fixed_factor_clks = ARRAY_SIZE(misc_fixed_factor_clks),
1675 .nr_clk_ids = CLKS_NR_MISC,
1676 .clk_regs = misc_clk_regs,
1677 .nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
1678 .clk_name = "noc",
1679 };
1680
1681 /* ---- CMU_HSI0 --------------------------------------------------------- */
1682
1683 /* Register Offset definitions for CMU_HSI0 (0x16000000) */
1684 #define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x600
1685 #define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB 0x1800
1686
1687 static const unsigned long hsi0_clk_regs[] __initconst = {
1688 PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,
1689 CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
1690 };
1691
1692 /* List of parent clocks for Muxes in CMU_HSI0 */
1693 PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" };
1694
1695 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
1696 MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user",
1697 mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1),
1698 };
1699
1700 static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
1701 DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb",
1702 "mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
1703 0, 4),
1704 };
1705
1706 static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
1707 .mux_clks = hsi0_mux_clks,
1708 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
1709 .div_clks = hsi0_div_clks,
1710 .nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
1711 .nr_clk_ids = CLKS_NR_HSI0,
1712 .clk_regs = hsi0_clk_regs,
1713 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
1714 .clk_name = "noc",
1715 };
1716
1717 /* ---- CMU_HSI1 --------------------------------------------------------- */
1718
1719 /* Register Offset definitions for CMU_HSI1 (0x16400000) */
1720 #define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x600
1721 #define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER 0x610
1722 #define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER 0x620
1723 #define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD 0x1000
1724
1725 static const unsigned long hsi1_clk_regs[] __initconst = {
1726 PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,
1727 PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER,
1728 PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER,
1729 CLK_CON_MUX_MUX_CLK_HSI1_USBDRD,
1730 };
1731
1732 /* List of parent clocks for Muxes in CMU_HSI1 */
1733 PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};
1734 PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };
1735 PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_hsi1_usbdrd" };
1736 PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };
1737
1738 static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
1739 MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user",
1740 mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1),
1741 MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user",
1742 mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1),
1743 MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user",
1744 mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1),
1745 MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd",
1746 mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1),
1747 };
1748
1749 static const struct samsung_cmu_info hsi1_cmu_info __initconst = {
1750 .mux_clks = hsi1_mux_clks,
1751 .nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks),
1752 .nr_clk_ids = CLKS_NR_HSI1,
1753 .clk_regs = hsi1_clk_regs,
1754 .nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs),
1755 .clk_name = "noc",
1756 };
1757
1758 /* ---- CMU_HSI2 --------------------------------------------------------- */
1759
1760 /* Register Offset definitions for CMU_HSI2 (0x16b00000) */
1761 #define PLL_LOCKTIME_PLL_ETH 0x0
1762 #define PLL_CON3_PLL_ETH 0x10c
1763 #define PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER 0x600
1764 #define PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER 0x610
1765 #define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x630
1766 #define CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET 0x1000
1767 #define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET 0x1800
1768 #define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP 0x1804
1769
1770 static const unsigned long hsi2_clk_regs[] __initconst = {
1771 PLL_LOCKTIME_PLL_ETH,
1772 PLL_CON3_PLL_ETH,
1773 PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER,
1774 PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER,
1775 PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
1776 CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET,
1777 CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,
1778 CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,
1779 };
1780
1781 static const struct samsung_pll_clock hsi2_pll_clks[] __initconst = {
1782 /* CMU_HSI2_PLL */
1783 PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk",
1784 PLL_LOCKTIME_PLL_ETH, PLL_CON3_PLL_ETH, NULL),
1785 };
1786
1787 /* List of parent clocks for Muxes in CMU_HSI2 */
1788 PNAME(mout_clkcmu_hsi2_noc_ufs_user_p) = { "oscclk", "dout_clkcmu_hsi2_noc_ufs" };
1789 PNAME(mout_clkcmu_hsi2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi2_ufs_embd" };
1790 PNAME(mout_hsi2_ethernet_p) = { "fout_pll_eth", "mout_clkcmu_hsi2_ethernet_user" };
1791 PNAME(mout_clkcmu_hsi2_ethernet_user_p) = { "oscclk", "dout_clkcmu_hsi2_ethernet" };
1792
1793 static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
1794 MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user",
1795 mout_clkcmu_hsi2_noc_ufs_user_p, PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, 4, 1),
1796 MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user",
1797 mout_clkcmu_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 4, 1),
1798 MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet",
1799 mout_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 0, 1),
1800 MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user",
1801 mout_clkcmu_hsi2_ethernet_user_p, PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, 4, 1),
1802 };
1803
1804 static const struct samsung_div_clock hsi2_div_clks[] __initconst = {
1805 DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet",
1806 "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,
1807 0, 4),
1808 DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp",
1809 "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,
1810 0, 4),
1811 };
1812
1813 static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
1814 .pll_clks = hsi2_pll_clks,
1815 .nr_pll_clks = ARRAY_SIZE(hsi2_pll_clks),
1816 .mux_clks = hsi2_mux_clks,
1817 .nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks),
1818 .div_clks = hsi2_div_clks,
1819 .nr_div_clks = ARRAY_SIZE(hsi2_div_clks),
1820 .nr_clk_ids = CLKS_NR_HSI2,
1821 .clk_regs = hsi2_clk_regs,
1822 .nr_clk_regs = ARRAY_SIZE(hsi2_clk_regs),
1823 .clk_name = "noc",
1824 };
1825
1826 /* ---- CMU_M2M --------------------------------------------------------- */
1827
1828 /* Register Offset definitions for CMU_M2M (0x1a800000) */
1829 #define PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER 0x600
1830 #define PLL_CON0_MUX_CLKCMU_M2M_NOC_USER 0x610
1831 #define CLK_CON_DIV_DIV_CLK_M2M_NOCP 0x1800
1832
1833 static const unsigned long m2m_clk_regs[] __initconst = {
1834 PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER,
1835 PLL_CON0_MUX_CLKCMU_M2M_NOC_USER,
1836 CLK_CON_DIV_DIV_CLK_M2M_NOCP,
1837 };
1838
1839 /* List of parent clocks for Muxes in CMU_M2M */
1840 PNAME(mout_clkcmu_m2m_noc_user_p) = { "oscclk", "dout_clkcmu_m2m_noc" };
1841 PNAME(mout_clkcmu_m2m_jpeg_user_p) = { "oscclk", "dout_clkcmu_m2m_jpeg" };
1842
1843 static const struct samsung_mux_clock m2m_mux_clks[] __initconst = {
1844 MUX(CLK_MOUT_M2M_JPEG_USER, "mout_clkcmu_m2m_jpeg_user",
1845 mout_clkcmu_m2m_jpeg_user_p, PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER, 4, 1),
1846 MUX(CLK_MOUT_M2M_NOC_USER, "mout_clkcmu_m2m_noc_user",
1847 mout_clkcmu_m2m_noc_user_p, PLL_CON0_MUX_CLKCMU_M2M_NOC_USER, 4, 1),
1848 };
1849
1850 static const struct samsung_div_clock m2m_div_clks[] __initconst = {
1851 DIV(CLK_DOUT_M2M_NOCP, "dout_m2m_nocp",
1852 "mout_clkcmu_m2m_noc_user", CLK_CON_DIV_DIV_CLK_M2M_NOCP,
1853 0, 3),
1854 };
1855
1856 static const struct samsung_cmu_info m2m_cmu_info __initconst = {
1857 .mux_clks = m2m_mux_clks,
1858 .nr_mux_clks = ARRAY_SIZE(m2m_mux_clks),
1859 .div_clks = m2m_div_clks,
1860 .nr_div_clks = ARRAY_SIZE(m2m_div_clks),
1861 .nr_clk_ids = CLKS_NR_M2M,
1862 .clk_regs = m2m_clk_regs,
1863 .nr_clk_regs = ARRAY_SIZE(m2m_clk_regs),
1864 .clk_name = "noc",
1865 };
1866
1867 /* ---- CMU_MFC --------------------------------------------------------- */
1868
1869 /* Register Offset definitions for CMU_MFC (0x19c00000) */
1870 #define PLL_CON0_MUX_CLKCMU_MFC_MFC_USER 0x600
1871 #define PLL_CON0_MUX_CLKCMU_MFC_WFD_USER 0x610
1872 #define CLK_CON_DIV_DIV_CLK_MFC_NOCP 0x1800
1873
1874 static const unsigned long mfc_clk_regs[] __initconst = {
1875 PLL_CON0_MUX_CLKCMU_MFC_MFC_USER,
1876 PLL_CON0_MUX_CLKCMU_MFC_WFD_USER,
1877 CLK_CON_DIV_DIV_CLK_MFC_NOCP,
1878 };
1879
1880 /* List of parent clocks for Muxes in CMU_MFC */
1881 PNAME(mout_clkcmu_mfc_mfc_user_p) = { "oscclk", "dout_clkcmu_mfc_mfc" };
1882 PNAME(mout_clkcmu_mfc_wfd_user_p) = { "oscclk", "dout_clkcmu_mfc_wfd" };
1883
1884 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
1885 MUX(CLK_MOUT_MFC_MFC_USER, "mout_clkcmu_mfc_mfc_user",
1886 mout_clkcmu_mfc_mfc_user_p, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER, 4, 1),
1887 MUX(CLK_MOUT_MFC_WFD_USER, "mout_clkcmu_mfc_wfd_user",
1888 mout_clkcmu_mfc_wfd_user_p, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER, 4, 1),
1889 };
1890
1891 static const struct samsung_div_clock mfc_div_clks[] __initconst = {
1892 DIV(CLK_DOUT_MFC_NOCP, "dout_mfc_nocp",
1893 "mout_clkcmu_mfc_mfc_user", CLK_CON_DIV_DIV_CLK_MFC_NOCP,
1894 0, 3),
1895 };
1896
1897 static const struct samsung_cmu_info mfc_cmu_info __initconst = {
1898 .mux_clks = mfc_mux_clks,
1899 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
1900 .div_clks = mfc_div_clks,
1901 .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
1902 .nr_clk_ids = CLKS_NR_MFC,
1903 .clk_regs = mfc_clk_regs,
1904 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
1905 .clk_name = "noc",
1906 };
1907
exynosautov920_cmu_probe(struct platform_device * pdev)1908 static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
1909 {
1910 const struct samsung_cmu_info *info;
1911 struct device *dev = &pdev->dev;
1912
1913 info = of_device_get_match_data(dev);
1914 exynos_arm64_register_cmu(dev, dev->of_node, info);
1915
1916 return 0;
1917 }
1918
1919 static const struct of_device_id exynosautov920_cmu_of_match[] = {
1920 {
1921 .compatible = "samsung,exynosautov920-cmu-peric0",
1922 .data = &peric0_cmu_info,
1923 }, {
1924 .compatible = "samsung,exynosautov920-cmu-peric1",
1925 .data = &peric1_cmu_info,
1926 }, {
1927 .compatible = "samsung,exynosautov920-cmu-misc",
1928 .data = &misc_cmu_info,
1929 }, {
1930 .compatible = "samsung,exynosautov920-cmu-hsi0",
1931 .data = &hsi0_cmu_info,
1932 }, {
1933 .compatible = "samsung,exynosautov920-cmu-hsi1",
1934 .data = &hsi1_cmu_info,
1935 }, {
1936 .compatible = "samsung,exynosautov920-cmu-hsi2",
1937 .data = &hsi2_cmu_info,
1938 }, {
1939 .compatible = "samsung,exynosautov920-cmu-m2m",
1940 .data = &m2m_cmu_info,
1941 }, {
1942 .compatible = "samsung,exynosautov920-cmu-mfc",
1943 .data = &mfc_cmu_info,
1944 },
1945 { }
1946 };
1947
1948 static struct platform_driver exynosautov920_cmu_driver __refdata = {
1949 .driver = {
1950 .name = "exynosautov920-cmu",
1951 .of_match_table = exynosautov920_cmu_of_match,
1952 .suppress_bind_attrs = true,
1953 },
1954 .probe = exynosautov920_cmu_probe,
1955 };
1956
exynosautov920_cmu_init(void)1957 static int __init exynosautov920_cmu_init(void)
1958 {
1959 return platform_driver_register(&exynosautov920_cmu_driver);
1960 }
1961 core_initcall(exynosautov920_cmu_init);
1962