1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/tty_flip.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/delay.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/console.h> 26 #include <linux/pm_qos.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/sys_soc.h> 30 #include <linux/reboot.h> 31 #include <linux/pinctrl/consumer.h> 32 33 #include "8250.h" 34 35 #define DEFAULT_CLK_SPEED 48000000 36 #define OMAP_UART_REGSHIFT 2 37 38 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 39 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 40 #define OMAP_DMA_TX_KICK (1 << 2) 41 /* 42 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 43 * The same errata is applicable to AM335x and DRA7x processors too. 44 */ 45 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 46 #define UART_HAS_EFR2 BIT(4) 47 #define UART_HAS_RHR_IT_DIS BIT(5) 48 #define UART_RX_TIMEOUT_QUIRK BIT(6) 49 #define UART_HAS_NATIVE_RS485 BIT(7) 50 51 #define OMAP_UART_FCR_RX_TRIG 6 52 #define OMAP_UART_FCR_TX_TRIG 4 53 54 /* SCR register bitmasks */ 55 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 56 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 57 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 58 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 59 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 60 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 61 62 /* MVR register bitmasks */ 63 #define OMAP_UART_MVR_SCHEME_SHIFT 30 64 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 65 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 66 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 67 #define OMAP_UART_MVR_MAJ_MASK 0x700 68 #define OMAP_UART_MVR_MAJ_SHIFT 8 69 #define OMAP_UART_MVR_MIN_MASK 0x3f 70 71 /* SYSC register bitmasks */ 72 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 73 74 /* SYSS register bitmasks */ 75 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 76 77 #define UART_TI752_TLR_TX 0 78 #define UART_TI752_TLR_RX 4 79 80 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 81 #define TRIGGER_FCR_MASK(x) (x & 3) 82 83 /* Enable XON/XOFF flow control on output */ 84 #define OMAP_UART_SW_TX 0x08 85 /* Enable XON/XOFF flow control on input */ 86 #define OMAP_UART_SW_RX 0x02 87 88 #define OMAP_UART_WER_MOD_WKUP 0x7f 89 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 90 91 #define TX_TRIGGER 1 92 #define RX_TRIGGER 48 93 94 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 95 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 96 97 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 98 99 #define OMAP_UART_REV_46 0x0406 100 #define OMAP_UART_REV_52 0x0502 101 #define OMAP_UART_REV_63 0x0603 102 103 /* Resume register */ 104 #define UART_OMAP_RESUME 0x0B 105 106 /* Interrupt Enable Register 2 */ 107 #define UART_OMAP_IER2 0x1B 108 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 109 110 /* Mode Definition Register 3 */ 111 #define UART_OMAP_MDR3 0x20 112 #define UART_OMAP_MDR3_DIR_POL BIT(3) 113 #define UART_OMAP_MDR3_DIR_EN BIT(4) 114 115 /* Enhanced features register 2 */ 116 #define UART_OMAP_EFR2 0x23 117 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 118 119 /* RX FIFO occupancy indicator */ 120 #define UART_OMAP_RX_LVL 0x19 121 122 /* Timeout low and High */ 123 #define UART_OMAP_TO_L 0x26 124 #define UART_OMAP_TO_H 0x27 125 struct omap8250_priv { 126 void __iomem *membase; 127 int line; 128 u8 habit; 129 u8 mdr1; 130 u8 mdr3; 131 u8 efr; 132 u8 scr; 133 u8 wer; 134 u8 xon; 135 u8 xoff; 136 u8 delayed_restore; 137 u16 quot; 138 139 u8 tx_trigger; 140 u8 rx_trigger; 141 atomic_t active; 142 bool is_suspending; 143 int wakeirq; 144 u32 latency; 145 u32 calc_latency; 146 struct pm_qos_request pm_qos_request; 147 struct work_struct qos_work; 148 struct uart_8250_dma omap8250_dma; 149 spinlock_t rx_dma_lock; 150 bool rx_dma_broken; 151 bool throttled; 152 153 struct pinctrl *pinctrl; 154 struct pinctrl_state *pinctrl_wakeup; 155 }; 156 157 struct omap8250_dma_params { 158 u32 rx_size; 159 u8 rx_trigger; 160 u8 tx_trigger; 161 }; 162 163 struct omap8250_platdata { 164 struct omap8250_dma_params *dma_params; 165 u8 habit; 166 }; 167 168 #ifdef CONFIG_SERIAL_8250_DMA 169 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 170 #else 171 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 172 #endif 173 174 static u32 uart_read(struct omap8250_priv *priv, u32 reg) 175 { 176 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 177 } 178 179 /* 180 * Called on runtime PM resume path from omap8250_restore_regs(), and 181 * omap8250_set_mctrl(). 182 */ 183 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 184 { 185 struct uart_8250_port *up = up_to_u8250p(port); 186 struct omap8250_priv *priv = port->private_data; 187 u8 lcr; 188 189 serial8250_do_set_mctrl(port, mctrl); 190 191 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 192 /* 193 * Turn off autoRTS if RTS is lowered and restore autoRTS 194 * setting if RTS is raised 195 */ 196 lcr = serial_in(up, UART_LCR); 197 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 198 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 199 priv->efr |= UART_EFR_RTS; 200 else 201 priv->efr &= ~UART_EFR_RTS; 202 serial_out(up, UART_EFR, priv->efr); 203 serial_out(up, UART_LCR, lcr); 204 } 205 } 206 207 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 208 { 209 int err; 210 211 err = pm_runtime_resume_and_get(port->dev); 212 if (err) 213 return; 214 215 __omap8250_set_mctrl(port, mctrl); 216 217 pm_runtime_mark_last_busy(port->dev); 218 pm_runtime_put_autosuspend(port->dev); 219 } 220 221 /* 222 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 223 * The access to uart register after MDR1 Access 224 * causes UART to corrupt data. 225 * 226 * Need a delay = 227 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 228 * give 10 times as much 229 */ 230 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 231 struct omap8250_priv *priv) 232 { 233 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 234 udelay(2); 235 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 236 UART_FCR_CLEAR_RCVR); 237 } 238 239 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 240 struct omap8250_priv *priv) 241 { 242 unsigned int uartclk = port->uartclk; 243 unsigned int div_13, div_16; 244 unsigned int abs_d13, abs_d16; 245 246 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 247 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 248 249 if (!div_13) 250 div_13 = 1; 251 if (!div_16) 252 div_16 = 1; 253 254 abs_d13 = abs(baud - uartclk / 13 / div_13); 255 abs_d16 = abs(baud - uartclk / 16 / div_16); 256 257 if (abs_d13 >= abs_d16) { 258 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 259 priv->quot = div_16; 260 } else { 261 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 262 priv->quot = div_13; 263 } 264 } 265 266 static void omap8250_update_scr(struct uart_8250_port *up, 267 struct omap8250_priv *priv) 268 { 269 u8 old_scr; 270 271 old_scr = serial_in(up, UART_OMAP_SCR); 272 if (old_scr == priv->scr) 273 return; 274 275 /* 276 * The manual recommends not to enable the DMA mode selector in the SCR 277 * (instead of the FCR) register _and_ selecting the DMA mode as one 278 * register write because this may lead to malfunction. 279 */ 280 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 281 serial_out(up, UART_OMAP_SCR, 282 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 283 serial_out(up, UART_OMAP_SCR, priv->scr); 284 } 285 286 static void omap8250_update_mdr1(struct uart_8250_port *up, 287 struct omap8250_priv *priv) 288 { 289 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 290 omap_8250_mdr1_errataset(up, priv); 291 else 292 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 293 } 294 295 static void omap8250_restore_regs(struct uart_8250_port *up) 296 { 297 struct uart_port *port = &up->port; 298 struct omap8250_priv *priv = port->private_data; 299 struct uart_8250_dma *dma = up->dma; 300 u8 mcr = serial8250_in_MCR(up); 301 302 /* Port locked to synchronize UART_IER access against the console. */ 303 lockdep_assert_held_once(&port->lock); 304 305 if (dma && dma->tx_running) { 306 /* 307 * TCSANOW requests the change to occur immediately however if 308 * we have a TX-DMA operation in progress then it has been 309 * observed that it might stall and never complete. Therefore we 310 * delay DMA completes to prevent this hang from happen. 311 */ 312 priv->delayed_restore = 1; 313 return; 314 } 315 316 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 317 serial_out(up, UART_EFR, UART_EFR_ECB); 318 319 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 320 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 321 serial_out(up, UART_FCR, up->fcr); 322 323 omap8250_update_scr(up, priv); 324 325 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 326 327 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 328 OMAP_UART_TCR_HALT(52)); 329 serial_out(up, UART_TI752_TLR, 330 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 331 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 332 333 serial_out(up, UART_LCR, 0); 334 335 /* drop TCR + TLR access, we setup XON/XOFF later */ 336 serial8250_out_MCR(up, mcr); 337 338 serial_out(up, UART_IER, up->ier); 339 340 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 341 serial_dl_write(up, priv->quot); 342 343 serial_out(up, UART_EFR, priv->efr); 344 345 /* Configure flow control */ 346 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 347 serial_out(up, UART_XON1, priv->xon); 348 serial_out(up, UART_XOFF1, priv->xoff); 349 350 serial_out(up, UART_LCR, up->lcr); 351 352 omap8250_update_mdr1(up, priv); 353 354 __omap8250_set_mctrl(port, port->mctrl); 355 356 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 357 358 if (port->rs485.flags & SER_RS485_ENABLED && 359 port->rs485_config == serial8250_em485_config) 360 serial8250_em485_stop_tx(up, true); 361 } 362 363 static void omap_8250_set_termios_atomic(struct uart_port *port, struct ktermios *termios, 364 const struct ktermios *old, unsigned int baud) 365 { 366 struct uart_8250_port *up = up_to_u8250p(port); 367 struct omap8250_priv *priv = port->private_data; 368 u8 cval; 369 370 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 371 372 if (termios->c_cflag & CSTOPB) 373 cval |= UART_LCR_STOP; 374 if (termios->c_cflag & PARENB) 375 cval |= UART_LCR_PARITY; 376 if (!(termios->c_cflag & PARODD)) 377 cval |= UART_LCR_EPAR; 378 if (termios->c_cflag & CMSPAR) 379 cval |= UART_LCR_SPAR; 380 381 omap_8250_get_divisor(port, baud, priv); 382 383 /* 384 * Ok, we're now changing the port state. Do it with 385 * interrupts disabled. 386 */ 387 guard(serial8250_rpm)(up); 388 guard(uart_port_lock_irq)(port); 389 390 /* 391 * Update the per-port timeout. 392 */ 393 uart_update_timeout(port, termios->c_cflag, baud); 394 395 /* 396 * Specify which conditions may be considered for error 397 * handling and the ignoring of characters. The actual 398 * ignoring of characters only occurs if the bit is set 399 * in @ignore_status_mask as well. 400 */ 401 port->read_status_mask = UART_LSR_OE | UART_LSR_DR; 402 if (termios->c_iflag & INPCK) 403 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 404 if (termios->c_iflag & (IGNBRK | PARMRK)) 405 port->read_status_mask |= UART_LSR_BI; 406 407 /* 408 * Characters to ignore 409 */ 410 port->ignore_status_mask = 0; 411 if (termios->c_iflag & IGNPAR) 412 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 413 if (termios->c_iflag & IGNBRK) { 414 port->ignore_status_mask |= UART_LSR_BI; 415 /* 416 * If we're ignoring parity and break indicators, 417 * ignore overruns too (for real raw support). 418 */ 419 if (termios->c_iflag & IGNPAR) 420 port->ignore_status_mask |= UART_LSR_OE; 421 } 422 423 /* 424 * ignore all characters if CREAD is not set 425 */ 426 if ((termios->c_cflag & CREAD) == 0) 427 port->ignore_status_mask |= UART_LSR_DR; 428 429 /* 430 * Modem status interrupts 431 */ 432 up->ier &= ~UART_IER_MSI; 433 if (UART_ENABLE_MS(port, termios->c_cflag)) 434 up->ier |= UART_IER_MSI; 435 436 up->lcr = cval; 437 /* Up to here it was mostly serial8250_do_set_termios() */ 438 439 /* 440 * We enable TRIG_GRANU for RX and TX and additionally we set 441 * SCR_TX_EMPTY bit. The result is the following: 442 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 443 * - less than RX_TRIGGER number of bytes will also cause an interrupt 444 * once the UART decides that there no new bytes arriving. 445 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 446 * empty - the trigger level is ignored here. 447 * 448 * Once DMA is enabled: 449 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 450 * bytes in the TX FIFO. On each assert the DMA engine will move 451 * TX_TRIGGER bytes into the FIFO. 452 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 453 * the FIFO and move RX_TRIGGER bytes. 454 * This is because threshold and trigger values are the same. 455 */ 456 up->fcr = UART_FCR_ENABLE_FIFO; 457 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 458 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 459 460 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 461 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 462 463 if (up->dma) 464 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 465 OMAP_UART_SCR_DMAMODE_CTL; 466 467 priv->xon = termios->c_cc[VSTART]; 468 priv->xoff = termios->c_cc[VSTOP]; 469 470 priv->efr = 0; 471 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 472 473 if (termios->c_cflag & CRTSCTS && port->flags & UPF_HARD_FLOW && 474 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 475 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 476 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 477 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 478 priv->efr |= UART_EFR_CTS; 479 } else if (port->flags & UPF_SOFT_FLOW) { 480 /* 481 * OMAP rx s/w flow control is borked; the transmitter remains 482 * stuck off even if rx flow control is subsequently disabled 483 */ 484 485 /* 486 * IXOFF Flag: 487 * Enable XON/XOFF flow control on output. 488 * Transmit XON1, XOFF1 489 */ 490 if (termios->c_iflag & IXOFF) { 491 port->status |= UPSTAT_AUTOXOFF; 492 priv->efr |= OMAP_UART_SW_TX; 493 } 494 } 495 omap8250_restore_regs(up); 496 } 497 498 /* 499 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 500 * some differences in how we want to handle flow control. 501 */ 502 static void omap_8250_set_termios(struct uart_port *port, 503 struct ktermios *termios, 504 const struct ktermios *old) 505 { 506 struct omap8250_priv *priv = port->private_data; 507 unsigned int baud; 508 509 /* 510 * Ask the core to calculate the divisor for us. 511 */ 512 baud = uart_get_baud_rate(port, termios, old, 513 port->uartclk / 16 / UART_DIV_MAX, 514 port->uartclk / 13); 515 516 omap_8250_set_termios_atomic(port, termios, old, baud); 517 518 /* calculate wakeup latency constraint */ 519 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 520 priv->latency = priv->calc_latency; 521 522 schedule_work(&priv->qos_work); 523 524 /* Don't rewrite B0 */ 525 if (tty_termios_baud_rate(termios)) 526 tty_termios_encode_baud_rate(termios, baud, baud); 527 } 528 529 /* same as 8250 except that we may have extra flow bits set in EFR */ 530 static void omap_8250_pm(struct uart_port *port, unsigned int state, 531 unsigned int oldstate) 532 { 533 struct uart_8250_port *up = up_to_u8250p(port); 534 u8 efr; 535 536 guard(serial8250_rpm)(up); 537 /* Synchronize UART_IER access against the console. */ 538 guard(uart_port_lock_irq)(port); 539 540 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 541 efr = serial_in(up, UART_EFR); 542 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 543 serial_out(up, UART_LCR, 0); 544 545 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 546 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 547 serial_out(up, UART_EFR, efr); 548 serial_out(up, UART_LCR, 0); 549 } 550 551 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 552 struct omap8250_priv *priv) 553 { 554 static const struct soc_device_attribute k3_soc_devices[] = { 555 { .family = "AM65X", }, 556 { .family = "J721E", .revision = "SR1.0" }, 557 { /* sentinel */ } 558 }; 559 u32 mvr, scheme; 560 u16 revision, major, minor; 561 562 mvr = uart_read(priv, UART_OMAP_MVER); 563 564 /* Check revision register scheme */ 565 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 566 567 switch (scheme) { 568 case 0: /* Legacy Scheme: OMAP2/3 */ 569 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 570 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 571 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 572 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 573 break; 574 case 1: 575 /* New Scheme: OMAP4+ */ 576 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 577 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 578 OMAP_UART_MVR_MAJ_SHIFT; 579 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 580 break; 581 default: 582 dev_warn(up->port.dev, 583 "Unknown revision, defaulting to highest\n"); 584 /* highest possible revision */ 585 major = 0xff; 586 minor = 0xff; 587 } 588 /* normalize revision for the driver */ 589 revision = UART_BUILD_REVISION(major, minor); 590 591 switch (revision) { 592 case OMAP_UART_REV_46: 593 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 594 break; 595 case OMAP_UART_REV_52: 596 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 597 OMAP_UART_WER_HAS_TX_WAKEUP; 598 break; 599 case OMAP_UART_REV_63: 600 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 601 OMAP_UART_WER_HAS_TX_WAKEUP; 602 break; 603 default: 604 break; 605 } 606 607 /* 608 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 609 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 610 * to enable errata workaround. 611 */ 612 if (soc_device_match(k3_soc_devices)) 613 priv->habit &= ~UART_HAS_RHR_IT_DIS; 614 } 615 616 static void omap8250_uart_qos_work(struct work_struct *work) 617 { 618 struct omap8250_priv *priv; 619 620 priv = container_of(work, struct omap8250_priv, qos_work); 621 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 622 } 623 624 #ifdef CONFIG_SERIAL_8250_DMA 625 static int omap_8250_dma_handle_irq(struct uart_port *port); 626 #endif 627 628 static irqreturn_t omap8250_irq(int irq, void *dev_id) 629 { 630 struct omap8250_priv *priv = dev_id; 631 struct uart_8250_port *up = serial8250_get_port(priv->line); 632 struct uart_port *port = &up->port; 633 unsigned int iir, lsr; 634 int ret; 635 636 pm_runtime_get_noresume(port->dev); 637 638 /* Shallow idle state wake-up to an IO interrupt? */ 639 if (atomic_add_unless(&priv->active, 1, 1)) { 640 priv->latency = priv->calc_latency; 641 schedule_work(&priv->qos_work); 642 } 643 644 #ifdef CONFIG_SERIAL_8250_DMA 645 if (up->dma) { 646 ret = omap_8250_dma_handle_irq(port); 647 pm_runtime_mark_last_busy(port->dev); 648 pm_runtime_put(port->dev); 649 return IRQ_RETVAL(ret); 650 } 651 #endif 652 653 lsr = serial_port_in(port, UART_LSR); 654 iir = serial_port_in(port, UART_IIR); 655 ret = serial8250_handle_irq(port, iir); 656 657 /* 658 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 659 * FIFO has been drained or erroneously. 660 * So apply solution of Errata i2310 as mentioned in 661 * https://www.ti.com/lit/pdf/sprz536 662 */ 663 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 664 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 665 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 666 unsigned char efr2, timeout_h, timeout_l; 667 668 efr2 = serial_in(up, UART_OMAP_EFR2); 669 timeout_h = serial_in(up, UART_OMAP_TO_H); 670 timeout_l = serial_in(up, UART_OMAP_TO_L); 671 serial_out(up, UART_OMAP_TO_H, 0xFF); 672 serial_out(up, UART_OMAP_TO_L, 0xFF); 673 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 674 serial_in(up, UART_IIR); 675 serial_out(up, UART_OMAP_EFR2, efr2); 676 serial_out(up, UART_OMAP_TO_H, timeout_h); 677 serial_out(up, UART_OMAP_TO_L, timeout_l); 678 } 679 680 /* Stop processing interrupts on input overrun */ 681 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 682 unsigned long delay; 683 684 /* Synchronize UART_IER access against the console. */ 685 uart_port_lock(port); 686 up->ier = serial_port_in(port, UART_IER); 687 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 688 port->ops->stop_rx(port); 689 } else { 690 /* Keep restarting the timer until 691 * the input overrun subsides. 692 */ 693 cancel_delayed_work(&up->overrun_backoff); 694 } 695 uart_port_unlock(port); 696 697 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 698 schedule_delayed_work(&up->overrun_backoff, delay); 699 } 700 701 pm_runtime_mark_last_busy(port->dev); 702 pm_runtime_put(port->dev); 703 704 return IRQ_RETVAL(ret); 705 } 706 707 static int omap_8250_startup(struct uart_port *port) 708 { 709 struct uart_8250_port *up = up_to_u8250p(port); 710 struct omap8250_priv *priv = port->private_data; 711 struct uart_8250_dma *dma = &priv->omap8250_dma; 712 int ret; 713 714 #ifdef CONFIG_PM 715 up->capabilities |= UART_CAP_RPM; 716 #endif 717 718 guard(serial8250_rpm)(up); 719 720 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 721 722 serial_out(up, UART_LCR, UART_LCR_WLEN8); 723 724 up->lsr_saved_flags = 0; 725 up->msr_saved_flags = 0; 726 727 /* Disable DMA for console UART */ 728 if (dma->fn && !uart_console(port)) { 729 up->dma = &priv->omap8250_dma; 730 ret = serial8250_request_dma(up); 731 if (ret) { 732 dev_warn_ratelimited(port->dev, 733 "failed to request DMA\n"); 734 up->dma = NULL; 735 } 736 } else { 737 up->dma = NULL; 738 } 739 740 /* Synchronize UART_IER access against the console. */ 741 scoped_guard(uart_port_lock_irq, port) { 742 up->ier = UART_IER_RLSI | UART_IER_RDI; 743 serial_out(up, UART_IER, up->ier); 744 } 745 746 /* Enable module level wake up */ 747 priv->wer = OMAP_UART_WER_MOD_WKUP; 748 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 749 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 750 serial_out(up, UART_OMAP_WER, priv->wer); 751 752 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 753 guard(uart_port_lock_irq)(port); 754 up->dma->rx_dma(up); 755 } 756 757 enable_irq(port->irq); 758 759 return 0; 760 } 761 762 static void omap_8250_shutdown(struct uart_port *port) 763 { 764 struct uart_8250_port *up = up_to_u8250p(port); 765 struct omap8250_priv *priv = port->private_data; 766 767 guard(serial8250_rpm)(up); 768 769 flush_work(&priv->qos_work); 770 if (up->dma) 771 omap_8250_rx_dma_flush(up); 772 773 serial_out(up, UART_OMAP_WER, 0); 774 if (priv->habit & UART_HAS_EFR2) 775 serial_out(up, UART_OMAP_EFR2, 0x0); 776 777 /* Synchronize UART_IER access against the console. */ 778 scoped_guard(uart_port_lock_irq, port) { 779 up->ier = 0; 780 serial_out(up, UART_IER, 0); 781 } 782 783 disable_irq_nosync(port->irq); 784 785 serial8250_release_dma(up); 786 up->dma = NULL; 787 788 /* 789 * Disable break condition and FIFOs 790 */ 791 if (up->lcr & UART_LCR_SBC) 792 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 793 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 794 } 795 796 static void omap_8250_throttle(struct uart_port *port) 797 { 798 struct omap8250_priv *priv = port->private_data; 799 800 guard(serial8250_rpm)(up_to_u8250p(port)); 801 guard(uart_port_lock_irqsave)(port); 802 803 port->ops->stop_rx(port); 804 priv->throttled = true; 805 } 806 807 static void omap_8250_unthrottle(struct uart_port *port) 808 { 809 struct omap8250_priv *priv = port->private_data; 810 struct uart_8250_port *up = up_to_u8250p(port); 811 812 guard(serial8250_rpm)(up); 813 /* Synchronize UART_IER access against the console. */ 814 guard(uart_port_lock_irqsave)(port); 815 816 priv->throttled = false; 817 if (up->dma) 818 up->dma->rx_dma(up); 819 up->ier |= UART_IER_RLSI | UART_IER_RDI; 820 serial_out(up, UART_IER, up->ier); 821 } 822 823 static int omap8250_rs485_config(struct uart_port *port, 824 struct ktermios *termios, 825 struct serial_rs485 *rs485) 826 { 827 struct omap8250_priv *priv = port->private_data; 828 struct uart_8250_port *up = up_to_u8250p(port); 829 u32 fixed_delay_rts_before_send = 0; 830 u32 fixed_delay_rts_after_send = 0; 831 unsigned int baud; 832 833 /* 834 * There is a fixed delay of 3 bit clock cycles after the TX shift 835 * register is going empty to allow time for the stop bit to transition 836 * through the transceiver before direction is changed to receive. 837 * 838 * Additionally there appears to be a 1 bit clock delay between writing 839 * to the THR register and transmission of the start bit, per page 8783 840 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 841 */ 842 if (priv->quot) { 843 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 844 baud = port->uartclk / (16 * priv->quot); 845 else 846 baud = port->uartclk / (13 * priv->quot); 847 848 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 849 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 850 } 851 852 /* 853 * Fall back to RS485 software emulation if the UART is missing 854 * hardware support, if the device tree specifies an mctrl_gpio 855 * (indicates that RTS is unavailable due to a pinmux conflict) 856 * or if the requested delays exceed the fixed hardware delays. 857 */ 858 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 859 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 860 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 861 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 862 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 863 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 864 865 port->rs485_config = serial8250_em485_config; 866 return serial8250_em485_config(port, termios, rs485); 867 } 868 869 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 870 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 871 872 if (rs485->flags & SER_RS485_ENABLED) 873 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 874 else 875 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 876 877 /* 878 * Retain same polarity semantics as RS485 software emulation, 879 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 880 */ 881 if (rs485->flags & SER_RS485_RTS_ON_SEND) 882 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 883 else 884 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 885 886 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 887 888 return 0; 889 } 890 891 #ifdef CONFIG_SERIAL_8250_DMA 892 static int omap_8250_rx_dma(struct uart_8250_port *p); 893 894 /* Must be called while priv->rx_dma_lock is held */ 895 static void __dma_rx_do_complete(struct uart_8250_port *p) 896 { 897 struct uart_8250_dma *dma = p->dma; 898 struct tty_port *tty_port = &p->port.state->port; 899 struct omap8250_priv *priv = p->port.private_data; 900 struct dma_chan *rxchan = dma->rxchan; 901 dma_cookie_t cookie; 902 struct dma_tx_state state; 903 int count; 904 int ret; 905 u32 reg; 906 907 if (!dma->rx_running) 908 goto out; 909 910 cookie = dma->rx_cookie; 911 912 /* Re-enable RX FIFO interrupt now that transfer is complete */ 913 if (priv->habit & UART_HAS_RHR_IT_DIS) { 914 reg = serial_in(p, UART_OMAP_IER2); 915 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 916 serial_out(p, UART_OMAP_IER2, reg); 917 } 918 919 dmaengine_tx_status(rxchan, cookie, &state); 920 921 count = dma->rx_size - state.residue + state.in_flight_bytes; 922 if (count < dma->rx_size) { 923 dmaengine_terminate_async(rxchan); 924 925 /* 926 * Poll for teardown to complete which guarantees in 927 * flight data is drained. 928 */ 929 if (state.in_flight_bytes) { 930 int poll_count = 25; 931 932 while (dmaengine_tx_status(rxchan, cookie, NULL) && 933 poll_count--) 934 cpu_relax(); 935 936 if (poll_count == -1) 937 dev_err(p->port.dev, "teardown incomplete\n"); 938 } 939 } 940 941 dma->rx_running = 0; 942 if (!count) 943 goto out; 944 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 945 946 p->port.icount.rx += ret; 947 p->port.icount.buf_overrun += count - ret; 948 out: 949 950 tty_flip_buffer_push(tty_port); 951 } 952 953 static void __dma_rx_complete(void *param) 954 { 955 struct uart_8250_port *p = param; 956 struct omap8250_priv *priv = p->port.private_data; 957 struct uart_8250_dma *dma = p->dma; 958 struct dma_tx_state state; 959 960 /* Synchronize UART_IER access against the console. */ 961 guard(uart_port_lock_irqsave)(&p->port); 962 963 /* 964 * If the tx status is not DMA_COMPLETE, then this is a delayed 965 * completion callback. A previous RX timeout flush would have 966 * already pushed the data, so exit. 967 */ 968 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != DMA_COMPLETE) 969 return; 970 971 __dma_rx_do_complete(p); 972 if (priv->throttled) 973 return; 974 975 p->ier |= UART_IER_RLSI | UART_IER_RDI; 976 serial_out(p, UART_IER, p->ier); 977 if (!(priv->habit & UART_HAS_EFR2)) 978 omap_8250_rx_dma(p); 979 } 980 981 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 982 { 983 struct omap8250_priv *priv = p->port.private_data; 984 struct uart_8250_dma *dma = p->dma; 985 struct dma_tx_state state; 986 unsigned long flags; 987 int ret; 988 989 spin_lock_irqsave(&priv->rx_dma_lock, flags); 990 991 if (!dma->rx_running) { 992 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 993 return; 994 } 995 996 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 997 if (ret == DMA_IN_PROGRESS) { 998 ret = dmaengine_pause(dma->rxchan); 999 if (WARN_ON_ONCE(ret)) 1000 priv->rx_dma_broken = true; 1001 } 1002 __dma_rx_do_complete(p); 1003 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1004 } 1005 1006 static int omap_8250_rx_dma(struct uart_8250_port *p) 1007 { 1008 struct omap8250_priv *priv = p->port.private_data; 1009 struct uart_8250_dma *dma = p->dma; 1010 int err = 0; 1011 struct dma_async_tx_descriptor *desc; 1012 unsigned long flags; 1013 u32 reg; 1014 1015 /* Port locked to synchronize UART_IER access against the console. */ 1016 lockdep_assert_held_once(&p->port.lock); 1017 1018 if (priv->rx_dma_broken) 1019 return -EINVAL; 1020 1021 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1022 1023 if (dma->rx_running) { 1024 enum dma_status state; 1025 1026 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1027 if (state == DMA_COMPLETE) { 1028 /* 1029 * Disable RX interrupts to allow RX DMA completion 1030 * callback to run. 1031 */ 1032 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1033 serial_out(p, UART_IER, p->ier); 1034 } 1035 goto out; 1036 } 1037 1038 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1039 dma->rx_size, DMA_DEV_TO_MEM, 1040 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1041 if (!desc) { 1042 err = -EBUSY; 1043 goto out; 1044 } 1045 1046 dma->rx_running = 1; 1047 desc->callback = __dma_rx_complete; 1048 desc->callback_param = p; 1049 1050 dma->rx_cookie = dmaengine_submit(desc); 1051 1052 /* 1053 * Disable RX FIFO interrupt while RX DMA is enabled, else 1054 * spurious interrupt may be raised when data is in the RX FIFO 1055 * but is yet to be drained by DMA. 1056 */ 1057 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1058 reg = serial_in(p, UART_OMAP_IER2); 1059 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1060 serial_out(p, UART_OMAP_IER2, reg); 1061 } 1062 1063 dma_async_issue_pending(dma->rxchan); 1064 out: 1065 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1066 return err; 1067 } 1068 1069 static int omap_8250_tx_dma(struct uart_8250_port *p); 1070 1071 static void omap_8250_dma_tx_complete(void *param) 1072 { 1073 struct uart_8250_port *p = param; 1074 struct uart_8250_dma *dma = p->dma; 1075 struct tty_port *tport = &p->port.state->port; 1076 bool en_thri = false; 1077 struct omap8250_priv *priv = p->port.private_data; 1078 1079 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1080 UART_XMIT_SIZE, DMA_TO_DEVICE); 1081 1082 guard(uart_port_lock_irqsave)(&p->port); 1083 1084 dma->tx_running = 0; 1085 1086 uart_xmit_advance(&p->port, dma->tx_size); 1087 1088 if (priv->delayed_restore) { 1089 priv->delayed_restore = 0; 1090 omap8250_restore_regs(p); 1091 } 1092 1093 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1094 uart_write_wakeup(&p->port); 1095 1096 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { 1097 int ret; 1098 1099 ret = omap_8250_tx_dma(p); 1100 if (ret) 1101 en_thri = true; 1102 } else if (p->capabilities & UART_CAP_RPM) { 1103 en_thri = true; 1104 } 1105 1106 if (en_thri) { 1107 dma->tx_err = 1; 1108 serial8250_set_THRI(p); 1109 } 1110 } 1111 1112 static int omap_8250_tx_dma(struct uart_8250_port *p) 1113 { 1114 struct uart_8250_dma *dma = p->dma; 1115 struct omap8250_priv *priv = p->port.private_data; 1116 struct tty_port *tport = &p->port.state->port; 1117 struct dma_async_tx_descriptor *desc; 1118 struct scatterlist sg; 1119 int skip_byte = -1; 1120 int ret; 1121 1122 if (dma->tx_running) 1123 return 0; 1124 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { 1125 1126 /* 1127 * Even if no data, we need to return an error for the two cases 1128 * below so serial8250_tx_chars() is invoked and properly clears 1129 * THRI and/or runtime suspend. 1130 */ 1131 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1132 ret = -EBUSY; 1133 goto err; 1134 } 1135 serial8250_clear_THRI(p); 1136 return 0; 1137 } 1138 1139 if (priv->habit & OMAP_DMA_TX_KICK) { 1140 unsigned char c; 1141 u8 tx_lvl; 1142 1143 /* 1144 * We need to put the first byte into the FIFO in order to start 1145 * the DMA transfer. For transfers smaller than four bytes we 1146 * don't bother doing DMA at all. It seem not matter if there 1147 * are still bytes in the FIFO from the last transfer (in case 1148 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1149 * leaving the FIFO seem not to trigger the DMA transfer. It is 1150 * really the byte that we put into the FIFO. 1151 * If the FIFO is already full then we most likely got here from 1152 * omap_8250_dma_tx_complete(). And this means the DMA engine 1153 * just completed its work. We don't have to wait the complete 1154 * 86us at 115200,8n1 but around 60us (not to mention lower 1155 * baudrates). So in that case we take the interrupt and try 1156 * again with an empty FIFO. 1157 */ 1158 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1159 if (tx_lvl == p->tx_loadsz) { 1160 ret = -EBUSY; 1161 goto err; 1162 } 1163 if (kfifo_len(&tport->xmit_fifo) < 4) { 1164 ret = -EINVAL; 1165 goto err; 1166 } 1167 if (!uart_fifo_out(&p->port, &c, 1)) { 1168 ret = -EINVAL; 1169 goto err; 1170 } 1171 skip_byte = c; 1172 } 1173 1174 sg_init_table(&sg, 1); 1175 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, UART_XMIT_SIZE, dma->tx_addr); 1176 if (ret != 1) { 1177 ret = -EINVAL; 1178 goto err; 1179 } 1180 1181 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, 1182 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1183 if (!desc) { 1184 ret = -EBUSY; 1185 goto err; 1186 } 1187 1188 dma->tx_size = sg_dma_len(&sg); 1189 dma->tx_running = 1; 1190 1191 desc->callback = omap_8250_dma_tx_complete; 1192 desc->callback_param = p; 1193 1194 dma->tx_cookie = dmaengine_submit(desc); 1195 1196 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1197 UART_XMIT_SIZE, DMA_TO_DEVICE); 1198 1199 dma_async_issue_pending(dma->txchan); 1200 if (dma->tx_err) 1201 dma->tx_err = 0; 1202 1203 serial8250_clear_THRI(p); 1204 ret = 0; 1205 goto out_skip; 1206 err: 1207 dma->tx_err = 1; 1208 out_skip: 1209 if (skip_byte >= 0) 1210 serial_out(p, UART_TX, skip_byte); 1211 return ret; 1212 } 1213 1214 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1215 { 1216 switch (iir & 0x3f) { 1217 case UART_IIR_RLSI: 1218 case UART_IIR_RX_TIMEOUT: 1219 case UART_IIR_RDI: 1220 omap_8250_rx_dma_flush(up); 1221 return true; 1222 } 1223 return omap_8250_rx_dma(up); 1224 } 1225 1226 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1227 { 1228 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1229 (iir & UART_IIR_RDI)) { 1230 if (handle_rx_dma(up, iir)) { 1231 status = serial8250_rx_chars(up, status); 1232 omap_8250_rx_dma(up); 1233 } 1234 } 1235 1236 return status; 1237 } 1238 1239 static void am654_8250_handle_uart_errors(struct uart_8250_port *up, u8 iir, u16 status) 1240 { 1241 if (status & UART_LSR_OE) { 1242 serial8250_clear_and_reinit_fifos(up); 1243 serial_in(up, UART_LSR); 1244 serial_in(up, UART_OMAP_RESUME); 1245 } else { 1246 if (status & (UART_LSR_FE | UART_LSR_PE | UART_LSR_BI)) 1247 serial_in(up, UART_RX); 1248 if (iir & UART_IIR_XOFF) 1249 serial_in(up, UART_IIR); 1250 } 1251 } 1252 1253 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1254 u16 status) 1255 { 1256 /* Port locked to synchronize UART_IER access against the console. */ 1257 lockdep_assert_held_once(&up->port.lock); 1258 1259 /* 1260 * Queue a new transfer if FIFO has data. 1261 */ 1262 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1263 (up->ier & UART_IER_RDI) && !(status & UART_LSR_OE)) { 1264 am654_8250_handle_uart_errors(up, iir, status); 1265 omap_8250_rx_dma(up); 1266 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1267 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1268 /* 1269 * Disable RX timeout, read IIR to clear 1270 * current timeout condition, clear EFR2 to 1271 * periodic timeouts, re-enable interrupts. 1272 */ 1273 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1274 serial_out(up, UART_IER, up->ier); 1275 omap_8250_rx_dma_flush(up); 1276 serial_in(up, UART_IIR); 1277 serial_out(up, UART_OMAP_EFR2, 0x0); 1278 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1279 serial_out(up, UART_IER, up->ier); 1280 } else { 1281 am654_8250_handle_uart_errors(up, iir, status); 1282 } 1283 } 1284 1285 /* 1286 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1287 * hook for RX/TX and need different logic for them in the ISR. Therefore we 1288 * use the default routine in the non-DMA case and this one for with DMA. 1289 */ 1290 static int omap_8250_dma_handle_irq(struct uart_port *port) 1291 { 1292 struct uart_8250_port *up = up_to_u8250p(port); 1293 struct omap8250_priv *priv = port->private_data; 1294 u16 status; 1295 u8 iir; 1296 1297 iir = serial_port_in(port, UART_IIR); 1298 if (iir & UART_IIR_NO_INT) { 1299 return IRQ_HANDLED; 1300 } 1301 1302 uart_port_lock(port); 1303 1304 status = serial_port_in(port, UART_LSR); 1305 1306 if ((iir & 0x3f) != UART_IIR_THRI) { 1307 if (priv->habit & UART_HAS_EFR2) 1308 am654_8250_handle_rx_dma(up, iir, status); 1309 else 1310 status = omap_8250_handle_rx_dma(up, iir, status); 1311 } 1312 1313 serial8250_modem_status(up); 1314 if (status & UART_LSR_THRE && up->dma->tx_err) { 1315 if (uart_tx_stopped(port) || 1316 kfifo_is_empty(&port->state->port.xmit_fifo)) { 1317 up->dma->tx_err = 0; 1318 serial8250_tx_chars(up); 1319 } else { 1320 /* 1321 * try again due to an earlier failure which 1322 * might have been resolved by now. 1323 */ 1324 if (omap_8250_tx_dma(up)) 1325 serial8250_tx_chars(up); 1326 } 1327 } 1328 1329 uart_unlock_and_check_sysrq(port); 1330 1331 return 1; 1332 } 1333 1334 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1335 { 1336 return false; 1337 } 1338 1339 #else 1340 1341 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1342 { 1343 return -EINVAL; 1344 } 1345 #endif 1346 1347 static int omap8250_no_handle_irq(struct uart_port *port) 1348 { 1349 /* IRQ has not been requested but handling irq? */ 1350 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1351 return 0; 1352 } 1353 1354 static int omap8250_select_wakeup_pinctrl(struct device *dev, 1355 struct omap8250_priv *priv) 1356 { 1357 if (IS_ERR_OR_NULL(priv->pinctrl_wakeup)) 1358 return 0; 1359 1360 if (!device_may_wakeup(dev)) 1361 return 0; 1362 1363 device_set_out_band_wakeup(dev); 1364 1365 return pinctrl_select_state(priv->pinctrl, priv->pinctrl_wakeup); 1366 } 1367 1368 static struct omap8250_dma_params am654_dma = { 1369 .rx_size = SZ_2K, 1370 .rx_trigger = 1, 1371 .tx_trigger = TX_TRIGGER, 1372 }; 1373 1374 static struct omap8250_dma_params am33xx_dma = { 1375 .rx_size = RX_TRIGGER, 1376 .rx_trigger = RX_TRIGGER, 1377 .tx_trigger = TX_TRIGGER, 1378 }; 1379 1380 static struct omap8250_platdata am654_platdata = { 1381 .dma_params = &am654_dma, 1382 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1383 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1384 }; 1385 1386 static struct omap8250_platdata am33xx_platdata = { 1387 .dma_params = &am33xx_dma, 1388 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1389 }; 1390 1391 static struct omap8250_platdata omap4_platdata = { 1392 .dma_params = &am33xx_dma, 1393 .habit = UART_ERRATA_CLOCK_DISABLE, 1394 }; 1395 1396 static const struct of_device_id omap8250_dt_ids[] = { 1397 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1398 { .compatible = "ti,omap2-uart" }, 1399 { .compatible = "ti,omap3-uart" }, 1400 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1401 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1402 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1403 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1404 {}, 1405 }; 1406 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1407 1408 static int omap8250_probe(struct platform_device *pdev) 1409 { 1410 struct device_node *np = pdev->dev.of_node; 1411 struct omap8250_priv *priv; 1412 const struct omap8250_platdata *pdata; 1413 struct uart_8250_port up; 1414 struct resource *regs; 1415 void __iomem *membase; 1416 int ret; 1417 1418 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1419 if (!regs) { 1420 dev_err(&pdev->dev, "missing registers\n"); 1421 return -EINVAL; 1422 } 1423 1424 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1425 if (!priv) 1426 return -ENOMEM; 1427 1428 membase = devm_ioremap(&pdev->dev, regs->start, 1429 resource_size(regs)); 1430 if (!membase) 1431 return -ENODEV; 1432 1433 memset(&up, 0, sizeof(up)); 1434 up.port.dev = &pdev->dev; 1435 up.port.mapbase = regs->start; 1436 up.port.membase = membase; 1437 /* 1438 * It claims to be 16C750 compatible however it is a little different. 1439 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1440 * have) is enabled via EFR instead of MCR. The type is set here 8250 1441 * just to get things going. UNKNOWN does not work for a few reasons and 1442 * we don't need our own type since we don't use 8250's set_termios() 1443 * or pm callback. 1444 */ 1445 up.port.type = PORT_8250; 1446 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; 1447 up.port.private_data = priv; 1448 1449 up.tx_loadsz = 64; 1450 up.capabilities = UART_CAP_FIFO; 1451 #ifdef CONFIG_PM 1452 /* 1453 * Runtime PM is mostly transparent. However to do it right we need to a 1454 * TX empty interrupt before we can put the device to auto idle. So if 1455 * PM is not enabled we don't add that flag and can spare that one extra 1456 * interrupt in the TX path. 1457 */ 1458 up.capabilities |= UART_CAP_RPM; 1459 #endif 1460 up.port.set_termios = omap_8250_set_termios; 1461 up.port.set_mctrl = omap8250_set_mctrl; 1462 up.port.pm = omap_8250_pm; 1463 up.port.startup = omap_8250_startup; 1464 up.port.shutdown = omap_8250_shutdown; 1465 up.port.throttle = omap_8250_throttle; 1466 up.port.unthrottle = omap_8250_unthrottle; 1467 up.port.rs485_config = omap8250_rs485_config; 1468 /* same rs485_supported for software emulation and native RS485 */ 1469 up.port.rs485_supported = serial8250_em485_supported; 1470 up.rs485_start_tx = serial8250_em485_start_tx; 1471 up.rs485_stop_tx = serial8250_em485_stop_tx; 1472 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1473 1474 ret = uart_read_port_properties(&up.port); 1475 if (ret) 1476 return ret; 1477 1478 up.port.regshift = OMAP_UART_REGSHIFT; 1479 up.port.fifosize = 64; 1480 1481 if (!up.port.uartclk) { 1482 struct clk *clk; 1483 1484 clk = devm_clk_get(&pdev->dev, NULL); 1485 if (IS_ERR(clk)) { 1486 if (PTR_ERR(clk) == -EPROBE_DEFER) 1487 return -EPROBE_DEFER; 1488 } else { 1489 up.port.uartclk = clk_get_rate(clk); 1490 } 1491 } 1492 1493 if (of_property_read_u32(np, "overrun-throttle-ms", 1494 &up.overrun_backoff_time_ms) != 0) 1495 up.overrun_backoff_time_ms = 0; 1496 1497 pdata = of_device_get_match_data(&pdev->dev); 1498 if (pdata) 1499 priv->habit |= pdata->habit; 1500 1501 if (!up.port.uartclk) { 1502 up.port.uartclk = DEFAULT_CLK_SPEED; 1503 dev_warn(&pdev->dev, 1504 "No clock speed specified: using default: %d\n", 1505 DEFAULT_CLK_SPEED); 1506 } 1507 1508 priv->membase = membase; 1509 priv->line = -ENODEV; 1510 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1511 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1512 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1513 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1514 1515 spin_lock_init(&priv->rx_dma_lock); 1516 1517 platform_set_drvdata(pdev, priv); 1518 1519 device_set_wakeup_capable(&pdev->dev, true); 1520 if (of_property_read_bool(np, "wakeup-source")) 1521 device_set_wakeup_enable(&pdev->dev, true); 1522 1523 pm_runtime_enable(&pdev->dev); 1524 pm_runtime_use_autosuspend(&pdev->dev); 1525 1526 /* 1527 * Disable runtime PM until autosuspend delay unless specifically 1528 * enabled by the user via sysfs. This is the historic way to 1529 * prevent an unsafe default policy with lossy characters on wake-up. 1530 * For serdev devices this is not needed, the policy can be managed by 1531 * the serdev driver. 1532 */ 1533 if (!of_get_available_child_count(pdev->dev.of_node)) 1534 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1535 1536 pm_runtime_get_sync(&pdev->dev); 1537 1538 omap_serial_fill_features_erratas(&up, priv); 1539 up.port.handle_irq = omap8250_no_handle_irq; 1540 priv->rx_trigger = RX_TRIGGER; 1541 priv->tx_trigger = TX_TRIGGER; 1542 #ifdef CONFIG_SERIAL_8250_DMA 1543 /* 1544 * Oh DMA support. If there are no DMA properties in the DT then 1545 * we will fall back to a generic DMA channel which does not 1546 * really work here. To ensure that we do not get a generic DMA 1547 * channel assigned, we have the the_no_dma_filter_fn() here. 1548 * To avoid "failed to request DMA" messages we check for DMA 1549 * properties in DT. 1550 */ 1551 ret = of_property_count_strings(np, "dma-names"); 1552 if (ret == 2) { 1553 struct omap8250_dma_params *dma_params = NULL; 1554 struct uart_8250_dma *dma = &priv->omap8250_dma; 1555 1556 dma->fn = the_no_dma_filter_fn; 1557 dma->tx_dma = omap_8250_tx_dma; 1558 dma->rx_dma = omap_8250_rx_dma; 1559 if (pdata) 1560 dma_params = pdata->dma_params; 1561 1562 if (dma_params) { 1563 dma->rx_size = dma_params->rx_size; 1564 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1565 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1566 priv->rx_trigger = dma_params->rx_trigger; 1567 priv->tx_trigger = dma_params->tx_trigger; 1568 } else { 1569 dma->rx_size = RX_TRIGGER; 1570 dma->rxconf.src_maxburst = RX_TRIGGER; 1571 dma->txconf.dst_maxburst = TX_TRIGGER; 1572 } 1573 } 1574 #endif 1575 1576 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); 1577 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, 1578 dev_name(&pdev->dev), priv); 1579 if (ret < 0) 1580 goto err; 1581 1582 priv->wakeirq = irq_of_parse_and_map(np, 1); 1583 1584 if (priv->wakeirq) { 1585 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, priv->wakeirq); 1586 if (ret) 1587 goto err; 1588 } 1589 1590 ret = serial8250_register_8250_port(&up); 1591 if (ret < 0) { 1592 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1593 goto err; 1594 } 1595 priv->line = ret; 1596 pm_runtime_mark_last_busy(&pdev->dev); 1597 pm_runtime_put_autosuspend(&pdev->dev); 1598 1599 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 1600 if (!IS_ERR_OR_NULL(priv->pinctrl)) 1601 priv->pinctrl_wakeup = pinctrl_lookup_state(priv->pinctrl, "wakeup"); 1602 1603 return 0; 1604 err: 1605 dev_pm_clear_wake_irq(&pdev->dev); 1606 pm_runtime_dont_use_autosuspend(&pdev->dev); 1607 pm_runtime_put_sync(&pdev->dev); 1608 flush_work(&priv->qos_work); 1609 pm_runtime_disable(&pdev->dev); 1610 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1611 return ret; 1612 } 1613 1614 static void omap8250_remove(struct platform_device *pdev) 1615 { 1616 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1617 struct uart_8250_port *up; 1618 int err; 1619 1620 err = pm_runtime_resume_and_get(&pdev->dev); 1621 if (err) 1622 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1623 1624 up = serial8250_get_port(priv->line); 1625 omap_8250_shutdown(&up->port); 1626 serial8250_unregister_port(priv->line); 1627 priv->line = -ENODEV; 1628 dev_pm_clear_wake_irq(&pdev->dev); 1629 pm_runtime_dont_use_autosuspend(&pdev->dev); 1630 pm_runtime_put_sync(&pdev->dev); 1631 flush_work(&priv->qos_work); 1632 pm_runtime_disable(&pdev->dev); 1633 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1634 device_set_wakeup_capable(&pdev->dev, false); 1635 } 1636 1637 static int omap8250_prepare(struct device *dev) 1638 { 1639 struct omap8250_priv *priv = dev_get_drvdata(dev); 1640 1641 if (!priv) 1642 return 0; 1643 priv->is_suspending = true; 1644 return 0; 1645 } 1646 1647 static void omap8250_complete(struct device *dev) 1648 { 1649 struct omap8250_priv *priv = dev_get_drvdata(dev); 1650 1651 if (!priv) 1652 return; 1653 priv->is_suspending = false; 1654 } 1655 1656 static int omap8250_suspend(struct device *dev) 1657 { 1658 struct omap8250_priv *priv = dev_get_drvdata(dev); 1659 struct uart_8250_port *up = serial8250_get_port(priv->line); 1660 int err = 0; 1661 1662 err = omap8250_select_wakeup_pinctrl(dev, priv); 1663 if (err) { 1664 dev_err(dev, "Failed to select wakeup pinctrl, aborting suspend %pe\n", 1665 ERR_PTR(err)); 1666 return err; 1667 } 1668 1669 serial8250_suspend_port(priv->line); 1670 1671 err = pm_runtime_resume_and_get(dev); 1672 if (err) 1673 return err; 1674 if (!device_may_wakeup(dev)) 1675 priv->wer = 0; 1676 serial_out(up, UART_OMAP_WER, priv->wer); 1677 if (uart_console(&up->port) && console_suspend_enabled) 1678 err = pm_runtime_force_suspend(dev); 1679 flush_work(&priv->qos_work); 1680 1681 return err; 1682 } 1683 1684 static int omap8250_resume(struct device *dev) 1685 { 1686 struct omap8250_priv *priv = dev_get_drvdata(dev); 1687 struct uart_8250_port *up = serial8250_get_port(priv->line); 1688 int err; 1689 1690 err = pinctrl_select_default_state(dev); 1691 if (err) { 1692 dev_err(dev, "Failed to select default pinctrl state on resume: %pe\n", 1693 ERR_PTR(err)); 1694 return err; 1695 } 1696 1697 if (uart_console(&up->port) && console_suspend_enabled) { 1698 err = pm_runtime_force_resume(dev); 1699 if (err) 1700 return err; 1701 } 1702 1703 serial8250_resume_port(priv->line); 1704 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1705 pm_runtime_mark_last_busy(dev); 1706 pm_runtime_put_autosuspend(dev); 1707 1708 return 0; 1709 } 1710 1711 static int omap8250_lost_context(struct uart_8250_port *up) 1712 { 1713 u32 val; 1714 1715 val = serial_in(up, UART_OMAP_SCR); 1716 /* 1717 * If we lose context, then SCR is set to its reset value of zero. 1718 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1719 * among other bits, to never set the register back to zero again. 1720 */ 1721 if (!val) 1722 return 1; 1723 return 0; 1724 } 1725 1726 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1727 { 1728 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1729 } 1730 1731 /* TODO: in future, this should happen via API in drivers/reset/ */ 1732 static int omap8250_soft_reset(struct device *dev) 1733 { 1734 struct omap8250_priv *priv = dev_get_drvdata(dev); 1735 int timeout = 100; 1736 int sysc; 1737 int syss; 1738 1739 /* 1740 * At least on omap4, unused uarts may not idle after reset without 1741 * a basic scr dma configuration even with no dma in use. The 1742 * module clkctrl status bits will be 1 instead of 3 blocking idle 1743 * for the whole clockdomain. The softreset below will clear scr, 1744 * and we restore it on resume so this is safe to do on all SoCs 1745 * needing omap8250_soft_reset() quirk. Do it in two writes as 1746 * recommended in the comment for omap8250_update_scr(). 1747 */ 1748 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1749 uart_write(priv, UART_OMAP_SCR, 1750 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1751 1752 sysc = uart_read(priv, UART_OMAP_SYSC); 1753 1754 /* softreset the UART */ 1755 sysc |= OMAP_UART_SYSC_SOFTRESET; 1756 uart_write(priv, UART_OMAP_SYSC, sysc); 1757 1758 /* By experiments, 1us enough for reset complete on AM335x */ 1759 do { 1760 udelay(1); 1761 syss = uart_read(priv, UART_OMAP_SYSS); 1762 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1763 1764 if (!timeout) { 1765 dev_err(dev, "timed out waiting for reset done\n"); 1766 return -ETIMEDOUT; 1767 } 1768 1769 return 0; 1770 } 1771 1772 static int omap8250_runtime_suspend(struct device *dev) 1773 { 1774 struct omap8250_priv *priv = dev_get_drvdata(dev); 1775 struct uart_8250_port *up = NULL; 1776 1777 if (priv->line >= 0) 1778 up = serial8250_get_port(priv->line); 1779 1780 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1781 int ret; 1782 1783 ret = omap8250_soft_reset(dev); 1784 if (ret) 1785 return ret; 1786 1787 if (up) { 1788 /* Restore to UART mode after reset (for wakeup) */ 1789 omap8250_update_mdr1(up, priv); 1790 /* Restore wakeup enable register */ 1791 serial_out(up, UART_OMAP_WER, priv->wer); 1792 } 1793 } 1794 1795 if (up && up->dma && up->dma->rxchan) 1796 omap_8250_rx_dma_flush(up); 1797 1798 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1799 schedule_work(&priv->qos_work); 1800 atomic_set(&priv->active, 0); 1801 1802 return 0; 1803 } 1804 1805 static int omap8250_runtime_resume(struct device *dev) 1806 { 1807 struct omap8250_priv *priv = dev_get_drvdata(dev); 1808 struct uart_8250_port *up = NULL; 1809 1810 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1811 if (atomic_read(&priv->active)) 1812 return 0; 1813 1814 if (priv->line >= 0) 1815 up = serial8250_get_port(priv->line); 1816 1817 if (up && omap8250_lost_context(up)) { 1818 guard(uart_port_lock_irq)(&up->port); 1819 omap8250_restore_regs(up); 1820 } 1821 1822 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1823 guard(uart_port_lock_irq)(&up->port); 1824 omap_8250_rx_dma(up); 1825 } 1826 1827 atomic_set(&priv->active, 1); 1828 priv->latency = priv->calc_latency; 1829 schedule_work(&priv->qos_work); 1830 1831 return 0; 1832 } 1833 1834 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1835 static int __init omap8250_console_fixup(void) 1836 { 1837 char *omap_str; 1838 char *options; 1839 u8 idx; 1840 1841 if (strstr(boot_command_line, "console=ttyS")) 1842 /* user set a ttyS based name for the console */ 1843 return 0; 1844 1845 omap_str = strstr(boot_command_line, "console=ttyO"); 1846 if (!omap_str) 1847 /* user did not set ttyO based console, so we don't care */ 1848 return 0; 1849 1850 omap_str += 12; 1851 if ('0' <= *omap_str && *omap_str <= '9') 1852 idx = *omap_str - '0'; 1853 else 1854 return 0; 1855 1856 omap_str++; 1857 if (omap_str[0] == ',') { 1858 omap_str++; 1859 options = omap_str; 1860 } else { 1861 options = NULL; 1862 } 1863 1864 add_preferred_console("ttyS", idx, options); 1865 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1866 idx, idx); 1867 pr_err("This ensures that you still see kernel messages. Please\n"); 1868 pr_err("update your kernel commandline.\n"); 1869 return 0; 1870 } 1871 console_initcall(omap8250_console_fixup); 1872 #endif 1873 1874 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1875 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1876 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1877 omap8250_runtime_resume, NULL) 1878 .prepare = pm_sleep_ptr(omap8250_prepare), 1879 .complete = pm_sleep_ptr(omap8250_complete), 1880 }; 1881 1882 static struct platform_driver omap8250_platform_driver = { 1883 .driver = { 1884 .name = "omap8250", 1885 .pm = pm_ptr(&omap8250_dev_pm_ops), 1886 .of_match_table = omap8250_dt_ids, 1887 }, 1888 .probe = omap8250_probe, 1889 .remove = omap8250_remove, 1890 }; 1891 module_platform_driver(omap8250_platform_driver); 1892 1893 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1894 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1895 MODULE_LICENSE("GPL v2"); 1896