1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019-2020 Icenowy Zheng <icenowy@aosc.io>
4 */
5
6 #include <linux/gpio/consumer.h>
7 #include <linux/delay.h>
8 #include <linux/module.h>
9 #include <linux/regulator/consumer.h>
10
11 #include <drm/drm_mipi_dsi.h>
12 #include <drm/drm_modes.h>
13 #include <drm/drm_panel.h>
14
15 #define K101_IM2BA02_INIT_CMD_LEN 2
16
17 static const char * const regulator_names[] = {
18 "dvdd",
19 "avdd",
20 "cvdd"
21 };
22
23 struct k101_im2ba02 {
24 struct drm_panel panel;
25 struct mipi_dsi_device *dsi;
26
27 struct regulator_bulk_data supplies[ARRAY_SIZE(regulator_names)];
28 struct gpio_desc *reset;
29 };
30
panel_to_k101_im2ba02(struct drm_panel * panel)31 static inline struct k101_im2ba02 *panel_to_k101_im2ba02(struct drm_panel *panel)
32 {
33 return container_of(panel, struct k101_im2ba02, panel);
34 }
35
36 struct k101_im2ba02_init_cmd {
37 u8 data[K101_IM2BA02_INIT_CMD_LEN];
38 };
39
40 static const struct k101_im2ba02_init_cmd k101_im2ba02_init_cmds[] = {
41 /* Switch to page 0 */
42 { .data = { 0xE0, 0x00 } },
43
44 /* Seems to be some password */
45 { .data = { 0xE1, 0x93} },
46 { .data = { 0xE2, 0x65 } },
47 { .data = { 0xE3, 0xF8 } },
48
49 /* Lane number, 0x02 - 3 lanes, 0x03 - 4 lanes */
50 { .data = { 0x80, 0x03 } },
51
52 /* Sequence control */
53 { .data = { 0x70, 0x02 } },
54 { .data = { 0x71, 0x23 } },
55 { .data = { 0x72, 0x06 } },
56
57 /* Switch to page 1 */
58 { .data = { 0xE0, 0x01 } },
59
60 /* Set VCOM */
61 { .data = { 0x00, 0x00 } },
62 { .data = { 0x01, 0x66 } },
63 /* Set VCOM_Reverse */
64 { .data = { 0x03, 0x00 } },
65 { .data = { 0x04, 0x25 } },
66
67 /* Set Gamma Power, VG[MS][PN] */
68 { .data = { 0x17, 0x00 } },
69 { .data = { 0x18, 0x6D } },
70 { .data = { 0x19, 0x00 } },
71 { .data = { 0x1A, 0x00 } },
72 { .data = { 0x1B, 0xBF } }, /* VGMN = -4.5V */
73 { .data = { 0x1C, 0x00 } },
74
75 /* Set Gate Power */
76 { .data = { 0x1F, 0x3E } }, /* VGH_R = 15V */
77 { .data = { 0x20, 0x28 } }, /* VGL_R = -11V */
78 { .data = { 0x21, 0x28 } }, /* VGL_R2 = -11V */
79 { .data = { 0x22, 0x0E } }, /* PA[6:4] = 0, PA[0] = 0 */
80
81 /* Set Panel */
82 { .data = { 0x37, 0x09 } }, /* SS = 1, BGR = 1 */
83
84 /* Set RGBCYC */
85 { .data = { 0x38, 0x04 } }, /* JDT = 100 column inversion */
86 { .data = { 0x39, 0x08 } }, /* RGB_N_EQ1 */
87 { .data = { 0x3A, 0x12 } }, /* RGB_N_EQ2 */
88 { .data = { 0x3C, 0x78 } }, /* set EQ3 for TE_H */
89 { .data = { 0x3D, 0xFF } }, /* set CHGEN_ON */
90 { .data = { 0x3E, 0xFF } }, /* set CHGEN_OFF */
91 { .data = { 0x3F, 0x7F } }, /* set CHGEN_OFF2 */
92
93 /* Set TCON parameter */
94 { .data = { 0x40, 0x06 } }, /* RSO = 800 points */
95 { .data = { 0x41, 0xA0 } }, /* LN = 1280 lines */
96
97 /* Set power voltage */
98 { .data = { 0x55, 0x0F } }, /* DCDCM */
99 { .data = { 0x56, 0x01 } },
100 { .data = { 0x57, 0x69 } },
101 { .data = { 0x58, 0x0A } },
102 { .data = { 0x59, 0x0A } },
103 { .data = { 0x5A, 0x45 } },
104 { .data = { 0x5B, 0x15 } },
105
106 /* Set gamma */
107 { .data = { 0x5D, 0x7C } },
108 { .data = { 0x5E, 0x65 } },
109 { .data = { 0x5F, 0x55 } },
110 { .data = { 0x60, 0x49 } },
111 { .data = { 0x61, 0x44 } },
112 { .data = { 0x62, 0x35 } },
113 { .data = { 0x63, 0x3A } },
114 { .data = { 0x64, 0x23 } },
115 { .data = { 0x65, 0x3D } },
116 { .data = { 0x66, 0x3C } },
117 { .data = { 0x67, 0x3D } },
118 { .data = { 0x68, 0x5D } },
119 { .data = { 0x69, 0x4D } },
120 { .data = { 0x6A, 0x56 } },
121 { .data = { 0x6B, 0x48 } },
122 { .data = { 0x6C, 0x45 } },
123 { .data = { 0x6D, 0x38 } },
124 { .data = { 0x6E, 0x25 } },
125 { .data = { 0x6F, 0x00 } },
126 { .data = { 0x70, 0x7C } },
127 { .data = { 0x71, 0x65 } },
128 { .data = { 0x72, 0x55 } },
129 { .data = { 0x73, 0x49 } },
130 { .data = { 0x74, 0x44 } },
131 { .data = { 0x75, 0x35 } },
132 { .data = { 0x76, 0x3A } },
133 { .data = { 0x77, 0x23 } },
134 { .data = { 0x78, 0x3D } },
135 { .data = { 0x79, 0x3C } },
136 { .data = { 0x7A, 0x3D } },
137 { .data = { 0x7B, 0x5D } },
138 { .data = { 0x7C, 0x4D } },
139 { .data = { 0x7D, 0x56 } },
140 { .data = { 0x7E, 0x48 } },
141 { .data = { 0x7F, 0x45 } },
142 { .data = { 0x80, 0x38 } },
143 { .data = { 0x81, 0x25 } },
144 { .data = { 0x82, 0x00 } },
145
146 /* Switch to page 2, for GIP */
147 { .data = { 0xE0, 0x02 } },
148
149 { .data = { 0x00, 0x1E } },
150 { .data = { 0x01, 0x1E } },
151 { .data = { 0x02, 0x41 } },
152 { .data = { 0x03, 0x41 } },
153 { .data = { 0x04, 0x43 } },
154 { .data = { 0x05, 0x43 } },
155 { .data = { 0x06, 0x1F } },
156 { .data = { 0x07, 0x1F } },
157 { .data = { 0x08, 0x1F } },
158 { .data = { 0x09, 0x1F } },
159 { .data = { 0x0A, 0x1E } },
160 { .data = { 0x0B, 0x1E } },
161 { .data = { 0x0C, 0x1F } },
162 { .data = { 0x0D, 0x47 } },
163 { .data = { 0x0E, 0x47 } },
164 { .data = { 0x0F, 0x45 } },
165 { .data = { 0x10, 0x45 } },
166 { .data = { 0x11, 0x4B } },
167 { .data = { 0x12, 0x4B } },
168 { .data = { 0x13, 0x49 } },
169 { .data = { 0x14, 0x49 } },
170 { .data = { 0x15, 0x1F } },
171
172 { .data = { 0x16, 0x1E } },
173 { .data = { 0x17, 0x1E } },
174 { .data = { 0x18, 0x40 } },
175 { .data = { 0x19, 0x40 } },
176 { .data = { 0x1A, 0x42 } },
177 { .data = { 0x1B, 0x42 } },
178 { .data = { 0x1C, 0x1F } },
179 { .data = { 0x1D, 0x1F } },
180 { .data = { 0x1E, 0x1F } },
181 { .data = { 0x1F, 0x1f } },
182 { .data = { 0x20, 0x1E } },
183 { .data = { 0x21, 0x1E } },
184 { .data = { 0x22, 0x1f } },
185 { .data = { 0x23, 0x46 } },
186 { .data = { 0x24, 0x46 } },
187 { .data = { 0x25, 0x44 } },
188 { .data = { 0x26, 0x44 } },
189 { .data = { 0x27, 0x4A } },
190 { .data = { 0x28, 0x4A } },
191 { .data = { 0x29, 0x48 } },
192 { .data = { 0x2A, 0x48 } },
193 { .data = { 0x2B, 0x1f } },
194
195 { .data = { 0x2C, 0x1F } },
196 { .data = { 0x2D, 0x1F } },
197 { .data = { 0x2E, 0x42 } },
198 { .data = { 0x2F, 0x42 } },
199 { .data = { 0x30, 0x40 } },
200 { .data = { 0x31, 0x40 } },
201 { .data = { 0x32, 0x1E } },
202 { .data = { 0x33, 0x1E } },
203 { .data = { 0x34, 0x1F } },
204 { .data = { 0x35, 0x1F } },
205 { .data = { 0x36, 0x1E } },
206 { .data = { 0x37, 0x1E } },
207 { .data = { 0x38, 0x1F } },
208 { .data = { 0x39, 0x48 } },
209 { .data = { 0x3A, 0x48 } },
210 { .data = { 0x3B, 0x4A } },
211 { .data = { 0x3C, 0x4A } },
212 { .data = { 0x3D, 0x44 } },
213 { .data = { 0x3E, 0x44 } },
214 { .data = { 0x3F, 0x46 } },
215 { .data = { 0x40, 0x46 } },
216 { .data = { 0x41, 0x1F } },
217
218 { .data = { 0x42, 0x1F } },
219 { .data = { 0x43, 0x1F } },
220 { .data = { 0x44, 0x43 } },
221 { .data = { 0x45, 0x43 } },
222 { .data = { 0x46, 0x41 } },
223 { .data = { 0x47, 0x41 } },
224 { .data = { 0x48, 0x1E } },
225 { .data = { 0x49, 0x1E } },
226 { .data = { 0x4A, 0x1E } },
227 { .data = { 0x4B, 0x1F } },
228 { .data = { 0x4C, 0x1E } },
229 { .data = { 0x4D, 0x1E } },
230 { .data = { 0x4E, 0x1F } },
231 { .data = { 0x4F, 0x49 } },
232 { .data = { 0x50, 0x49 } },
233 { .data = { 0x51, 0x4B } },
234 { .data = { 0x52, 0x4B } },
235 { .data = { 0x53, 0x45 } },
236 { .data = { 0x54, 0x45 } },
237 { .data = { 0x55, 0x47 } },
238 { .data = { 0x56, 0x47 } },
239 { .data = { 0x57, 0x1F } },
240
241 { .data = { 0x58, 0x10 } },
242 { .data = { 0x59, 0x00 } },
243 { .data = { 0x5A, 0x00 } },
244 { .data = { 0x5B, 0x30 } },
245 { .data = { 0x5C, 0x02 } },
246 { .data = { 0x5D, 0x40 } },
247 { .data = { 0x5E, 0x01 } },
248 { .data = { 0x5F, 0x02 } },
249 { .data = { 0x60, 0x30 } },
250 { .data = { 0x61, 0x01 } },
251 { .data = { 0x62, 0x02 } },
252 { .data = { 0x63, 0x6A } },
253 { .data = { 0x64, 0x6A } },
254 { .data = { 0x65, 0x05 } },
255 { .data = { 0x66, 0x12 } },
256 { .data = { 0x67, 0x74 } },
257 { .data = { 0x68, 0x04 } },
258 { .data = { 0x69, 0x6A } },
259 { .data = { 0x6A, 0x6A } },
260 { .data = { 0x6B, 0x08 } },
261
262 { .data = { 0x6C, 0x00 } },
263 { .data = { 0x6D, 0x04 } },
264 { .data = { 0x6E, 0x04 } },
265 { .data = { 0x6F, 0x88 } },
266 { .data = { 0x70, 0x00 } },
267 { .data = { 0x71, 0x00 } },
268 { .data = { 0x72, 0x06 } },
269 { .data = { 0x73, 0x7B } },
270 { .data = { 0x74, 0x00 } },
271 { .data = { 0x75, 0x07 } },
272 { .data = { 0x76, 0x00 } },
273 { .data = { 0x77, 0x5D } },
274 { .data = { 0x78, 0x17 } },
275 { .data = { 0x79, 0x1F } },
276 { .data = { 0x7A, 0x00 } },
277 { .data = { 0x7B, 0x00 } },
278 { .data = { 0x7C, 0x00 } },
279 { .data = { 0x7D, 0x03 } },
280 { .data = { 0x7E, 0x7B } },
281
282 { .data = { 0xE0, 0x04 } },
283 { .data = { 0x2B, 0x2B } },
284 { .data = { 0x2E, 0x44 } },
285
286 { .data = { 0xE0, 0x01 } },
287 { .data = { 0x0E, 0x01 } },
288
289 { .data = { 0xE0, 0x03 } },
290 { .data = { 0x98, 0x2F } },
291
292 { .data = { 0xE0, 0x00 } },
293 { .data = { 0xE6, 0x02 } },
294 { .data = { 0xE7, 0x02 } },
295
296 { .data = { 0x11, 0x00 } },
297 };
298
299 static const struct k101_im2ba02_init_cmd timed_cmds[] = {
300 { .data = { 0x29, 0x00 } },
301 { .data = { 0x35, 0x00 } },
302 };
303
k101_im2ba02_prepare(struct drm_panel * panel)304 static int k101_im2ba02_prepare(struct drm_panel *panel)
305 {
306 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
307 struct mipi_dsi_device *dsi = ctx->dsi;
308 unsigned int i;
309 int ret;
310
311 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
312 if (ret)
313 return ret;
314
315 msleep(30);
316
317 gpiod_set_value(ctx->reset, 1);
318 msleep(50);
319
320 gpiod_set_value(ctx->reset, 0);
321 msleep(50);
322
323 gpiod_set_value(ctx->reset, 1);
324 msleep(200);
325
326 for (i = 0; i < ARRAY_SIZE(k101_im2ba02_init_cmds); i++) {
327 const struct k101_im2ba02_init_cmd *cmd = &k101_im2ba02_init_cmds[i];
328
329 ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data, K101_IM2BA02_INIT_CMD_LEN);
330 if (ret < 0)
331 goto powerdown;
332 }
333
334 return 0;
335
336 powerdown:
337 gpiod_set_value(ctx->reset, 0);
338 msleep(50);
339
340 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
341 }
342
k101_im2ba02_enable(struct drm_panel * panel)343 static int k101_im2ba02_enable(struct drm_panel *panel)
344 {
345 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
346 const struct k101_im2ba02_init_cmd *cmd = &timed_cmds[1];
347 int ret;
348
349 msleep(150);
350
351 ret = mipi_dsi_dcs_set_display_on(ctx->dsi);
352 if (ret < 0)
353 return ret;
354
355 msleep(50);
356
357 return mipi_dsi_dcs_write_buffer(ctx->dsi, cmd->data, K101_IM2BA02_INIT_CMD_LEN);
358 }
359
k101_im2ba02_disable(struct drm_panel * panel)360 static int k101_im2ba02_disable(struct drm_panel *panel)
361 {
362 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
363
364 return mipi_dsi_dcs_set_display_off(ctx->dsi);
365 }
366
k101_im2ba02_unprepare(struct drm_panel * panel)367 static int k101_im2ba02_unprepare(struct drm_panel *panel)
368 {
369 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
370 int ret;
371
372 ret = mipi_dsi_dcs_set_display_off(ctx->dsi);
373 if (ret < 0)
374 dev_err(panel->dev, "failed to set display off: %d\n", ret);
375
376 ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
377 if (ret < 0)
378 dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
379
380 msleep(200);
381
382 gpiod_set_value(ctx->reset, 0);
383 msleep(20);
384
385 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
386 }
387
388 static const struct drm_display_mode k101_im2ba02_default_mode = {
389 .clock = 70000,
390
391 .hdisplay = 800,
392 .hsync_start = 800 + 20,
393 .hsync_end = 800 + 20 + 20,
394 .htotal = 800 + 20 + 20 + 20,
395
396 .vdisplay = 1280,
397 .vsync_start = 1280 + 16,
398 .vsync_end = 1280 + 16 + 4,
399 .vtotal = 1280 + 16 + 4 + 4,
400
401 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
402 .width_mm = 136,
403 .height_mm = 217,
404 };
405
k101_im2ba02_get_modes(struct drm_panel * panel,struct drm_connector * connector)406 static int k101_im2ba02_get_modes(struct drm_panel *panel,
407 struct drm_connector *connector)
408 {
409 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);
410 struct drm_display_mode *mode;
411
412 mode = drm_mode_duplicate(connector->dev, &k101_im2ba02_default_mode);
413 if (!mode) {
414 dev_err(&ctx->dsi->dev, "failed to add mode %ux%u@%u\n",
415 k101_im2ba02_default_mode.hdisplay,
416 k101_im2ba02_default_mode.vdisplay,
417 drm_mode_vrefresh(&k101_im2ba02_default_mode));
418 return -ENOMEM;
419 }
420
421 drm_mode_set_name(mode);
422
423 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
424 connector->display_info.width_mm = mode->width_mm;
425 connector->display_info.height_mm = mode->height_mm;
426 drm_mode_probed_add(connector, mode);
427
428 return 1;
429 }
430
431 static const struct drm_panel_funcs k101_im2ba02_funcs = {
432 .disable = k101_im2ba02_disable,
433 .unprepare = k101_im2ba02_unprepare,
434 .prepare = k101_im2ba02_prepare,
435 .enable = k101_im2ba02_enable,
436 .get_modes = k101_im2ba02_get_modes,
437 };
438
k101_im2ba02_dsi_probe(struct mipi_dsi_device * dsi)439 static int k101_im2ba02_dsi_probe(struct mipi_dsi_device *dsi)
440 {
441 struct k101_im2ba02 *ctx;
442 unsigned int i;
443 int ret;
444
445 ctx = devm_drm_panel_alloc(&dsi->dev, struct k101_im2ba02, panel,
446 &k101_im2ba02_funcs,
447 DRM_MODE_CONNECTOR_DSI);
448 if (IS_ERR(ctx))
449 return PTR_ERR(ctx);
450
451 mipi_dsi_set_drvdata(dsi, ctx);
452 ctx->dsi = dsi;
453
454 for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++)
455 ctx->supplies[i].supply = regulator_names[i];
456
457 ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(ctx->supplies),
458 ctx->supplies);
459 if (ret < 0)
460 return dev_err_probe(&dsi->dev, ret, "Couldn't get regulators\n");
461
462 ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
463 if (IS_ERR(ctx->reset))
464 return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset),
465 "Couldn't get our reset GPIO\n");
466
467 ret = drm_panel_of_backlight(&ctx->panel);
468 if (ret)
469 return ret;
470
471 drm_panel_add(&ctx->panel);
472
473 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
474 dsi->format = MIPI_DSI_FMT_RGB888;
475 dsi->lanes = 4;
476
477 ret = mipi_dsi_attach(dsi);
478 if (ret < 0) {
479 drm_panel_remove(&ctx->panel);
480 return ret;
481 }
482
483 return 0;
484 }
485
k101_im2ba02_dsi_remove(struct mipi_dsi_device * dsi)486 static void k101_im2ba02_dsi_remove(struct mipi_dsi_device *dsi)
487 {
488 struct k101_im2ba02 *ctx = mipi_dsi_get_drvdata(dsi);
489
490 mipi_dsi_detach(dsi);
491 drm_panel_remove(&ctx->panel);
492 }
493
494 static const struct of_device_id k101_im2ba02_of_match[] = {
495 { .compatible = "feixin,k101-im2ba02", },
496 { /* sentinel */ }
497 };
498 MODULE_DEVICE_TABLE(of, k101_im2ba02_of_match);
499
500 static struct mipi_dsi_driver k101_im2ba02_driver = {
501 .probe = k101_im2ba02_dsi_probe,
502 .remove = k101_im2ba02_dsi_remove,
503 .driver = {
504 .name = "feixin-k101-im2ba02",
505 .of_match_table = k101_im2ba02_of_match,
506 },
507 };
508 module_mipi_dsi_driver(k101_im2ba02_driver);
509
510 MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
511 MODULE_DESCRIPTION("Feixin K101 IM2BA02 MIPI-DSI LCD panel");
512 MODULE_LICENSE("GPL");
513