1 // SPDX-License-Identifier: GPL-2.0-only
2
3 /*
4 * Realtek Otto MIPS platform watchdog
5 *
6 * Watchdog timer that will reset the system after timeout, using the selected
7 * reset mode.
8 *
9 * Counter scaling and timeouts:
10 * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz
11 * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
12 * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
13 * Generates an interrupt, WDT cannot be stopped after phase 1
14 * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
15 * Resets the system according to RST_MODE
16 */
17
18 #include <linux/bits.h>
19 #include <linux/bitfield.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/math.h>
25 #include <linux/minmax.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/property.h>
29 #include <linux/reboot.h>
30 #include <linux/regmap.h>
31 #include <linux/watchdog.h>
32
33 #define OTTO_WDT_REG_CNTR 0x0
34 #define OTTO_WDT_CNTR_PING BIT(31)
35
36 #define OTTO_WDT_REG_INTR 0x4
37 #define OTTO_WDT_INTR_PHASE_1 BIT(31)
38 #define OTTO_WDT_INTR_PHASE_2 BIT(30)
39
40 #define OTTO_WDT_REG_CTRL 0x8
41 #define OTTO_WDT_CTRL_ENABLE BIT(31)
42 #define OTTO_WDT_CTRL_PRESCALE GENMASK(30, 29)
43 #define OTTO_WDT_CTRL_PHASE1 GENMASK(26, 22)
44 #define OTTO_WDT_CTRL_PHASE2 GENMASK(19, 15)
45 #define OTTO_WDT_CTRL_RST_MODE GENMASK(1, 0)
46 #define OTTO_WDT_MODE_SOC 0
47 #define OTTO_WDT_MODE_CPU 1
48 #define OTTO_WDT_MODE_SOFTWARE 2
49 #define OTTO_WDT_CTRL_DEFAULT OTTO_WDT_MODE_CPU
50
51 #define OTTO_WDT_PRESCALE_MAX 3
52
53 /*
54 * One higher than the max values contained in PHASE{1,2}, since a value of 0
55 * corresponds to one tick.
56 */
57 #define OTTO_WDT_PHASE_TICKS_MAX 32
58
59 /*
60 * The maximum reset delay is actually 2×32 ticks, but that would require large
61 * pretimeout values for timeouts longer than 32 ticks. Limit the maximum timeout
62 * to 32 + 1 to ensure small pretimeout values can be configured as expected.
63 */
64 #define OTTO_WDT_TIMEOUT_TICKS_MAX (OTTO_WDT_PHASE_TICKS_MAX + 1)
65
66 struct otto_wdt_ctrl {
67 struct watchdog_device wdev;
68 struct device *dev;
69 struct regmap *regmap;
70 unsigned int clk_rate_khz;
71 int irq_phase1;
72 };
73
otto_wdt_start(struct watchdog_device * wdev)74 static int otto_wdt_start(struct watchdog_device *wdev)
75 {
76 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
77
78 regmap_set_bits(ctrl->regmap, OTTO_WDT_REG_CTRL, OTTO_WDT_CTRL_ENABLE);
79 return 0;
80 }
81
otto_wdt_stop(struct watchdog_device * wdev)82 static int otto_wdt_stop(struct watchdog_device *wdev)
83 {
84 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
85
86 regmap_clear_bits(ctrl->regmap, OTTO_WDT_REG_CTRL,
87 OTTO_WDT_CTRL_ENABLE);
88 return 0;
89 }
90
otto_wdt_ping(struct watchdog_device * wdev)91 static int otto_wdt_ping(struct watchdog_device *wdev)
92 {
93 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
94
95 regmap_write(ctrl->regmap, OTTO_WDT_REG_CNTR, OTTO_WDT_CNTR_PING);
96 return 0;
97 }
98
otto_wdt_tick_ms(struct otto_wdt_ctrl * ctrl,int prescale)99 static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale)
100 {
101 return DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz);
102 }
103
104 /*
105 * The timer asserts the PHASE1/PHASE2 IRQs when the number of ticks exceeds
106 * the value stored in those fields. This means each phase will run for at least
107 * one tick, so small values need to be clamped to correctly reflect the timeout.
108 */
otto_wdt_determine_timeouts(struct watchdog_device * wdev,unsigned int timeout,unsigned int pretimeout)109 static int otto_wdt_determine_timeouts(struct watchdog_device *wdev, unsigned int timeout,
110 unsigned int pretimeout)
111 {
112 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
113 unsigned int pretimeout_ms = pretimeout * 1000;
114 unsigned int timeout_ms = timeout * 1000;
115 unsigned int prescale_next = 0;
116 unsigned int phase1_ticks;
117 unsigned int phase2_ticks;
118 unsigned int total_ticks;
119 unsigned int prescale;
120 unsigned int tick_ms;
121 u32 mask, val;
122
123 do {
124 prescale = prescale_next;
125 if (prescale > OTTO_WDT_PRESCALE_MAX)
126 return -EINVAL;
127
128 tick_ms = otto_wdt_tick_ms(ctrl, prescale);
129 total_ticks = max(2, DIV_ROUND_UP(timeout_ms, tick_ms));
130 phase2_ticks = max(1, pretimeout_ms / tick_ms);
131 phase1_ticks = total_ticks - phase2_ticks;
132
133 prescale_next++;
134 } while (phase1_ticks > OTTO_WDT_PHASE_TICKS_MAX
135 || phase2_ticks > OTTO_WDT_PHASE_TICKS_MAX);
136
137 mask = OTTO_WDT_CTRL_PRESCALE | OTTO_WDT_CTRL_PHASE1 | OTTO_WDT_CTRL_PHASE2;
138 val = FIELD_PREP(OTTO_WDT_CTRL_PHASE1, phase1_ticks - 1);
139 val |= FIELD_PREP(OTTO_WDT_CTRL_PHASE2, phase2_ticks - 1);
140 val |= FIELD_PREP(OTTO_WDT_CTRL_PRESCALE, prescale);
141 regmap_update_bits(ctrl->regmap, OTTO_WDT_REG_CTRL, mask, val);
142
143 timeout_ms = total_ticks * tick_ms;
144 ctrl->wdev.timeout = timeout_ms / 1000;
145
146 pretimeout_ms = phase2_ticks * tick_ms;
147 ctrl->wdev.pretimeout = pretimeout_ms / 1000;
148
149 return 0;
150 }
151
otto_wdt_set_timeout(struct watchdog_device * wdev,unsigned int val)152 static int otto_wdt_set_timeout(struct watchdog_device *wdev, unsigned int val)
153 {
154 return otto_wdt_determine_timeouts(wdev, val, min(wdev->pretimeout, val - 1));
155 }
156
otto_wdt_set_pretimeout(struct watchdog_device * wdev,unsigned int val)157 static int otto_wdt_set_pretimeout(struct watchdog_device *wdev, unsigned int val)
158 {
159 return otto_wdt_determine_timeouts(wdev, wdev->timeout, val);
160 }
161
otto_wdt_restart(struct watchdog_device * wdev,unsigned long reboot_mode,void * data)162 static int otto_wdt_restart(struct watchdog_device *wdev, unsigned long reboot_mode,
163 void *data)
164 {
165 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
166 u32 reset_mode;
167 u32 v;
168
169 disable_irq(ctrl->irq_phase1);
170
171 switch (reboot_mode) {
172 case REBOOT_SOFT:
173 reset_mode = OTTO_WDT_MODE_SOFTWARE;
174 break;
175 case REBOOT_WARM:
176 reset_mode = OTTO_WDT_MODE_CPU;
177 break;
178 default:
179 reset_mode = OTTO_WDT_MODE_SOC;
180 break;
181 }
182
183 /* Configure for shortest timeout and wait for reset to occur */
184 v = FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, reset_mode) | OTTO_WDT_CTRL_ENABLE;
185 regmap_write(ctrl->regmap, OTTO_WDT_REG_CTRL, v);
186
187 mdelay(3 * otto_wdt_tick_ms(ctrl, 0));
188
189 return 0;
190 }
191
otto_wdt_phase1_isr(int irq,void * dev_id)192 static irqreturn_t otto_wdt_phase1_isr(int irq, void *dev_id)
193 {
194 struct otto_wdt_ctrl *ctrl = dev_id;
195
196 regmap_write(ctrl->regmap, OTTO_WDT_REG_INTR, OTTO_WDT_INTR_PHASE_1);
197 dev_crit(ctrl->dev, "phase 1 timeout\n");
198 watchdog_notify_pretimeout(&ctrl->wdev);
199
200 return IRQ_HANDLED;
201 }
202
203 static const struct watchdog_ops otto_wdt_ops = {
204 .owner = THIS_MODULE,
205 .start = otto_wdt_start,
206 .stop = otto_wdt_stop,
207 .ping = otto_wdt_ping,
208 .set_timeout = otto_wdt_set_timeout,
209 .set_pretimeout = otto_wdt_set_pretimeout,
210 .restart = otto_wdt_restart,
211 };
212
213 static const struct watchdog_info otto_wdt_info = {
214 .identity = "Realtek Otto watchdog timer",
215 .options = WDIOF_KEEPALIVEPING |
216 WDIOF_MAGICCLOSE |
217 WDIOF_SETTIMEOUT |
218 WDIOF_PRETIMEOUT,
219 };
220
otto_wdt_probe_clk(struct otto_wdt_ctrl * ctrl)221 static int otto_wdt_probe_clk(struct otto_wdt_ctrl *ctrl)
222 {
223 struct clk *clk;
224
225 clk = devm_clk_get_enabled(ctrl->dev, NULL);
226 if (IS_ERR(clk))
227 return dev_err_probe(ctrl->dev, PTR_ERR(clk), "Failed to get clock\n");
228
229 ctrl->clk_rate_khz = clk_get_rate(clk) / 1000;
230 if (ctrl->clk_rate_khz == 0)
231 return dev_err_probe(ctrl->dev, -ENXIO, "Failed to get clock rate\n");
232
233 return 0;
234 }
235
otto_wdt_probe_reset_mode(struct otto_wdt_ctrl * ctrl)236 static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl)
237 {
238 static const char *mode_property = "realtek,reset-mode";
239 const struct fwnode_handle *node = ctrl->dev->fwnode;
240 int mode_count;
241 u32 mode;
242
243 if (!node)
244 return -ENXIO;
245
246 mode_count = fwnode_property_string_array_count(node, mode_property);
247 if (mode_count < 0)
248 return mode_count;
249 else if (mode_count == 0)
250 return 0;
251 else if (mode_count != 1)
252 return -EINVAL;
253
254 if (fwnode_property_match_string(node, mode_property, "soc") == 0)
255 mode = OTTO_WDT_MODE_SOC;
256 else if (fwnode_property_match_string(node, mode_property, "cpu") == 0)
257 mode = OTTO_WDT_MODE_CPU;
258 else if (fwnode_property_match_string(node, mode_property, "software") == 0)
259 mode = OTTO_WDT_MODE_SOFTWARE;
260 else
261 return -EINVAL;
262
263 regmap_update_bits(ctrl->regmap, OTTO_WDT_REG_CTRL,
264 OTTO_WDT_CTRL_RST_MODE,
265 FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, mode));
266 return 0;
267 }
268
269 static const struct regmap_config realtek_otto_wdt_regmap_config = {
270 .reg_bits = 32,
271 .reg_stride = 4,
272 .val_bits = 32,
273 .disable_locking = true,
274 };
275
otto_wdt_probe(struct platform_device * pdev)276 static int otto_wdt_probe(struct platform_device *pdev)
277 {
278 struct device *dev = &pdev->dev;
279 struct otto_wdt_ctrl *ctrl;
280 unsigned int max_tick_ms;
281 void __iomem *base;
282 int ret;
283
284 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
285 if (!ctrl)
286 return -ENOMEM;
287
288 ctrl->dev = dev;
289 base = devm_platform_ioremap_resource(pdev, 0);
290 if (IS_ERR(base))
291 return PTR_ERR(base);
292
293 ctrl->regmap = devm_regmap_init_mmio(dev, base,
294 &realtek_otto_wdt_regmap_config);
295 if (IS_ERR(ctrl->regmap)) {
296 dev_err(dev, "regmap init failed\n");
297 return PTR_ERR(ctrl->regmap);
298 }
299
300 ret = otto_wdt_probe_clk(ctrl);
301 if (ret)
302 return ret;
303
304 /* Clear any old interrupts and reset initial state */
305 regmap_write(ctrl->regmap, OTTO_WDT_REG_INTR,
306 OTTO_WDT_INTR_PHASE_1 | OTTO_WDT_INTR_PHASE_2);
307 regmap_write(ctrl->regmap, OTTO_WDT_REG_CTRL, OTTO_WDT_CTRL_DEFAULT);
308
309 ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1");
310 if (ctrl->irq_phase1 < 0)
311 return ctrl->irq_phase1;
312
313 ret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0,
314 "realtek-otto-wdt", ctrl);
315 if (ret)
316 return ret;
317
318 ret = otto_wdt_probe_reset_mode(ctrl);
319 if (ret)
320 return dev_err_probe(dev, ret, "Invalid reset mode specified\n");
321
322 ctrl->wdev.parent = dev;
323 ctrl->wdev.info = &otto_wdt_info;
324 ctrl->wdev.ops = &otto_wdt_ops;
325
326 /*
327 * Since pretimeout cannot be disabled, min. timeout is twice the
328 * subsystem resolution. Max. timeout is ca. 43s at a bus clock of 200MHz.
329 */
330 ctrl->wdev.min_timeout = 2;
331 max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX);
332 ctrl->wdev.max_hw_heartbeat_ms = max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX;
333 ctrl->wdev.timeout = min(30U, ctrl->wdev.max_hw_heartbeat_ms / 1000);
334
335 watchdog_set_drvdata(&ctrl->wdev, ctrl);
336 watchdog_init_timeout(&ctrl->wdev, 0, dev);
337 watchdog_stop_on_reboot(&ctrl->wdev);
338 watchdog_set_restart_priority(&ctrl->wdev, 128);
339
340 ret = otto_wdt_determine_timeouts(&ctrl->wdev, ctrl->wdev.timeout, 1);
341 if (ret)
342 return dev_err_probe(dev, ret, "Failed to set timeout\n");
343
344 return devm_watchdog_register_device(dev, &ctrl->wdev);
345 }
346
347 static const struct of_device_id otto_wdt_ids[] = {
348 { .compatible = "realtek,rtl8380-wdt" },
349 { .compatible = "realtek,rtl8390-wdt" },
350 { .compatible = "realtek,rtl9300-wdt" },
351 { .compatible = "realtek,rtl9310-wdt" },
352 { }
353 };
354 MODULE_DEVICE_TABLE(of, otto_wdt_ids);
355
356 static struct platform_driver otto_wdt_driver = {
357 .probe = otto_wdt_probe,
358 .driver = {
359 .name = "realtek-otto-watchdog",
360 .of_match_table = otto_wdt_ids,
361 },
362 };
363 module_platform_driver(otto_wdt_driver);
364
365 MODULE_LICENSE("GPL v2");
366 MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>");
367 MODULE_DESCRIPTION("Realtek Otto watchdog timer driver");
368