1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TI QSPI driver
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
6 * Author: Sourav Poddar <sourav.poddar@ti.com>
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/omap-dma.h>
18 #include <linux/platform_device.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/of.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/regmap.h>
28 #include <linux/sizes.h>
29
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi-mem.h>
32
33 struct ti_qspi_regs {
34 u32 clkctrl;
35 };
36
37 struct ti_qspi {
38 struct completion transfer_complete;
39
40 /* list synchronization */
41 struct mutex list_lock;
42
43 struct spi_controller *host;
44 void __iomem *base;
45 void __iomem *mmap_base;
46 size_t mmap_size;
47 struct regmap *ctrl_base;
48 unsigned int ctrl_reg;
49 struct clk *fclk;
50 struct device *dev;
51
52 struct ti_qspi_regs ctx_reg;
53
54 dma_addr_t mmap_phys_base;
55 dma_addr_t rx_bb_dma_addr;
56 void *rx_bb_addr;
57 struct dma_chan *rx_chan;
58
59 u32 cmd;
60 u32 dc;
61
62 bool mmap_enabled;
63 int current_cs;
64 };
65
66 #define QSPI_PID (0x0)
67 #define QSPI_SYSCONFIG (0x10)
68 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
69 #define QSPI_SPI_DC_REG (0x44)
70 #define QSPI_SPI_CMD_REG (0x48)
71 #define QSPI_SPI_STATUS_REG (0x4c)
72 #define QSPI_SPI_DATA_REG (0x50)
73 #define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
74 #define QSPI_SPI_SWITCH_REG (0x64)
75 #define QSPI_SPI_DATA_REG_1 (0x68)
76 #define QSPI_SPI_DATA_REG_2 (0x6c)
77 #define QSPI_SPI_DATA_REG_3 (0x70)
78
79 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
80
81 /* Clock Control */
82 #define QSPI_CLK_EN (1 << 31)
83 #define QSPI_CLK_DIV_MAX 0xffff
84
85 /* Command */
86 #define QSPI_EN_CS(n) (n << 28)
87 #define QSPI_WLEN(n) ((n - 1) << 19)
88 #define QSPI_3_PIN (1 << 18)
89 #define QSPI_RD_SNGL (1 << 16)
90 #define QSPI_WR_SNGL (2 << 16)
91 #define QSPI_RD_DUAL (3 << 16)
92 #define QSPI_RD_QUAD (7 << 16)
93 #define QSPI_INVAL (4 << 16)
94 #define QSPI_FLEN(n) ((n - 1) << 0)
95 #define QSPI_WLEN_MAX_BITS 128
96 #define QSPI_WLEN_MAX_BYTES 16
97 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
98
99 /* STATUS REGISTER */
100 #define BUSY 0x01
101 #define WC 0x02
102
103 /* Device Control */
104 #define QSPI_DD(m, n) (m << (3 + n * 8))
105 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
106 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
107 #define QSPI_CKPOL(n) (1 << (n * 8))
108
109 #define QSPI_FRAME 4096
110
111 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
112
113 #define MEM_CS_EN(n) ((n + 1) << 8)
114 #define MEM_CS_MASK (7 << 8)
115
116 #define MM_SWITCH 0x1
117
118 #define QSPI_SETUP_RD_NORMAL (0x0 << 12)
119 #define QSPI_SETUP_RD_DUAL (0x1 << 12)
120 #define QSPI_SETUP_RD_QUAD (0x3 << 12)
121 #define QSPI_SETUP_ADDR_SHIFT 8
122 #define QSPI_SETUP_DUMMY_SHIFT 10
123
124 #define QSPI_DMA_BUFFER_SIZE SZ_64K
125
ti_qspi_read(struct ti_qspi * qspi,unsigned long reg)126 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
127 unsigned long reg)
128 {
129 return readl(qspi->base + reg);
130 }
131
ti_qspi_write(struct ti_qspi * qspi,unsigned long val,unsigned long reg)132 static inline void ti_qspi_write(struct ti_qspi *qspi,
133 unsigned long val, unsigned long reg)
134 {
135 writel(val, qspi->base + reg);
136 }
137
ti_qspi_setup(struct spi_device * spi)138 static int ti_qspi_setup(struct spi_device *spi)
139 {
140 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller);
141 int ret;
142
143 if (spi->controller->busy) {
144 dev_dbg(qspi->dev, "host busy doing other transfers\n");
145 return -EBUSY;
146 }
147
148 if (!qspi->host->max_speed_hz) {
149 dev_err(qspi->dev, "spi max frequency not defined\n");
150 return -EINVAL;
151 }
152
153 spi->max_speed_hz = min(spi->max_speed_hz, qspi->host->max_speed_hz);
154
155 ret = pm_runtime_resume_and_get(qspi->dev);
156 if (ret < 0) {
157 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
158 return ret;
159 }
160
161 ret = pm_runtime_put_autosuspend(qspi->dev);
162 if (ret < 0) {
163 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
164 return ret;
165 }
166
167 return 0;
168 }
169
ti_qspi_setup_clk(struct ti_qspi * qspi,u32 speed_hz)170 static void ti_qspi_setup_clk(struct ti_qspi *qspi, u32 speed_hz)
171 {
172 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
173 int clk_div;
174 u32 clk_ctrl_reg, clk_rate, clk_ctrl_new;
175
176 clk_rate = clk_get_rate(qspi->fclk);
177 clk_div = DIV_ROUND_UP(clk_rate, speed_hz) - 1;
178 clk_div = clamp(clk_div, 0, QSPI_CLK_DIV_MAX);
179 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", speed_hz, clk_div);
180
181 pm_runtime_resume_and_get(qspi->dev);
182
183 clk_ctrl_new = QSPI_CLK_EN | clk_div;
184 if (ctx_reg->clkctrl != clk_ctrl_new) {
185 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
186
187 clk_ctrl_reg &= ~QSPI_CLK_EN;
188
189 /* disable SCLK */
190 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
191
192 /* enable SCLK */
193 ti_qspi_write(qspi, clk_ctrl_new, QSPI_SPI_CLOCK_CNTRL_REG);
194 ctx_reg->clkctrl = clk_ctrl_new;
195 }
196
197 pm_runtime_put_autosuspend(qspi->dev);
198 }
199
ti_qspi_restore_ctx(struct ti_qspi * qspi)200 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
201 {
202 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
203
204 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
205 }
206
qspi_is_busy(struct ti_qspi * qspi)207 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
208 {
209 u32 stat;
210 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
211
212 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
213 while ((stat & BUSY) && time_after(timeout, jiffies)) {
214 cpu_relax();
215 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
216 }
217
218 WARN(stat & BUSY, "qspi busy\n");
219 return stat & BUSY;
220 }
221
ti_qspi_poll_wc(struct ti_qspi * qspi)222 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
223 {
224 u32 stat;
225 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
226
227 do {
228 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
229 if (stat & WC)
230 return 0;
231 cpu_relax();
232 } while (time_after(timeout, jiffies));
233
234 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
235 if (stat & WC)
236 return 0;
237 return -ETIMEDOUT;
238 }
239
qspi_write_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)240 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
241 int count)
242 {
243 int wlen, xfer_len;
244 unsigned int cmd;
245 const u8 *txbuf;
246 u32 data;
247
248 txbuf = t->tx_buf;
249 cmd = qspi->cmd | QSPI_WR_SNGL;
250 wlen = t->bits_per_word >> 3; /* in bytes */
251 xfer_len = wlen;
252
253 while (count) {
254 if (qspi_is_busy(qspi))
255 return -EBUSY;
256
257 switch (wlen) {
258 case 1:
259 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
260 cmd, qspi->dc, *txbuf);
261 if (count >= QSPI_WLEN_MAX_BYTES) {
262 u32 *txp = (u32 *)txbuf;
263
264 data = cpu_to_be32(*txp++);
265 writel(data, qspi->base +
266 QSPI_SPI_DATA_REG_3);
267 data = cpu_to_be32(*txp++);
268 writel(data, qspi->base +
269 QSPI_SPI_DATA_REG_2);
270 data = cpu_to_be32(*txp++);
271 writel(data, qspi->base +
272 QSPI_SPI_DATA_REG_1);
273 data = cpu_to_be32(*txp++);
274 writel(data, qspi->base +
275 QSPI_SPI_DATA_REG);
276 xfer_len = QSPI_WLEN_MAX_BYTES;
277 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
278 } else {
279 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
280 cmd = qspi->cmd | QSPI_WR_SNGL;
281 xfer_len = wlen;
282 cmd |= QSPI_WLEN(wlen);
283 }
284 break;
285 case 2:
286 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
287 cmd, qspi->dc, *txbuf);
288 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
289 break;
290 case 4:
291 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
292 cmd, qspi->dc, *txbuf);
293 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
294 break;
295 }
296
297 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
298 if (ti_qspi_poll_wc(qspi)) {
299 dev_err(qspi->dev, "write timed out\n");
300 return -ETIMEDOUT;
301 }
302 txbuf += xfer_len;
303 count -= xfer_len;
304 }
305
306 return 0;
307 }
308
qspi_read_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)309 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
310 int count)
311 {
312 int wlen;
313 unsigned int cmd;
314 u32 rx;
315 u8 rxlen, rx_wlen;
316 u8 *rxbuf;
317
318 rxbuf = t->rx_buf;
319 cmd = qspi->cmd;
320 switch (t->rx_nbits) {
321 case SPI_NBITS_DUAL:
322 cmd |= QSPI_RD_DUAL;
323 break;
324 case SPI_NBITS_QUAD:
325 cmd |= QSPI_RD_QUAD;
326 break;
327 default:
328 cmd |= QSPI_RD_SNGL;
329 break;
330 }
331 wlen = t->bits_per_word >> 3; /* in bytes */
332 rx_wlen = wlen;
333
334 while (count) {
335 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
336 if (qspi_is_busy(qspi))
337 return -EBUSY;
338
339 switch (wlen) {
340 case 1:
341 /*
342 * Optimize the 8-bit words transfers, as used by
343 * the SPI flash devices.
344 */
345 if (count >= QSPI_WLEN_MAX_BYTES) {
346 rxlen = QSPI_WLEN_MAX_BYTES;
347 } else {
348 rxlen = min(count, 4);
349 }
350 rx_wlen = rxlen << 3;
351 cmd &= ~QSPI_WLEN_MASK;
352 cmd |= QSPI_WLEN(rx_wlen);
353 break;
354 default:
355 rxlen = wlen;
356 break;
357 }
358
359 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
360 if (ti_qspi_poll_wc(qspi)) {
361 dev_err(qspi->dev, "read timed out\n");
362 return -ETIMEDOUT;
363 }
364
365 switch (wlen) {
366 case 1:
367 /*
368 * Optimize the 8-bit words transfers, as used by
369 * the SPI flash devices.
370 */
371 if (count >= QSPI_WLEN_MAX_BYTES) {
372 u32 *rxp = (u32 *) rxbuf;
373 rx = readl(qspi->base + QSPI_SPI_DATA_REG_3);
374 *rxp++ = be32_to_cpu(rx);
375 rx = readl(qspi->base + QSPI_SPI_DATA_REG_2);
376 *rxp++ = be32_to_cpu(rx);
377 rx = readl(qspi->base + QSPI_SPI_DATA_REG_1);
378 *rxp++ = be32_to_cpu(rx);
379 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
380 *rxp++ = be32_to_cpu(rx);
381 } else {
382 u8 *rxp = rxbuf;
383 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
384 if (rx_wlen >= 8)
385 *rxp++ = rx >> (rx_wlen - 8);
386 if (rx_wlen >= 16)
387 *rxp++ = rx >> (rx_wlen - 16);
388 if (rx_wlen >= 24)
389 *rxp++ = rx >> (rx_wlen - 24);
390 if (rx_wlen >= 32)
391 *rxp++ = rx;
392 }
393 break;
394 case 2:
395 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
396 break;
397 case 4:
398 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
399 break;
400 }
401 rxbuf += rxlen;
402 count -= rxlen;
403 }
404
405 return 0;
406 }
407
qspi_transfer_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)408 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
409 int count)
410 {
411 int ret;
412
413 if (t->tx_buf) {
414 ret = qspi_write_msg(qspi, t, count);
415 if (ret) {
416 dev_dbg(qspi->dev, "Error while writing\n");
417 return ret;
418 }
419 }
420
421 if (t->rx_buf) {
422 ret = qspi_read_msg(qspi, t, count);
423 if (ret) {
424 dev_dbg(qspi->dev, "Error while reading\n");
425 return ret;
426 }
427 }
428
429 return 0;
430 }
431
ti_qspi_dma_callback(void * param)432 static void ti_qspi_dma_callback(void *param)
433 {
434 struct ti_qspi *qspi = param;
435
436 complete(&qspi->transfer_complete);
437 }
438
ti_qspi_dma_xfer(struct ti_qspi * qspi,dma_addr_t dma_dst,dma_addr_t dma_src,size_t len)439 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
440 dma_addr_t dma_src, size_t len)
441 {
442 struct dma_chan *chan = qspi->rx_chan;
443 dma_cookie_t cookie;
444 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
445 struct dma_async_tx_descriptor *tx;
446 int ret;
447 unsigned long time_left;
448
449 tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
450 if (!tx) {
451 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
452 return -EIO;
453 }
454
455 tx->callback = ti_qspi_dma_callback;
456 tx->callback_param = qspi;
457 cookie = tx->tx_submit(tx);
458 reinit_completion(&qspi->transfer_complete);
459
460 ret = dma_submit_error(cookie);
461 if (ret) {
462 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
463 return -EIO;
464 }
465
466 dma_async_issue_pending(chan);
467 time_left = wait_for_completion_timeout(&qspi->transfer_complete,
468 msecs_to_jiffies(len));
469 if (time_left == 0) {
470 dmaengine_terminate_sync(chan);
471 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
472 return -ETIMEDOUT;
473 }
474
475 return 0;
476 }
477
ti_qspi_dma_bounce_buffer(struct ti_qspi * qspi,loff_t offs,void * to,size_t readsize)478 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
479 void *to, size_t readsize)
480 {
481 dma_addr_t dma_src = qspi->mmap_phys_base + offs;
482 int ret = 0;
483
484 /*
485 * Use bounce buffer as FS like jffs2, ubifs may pass
486 * buffers that does not belong to kernel lowmem region.
487 */
488 while (readsize != 0) {
489 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
490 readsize);
491
492 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
493 dma_src, xfer_len);
494 if (ret != 0)
495 return ret;
496 memcpy(to, qspi->rx_bb_addr, xfer_len);
497 readsize -= xfer_len;
498 dma_src += xfer_len;
499 to += xfer_len;
500 }
501
502 return ret;
503 }
504
ti_qspi_dma_xfer_sg(struct ti_qspi * qspi,struct sg_table rx_sg,loff_t from)505 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
506 loff_t from)
507 {
508 struct scatterlist *sg;
509 dma_addr_t dma_src = qspi->mmap_phys_base + from;
510 dma_addr_t dma_dst;
511 int i, len, ret;
512
513 for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
514 dma_dst = sg_dma_address(sg);
515 len = sg_dma_len(sg);
516 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
517 if (ret)
518 return ret;
519 dma_src += len;
520 }
521
522 return 0;
523 }
524
ti_qspi_enable_memory_map(struct spi_device * spi)525 static void ti_qspi_enable_memory_map(struct spi_device *spi)
526 {
527 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller);
528
529 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
530 if (qspi->ctrl_base) {
531 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
532 MEM_CS_MASK,
533 MEM_CS_EN(spi_get_chipselect(spi, 0)));
534 }
535 qspi->mmap_enabled = true;
536 qspi->current_cs = spi_get_chipselect(spi, 0);
537 }
538
ti_qspi_disable_memory_map(struct spi_device * spi)539 static void ti_qspi_disable_memory_map(struct spi_device *spi)
540 {
541 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller);
542
543 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
544 if (qspi->ctrl_base)
545 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
546 MEM_CS_MASK, 0);
547 qspi->mmap_enabled = false;
548 qspi->current_cs = -1;
549 }
550
ti_qspi_setup_mmap_read(struct spi_device * spi,u8 opcode,u8 data_nbits,u8 addr_width,u8 dummy_bytes)551 static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
552 u8 data_nbits, u8 addr_width,
553 u8 dummy_bytes)
554 {
555 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller);
556 u32 memval = opcode;
557
558 switch (data_nbits) {
559 case SPI_NBITS_QUAD:
560 memval |= QSPI_SETUP_RD_QUAD;
561 break;
562 case SPI_NBITS_DUAL:
563 memval |= QSPI_SETUP_RD_DUAL;
564 break;
565 default:
566 memval |= QSPI_SETUP_RD_NORMAL;
567 break;
568 }
569 memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
570 dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
571 ti_qspi_write(qspi, memval,
572 QSPI_SPI_SETUP_REG(spi_get_chipselect(spi, 0)));
573 }
574
ti_qspi_adjust_op_size(struct spi_mem * mem,struct spi_mem_op * op)575 static int ti_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
576 {
577 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller);
578 size_t max_len;
579
580 if (op->data.dir == SPI_MEM_DATA_IN) {
581 if (op->addr.val < qspi->mmap_size) {
582 /* Limit MMIO to the mmaped region */
583 if (op->addr.val + op->data.nbytes > qspi->mmap_size) {
584 max_len = qspi->mmap_size - op->addr.val;
585 op->data.nbytes = min((size_t) op->data.nbytes,
586 max_len);
587 }
588 } else {
589 /*
590 * Use fallback mode (SW generated transfers) above the
591 * mmaped region.
592 * Adjust size to comply with the QSPI max frame length.
593 */
594 max_len = QSPI_FRAME;
595 max_len -= 1 + op->addr.nbytes + op->dummy.nbytes;
596 op->data.nbytes = min((size_t) op->data.nbytes,
597 max_len);
598 }
599 }
600
601 return 0;
602 }
603
ti_qspi_exec_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)604 static int ti_qspi_exec_mem_op(struct spi_mem *mem,
605 const struct spi_mem_op *op)
606 {
607 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller);
608 u32 from = 0;
609 int ret = 0;
610
611 /* Only optimize read path. */
612 if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
613 !op->addr.nbytes || op->addr.nbytes > 4)
614 return -EOPNOTSUPP;
615
616 /* Address exceeds MMIO window size, fall back to regular mode. */
617 from = op->addr.val;
618 if (from + op->data.nbytes > qspi->mmap_size)
619 return -EOPNOTSUPP;
620
621 mutex_lock(&qspi->list_lock);
622
623 if (!qspi->mmap_enabled || qspi->current_cs != spi_get_chipselect(mem->spi, 0)) {
624 ti_qspi_setup_clk(qspi, op->max_freq);
625 ti_qspi_enable_memory_map(mem->spi);
626 }
627 ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
628 op->addr.nbytes, op->dummy.nbytes);
629
630 if (qspi->rx_chan) {
631 struct sg_table sgt;
632
633 if (virt_addr_valid(op->data.buf.in) &&
634 !spi_controller_dma_map_mem_op_data(mem->spi->controller, op,
635 &sgt)) {
636 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
637 spi_controller_dma_unmap_mem_op_data(mem->spi->controller,
638 op, &sgt);
639 } else {
640 ret = ti_qspi_dma_bounce_buffer(qspi, from,
641 op->data.buf.in,
642 op->data.nbytes);
643 }
644 } else {
645 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
646 op->data.nbytes);
647 }
648
649 mutex_unlock(&qspi->list_lock);
650
651 return ret;
652 }
653
654 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
655 .exec_op = ti_qspi_exec_mem_op,
656 .adjust_op_size = ti_qspi_adjust_op_size,
657 };
658
659 static const struct spi_controller_mem_caps ti_qspi_mem_caps = {
660 .per_op_freq = true,
661 };
662
ti_qspi_start_transfer_one(struct spi_controller * host,struct spi_message * m)663 static int ti_qspi_start_transfer_one(struct spi_controller *host,
664 struct spi_message *m)
665 {
666 struct ti_qspi *qspi = spi_controller_get_devdata(host);
667 struct spi_device *spi = m->spi;
668 struct spi_transfer *t;
669 int status = 0, ret;
670 unsigned int frame_len_words, transfer_len_words;
671 int wlen;
672
673 /* setup device control reg */
674 qspi->dc = 0;
675
676 if (spi->mode & SPI_CPHA)
677 qspi->dc |= QSPI_CKPHA(spi_get_chipselect(spi, 0));
678 if (spi->mode & SPI_CPOL)
679 qspi->dc |= QSPI_CKPOL(spi_get_chipselect(spi, 0));
680 if (spi->mode & SPI_CS_HIGH)
681 qspi->dc |= QSPI_CSPOL(spi_get_chipselect(spi, 0));
682
683 frame_len_words = 0;
684 list_for_each_entry(t, &m->transfers, transfer_list)
685 frame_len_words += t->len / (t->bits_per_word >> 3);
686 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
687
688 /* setup command reg */
689 qspi->cmd = 0;
690 qspi->cmd |= QSPI_EN_CS(spi_get_chipselect(spi, 0));
691 qspi->cmd |= QSPI_FLEN(frame_len_words);
692
693 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
694
695 mutex_lock(&qspi->list_lock);
696
697 if (qspi->mmap_enabled)
698 ti_qspi_disable_memory_map(spi);
699
700 list_for_each_entry(t, &m->transfers, transfer_list) {
701 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
702 QSPI_WLEN(t->bits_per_word));
703
704 wlen = t->bits_per_word >> 3;
705 transfer_len_words = min(t->len / wlen, frame_len_words);
706
707 ti_qspi_setup_clk(qspi, t->speed_hz);
708 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
709 if (ret) {
710 dev_dbg(qspi->dev, "transfer message failed\n");
711 mutex_unlock(&qspi->list_lock);
712 return -EINVAL;
713 }
714
715 m->actual_length += transfer_len_words * wlen;
716 frame_len_words -= transfer_len_words;
717 if (frame_len_words == 0)
718 break;
719 }
720
721 mutex_unlock(&qspi->list_lock);
722
723 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
724 m->status = status;
725 spi_finalize_current_message(host);
726
727 return status;
728 }
729
ti_qspi_runtime_resume(struct device * dev)730 static int ti_qspi_runtime_resume(struct device *dev)
731 {
732 struct ti_qspi *qspi;
733
734 qspi = dev_get_drvdata(dev);
735 ti_qspi_restore_ctx(qspi);
736
737 return 0;
738 }
739
ti_qspi_dma_cleanup(struct ti_qspi * qspi)740 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi)
741 {
742 if (qspi->rx_bb_addr)
743 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
744 qspi->rx_bb_addr,
745 qspi->rx_bb_dma_addr);
746
747 if (qspi->rx_chan)
748 dma_release_channel(qspi->rx_chan);
749 }
750
751 static const struct of_device_id ti_qspi_match[] = {
752 {.compatible = "ti,dra7xxx-qspi" },
753 {.compatible = "ti,am4372-qspi" },
754 {},
755 };
756 MODULE_DEVICE_TABLE(of, ti_qspi_match);
757
ti_qspi_probe(struct platform_device * pdev)758 static int ti_qspi_probe(struct platform_device *pdev)
759 {
760 struct ti_qspi *qspi;
761 struct spi_controller *host;
762 struct resource *r, *res_mmap;
763 struct device_node *np = pdev->dev.of_node;
764 u32 max_freq;
765 int ret = 0, num_cs, irq;
766 dma_cap_mask_t mask;
767
768 host = spi_alloc_host(&pdev->dev, sizeof(*qspi));
769 if (!host)
770 return -ENOMEM;
771
772 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
773
774 host->flags = SPI_CONTROLLER_HALF_DUPLEX;
775 host->setup = ti_qspi_setup;
776 host->auto_runtime_pm = true;
777 host->transfer_one_message = ti_qspi_start_transfer_one;
778 host->dev.of_node = pdev->dev.of_node;
779 host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
780 SPI_BPW_MASK(8);
781 host->mem_ops = &ti_qspi_mem_ops;
782 host->mem_caps = &ti_qspi_mem_caps;
783
784 if (!of_property_read_u32(np, "num-cs", &num_cs))
785 host->num_chipselect = num_cs;
786
787 qspi = spi_controller_get_devdata(host);
788 qspi->host = host;
789 qspi->dev = &pdev->dev;
790 platform_set_drvdata(pdev, qspi);
791
792 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
793 if (r == NULL) {
794 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
795 if (r == NULL) {
796 dev_err(&pdev->dev, "missing platform data\n");
797 ret = -ENODEV;
798 goto free_host;
799 }
800 }
801
802 res_mmap = platform_get_resource_byname(pdev,
803 IORESOURCE_MEM, "qspi_mmap");
804 if (res_mmap == NULL) {
805 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
806 if (res_mmap == NULL) {
807 dev_err(&pdev->dev,
808 "memory mapped resource not required\n");
809 }
810 }
811
812 if (res_mmap)
813 qspi->mmap_size = resource_size(res_mmap);
814
815 irq = platform_get_irq(pdev, 0);
816 if (irq < 0) {
817 ret = irq;
818 goto free_host;
819 }
820
821 mutex_init(&qspi->list_lock);
822
823 qspi->base = devm_ioremap_resource(&pdev->dev, r);
824 if (IS_ERR(qspi->base)) {
825 ret = PTR_ERR(qspi->base);
826 goto free_host;
827 }
828
829
830 if (of_property_present(np, "syscon-chipselects")) {
831 qspi->ctrl_base =
832 syscon_regmap_lookup_by_phandle_args(np, "syscon-chipselects",
833 1, &qspi->ctrl_reg);
834 if (IS_ERR(qspi->ctrl_base)) {
835 ret = PTR_ERR(qspi->ctrl_base);
836 goto free_host;
837 }
838 }
839
840 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
841 if (IS_ERR(qspi->fclk)) {
842 ret = PTR_ERR(qspi->fclk);
843 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
844 }
845
846 pm_runtime_use_autosuspend(&pdev->dev);
847 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
848 pm_runtime_enable(&pdev->dev);
849
850 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
851 host->max_speed_hz = max_freq;
852
853 dma_cap_zero(mask);
854 dma_cap_set(DMA_MEMCPY, mask);
855
856 qspi->rx_chan = dma_request_chan_by_mask(&mask);
857 if (IS_ERR(qspi->rx_chan)) {
858 dev_err(qspi->dev,
859 "No Rx DMA available, trying mmap mode\n");
860 qspi->rx_chan = NULL;
861 goto no_dma;
862 }
863 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
864 QSPI_DMA_BUFFER_SIZE,
865 &qspi->rx_bb_dma_addr,
866 GFP_KERNEL | GFP_DMA);
867 if (!qspi->rx_bb_addr) {
868 dev_err(qspi->dev,
869 "dma_alloc_coherent failed, using PIO mode\n");
870 dma_release_channel(qspi->rx_chan);
871 goto no_dma;
872 }
873 host->dma_rx = qspi->rx_chan;
874 init_completion(&qspi->transfer_complete);
875 if (res_mmap)
876 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
877
878 no_dma:
879 if (!qspi->rx_chan && res_mmap) {
880 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
881 if (IS_ERR(qspi->mmap_base)) {
882 dev_info(&pdev->dev,
883 "mmap failed with error %ld using PIO mode\n",
884 PTR_ERR(qspi->mmap_base));
885 qspi->mmap_base = NULL;
886 host->mem_ops = NULL;
887 }
888 }
889 qspi->mmap_enabled = false;
890 qspi->current_cs = -1;
891
892 ret = devm_spi_register_controller(&pdev->dev, host);
893 if (!ret)
894 return 0;
895
896 ti_qspi_dma_cleanup(qspi);
897
898 pm_runtime_disable(&pdev->dev);
899 free_host:
900 spi_controller_put(host);
901 return ret;
902 }
903
ti_qspi_remove(struct platform_device * pdev)904 static void ti_qspi_remove(struct platform_device *pdev)
905 {
906 struct ti_qspi *qspi = platform_get_drvdata(pdev);
907 int rc;
908
909 rc = spi_controller_suspend(qspi->host);
910 if (rc) {
911 dev_alert(&pdev->dev, "spi_controller_suspend() failed (%pe)\n",
912 ERR_PTR(rc));
913 return;
914 }
915
916 pm_runtime_put_sync(&pdev->dev);
917 pm_runtime_disable(&pdev->dev);
918
919 ti_qspi_dma_cleanup(qspi);
920 }
921
922 static const struct dev_pm_ops ti_qspi_pm_ops = {
923 .runtime_resume = ti_qspi_runtime_resume,
924 };
925
926 static struct platform_driver ti_qspi_driver = {
927 .probe = ti_qspi_probe,
928 .remove = ti_qspi_remove,
929 .driver = {
930 .name = "ti-qspi",
931 .pm = &ti_qspi_pm_ops,
932 .of_match_table = ti_qspi_match,
933 }
934 };
935
936 module_platform_driver(ti_qspi_driver);
937
938 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
939 MODULE_LICENSE("GPL v2");
940 MODULE_DESCRIPTION("TI QSPI controller driver");
941 MODULE_ALIAS("platform:ti-qspi");
942