1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #include "mpc.h" 37 #include "dwb.h" 38 #include "hw/dio.h" 39 #include "mcif_wb.h" 40 #include "panel_cntl.h" 41 #include "dmub/inc/dmub_cmd.h" 42 #include "pg_cntl.h" 43 #include "sspl/dc_spl.h" 44 45 #define MAX_CLOCK_SOURCES 7 46 #define MAX_SVP_PHANTOM_STREAMS 2 47 #define MAX_SVP_PHANTOM_PLANES 2 48 49 #include "grph_object_id.h" 50 #include "link_encoder.h" 51 #include "stream_encoder.h" 52 #include "clock_source.h" 53 #include "audio.h" 54 #include "dm_pp_smu.h" 55 #include "dm_cp_psp.h" 56 #include "link_hwss.h" 57 58 /********** DAL Core*********************/ 59 #include "transform.h" 60 #include "dpp.h" 61 62 #include "dml2_0/dml21/inc/dml_top_dchub_registers.h" 63 #include "dml2_0/dml21/inc/dml_top_types.h" 64 65 struct resource_pool; 66 struct dc_state; 67 struct resource_context; 68 struct clk_bw_params; 69 struct dc_mcache_params; 70 71 #define MAX_RMCM_INST 2 72 73 struct resource_funcs { 74 enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index); 75 void (*destroy)(struct resource_pool **pool); 76 void (*link_init)(struct dc_link *link); 77 struct panel_cntl*(*panel_cntl_create)( 78 const struct panel_cntl_init_data *panel_cntl_init_data); 79 struct link_encoder *(*link_enc_create)( 80 struct dc_context *ctx, 81 const struct encoder_init_data *init); 82 /* Create a minimal link encoder object with no dc_link object 83 * associated with it. */ 84 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 85 enum dc_status (*validate_bandwidth)( 86 struct dc *dc, 87 struct dc_state *context, 88 enum dc_validate_mode validate_mode); 89 void (*calculate_wm_and_dlg)( 90 struct dc *dc, struct dc_state *context, 91 display_e2e_pipe_params_st *pipes, 92 int pipe_cnt, 93 int vlevel); 94 void (*update_soc_for_wm_a)( 95 struct dc *dc, struct dc_state *context); 96 97 unsigned int (*calculate_mall_ways_from_bytes)( 98 const struct dc *dc, 99 unsigned int total_size_in_mall_bytes); 100 void (*prepare_mcache_programming)( 101 struct dc *dc, 102 struct dc_state *context); 103 /** 104 * @populate_dml_pipes - Populate pipe data struct 105 * 106 * Returns: 107 * Total of pipes available in the specific ASIC. 108 */ 109 int (*populate_dml_pipes)( 110 struct dc *dc, 111 struct dc_state *context, 112 display_e2e_pipe_params_st *pipes, 113 enum dc_validate_mode validate_mode); 114 115 /* 116 * Algorithm for assigning available link encoders to links. 117 * 118 * Update link_enc_assignments table and link_enc_avail list accordingly in 119 * struct resource_context. 120 */ 121 void (*link_encs_assign)( 122 struct dc *dc, 123 struct dc_state *state, 124 struct dc_stream_state *streams[], 125 uint8_t stream_count); 126 /* 127 * Unassign a link encoder from a stream. 128 * 129 * Update link_enc_assignments table and link_enc_avail list accordingly in 130 * struct resource_context. 131 */ 132 void (*link_enc_unassign)( 133 struct dc_state *state, 134 struct dc_stream_state *stream); 135 136 enum dc_status (*validate_global)( 137 struct dc *dc, 138 struct dc_state *context); 139 140 struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)( 141 const struct dc_state *cur_ctx, 142 struct dc_state *new_ctx, 143 const struct resource_pool *pool, 144 const struct pipe_ctx *opp_head_pipe); 145 146 struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)( 147 const struct dc_state *cur_ctx, 148 struct dc_state *new_ctx, 149 const struct resource_pool *pool, 150 const struct pipe_ctx *otg_master); 151 152 void (*release_pipe)(struct dc_state *context, 153 struct pipe_ctx *pipe, 154 const struct resource_pool *pool); 155 156 enum dc_status (*validate_plane)( 157 const struct dc_plane_state *plane_state, 158 struct dc_caps *caps); 159 160 enum dc_status (*add_stream_to_ctx)( 161 struct dc *dc, 162 struct dc_state *new_ctx, 163 struct dc_stream_state *dc_stream); 164 165 enum dc_status (*remove_stream_from_ctx)( 166 struct dc *dc, 167 struct dc_state *new_ctx, 168 struct dc_stream_state *stream); 169 170 enum dc_status (*patch_unknown_plane_state)( 171 struct dc_plane_state *plane_state); 172 173 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 174 struct resource_context *res_ctx, 175 const struct resource_pool *pool, 176 struct dc_stream_state *stream); 177 178 void (*populate_dml_writeback_from_context)( 179 struct dc *dc, 180 struct resource_context *res_ctx, 181 display_e2e_pipe_params_st *pipes); 182 183 void (*set_mcif_arb_params)( 184 struct dc *dc, 185 struct dc_state *context, 186 display_e2e_pipe_params_st *pipes, 187 int pipe_cnt); 188 189 void (*update_bw_bounding_box)( 190 struct dc *dc, 191 struct clk_bw_params *bw_params); 192 bool (*acquire_post_bldn_3dlut)( 193 struct resource_context *res_ctx, 194 const struct resource_pool *pool, 195 int mpcc_id, 196 struct dc_3dlut **lut, 197 struct dc_transfer_func **shaper); 198 199 bool (*release_post_bldn_3dlut)( 200 struct resource_context *res_ctx, 201 const struct resource_pool *pool, 202 struct dc_3dlut **lut, 203 struct dc_transfer_func **shaper); 204 205 enum dc_status (*add_dsc_to_stream_resource)( 206 struct dc *dc, struct dc_state *state, 207 struct dc_stream_state *stream); 208 209 void (*add_phantom_pipes)( 210 struct dc *dc, 211 struct dc_state *context, 212 display_e2e_pipe_params_st *pipes, 213 unsigned int pipe_cnt, 214 unsigned int index); 215 216 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 217 void (*get_default_tiling_info)(struct dc_tiling_info *tiling_info); 218 void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); 219 /* 220 * Get indicator of power from a context that went through full validation 221 */ 222 int (*get_power_profile)(const struct dc_state *context); 223 unsigned int (*get_det_buffer_size)(const struct dc_state *context); 224 unsigned int (*get_vstartup_for_pipe)(struct pipe_ctx *pipe_ctx); 225 unsigned int (*get_max_hw_cursor_size)(const struct dc *dc, 226 struct dc_state *state, 227 const struct dc_stream_state *stream); 228 bool (*program_mcache_pipe_config)(struct dc_state *context, 229 const struct dc_mcache_params *mcache_params); 230 enum dc_status (*update_dc_state_for_encoder_switch)(struct dc_link *link, 231 struct dc_link_settings *link_setting, 232 uint8_t pipe_count, 233 struct pipe_ctx *pipes, 234 struct audio_output *audio_output); 235 }; 236 237 struct audio_support{ 238 bool dp_audio; 239 bool hdmi_audio_on_dongle; 240 bool hdmi_audio_native; 241 }; 242 243 #define NO_UNDERLAY_PIPE -1 244 245 struct resource_pool { 246 struct mem_input *mis[MAX_PIPES]; 247 struct hubp *hubps[MAX_PIPES]; 248 struct input_pixel_processor *ipps[MAX_PIPES]; 249 struct transform *transforms[MAX_PIPES]; 250 struct dpp *dpps[MAX_PIPES]; 251 struct output_pixel_processor *opps[MAX_PIPES]; 252 struct timing_generator *timing_generators[MAX_PIPES]; 253 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 254 struct hubbub *hubbub; 255 struct dio *dio; 256 struct mpc *mpc; 257 struct pp_smu_funcs *pp_smu; 258 struct dce_aux *engines[MAX_PIPES]; 259 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 260 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 261 bool i2c_hw_buffer_in_use; 262 263 struct dwbc *dwbc[MAX_DWB_PIPES]; 264 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 265 struct { 266 unsigned int gsl_0:1; 267 unsigned int gsl_1:1; 268 unsigned int gsl_2:1; 269 } gsl_groups; 270 271 struct display_stream_compressor *dscs[MAX_PIPES]; 272 273 unsigned int pipe_count; 274 unsigned int underlay_pipe_index; 275 unsigned int stream_enc_count; 276 277 /* An array for accessing the link encoder objects that have been created. 278 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 279 */ 280 struct link_encoder *link_encoders[MAX_LINK_ENCODERS]; 281 /* Number of DIG link encoder objects created - i.e. number of valid 282 * entries in link_encoders array. 283 */ 284 unsigned int dig_link_enc_count; 285 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 286 unsigned int usb4_dpia_count; 287 288 unsigned int hpo_dp_stream_enc_count; 289 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 290 unsigned int hpo_dp_link_enc_count; 291 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 292 struct dc_3dlut *mpc_lut[MAX_PIPES]; 293 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 294 struct dc_rmcm_3dlut rmcm_3dlut[MAX_RMCM_INST]; 295 296 struct { 297 unsigned int xtalin_clock_inKhz; 298 unsigned int dccg_ref_clock_inKhz; 299 unsigned int dchub_ref_clock_inKhz; 300 } ref_clocks; 301 unsigned int timing_generator_count; 302 unsigned int mpcc_count; 303 304 unsigned int writeback_pipe_count; 305 /* 306 * reserved clock source for DP 307 */ 308 struct clock_source *dp_clock_source; 309 310 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 311 unsigned int clk_src_count; 312 313 struct audio *audios[MAX_AUDIOS]; 314 unsigned int audio_count; 315 struct audio_support audio_support; 316 317 struct dccg *dccg; 318 struct pg_cntl *pg_cntl; 319 struct irq_service *irqs; 320 321 struct abm *abm; 322 struct dmcu *dmcu; 323 struct dmub_psr *psr; 324 struct dmub_replay *replay; 325 326 struct abm *multiple_abms[MAX_PIPES]; 327 328 const struct resource_funcs *funcs; 329 const struct resource_caps *res_cap; 330 331 struct ddc_service *oem_device; 332 }; 333 334 struct dcn_fe_bandwidth { 335 int dppclk_khz; 336 337 }; 338 339 /* Parameters needed to call set_disp_pattern_generator */ 340 struct test_pattern_params { 341 enum controller_dp_test_pattern test_pattern; 342 enum controller_dp_color_space color_space; 343 enum dc_color_depth color_depth; 344 int width; 345 int height; 346 int offset; 347 }; 348 349 struct stream_resource { 350 struct output_pixel_processor *opp; 351 struct display_stream_compressor *dsc; 352 struct timing_generator *tg; 353 struct stream_encoder *stream_enc; 354 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 355 struct audio *audio; 356 357 struct pixel_clk_params pix_clk_params; 358 struct encoder_info_frame encoder_info_frame; 359 360 struct abm *abm; 361 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 362 * otherwise it's using group number 'gsl_group-1' 363 */ 364 uint8_t gsl_group; 365 366 struct test_pattern_params test_pattern_params; 367 }; 368 369 struct plane_resource { 370 /* scl_data is scratch space required to program a plane */ 371 struct scaler_data scl_data; 372 /* Below pointers to hw objects are required to enable the plane */ 373 /* spl_in and spl_out are the input and output structures for SPL 374 * which are required when using Scaler Programming Library 375 * these are scratch spaces needed when programming a plane 376 */ 377 struct spl_in spl_in; 378 struct spl_out spl_out; 379 /* Below pointers to hw objects are required to enable the plane */ 380 struct hubp *hubp; 381 struct mem_input *mi; 382 struct input_pixel_processor *ipp; 383 struct transform *xfm; 384 struct dpp *dpp; 385 uint8_t mpcc_inst; 386 387 struct dcn_fe_bandwidth bw; 388 }; 389 390 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 391 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 392 393 /* all mappable hardware resources used to enable a link */ 394 struct link_resource { 395 struct link_encoder *dio_link_enc; 396 struct hpo_dp_link_encoder *hpo_dp_link_enc; 397 }; 398 399 struct link_config { 400 struct dc_link_settings dp_link_settings; 401 struct dc_tunnel_settings dp_tunnel_settings; 402 }; 403 404 union pipe_update_flags { 405 struct { 406 uint32_t enable : 1; 407 uint32_t disable : 1; 408 uint32_t odm : 1; 409 uint32_t global_sync : 1; 410 uint32_t opp_changed : 1; 411 uint32_t tg_changed : 1; 412 uint32_t mpcc : 1; 413 uint32_t dppclk : 1; 414 uint32_t hubp_interdependent : 1; 415 uint32_t hubp_rq_dlg_ttu : 1; 416 uint32_t gamut_remap : 1; 417 uint32_t scaler : 1; 418 uint32_t viewport : 1; 419 uint32_t plane_changed : 1; 420 uint32_t det_size : 1; 421 uint32_t unbounded_req : 1; 422 uint32_t test_pattern_changed : 1; 423 } bits; 424 uint32_t raw; 425 }; 426 427 struct pixel_rate_divider { 428 uint32_t div_factor1; 429 uint32_t div_factor2; 430 }; 431 432 enum p_state_switch_method { 433 P_STATE_UNKNOWN = 0, 434 P_STATE_V_BLANK = 1, 435 P_STATE_FPO, 436 P_STATE_V_ACTIVE, 437 P_STATE_SUB_VP, 438 P_STATE_DRR_SUB_VP, 439 P_STATE_V_BLANK_SUB_VP, 440 }; 441 442 struct dsc_padding_params { 443 /* pixels borrowed from hblank to hactive */ 444 uint8_t dsc_hactive_padding; 445 uint32_t dsc_htotal_padding; 446 uint32_t dsc_pix_clk_100hz; 447 }; 448 449 struct pipe_ctx { 450 struct dc_plane_state *plane_state; 451 struct dc_stream_state *stream; 452 453 struct plane_resource plane_res; 454 455 /** 456 * @stream_res: Reference to DCN resource components such OPP and DSC. 457 */ 458 struct stream_resource stream_res; 459 struct link_resource link_res; 460 461 struct clock_source *clock_source; 462 463 struct pll_settings pll_settings; 464 465 /** 466 * @link_config: 467 * 468 * link config records software decision for what link config should be 469 * enabled given current link capability and stream during hw resource 470 * mapping. This is to decouple the dependency on link capability during 471 * dc commit or update. 472 */ 473 struct link_config link_config; 474 475 uint8_t pipe_idx; 476 uint8_t pipe_idx_syncd; 477 478 struct pipe_ctx *top_pipe; 479 struct pipe_ctx *bottom_pipe; 480 struct pipe_ctx *next_odm_pipe; 481 struct pipe_ctx *prev_odm_pipe; 482 483 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 484 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 485 struct _vcs_dpi_display_rq_regs_st rq_regs; 486 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 487 struct _vcs_dpi_display_rq_params_st dml_rq_param; 488 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 489 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 490 int det_buffer_size_kb; 491 bool unbounded_req; 492 unsigned int surface_size_in_mall_bytes; 493 struct dml2_dchub_per_pipe_register_set hubp_regs; 494 struct dml2_hubp_pipe_mcache_regs mcache_regs; 495 union dml2_global_sync_programming global_sync; 496 497 struct dwbc *dwbc; 498 struct mcif_wb *mcif_wb; 499 union pipe_update_flags update_flags; 500 enum p_state_switch_method p_state_type; 501 struct tg_color visual_confirm_color; 502 bool has_vactive_margin; 503 /* subvp_index: only valid if the pipe is a SUBVP_MAIN*/ 504 uint8_t subvp_index; 505 struct pixel_rate_divider pixel_rate_divider; 506 struct dsc_padding_params dsc_padding_params; 507 /* next vupdate */ 508 uint32_t next_vupdate; 509 uint32_t wait_frame_count; 510 bool wait_is_required; 511 }; 512 513 /* Data used for dynamic link encoder assignment. 514 * Tracks current and future assignments; available link encoders; 515 * and mode of operation (whether to use current or future assignments). 516 */ 517 struct link_enc_cfg_context { 518 enum link_enc_cfg_mode mode; 519 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 520 enum engine_id link_enc_avail[MAX_LINK_ENCODERS]; 521 struct link_enc_assignment transient_assignments[MAX_PIPES]; 522 }; 523 524 struct resource_context { 525 struct pipe_ctx pipe_ctx[MAX_PIPES]; 526 bool is_stream_enc_acquired[MAX_PIPES * 2]; 527 bool is_audio_acquired[MAX_PIPES]; 528 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 529 uint8_t dp_clock_source_ref_count; 530 bool is_dsc_acquired[MAX_PIPES]; 531 struct link_enc_cfg_context link_enc_cfg_ctx; 532 unsigned int dio_link_enc_to_link_idx[MAX_LINK_ENCODERS]; 533 int dio_link_enc_ref_cnts[MAX_LINK_ENCODERS]; 534 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 535 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 536 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 537 bool is_mpc_3dlut_acquired[MAX_PIPES]; 538 /* used to build scalar data in dml2 and for edp backlight programming */ 539 struct pipe_ctx temp_pipe; 540 }; 541 542 struct dce_bw_output { 543 bool cpuc_state_change_enable; 544 bool cpup_state_change_enable; 545 bool stutter_mode_enable; 546 bool nbp_state_change_enable; 547 bool all_displays_in_sync; 548 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 549 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 550 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 551 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 552 int sclk_khz; 553 int sclk_deep_sleep_khz; 554 int yclk_khz; 555 int dispclk_khz; 556 int blackout_recovery_time_us; 557 }; 558 559 struct dcn_bw_writeback { 560 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 561 }; 562 563 struct dcn_bw_output { 564 struct dc_clocks clk; 565 union dcn_watermark_set watermarks; 566 struct dcn_bw_writeback bw_writeback; 567 int compbuf_size_kb; 568 unsigned int mall_ss_size_bytes; 569 unsigned int mall_ss_psr_active_size_bytes; 570 unsigned int mall_subvp_size_bytes; 571 unsigned int legacy_svp_drr_stream_index; 572 bool legacy_svp_drr_stream_index_valid; 573 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 574 struct dmub_cmd_fams2_global_config fams2_global_config; 575 union dmub_cmd_fams2_config fams2_stream_base_params[DML2_MAX_PLANES]; 576 union { 577 union dmub_cmd_fams2_config fams2_stream_sub_params[DML2_MAX_PLANES]; 578 union dmub_fams2_stream_static_sub_state_v2 fams2_stream_sub_params_v2[DML2_MAX_PLANES]; 579 }; 580 struct dml2_display_arb_regs arb_regs; 581 }; 582 583 union bw_output { 584 struct dcn_bw_output dcn; 585 struct dce_bw_output dce; 586 }; 587 588 struct bw_context { 589 union bw_output bw; 590 struct display_mode_lib dml; 591 struct dml2_context *dml2; 592 struct dml2_context *dml2_dc_power_source; 593 }; 594 595 struct dc_dmub_cmd { 596 union dmub_rb_cmd dmub_cmd; 597 enum dm_dmub_wait_type wait_type; 598 }; 599 600 /** 601 * struct dc_state - The full description of a state requested by users 602 */ 603 struct dc_state { 604 /** 605 * @streams: Stream state properties 606 */ 607 struct dc_stream_state *streams[MAX_PIPES]; 608 609 /** 610 * @stream_status: Planes status on a given stream 611 */ 612 struct dc_stream_status stream_status[MAX_PIPES]; 613 /** 614 * @phantom_streams: Stream state properties for phantoms 615 */ 616 struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES]; 617 /** 618 * @phantom_planes: Planes state properties for phantoms 619 */ 620 struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES]; 621 622 /** 623 * @stream_count: Total of streams in use 624 */ 625 uint8_t stream_count; 626 uint8_t stream_mask; 627 628 /** 629 * @stream_count: Total phantom streams in use 630 */ 631 uint8_t phantom_stream_count; 632 /** 633 * @stream_count: Total phantom planes in use 634 */ 635 uint8_t phantom_plane_count; 636 /** 637 * @res_ctx: Persistent state of resources 638 */ 639 struct resource_context res_ctx; 640 641 /** 642 * @pp_display_cfg: PowerPlay clocks and settings 643 * Note: this is a big struct, do *not* put on stack! 644 */ 645 struct dm_pp_display_configuration pp_display_cfg; 646 647 /** 648 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 649 * Note: this is a big struct, do *not* put on stack! 650 */ 651 struct dcn_bw_internal_vars dcn_bw_vars; 652 653 struct clk_mgr *clk_mgr; 654 655 /** 656 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 657 * 658 * Each context must have its own instance of VBA, and in order to 659 * initialize and obtain IP and SOC, the base DML instance from DC is 660 * initially copied into every context. 661 */ 662 struct bw_context bw_ctx; 663 664 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE]; 665 unsigned int block_sequence_steps; 666 struct dc_dmub_cmd dc_dmub_cmd[10]; 667 unsigned int dmub_cmd_count; 668 669 /** 670 * @refcount: refcount reference 671 * 672 * Notice that dc_state is used around the code to capture the current 673 * context, so we need to pass it everywhere. That's why we want to use 674 * kref in this struct. 675 */ 676 struct kref refcount; 677 678 struct { 679 unsigned int stutter_period_us; 680 } perf_params; 681 682 enum dc_power_source_type power_source; 683 }; 684 685 struct replay_context { 686 /* ddc line */ 687 enum channel_id aux_inst; 688 /* Transmitter id */ 689 enum transmitter digbe_inst; 690 /* Engine Id is used for Dig Be source select */ 691 enum engine_id digfe_inst; 692 /* Controller Id used for Dig Fe source select */ 693 enum controller_id controllerId; 694 unsigned int line_time_in_ns; 695 bool os_request_force_ffu; 696 }; 697 698 enum dc_replay_enable { 699 DC_REPLAY_DISABLE = 0, 700 DC_REPLAY_ENABLE = 1, 701 }; 702 703 struct dc_bounding_box_max_clk { 704 int max_dcfclk_mhz; 705 int max_dispclk_mhz; 706 int max_dppclk_mhz; 707 int max_phyclk_mhz; 708 }; 709 710 struct memory_qos { 711 uint32_t peak_bw_mbps; 712 uint32_t avg_bw_mbps; 713 uint32_t max_latency_ns; 714 uint32_t min_latency_ns; 715 uint32_t avg_latency_ns; 716 }; 717 718 #endif /* _CORE_TYPES_H_ */ 719