xref: /linux/drivers/gpu/drm/msm/dp/dp_link.h (revision ba23adb6533149df33b9a247f31a87227b3c86d5)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef _DP_LINK_H_
7 #define _DP_LINK_H_
8 
9 #include "dp_aux.h"
10 #include <drm/display/drm_dp_helper.h>
11 
12 #define DS_PORT_STATUS_CHANGED 0x200
13 #define DP_TEST_BIT_DEPTH_UNKNOWN 0xFFFFFFFF
14 #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
15 #define DP_MAX_NUM_DP_LANES    4
16 
17 struct msm_dp_link_info {
18 	unsigned char revision;
19 	unsigned int rate;
20 	unsigned int supported_rates[DP_MAX_SUPPORTED_RATES];
21 	unsigned int rate_set;
22 	bool use_rate_set;
23 	unsigned int num_lanes;
24 	unsigned long capabilities;
25 };
26 
27 #define DP_TRAIN_LEVEL_MAX	3
28 
29 struct msm_dp_link_test_video {
30 	u32 test_video_pattern;
31 	u32 test_bit_depth;
32 	u32 test_dyn_range;
33 	u32 test_h_total;
34 	u32 test_v_total;
35 	u32 test_h_start;
36 	u32 test_v_start;
37 	u32 test_hsync_pol;
38 	u32 test_hsync_width;
39 	u32 test_vsync_pol;
40 	u32 test_vsync_width;
41 	u32 test_h_width;
42 	u32 test_v_height;
43 	u32 test_rr_d;
44 	u32 test_rr_n;
45 };
46 
47 struct msm_dp_link_test_audio {
48 	u32 test_audio_sampling_rate;
49 	u32 test_audio_channel_count;
50 	u32 test_audio_pattern_type;
51 	u32 test_audio_period_ch_1;
52 	u32 test_audio_period_ch_2;
53 	u32 test_audio_period_ch_3;
54 	u32 test_audio_period_ch_4;
55 	u32 test_audio_period_ch_5;
56 	u32 test_audio_period_ch_6;
57 	u32 test_audio_period_ch_7;
58 	u32 test_audio_period_ch_8;
59 };
60 
61 struct msm_dp_link_phy_params {
62 	u32 phy_test_pattern_sel;
63 	u8 v_level;
64 	u8 p_level;
65 };
66 
67 struct msm_dp_link {
68 	u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
69 	int lttpr_count;
70 
71 	u32 sink_request;
72 	u32 test_response;
73 
74 	u8 sink_count;
75 	struct msm_dp_link_test_video test_video;
76 	struct msm_dp_link_test_audio test_audio;
77 	struct msm_dp_link_phy_params phy_params;
78 	struct msm_dp_link_info link_params;
79 
80 	u32 lane_map[DP_MAX_NUM_DP_LANES];
81 	u32 max_dp_lanes;
82 	u32 max_dp_link_rate;
83 };
84 
85 /**
86  * msm_dp_link_bit_depth_to_bpp() - convert test bit depth to bpp
87  * @tbd: test bit depth
88  *
89  * Returns: the bits per pixel (bpp) to be used corresponding to the
90  * bit depth value. This function assumes that bit depth has
91  * already been validated.
92  */
msm_dp_link_bit_depth_to_bpp(u32 tbd)93 static inline u32 msm_dp_link_bit_depth_to_bpp(u32 tbd)
94 {
95 	/*
96 	 * Few simplistic rules and assumptions made here:
97 	 *    1. Bit depth is per color component
98 	 *    2. If bit depth is unknown return 0
99 	 *    3. Assume 3 color components
100 	 */
101 	switch (tbd) {
102 	case DP_TEST_BIT_DEPTH_6:
103 		return 18;
104 	case DP_TEST_BIT_DEPTH_8:
105 		return 24;
106 	case DP_TEST_BIT_DEPTH_10:
107 		return 30;
108 	case DP_TEST_BIT_DEPTH_UNKNOWN:
109 	default:
110 		return 0;
111 	}
112 }
113 
114 void msm_dp_link_reset_phy_params_vx_px(struct msm_dp_link *msm_dp_link);
115 u32 msm_dp_link_get_test_bits_depth(struct msm_dp_link *msm_dp_link, u32 bpp);
116 int msm_dp_link_process_request(struct msm_dp_link *msm_dp_link);
117 int msm_dp_link_get_colorimetry_config(struct msm_dp_link *msm_dp_link);
118 int msm_dp_link_adjust_levels(struct msm_dp_link *msm_dp_link, u8 *link_status);
119 bool msm_dp_link_send_test_response(struct msm_dp_link *msm_dp_link);
120 int msm_dp_link_psm_config(struct msm_dp_link *msm_dp_link,
121 		struct msm_dp_link_info *link_info, bool enable);
122 bool msm_dp_link_send_edid_checksum(struct msm_dp_link *msm_dp_link, u8 checksum);
123 
124 /**
125  * msm_dp_link_get() - get the functionalities of dp test module
126  * @dev: kernel device structure
127  * @aux: DisplayPort AUX channel
128  *
129  * return: a pointer to msm_dp_link struct
130  */
131 struct msm_dp_link *msm_dp_link_get(struct device *dev, struct drm_dp_aux *aux);
132 
133 #endif /* _DP_LINK_H_ */
134