1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * set_id_regs - Test for setting ID register from usersapce.
4 *
5 * Copyright (c) 2023 Google LLC.
6 *
7 *
8 * Test that KVM supports setting ID registers from userspace and handles the
9 * feature set correctly.
10 */
11
12 #include <stdint.h>
13 #include "kvm_util.h"
14 #include "processor.h"
15 #include "test_util.h"
16 #include <linux/bitfield.h>
17
18 bool have_cap_arm_mte;
19
20 enum ftr_type {
21 FTR_EXACT, /* Use a predefined safe value */
22 FTR_LOWER_SAFE, /* Smaller value is safe */
23 FTR_HIGHER_SAFE, /* Bigger value is safe */
24 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
25 FTR_END, /* Mark the last ftr bits */
26 };
27
28 #define FTR_SIGNED true /* Value should be treated as signed */
29 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
30
31 struct reg_ftr_bits {
32 char *name;
33 bool sign;
34 enum ftr_type type;
35 uint8_t shift;
36 uint64_t mask;
37 /*
38 * For FTR_EXACT, safe_val is used as the exact safe value.
39 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value.
40 */
41 int64_t safe_val;
42 };
43
44 struct test_feature_reg {
45 uint32_t reg;
46 const struct reg_ftr_bits *ftr_bits;
47 };
48
49 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \
50 { \
51 .name = #NAME, \
52 .sign = SIGNED, \
53 .type = TYPE, \
54 .shift = SHIFT, \
55 .mask = MASK, \
56 .safe_val = SAFE_VAL, \
57 }
58
59 #define REG_FTR_BITS(type, reg, field, safe_val) \
60 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \
61 reg##_##field##_MASK, safe_val)
62
63 #define S_REG_FTR_BITS(type, reg, field, safe_val) \
64 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \
65 reg##_##field##_MASK, safe_val)
66
67 #define REG_FTR_END \
68 { \
69 .type = FTR_END, \
70 }
71
72 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
73 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0),
74 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0),
75 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
76 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP),
77 REG_FTR_END,
78 };
79
80 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = {
81 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3),
82 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8),
83 REG_FTR_END,
84 };
85
86 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = {
87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0),
88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0),
89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0),
90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0),
91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0),
92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0),
93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0),
94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0),
95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0),
96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0),
97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0),
98 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0),
99 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0),
100 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0),
101 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0),
102 REG_FTR_END,
103 };
104
105 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = {
106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0),
107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0),
108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0),
109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0),
110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0),
111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0),
112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0),
113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0),
114 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0),
115 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0),
116 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0),
117 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0),
118 REG_FTR_END,
119 };
120
121 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = {
122 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0),
123 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0),
124 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0),
125 REG_FTR_END,
126 };
127
128 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = {
129 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0),
130 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0),
131 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0),
132 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0),
133 REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0),
134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 1),
135 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 1),
136 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 1),
137 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 1),
138 REG_FTR_END,
139 };
140
141 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = {
142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, DF2, 0),
143 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0),
144 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI),
145 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0),
146 REG_FTR_END,
147 };
148
149 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = {
150 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0),
151 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0),
152 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN4_2, 1),
153 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN64_2, 1),
154 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN16_2, 1),
155 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0),
156 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0),
157 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0),
158 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0),
159 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0),
160 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0),
161 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
162 REG_FTR_END,
163 };
164
165 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = {
166 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0),
167 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0),
168 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0),
169 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0),
170 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0),
171 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0),
172 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0),
173 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0),
174 REG_FTR_END,
175 };
176
177 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = {
178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0),
179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0),
180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0),
181 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0),
182 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0),
183 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0),
184 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0),
185 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0),
186 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0),
187 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0),
188 REG_FTR_END,
189 };
190
191 static const struct reg_ftr_bits ftr_id_aa64mmfr3_el1[] = {
192 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1POE, 0),
193 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1PIE, 0),
194 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, SCTLRX, 0),
195 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, TCRX, 0),
196 REG_FTR_END,
197 };
198
199 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
200 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
201 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
202 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0),
203 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0),
204 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0),
205 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0),
206 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0),
207 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0),
208 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0),
209 REG_FTR_END,
210 };
211
212 #define TEST_REG(id, table) \
213 { \
214 .reg = id, \
215 .ftr_bits = &((table)[0]), \
216 }
217
218 static struct test_feature_reg test_regs[] = {
219 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1),
220 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1),
221 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1),
222 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1),
223 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1),
224 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1),
225 TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1),
226 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1),
227 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
228 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
229 TEST_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3_el1),
230 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
231 };
232
233 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0);
234
guest_code(void)235 static void guest_code(void)
236 {
237 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1);
238 GUEST_REG_SYNC(SYS_ID_DFR0_EL1);
239 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1);
240 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1);
241 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1);
242 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1);
243 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
244 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
245 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
246 GUEST_REG_SYNC(SYS_ID_AA64MMFR3_EL1);
247 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
248 GUEST_REG_SYNC(SYS_CTR_EL0);
249 GUEST_REG_SYNC(SYS_MIDR_EL1);
250 GUEST_REG_SYNC(SYS_REVIDR_EL1);
251 GUEST_REG_SYNC(SYS_AIDR_EL1);
252
253 GUEST_DONE();
254 }
255
256 /* Return a safe value to a given ftr_bits an ftr value */
get_safe_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)257 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
258 {
259 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
260
261 if (ftr_bits->sign == FTR_UNSIGNED) {
262 switch (ftr_bits->type) {
263 case FTR_EXACT:
264 ftr = ftr_bits->safe_val;
265 break;
266 case FTR_LOWER_SAFE:
267 if (ftr > ftr_bits->safe_val)
268 ftr--;
269 break;
270 case FTR_HIGHER_SAFE:
271 if (ftr < ftr_max)
272 ftr++;
273 break;
274 case FTR_HIGHER_OR_ZERO_SAFE:
275 if (ftr == ftr_max)
276 ftr = 0;
277 else if (ftr != 0)
278 ftr++;
279 break;
280 default:
281 break;
282 }
283 } else if (ftr != ftr_max) {
284 switch (ftr_bits->type) {
285 case FTR_EXACT:
286 ftr = ftr_bits->safe_val;
287 break;
288 case FTR_LOWER_SAFE:
289 if (ftr > ftr_bits->safe_val)
290 ftr--;
291 break;
292 case FTR_HIGHER_SAFE:
293 if (ftr < ftr_max - 1)
294 ftr++;
295 break;
296 case FTR_HIGHER_OR_ZERO_SAFE:
297 if (ftr != 0 && ftr != ftr_max - 1)
298 ftr++;
299 break;
300 default:
301 break;
302 }
303 }
304
305 return ftr;
306 }
307
308 /* Return an invalid value to a given ftr_bits an ftr value */
get_invalid_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)309 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
310 {
311 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
312
313 if (ftr_bits->sign == FTR_UNSIGNED) {
314 switch (ftr_bits->type) {
315 case FTR_EXACT:
316 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
317 break;
318 case FTR_LOWER_SAFE:
319 ftr++;
320 break;
321 case FTR_HIGHER_SAFE:
322 ftr--;
323 break;
324 case FTR_HIGHER_OR_ZERO_SAFE:
325 if (ftr == 0)
326 ftr = ftr_max;
327 else
328 ftr--;
329 break;
330 default:
331 break;
332 }
333 } else if (ftr != ftr_max) {
334 switch (ftr_bits->type) {
335 case FTR_EXACT:
336 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
337 break;
338 case FTR_LOWER_SAFE:
339 ftr++;
340 break;
341 case FTR_HIGHER_SAFE:
342 ftr--;
343 break;
344 case FTR_HIGHER_OR_ZERO_SAFE:
345 if (ftr == 0)
346 ftr = ftr_max - 1;
347 else
348 ftr--;
349 break;
350 default:
351 break;
352 }
353 } else {
354 ftr = 0;
355 }
356
357 return ftr;
358 }
359
test_reg_set_success(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)360 static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
361 const struct reg_ftr_bits *ftr_bits)
362 {
363 uint8_t shift = ftr_bits->shift;
364 uint64_t mask = ftr_bits->mask;
365 uint64_t val, new_val, ftr;
366
367 val = vcpu_get_reg(vcpu, reg);
368 ftr = (val & mask) >> shift;
369
370 ftr = get_safe_value(ftr_bits, ftr);
371
372 ftr <<= shift;
373 val &= ~mask;
374 val |= ftr;
375
376 vcpu_set_reg(vcpu, reg, val);
377 new_val = vcpu_get_reg(vcpu, reg);
378 TEST_ASSERT_EQ(new_val, val);
379
380 return new_val;
381 }
382
test_reg_set_fail(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)383 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
384 const struct reg_ftr_bits *ftr_bits)
385 {
386 uint8_t shift = ftr_bits->shift;
387 uint64_t mask = ftr_bits->mask;
388 uint64_t val, old_val, ftr;
389 int r;
390
391 val = vcpu_get_reg(vcpu, reg);
392 ftr = (val & mask) >> shift;
393
394 ftr = get_invalid_value(ftr_bits, ftr);
395
396 old_val = val;
397 ftr <<= shift;
398 val &= ~mask;
399 val |= ftr;
400
401 r = __vcpu_set_reg(vcpu, reg, val);
402 TEST_ASSERT(r < 0 && errno == EINVAL,
403 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
404
405 val = vcpu_get_reg(vcpu, reg);
406 TEST_ASSERT_EQ(val, old_val);
407 }
408
409 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE];
410
411 #define encoding_to_range_idx(encoding) \
412 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \
413 sys_reg_CRn(encoding), sys_reg_CRm(encoding), \
414 sys_reg_Op2(encoding))
415
416
test_vm_ftr_id_regs(struct kvm_vcpu * vcpu,bool aarch64_only)417 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only)
418 {
419 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
420 struct reg_mask_range range = {
421 .addr = (__u64)masks,
422 };
423 int ret;
424
425 /* KVM should return error when reserved field is not zero */
426 range.reserved[0] = 1;
427 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
428 TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
429
430 /* Get writable masks for feature ID registers */
431 memset(range.reserved, 0, sizeof(range.reserved));
432 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
433
434 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) {
435 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits;
436 uint32_t reg_id = test_regs[i].reg;
437 uint64_t reg = KVM_ARM64_SYS_REG(reg_id);
438 int idx;
439
440 /* Get the index to masks array for the idreg */
441 idx = encoding_to_range_idx(reg_id);
442
443 for (int j = 0; ftr_bits[j].type != FTR_END; j++) {
444 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */
445 if (aarch64_only && sys_reg_CRm(reg_id) < 4) {
446 ksft_test_result_skip("%s on AARCH64 only system\n",
447 ftr_bits[j].name);
448 continue;
449 }
450
451 /* Make sure the feature field is writable */
452 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask);
453
454 test_reg_set_fail(vcpu, reg, &ftr_bits[j]);
455
456 test_reg_vals[idx] = test_reg_set_success(vcpu, reg,
457 &ftr_bits[j]);
458
459 ksft_test_result_pass("%s\n", ftr_bits[j].name);
460 }
461 }
462 }
463
464 #define MPAM_IDREG_TEST 6
test_user_set_mpam_reg(struct kvm_vcpu * vcpu)465 static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu)
466 {
467 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
468 struct reg_mask_range range = {
469 .addr = (__u64)masks,
470 };
471 uint64_t val;
472 int idx, err;
473
474 /*
475 * If ID_AA64PFR0.MPAM is _not_ officially modifiable and is zero,
476 * check that if it can be set to 1, (i.e. it is supported by the
477 * hardware), that it can't be set to other values.
478 */
479
480 /* Get writable masks for feature ID registers */
481 memset(range.reserved, 0, sizeof(range.reserved));
482 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
483
484 /* Writeable? Nothing to test! */
485 idx = encoding_to_range_idx(SYS_ID_AA64PFR0_EL1);
486 if ((masks[idx] & ID_AA64PFR0_EL1_MPAM_MASK) == ID_AA64PFR0_EL1_MPAM_MASK) {
487 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is officially writable, nothing to test\n");
488 return;
489 }
490
491 /* Get the id register value */
492 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
493
494 /* Try to set MPAM=0. This should always be possible. */
495 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
496 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 0);
497 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
498 if (err)
499 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM=0 was not accepted\n");
500 else
501 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=0 worked\n");
502
503 /* Try to set MPAM=1 */
504 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
505 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 1);
506 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
507 if (err)
508 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is not writable, nothing to test\n");
509 else
510 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=1 was writable\n");
511
512 /* Try to set MPAM=2 */
513 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
514 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 2);
515 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
516 if (err)
517 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM not arbitrarily modifiable\n");
518 else
519 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM value should not be ignored\n");
520
521 /* And again for ID_AA64PFR1_EL1.MPAM_frac */
522 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1);
523 if ((masks[idx] & ID_AA64PFR1_EL1_MPAM_frac_MASK) == ID_AA64PFR1_EL1_MPAM_frac_MASK) {
524 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is officially writable, nothing to test\n");
525 return;
526 }
527
528 /* Get the id register value */
529 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
530
531 /* Try to set MPAM_frac=0. This should always be possible. */
532 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
533 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 0);
534 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
535 if (err)
536 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM_frac=0 was not accepted\n");
537 else
538 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=0 worked\n");
539
540 /* Try to set MPAM_frac=1 */
541 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
542 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 1);
543 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
544 if (err)
545 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is not writable, nothing to test\n");
546 else
547 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=1 was writable\n");
548
549 /* Try to set MPAM_frac=2 */
550 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
551 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 2);
552 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
553 if (err)
554 ksft_test_result_pass("ID_AA64PFR1_EL1.MPAM_frac not arbitrarily modifiable\n");
555 else
556 ksft_test_result_fail("ID_AA64PFR1_EL1.MPAM_frac value should not be ignored\n");
557 }
558
559 #define MTE_IDREG_TEST 1
test_user_set_mte_reg(struct kvm_vcpu * vcpu)560 static void test_user_set_mte_reg(struct kvm_vcpu *vcpu)
561 {
562 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
563 struct reg_mask_range range = {
564 .addr = (__u64)masks,
565 };
566 uint64_t val;
567 uint64_t mte;
568 uint64_t mte_frac;
569 int idx, err;
570
571 if (!have_cap_arm_mte) {
572 ksft_test_result_skip("MTE capability not supported, nothing to test\n");
573 return;
574 }
575
576 /* Get writable masks for feature ID registers */
577 memset(range.reserved, 0, sizeof(range.reserved));
578 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
579
580 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1);
581 if ((masks[idx] & ID_AA64PFR1_EL1_MTE_frac_MASK) == ID_AA64PFR1_EL1_MTE_frac_MASK) {
582 ksft_test_result_skip("ID_AA64PFR1_EL1.MTE_frac is officially writable, nothing to test\n");
583 return;
584 }
585
586 /*
587 * When MTE is supported but MTE_ASYMM is not (ID_AA64PFR1_EL1.MTE == 2)
588 * ID_AA64PFR1_EL1.MTE_frac == 0xF indicates MTE_ASYNC is unsupported
589 * and MTE_frac == 0 indicates it is supported.
590 *
591 * As MTE_frac was previously unconditionally read as 0, check
592 * that the set to 0 succeeds but does not change MTE_frac
593 * from unsupported (0xF) to supported (0).
594 *
595 */
596 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
597
598 mte = FIELD_GET(ID_AA64PFR1_EL1_MTE, val);
599 mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val);
600 if (mte != ID_AA64PFR1_EL1_MTE_MTE2 ||
601 mte_frac != ID_AA64PFR1_EL1_MTE_frac_NI) {
602 ksft_test_result_skip("MTE_ASYNC or MTE_ASYMM are supported, nothing to test\n");
603 return;
604 }
605
606 /* Try to set MTE_frac=0. */
607 val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK;
608 val |= FIELD_PREP(ID_AA64PFR1_EL1_MTE_frac_MASK, 0);
609 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
610 if (err) {
611 ksft_test_result_fail("ID_AA64PFR1_EL1.MTE_frac=0 was not accepted\n");
612 return;
613 }
614
615 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
616 mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val);
617 if (mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI)
618 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac=0 accepted and still 0xF\n");
619 else
620 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac no longer 0xF\n");
621 }
622
test_guest_reg_read(struct kvm_vcpu * vcpu)623 static void test_guest_reg_read(struct kvm_vcpu *vcpu)
624 {
625 bool done = false;
626 struct ucall uc;
627
628 while (!done) {
629 vcpu_run(vcpu);
630
631 switch (get_ucall(vcpu, &uc)) {
632 case UCALL_ABORT:
633 REPORT_GUEST_ASSERT(uc);
634 break;
635 case UCALL_SYNC:
636 /* Make sure the written values are seen by guest */
637 TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])],
638 uc.args[3]);
639 break;
640 case UCALL_DONE:
641 done = true;
642 break;
643 default:
644 TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
645 }
646 }
647 }
648
649 /* Politely lifted from arch/arm64/include/asm/cache.h */
650 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
651 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
652 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
653 #define CLIDR_CTYPE(clidr, level) \
654 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
655
test_clidr(struct kvm_vcpu * vcpu)656 static void test_clidr(struct kvm_vcpu *vcpu)
657 {
658 uint64_t clidr;
659 int level;
660
661 clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1));
662
663 /* find the first empty level in the cache hierarchy */
664 for (level = 1; level < 7; level++) {
665 if (!CLIDR_CTYPE(clidr, level))
666 break;
667 }
668
669 /*
670 * If you have a mind-boggling 7 levels of cache, congratulations, you
671 * get to fix this.
672 */
673 TEST_ASSERT(level <= 7, "can't find an empty level in cache hierarchy");
674
675 /* stick in a unified cache level */
676 clidr |= BIT(2) << CLIDR_CTYPE_SHIFT(level);
677
678 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), clidr);
679 test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] = clidr;
680 }
681
test_ctr(struct kvm_vcpu * vcpu)682 static void test_ctr(struct kvm_vcpu *vcpu)
683 {
684 u64 ctr;
685
686 ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0));
687 ctr &= ~CTR_EL0_DIC_MASK;
688 if (ctr & CTR_EL0_IminLine_MASK)
689 ctr--;
690
691 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr);
692 test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] = ctr;
693 }
694
test_id_reg(struct kvm_vcpu * vcpu,u32 id)695 static void test_id_reg(struct kvm_vcpu *vcpu, u32 id)
696 {
697 u64 val;
698
699 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(id));
700 val++;
701 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(id), val);
702 test_reg_vals[encoding_to_range_idx(id)] = val;
703 }
704
test_vcpu_ftr_id_regs(struct kvm_vcpu * vcpu)705 static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu)
706 {
707 test_clidr(vcpu);
708 test_ctr(vcpu);
709
710 test_id_reg(vcpu, SYS_MPIDR_EL1);
711 ksft_test_result_pass("%s\n", __func__);
712 }
713
test_vcpu_non_ftr_id_regs(struct kvm_vcpu * vcpu)714 static void test_vcpu_non_ftr_id_regs(struct kvm_vcpu *vcpu)
715 {
716 test_id_reg(vcpu, SYS_MIDR_EL1);
717 test_id_reg(vcpu, SYS_REVIDR_EL1);
718 test_id_reg(vcpu, SYS_AIDR_EL1);
719
720 ksft_test_result_pass("%s\n", __func__);
721 }
722
test_assert_id_reg_unchanged(struct kvm_vcpu * vcpu,uint32_t encoding)723 static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding)
724 {
725 size_t idx = encoding_to_range_idx(encoding);
726 uint64_t observed;
727
728 observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding));
729 TEST_ASSERT_EQ(test_reg_vals[idx], observed);
730 }
731
test_reset_preserves_id_regs(struct kvm_vcpu * vcpu)732 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu)
733 {
734 /*
735 * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an
736 * architectural reset of the vCPU.
737 */
738 aarch64_vcpu_setup(vcpu, NULL);
739
740 for (int i = 0; i < ARRAY_SIZE(test_regs); i++)
741 test_assert_id_reg_unchanged(vcpu, test_regs[i].reg);
742
743 test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1);
744 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1);
745 test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0);
746 test_assert_id_reg_unchanged(vcpu, SYS_MIDR_EL1);
747 test_assert_id_reg_unchanged(vcpu, SYS_REVIDR_EL1);
748 test_assert_id_reg_unchanged(vcpu, SYS_AIDR_EL1);
749
750 ksft_test_result_pass("%s\n", __func__);
751 }
752
kvm_arch_vm_post_create(struct kvm_vm * vm)753 void kvm_arch_vm_post_create(struct kvm_vm *vm)
754 {
755 if (vm_check_cap(vm, KVM_CAP_ARM_MTE)) {
756 vm_enable_cap(vm, KVM_CAP_ARM_MTE, 0);
757 have_cap_arm_mte = true;
758 }
759 }
760
main(void)761 int main(void)
762 {
763 struct kvm_vcpu *vcpu;
764 struct kvm_vm *vm;
765 bool aarch64_only;
766 uint64_t val, el0;
767 int test_cnt;
768
769 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES));
770 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_WRITABLE_IMP_ID_REGS));
771
772 vm = vm_create(1);
773 vm_enable_cap(vm, KVM_CAP_ARM_WRITABLE_IMP_ID_REGS, 0);
774 vcpu = vm_vcpu_add(vm, 0, guest_code);
775
776 /* Check for AARCH64 only system */
777 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
778 el0 = FIELD_GET(ID_AA64PFR0_EL1_EL0, val);
779 aarch64_only = (el0 == ID_AA64PFR0_EL1_EL0_IMP);
780
781 ksft_print_header();
782
783 test_cnt = ARRAY_SIZE(ftr_id_aa64dfr0_el1) + ARRAY_SIZE(ftr_id_dfr0_el1) +
784 ARRAY_SIZE(ftr_id_aa64isar0_el1) + ARRAY_SIZE(ftr_id_aa64isar1_el1) +
785 ARRAY_SIZE(ftr_id_aa64isar2_el1) + ARRAY_SIZE(ftr_id_aa64pfr0_el1) +
786 ARRAY_SIZE(ftr_id_aa64pfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr0_el1) +
787 ARRAY_SIZE(ftr_id_aa64mmfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr2_el1) +
788 ARRAY_SIZE(ftr_id_aa64mmfr3_el1) + ARRAY_SIZE(ftr_id_aa64zfr0_el1) -
789 ARRAY_SIZE(test_regs) + 3 + MPAM_IDREG_TEST + MTE_IDREG_TEST;
790
791 ksft_set_plan(test_cnt);
792
793 test_vm_ftr_id_regs(vcpu, aarch64_only);
794 test_vcpu_ftr_id_regs(vcpu);
795 test_vcpu_non_ftr_id_regs(vcpu);
796 test_user_set_mpam_reg(vcpu);
797 test_user_set_mte_reg(vcpu);
798
799 test_guest_reg_read(vcpu);
800
801 test_reset_preserves_id_regs(vcpu);
802
803 kvm_vm_free(vm);
804
805 ksft_finished();
806 }
807