1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * arch/arm/mach-tegra/gpio.c
4 *
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author:
9 * Erik Gilling <konkers@google.com>
10 */
11
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/irq.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/module.h>
21 #include <linux/irqdomain.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pm.h>
25 #include <linux/property.h>
26 #include <linux/seq_file.h>
27
28 #define GPIO_BANK(x) ((x) >> 5)
29 #define GPIO_PORT(x) (((x) >> 3) & 0x3)
30 #define GPIO_BIT(x) ((x) & 0x7)
31
32 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
33 GPIO_PORT(x) * 4)
34
35 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
36 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
37 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
38 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
39 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
40 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
41 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
42 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
43 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
44
45
46 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
47 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
48 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
49 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
50 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
51 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
52 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
53
54 #define GPIO_INT_LVL_MASK 0x010101
55 #define GPIO_INT_LVL_EDGE_RISING 0x000101
56 #define GPIO_INT_LVL_EDGE_FALLING 0x000100
57 #define GPIO_INT_LVL_EDGE_BOTH 0x010100
58 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
59 #define GPIO_INT_LVL_LEVEL_LOW 0x000000
60
61 struct tegra_gpio_info;
62
63 struct tegra_gpio_bank {
64 unsigned int bank;
65
66 /*
67 * IRQ-core code uses raw locking, and thus, nested locking also
68 * should be raw in order not to trip spinlock debug warnings.
69 */
70 raw_spinlock_t lvl_lock[4];
71
72 /* Lock for updating debounce count register */
73 spinlock_t dbc_lock[4];
74
75 #ifdef CONFIG_PM_SLEEP
76 u32 cnf[4];
77 u32 out[4];
78 u32 oe[4];
79 u32 int_enb[4];
80 u32 int_lvl[4];
81 u32 wake_enb[4];
82 u32 dbc_enb[4];
83 #endif
84 u32 dbc_cnt[4];
85 };
86
87 struct tegra_gpio_soc_config {
88 bool debounce_supported;
89 u32 bank_stride;
90 u32 upper_offset;
91 };
92
93 struct tegra_gpio_info {
94 struct device *dev;
95 void __iomem *regs;
96 struct tegra_gpio_bank *bank_info;
97 const struct tegra_gpio_soc_config *soc;
98 struct gpio_chip gc;
99 u32 bank_count;
100 unsigned int *irqs;
101 };
102
tegra_gpio_writel(struct tegra_gpio_info * tgi,u32 val,u32 reg)103 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
104 u32 val, u32 reg)
105 {
106 writel_relaxed(val, tgi->regs + reg);
107 }
108
tegra_gpio_readl(struct tegra_gpio_info * tgi,u32 reg)109 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
110 {
111 return readl_relaxed(tgi->regs + reg);
112 }
113
tegra_gpio_compose(unsigned int bank,unsigned int port,unsigned int bit)114 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
115 unsigned int bit)
116 {
117 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
118 }
119
tegra_gpio_mask_write(struct tegra_gpio_info * tgi,u32 reg,unsigned int gpio,u32 value)120 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
121 unsigned int gpio, u32 value)
122 {
123 u32 val;
124
125 val = 0x100 << GPIO_BIT(gpio);
126 if (value)
127 val |= 1 << GPIO_BIT(gpio);
128 tegra_gpio_writel(tgi, val, reg);
129 }
130
tegra_gpio_enable(struct tegra_gpio_info * tgi,unsigned int gpio)131 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
132 {
133 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
134 }
135
tegra_gpio_disable(struct tegra_gpio_info * tgi,unsigned int gpio)136 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
137 {
138 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
139 }
140
tegra_gpio_free(struct gpio_chip * chip,unsigned int offset)141 static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
142 {
143 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
144
145 pinctrl_gpio_free(chip, offset);
146 tegra_gpio_disable(tgi, offset);
147 }
148
tegra_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)149 static int tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
150 int value)
151 {
152 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
153
154 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
155
156 return 0;
157 }
158
tegra_gpio_get(struct gpio_chip * chip,unsigned int offset)159 static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
160 {
161 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
162 unsigned int bval = BIT(GPIO_BIT(offset));
163
164 /* If gpio is in output mode then read from the out value */
165 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
166 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
167
168 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
169 }
170
tegra_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)171 static int tegra_gpio_direction_input(struct gpio_chip *chip,
172 unsigned int offset)
173 {
174 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
175 int ret;
176
177 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
178 tegra_gpio_enable(tgi, offset);
179
180 ret = pinctrl_gpio_direction_input(chip, offset);
181 if (ret < 0)
182 dev_err(tgi->dev,
183 "Failed to set pinctrl input direction of GPIO %d: %d",
184 chip->base + offset, ret);
185
186 return ret;
187 }
188
tegra_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)189 static int tegra_gpio_direction_output(struct gpio_chip *chip,
190 unsigned int offset,
191 int value)
192 {
193 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
194 int ret;
195
196 tegra_gpio_set(chip, offset, value);
197 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
198 tegra_gpio_enable(tgi, offset);
199
200 ret = pinctrl_gpio_direction_output(chip, offset);
201 if (ret < 0)
202 dev_err(tgi->dev,
203 "Failed to set pinctrl output direction of GPIO %d: %d",
204 chip->base + offset, ret);
205
206 return ret;
207 }
208
tegra_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)209 static int tegra_gpio_get_direction(struct gpio_chip *chip,
210 unsigned int offset)
211 {
212 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
213 u32 pin_mask = BIT(GPIO_BIT(offset));
214 u32 cnf, oe;
215
216 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
217 if (!(cnf & pin_mask))
218 return -EINVAL;
219
220 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
221
222 if (oe & pin_mask)
223 return GPIO_LINE_DIRECTION_OUT;
224
225 return GPIO_LINE_DIRECTION_IN;
226 }
227
tegra_gpio_set_debounce(struct gpio_chip * chip,unsigned int offset,unsigned int debounce)228 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
229 unsigned int debounce)
230 {
231 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
232 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
233 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
234 unsigned long flags;
235 unsigned int port;
236
237 if (!debounce_ms) {
238 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
239 offset, 0);
240 return 0;
241 }
242
243 debounce_ms = min(debounce_ms, 255U);
244 port = GPIO_PORT(offset);
245
246 /* There is only one debounce count register per port and hence
247 * set the maximum of current and requested debounce time.
248 */
249 spin_lock_irqsave(&bank->dbc_lock[port], flags);
250 if (bank->dbc_cnt[port] < debounce_ms) {
251 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
252 bank->dbc_cnt[port] = debounce_ms;
253 }
254 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
255
256 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
257
258 return 0;
259 }
260
tegra_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)261 static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
262 unsigned long config)
263 {
264 u32 debounce;
265
266 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
267 return -ENOTSUPP;
268
269 debounce = pinconf_to_config_argument(config);
270 return tegra_gpio_set_debounce(chip, offset, debounce);
271 }
272
tegra_gpio_irq_ack(struct irq_data * d)273 static void tegra_gpio_irq_ack(struct irq_data *d)
274 {
275 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
276 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
277 unsigned int gpio = d->hwirq;
278
279 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
280 }
281
tegra_gpio_irq_mask(struct irq_data * d)282 static void tegra_gpio_irq_mask(struct irq_data *d)
283 {
284 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
285 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
286 unsigned int gpio = d->hwirq;
287
288 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
289 gpiochip_disable_irq(chip, gpio);
290 }
291
tegra_gpio_irq_unmask(struct irq_data * d)292 static void tegra_gpio_irq_unmask(struct irq_data *d)
293 {
294 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
295 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
296 unsigned int gpio = d->hwirq;
297
298 gpiochip_enable_irq(chip, gpio);
299 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
300 }
301
tegra_gpio_irq_set_type(struct irq_data * d,unsigned int type)302 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
303 {
304 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
305 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
306 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
307 struct tegra_gpio_bank *bank;
308 unsigned long flags;
309 int ret;
310 u32 val;
311
312 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
313
314 switch (type & IRQ_TYPE_SENSE_MASK) {
315 case IRQ_TYPE_EDGE_RISING:
316 lvl_type = GPIO_INT_LVL_EDGE_RISING;
317 break;
318
319 case IRQ_TYPE_EDGE_FALLING:
320 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
321 break;
322
323 case IRQ_TYPE_EDGE_BOTH:
324 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
325 break;
326
327 case IRQ_TYPE_LEVEL_HIGH:
328 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
329 break;
330
331 case IRQ_TYPE_LEVEL_LOW:
332 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
333 break;
334
335 default:
336 return -EINVAL;
337 }
338
339 raw_spin_lock_irqsave(&bank->lvl_lock[port], flags);
340
341 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
342 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
343 val |= lvl_type << GPIO_BIT(gpio);
344 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
345
346 raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
347
348 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
349 tegra_gpio_enable(tgi, gpio);
350
351 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
352 if (ret) {
353 dev_err(tgi->dev,
354 "unable to lock Tegra GPIO %u as IRQ\n", gpio);
355 tegra_gpio_disable(tgi, gpio);
356 return ret;
357 }
358
359 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
360 irq_set_handler_locked(d, handle_level_irq);
361 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
362 irq_set_handler_locked(d, handle_edge_irq);
363
364 if (d->parent_data)
365 ret = irq_chip_set_type_parent(d, type);
366
367 return ret;
368 }
369
tegra_gpio_irq_shutdown(struct irq_data * d)370 static void tegra_gpio_irq_shutdown(struct irq_data *d)
371 {
372 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
373 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
374 unsigned int gpio = d->hwirq;
375
376 tegra_gpio_irq_mask(d);
377 gpiochip_unlock_as_irq(&tgi->gc, gpio);
378 }
379
tegra_gpio_irq_handler(struct irq_desc * desc)380 static void tegra_gpio_irq_handler(struct irq_desc *desc)
381 {
382 struct tegra_gpio_info *tgi = irq_desc_get_handler_data(desc);
383 struct irq_chip *chip = irq_desc_get_chip(desc);
384 struct irq_domain *domain = tgi->gc.irq.domain;
385 unsigned int irq = irq_desc_get_irq(desc);
386 struct tegra_gpio_bank *bank = NULL;
387 unsigned int port, pin, gpio, i;
388 bool unmasked = false;
389 unsigned long sta;
390 u32 lvl;
391
392 for (i = 0; i < tgi->bank_count; i++) {
393 if (tgi->irqs[i] == irq) {
394 bank = &tgi->bank_info[i];
395 break;
396 }
397 }
398
399 if (WARN_ON(bank == NULL))
400 return;
401
402 chained_irq_enter(chip, desc);
403
404 for (port = 0; port < 4; port++) {
405 gpio = tegra_gpio_compose(bank->bank, port, 0);
406 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
407 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
408 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
409
410 for_each_set_bit(pin, &sta, 8) {
411 int ret;
412
413 tegra_gpio_writel(tgi, 1 << pin,
414 GPIO_INT_CLR(tgi, gpio));
415
416 /* if gpio is edge triggered, clear condition
417 * before executing the handler so that we don't
418 * miss edges
419 */
420 if (!unmasked && lvl & (0x100 << pin)) {
421 unmasked = true;
422 chained_irq_exit(chip, desc);
423 }
424
425 ret = generic_handle_domain_irq(domain, gpio + pin);
426 WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
427 }
428 }
429
430 if (!unmasked)
431 chained_irq_exit(chip, desc);
432 }
433
tegra_gpio_child_to_parent_hwirq(struct gpio_chip * chip,unsigned int hwirq,unsigned int type,unsigned int * parent_hwirq,unsigned int * parent_type)434 static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
435 unsigned int hwirq,
436 unsigned int type,
437 unsigned int *parent_hwirq,
438 unsigned int *parent_type)
439 {
440 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
441 *parent_type = type;
442
443 return 0;
444 }
445
tegra_gpio_populate_parent_fwspec(struct gpio_chip * chip,union gpio_irq_fwspec * gfwspec,unsigned int parent_hwirq,unsigned int parent_type)446 static int tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip,
447 union gpio_irq_fwspec *gfwspec,
448 unsigned int parent_hwirq,
449 unsigned int parent_type)
450 {
451 struct irq_fwspec *fwspec = &gfwspec->fwspec;
452
453 fwspec->fwnode = chip->irq.parent_domain->fwnode;
454 fwspec->param_count = 3;
455 fwspec->param[0] = 0;
456 fwspec->param[1] = parent_hwirq;
457 fwspec->param[2] = parent_type;
458
459 return 0;
460 }
461
462 #ifdef CONFIG_PM_SLEEP
tegra_gpio_resume(struct device * dev)463 static int tegra_gpio_resume(struct device *dev)
464 {
465 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
466 unsigned int b, p;
467
468 for (b = 0; b < tgi->bank_count; b++) {
469 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
470
471 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
472 unsigned int gpio = (b << 5) | (p << 3);
473
474 tegra_gpio_writel(tgi, bank->cnf[p],
475 GPIO_CNF(tgi, gpio));
476
477 if (tgi->soc->debounce_supported) {
478 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
479 GPIO_DBC_CNT(tgi, gpio));
480 tegra_gpio_writel(tgi, bank->dbc_enb[p],
481 GPIO_MSK_DBC_EN(tgi, gpio));
482 }
483
484 tegra_gpio_writel(tgi, bank->out[p],
485 GPIO_OUT(tgi, gpio));
486 tegra_gpio_writel(tgi, bank->oe[p],
487 GPIO_OE(tgi, gpio));
488 tegra_gpio_writel(tgi, bank->int_lvl[p],
489 GPIO_INT_LVL(tgi, gpio));
490 tegra_gpio_writel(tgi, bank->int_enb[p],
491 GPIO_INT_ENB(tgi, gpio));
492 }
493 }
494
495 return 0;
496 }
497
tegra_gpio_suspend(struct device * dev)498 static int tegra_gpio_suspend(struct device *dev)
499 {
500 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
501 unsigned int b, p;
502
503 for (b = 0; b < tgi->bank_count; b++) {
504 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
505
506 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
507 unsigned int gpio = (b << 5) | (p << 3);
508
509 bank->cnf[p] = tegra_gpio_readl(tgi,
510 GPIO_CNF(tgi, gpio));
511 bank->out[p] = tegra_gpio_readl(tgi,
512 GPIO_OUT(tgi, gpio));
513 bank->oe[p] = tegra_gpio_readl(tgi,
514 GPIO_OE(tgi, gpio));
515 if (tgi->soc->debounce_supported) {
516 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
517 GPIO_MSK_DBC_EN(tgi, gpio));
518 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
519 bank->dbc_enb[p];
520 }
521
522 bank->int_enb[p] = tegra_gpio_readl(tgi,
523 GPIO_INT_ENB(tgi, gpio));
524 bank->int_lvl[p] = tegra_gpio_readl(tgi,
525 GPIO_INT_LVL(tgi, gpio));
526
527 /* Enable gpio irq for wake up source */
528 tegra_gpio_writel(tgi, bank->wake_enb[p],
529 GPIO_INT_ENB(tgi, gpio));
530 }
531 }
532
533 return 0;
534 }
535
tegra_gpio_irq_set_wake(struct irq_data * d,unsigned int enable)536 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
537 {
538 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
539 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
540 struct tegra_gpio_bank *bank;
541 unsigned int gpio = d->hwirq;
542 u32 port, bit, mask;
543 int err;
544
545 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
546
547 port = GPIO_PORT(gpio);
548 bit = GPIO_BIT(gpio);
549 mask = BIT(bit);
550
551 err = irq_set_irq_wake(tgi->irqs[bank->bank], enable);
552 if (err)
553 return err;
554
555 if (d->parent_data) {
556 err = irq_chip_set_wake_parent(d, enable);
557 if (err) {
558 irq_set_irq_wake(tgi->irqs[bank->bank], !enable);
559 return err;
560 }
561 }
562
563 if (enable)
564 bank->wake_enb[port] |= mask;
565 else
566 bank->wake_enb[port] &= ~mask;
567
568 return 0;
569 }
570 #endif
571
tegra_gpio_irq_set_affinity(struct irq_data * data,const struct cpumask * dest,bool force)572 static int tegra_gpio_irq_set_affinity(struct irq_data *data,
573 const struct cpumask *dest,
574 bool force)
575 {
576 if (data->parent_data)
577 return irq_chip_set_affinity_parent(data, dest, force);
578
579 return -EINVAL;
580 }
581
tegra_gpio_irq_request_resources(struct irq_data * d)582 static int tegra_gpio_irq_request_resources(struct irq_data *d)
583 {
584 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
585 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
586
587 tegra_gpio_enable(tgi, d->hwirq);
588
589 return gpiochip_reqres_irq(chip, d->hwirq);
590 }
591
tegra_gpio_irq_release_resources(struct irq_data * d)592 static void tegra_gpio_irq_release_resources(struct irq_data *d)
593 {
594 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
595 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
596
597 gpiochip_relres_irq(chip, d->hwirq);
598 tegra_gpio_enable(tgi, d->hwirq);
599 }
600
tegra_gpio_irq_print_chip(struct irq_data * d,struct seq_file * s)601 static void tegra_gpio_irq_print_chip(struct irq_data *d, struct seq_file *s)
602 {
603 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
604
605 seq_puts(s, dev_name(chip->parent));
606 }
607
608 static const struct irq_chip tegra_gpio_irq_chip = {
609 .irq_shutdown = tegra_gpio_irq_shutdown,
610 .irq_ack = tegra_gpio_irq_ack,
611 .irq_mask = tegra_gpio_irq_mask,
612 .irq_unmask = tegra_gpio_irq_unmask,
613 .irq_set_type = tegra_gpio_irq_set_type,
614 #ifdef CONFIG_PM_SLEEP
615 .irq_set_wake = tegra_gpio_irq_set_wake,
616 #endif
617 .irq_print_chip = tegra_gpio_irq_print_chip,
618 .irq_request_resources = tegra_gpio_irq_request_resources,
619 .irq_release_resources = tegra_gpio_irq_release_resources,
620 .flags = IRQCHIP_IMMUTABLE,
621 };
622
623 static const struct irq_chip tegra210_gpio_irq_chip = {
624 .irq_shutdown = tegra_gpio_irq_shutdown,
625 .irq_ack = tegra_gpio_irq_ack,
626 .irq_mask = tegra_gpio_irq_mask,
627 .irq_unmask = tegra_gpio_irq_unmask,
628 .irq_set_affinity = tegra_gpio_irq_set_affinity,
629 .irq_set_type = tegra_gpio_irq_set_type,
630 #ifdef CONFIG_PM_SLEEP
631 .irq_set_wake = tegra_gpio_irq_set_wake,
632 #endif
633 .irq_print_chip = tegra_gpio_irq_print_chip,
634 .irq_request_resources = tegra_gpio_irq_request_resources,
635 .irq_release_resources = tegra_gpio_irq_release_resources,
636 .flags = IRQCHIP_IMMUTABLE,
637 };
638
639 #ifdef CONFIG_DEBUG_FS
640
641 #include <linux/debugfs.h>
642
tegra_dbg_gpio_show(struct seq_file * s,void * unused)643 static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
644 {
645 struct tegra_gpio_info *tgi = dev_get_drvdata(s->private);
646 unsigned int i, j;
647
648 for (i = 0; i < tgi->bank_count; i++) {
649 for (j = 0; j < 4; j++) {
650 unsigned int gpio = tegra_gpio_compose(i, j, 0);
651
652 seq_printf(s,
653 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
654 i, j,
655 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
656 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
657 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
658 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
659 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
660 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
661 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
662 }
663 }
664 return 0;
665 }
666
tegra_gpio_debuginit(struct tegra_gpio_info * tgi)667 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
668 {
669 debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL,
670 tegra_dbg_gpio_show);
671 }
672
673 #else
674
tegra_gpio_debuginit(struct tegra_gpio_info * tgi)675 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
676 {
677 }
678
679 #endif
680
681 static const struct dev_pm_ops tegra_gpio_pm_ops = {
682 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
683 };
684
685 static const struct of_device_id tegra_pmc_of_match[] = {
686 { .compatible = "nvidia,tegra210-pmc", },
687 { /* sentinel */ },
688 };
689
tegra_gpio_probe(struct platform_device * pdev)690 static int tegra_gpio_probe(struct platform_device *pdev)
691 {
692 struct tegra_gpio_bank *bank;
693 struct tegra_gpio_info *tgi;
694 struct gpio_irq_chip *irq;
695 struct device_node *np;
696 unsigned int i, j;
697 int ret;
698
699 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
700 if (!tgi)
701 return -ENODEV;
702
703 tgi->soc = of_device_get_match_data(&pdev->dev);
704 tgi->dev = &pdev->dev;
705
706 ret = platform_irq_count(pdev);
707 if (ret < 0)
708 return ret;
709
710 tgi->bank_count = ret;
711
712 if (!tgi->bank_count) {
713 dev_err(&pdev->dev, "Missing IRQ resource\n");
714 return -ENODEV;
715 }
716
717 tgi->gc.label = "tegra-gpio";
718 tgi->gc.request = pinctrl_gpio_request;
719 tgi->gc.free = tegra_gpio_free;
720 tgi->gc.direction_input = tegra_gpio_direction_input;
721 tgi->gc.get = tegra_gpio_get;
722 tgi->gc.direction_output = tegra_gpio_direction_output;
723 tgi->gc.set_rv = tegra_gpio_set;
724 tgi->gc.get_direction = tegra_gpio_get_direction;
725 tgi->gc.base = 0;
726 tgi->gc.ngpio = tgi->bank_count * 32;
727 tgi->gc.parent = &pdev->dev;
728
729 platform_set_drvdata(pdev, tgi);
730
731 if (tgi->soc->debounce_supported)
732 tgi->gc.set_config = tegra_gpio_set_config;
733
734 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
735 sizeof(*tgi->bank_info), GFP_KERNEL);
736 if (!tgi->bank_info)
737 return -ENOMEM;
738
739 tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count,
740 sizeof(*tgi->irqs), GFP_KERNEL);
741 if (!tgi->irqs)
742 return -ENOMEM;
743
744 for (i = 0; i < tgi->bank_count; i++) {
745 ret = platform_get_irq(pdev, i);
746 if (ret < 0)
747 return ret;
748
749 bank = &tgi->bank_info[i];
750 bank->bank = i;
751
752 tgi->irqs[i] = ret;
753
754 for (j = 0; j < 4; j++) {
755 raw_spin_lock_init(&bank->lvl_lock[j]);
756 spin_lock_init(&bank->dbc_lock[j]);
757 }
758 }
759
760 irq = &tgi->gc.irq;
761 irq->fwnode = dev_fwnode(&pdev->dev);
762 irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq;
763 irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec;
764 irq->handler = handle_simple_irq;
765 irq->default_type = IRQ_TYPE_NONE;
766 irq->parent_handler = tegra_gpio_irq_handler;
767 irq->parent_handler_data = tgi;
768 irq->num_parents = tgi->bank_count;
769 irq->parents = tgi->irqs;
770
771 np = of_find_matching_node(NULL, tegra_pmc_of_match);
772 if (np) {
773 irq->parent_domain = irq_find_host(np);
774 of_node_put(np);
775
776 if (!irq->parent_domain)
777 return -EPROBE_DEFER;
778
779 gpio_irq_chip_set_chip(irq, &tegra210_gpio_irq_chip);
780 } else {
781 gpio_irq_chip_set_chip(irq, &tegra_gpio_irq_chip);
782 }
783
784 tgi->regs = devm_platform_ioremap_resource(pdev, 0);
785 if (IS_ERR(tgi->regs))
786 return PTR_ERR(tgi->regs);
787
788 for (i = 0; i < tgi->bank_count; i++) {
789 for (j = 0; j < 4; j++) {
790 int gpio = tegra_gpio_compose(i, j, 0);
791
792 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
793 }
794 }
795
796 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
797 if (ret < 0)
798 return ret;
799
800 tegra_gpio_debuginit(tgi);
801
802 return 0;
803 }
804
805 static const struct tegra_gpio_soc_config tegra20_gpio_config = {
806 .bank_stride = 0x80,
807 .upper_offset = 0x800,
808 };
809
810 static const struct tegra_gpio_soc_config tegra30_gpio_config = {
811 .bank_stride = 0x100,
812 .upper_offset = 0x80,
813 };
814
815 static const struct tegra_gpio_soc_config tegra210_gpio_config = {
816 .debounce_supported = true,
817 .bank_stride = 0x100,
818 .upper_offset = 0x80,
819 };
820
821 static const struct of_device_id tegra_gpio_of_match[] = {
822 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
823 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
824 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
825 { },
826 };
827 MODULE_DEVICE_TABLE(of, tegra_gpio_of_match);
828
829 static struct platform_driver tegra_gpio_driver = {
830 .driver = {
831 .name = "tegra-gpio",
832 .pm = &tegra_gpio_pm_ops,
833 .of_match_table = tegra_gpio_of_match,
834 },
835 .probe = tegra_gpio_probe,
836 };
837 module_platform_driver(tegra_gpio_driver);
838
839 MODULE_DESCRIPTION("NVIDIA Tegra GPIO controller driver");
840 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
841 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
842 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
843 MODULE_AUTHOR("Erik Gilling <konkers@google.com>");
844 MODULE_LICENSE("GPL v2");
845