1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * drivers/i2c/busses/i2c-tegra.c
4 *
5 * Copyright (C) 2010 Google, Inc.
6 * Author: Colin Cross <ccross@android.com>
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/irq.h>
22 #include <linux/kernel.h>
23 #include <linux/ktime.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/reset.h>
30
31 #define BYTES_PER_FIFO_WORD 4
32
33 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12)
34 #define I2C_CNFG_PACKET_MODE_EN BIT(10)
35 #define I2C_CNFG_NEW_MASTER_FSM BIT(11)
36 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
37
38 #define I2C_SL_CNFG_NACK BIT(1)
39 #define I2C_SL_CNFG_NEWSL BIT(2)
40
41 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
42 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
43 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
44 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
45
46 #define I2C_FIFO_STATUS_TX GENMASK(7, 4)
47 #define I2C_FIFO_STATUS_RX GENMASK(3, 0)
48
49 #define I2C_INT_BUS_CLR_DONE BIT(11)
50 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
51 #define I2C_INT_NO_ACK BIT(3)
52 #define I2C_INT_ARBITRATION_LOST BIT(2)
53 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
54 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
55
56 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16)
57 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0)
58
59 #define DVC_CTRL_REG1 0x000
60 #define DVC_CTRL_REG1_INTR_EN BIT(10)
61 #define DVC_CTRL_REG3 0x008
62 #define DVC_CTRL_REG3_SW_PROG BIT(26)
63 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
64 #define DVC_STATUS 0x00c
65 #define DVC_STATUS_I2C_DONE_INTR BIT(30)
66
67 #define I2C_ERR_NONE 0x00
68 #define I2C_ERR_NO_ACK BIT(0)
69 #define I2C_ERR_ARBITRATION_LOST BIT(1)
70 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2)
71 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3)
72
73 #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28)
74 #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16)
75 #define PACKET_HEADER0_CONT_ID GENMASK(15, 12)
76 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4)
77 #define PACKET_HEADER0_PROTOCOL_I2C 1
78
79 #define I2C_HEADER_HS_MODE BIT(22)
80 #define I2C_HEADER_CONT_ON_NAK BIT(21)
81 #define I2C_HEADER_READ BIT(19)
82 #define I2C_HEADER_10BIT_ADDR BIT(18)
83 #define I2C_HEADER_IE_ENABLE BIT(17)
84 #define I2C_HEADER_REPEAT_START BIT(16)
85 #define I2C_HEADER_CONTINUE_XFER BIT(15)
86 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
87
88 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16)
89 #define I2C_BC_STOP_COND BIT(2)
90 #define I2C_BC_TERMINATE BIT(1)
91 #define I2C_BC_ENABLE BIT(0)
92
93 #define I2C_BC_STATUS BIT(0)
94
95 #define I2C_MSTR_CONFIG_LOAD BIT(0)
96
97 #define I2C_MST_CORE_CLKEN_OVR BIT(0)
98
99 #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8)
100 #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0)
101 #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24)
102 #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
103 #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
104 #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
105
106 #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8)
107 #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0)
108 #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
109 #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
110 #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
111
112 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0)
113 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1)
114 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
115 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
116
117 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16)
118 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0)
119
120 #define I2C_SW_MUTEX_REQUEST GENMASK(3, 0)
121 #define I2C_SW_MUTEX_GRANT GENMASK(7, 4)
122 #define I2C_SW_MUTEX_ID_CCPLEX 9
123
124 /* SW mutex acquire timeout value in microseconds. */
125 #define I2C_SW_MUTEX_TIMEOUT_US (25 * USEC_PER_MSEC)
126
127 /* configuration load timeout in microseconds */
128 #define I2C_CONFIG_LOAD_TIMEOUT 1000000
129
130 /* packet header size in bytes */
131 #define I2C_PACKET_HEADER_SIZE 12
132
133 /*
134 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
135 * avoid DMA overhead, otherwise external APB DMA controller will be used.
136 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include
137 * I2C_PACKET_HEADER_SIZE.
138 */
139 #define I2C_PIO_MODE_PREFERRED_LEN 32
140
141 struct tegra_i2c_regs {
142 unsigned int cnfg;
143 unsigned int status;
144 unsigned int sl_cnfg;
145 unsigned int sl_addr1;
146 unsigned int sl_addr2;
147 unsigned int tlow_sext;
148 unsigned int tx_fifo;
149 unsigned int rx_fifo;
150 unsigned int packet_transfer_status;
151 unsigned int fifo_control;
152 unsigned int fifo_status;
153 unsigned int int_mask;
154 unsigned int int_status;
155 unsigned int clk_divisor;
156 unsigned int bus_clear_cnfg;
157 unsigned int bus_clear_status;
158 unsigned int config_load;
159 unsigned int clken_override;
160 unsigned int interface_timing_0;
161 unsigned int interface_timing_1;
162 unsigned int hs_interface_timing_0;
163 unsigned int hs_interface_timing_1;
164 unsigned int master_reset_cntrl;
165 unsigned int mst_fifo_control;
166 unsigned int mst_fifo_status;
167 unsigned int sw_mutex;
168 };
169
170 static const struct tegra_i2c_regs tegra20_i2c_regs = {
171 .cnfg = 0x000,
172 .status = 0x01c,
173 .sl_cnfg = 0x020,
174 .sl_addr1 = 0x02c,
175 .sl_addr2 = 0x030,
176 .tx_fifo = 0x050,
177 .rx_fifo = 0x054,
178 .packet_transfer_status = 0x058,
179 .fifo_control = 0x05c,
180 .fifo_status = 0x060,
181 .int_mask = 0x064,
182 .int_status = 0x068,
183 .clk_divisor = 0x06c,
184 .bus_clear_cnfg = 0x084,
185 .bus_clear_status = 0x088,
186 .config_load = 0x08c,
187 .clken_override = 0x090,
188 .interface_timing_0 = 0x094,
189 .interface_timing_1 = 0x098,
190 .hs_interface_timing_0 = 0x09c,
191 .hs_interface_timing_1 = 0x0a0,
192 .master_reset_cntrl = 0x0a8,
193 .mst_fifo_control = 0x0b4,
194 .mst_fifo_status = 0x0b8,
195 };
196
197 #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
198 static const struct tegra_i2c_regs tegra20_dvc_i2c_regs = {
199 .cnfg = 0x040,
200 .status = 0x05c,
201 .tx_fifo = 0x060,
202 .rx_fifo = 0x064,
203 .packet_transfer_status = 0x068,
204 .fifo_control = 0x06c,
205 .fifo_status = 0x070,
206 .int_mask = 0x074,
207 .int_status = 0x078,
208 .clk_divisor = 0x07c,
209 .bus_clear_cnfg = 0x094,
210 .bus_clear_status = 0x098,
211 .config_load = 0x09c,
212 .clken_override = 0x0a0,
213 .interface_timing_0 = 0x0a4,
214 .interface_timing_1 = 0x0a8,
215 .hs_interface_timing_0 = 0x0ac,
216 .hs_interface_timing_1 = 0x0b0,
217 .master_reset_cntrl = 0x0b8,
218 .mst_fifo_control = 0x0c4,
219 .mst_fifo_status = 0x0c8,
220 };
221 #endif
222
223 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
224 static const struct tegra_i2c_regs tegra210_vi_i2c_regs = {
225 .cnfg = 0x0c00,
226 .status = 0x0c70,
227 .tlow_sext = 0x0cd0,
228 .tx_fifo = 0x0d40,
229 .rx_fifo = 0x0d50,
230 .packet_transfer_status = 0x0d60,
231 .fifo_control = 0x0d70,
232 .fifo_status = 0x0d80,
233 .int_mask = 0x0d90,
234 .int_status = 0x0da0,
235 .clk_divisor = 0x0db0,
236 .bus_clear_cnfg = 0x0e10,
237 .bus_clear_status = 0x0e20,
238 .config_load = 0x0e30,
239 .clken_override = 0x0e40,
240 .interface_timing_0 = 0x0e50,
241 .interface_timing_1 = 0x0e60,
242 .hs_interface_timing_0 = 0x0e70,
243 .hs_interface_timing_1 = 0x0e80,
244 .master_reset_cntrl = 0x0ea0,
245 .mst_fifo_control = 0x0ed0,
246 .mst_fifo_status = 0x0ee0,
247 };
248 #endif
249
250 static const struct tegra_i2c_regs tegra264_i2c_regs = {
251 .cnfg = 0x000,
252 .status = 0x01c,
253 .sl_cnfg = 0x020,
254 .sl_addr1 = 0x02c,
255 .sl_addr2 = 0x030,
256 .tx_fifo = 0x050,
257 .rx_fifo = 0x054,
258 .packet_transfer_status = 0x058,
259 .fifo_control = 0x05c,
260 .fifo_status = 0x060,
261 .int_mask = 0x064,
262 .int_status = 0x068,
263 .clk_divisor = 0x06c,
264 .bus_clear_cnfg = 0x084,
265 .bus_clear_status = 0x088,
266 .config_load = 0x08c,
267 .clken_override = 0x090,
268 .interface_timing_0 = 0x094,
269 .interface_timing_1 = 0x098,
270 .hs_interface_timing_0 = 0x09c,
271 .hs_interface_timing_1 = 0x0a0,
272 .master_reset_cntrl = 0x0a8,
273 .mst_fifo_control = 0x0b4,
274 .mst_fifo_status = 0x0b8,
275 .sw_mutex = 0x0ec,
276 };
277
278 static const struct tegra_i2c_regs tegra410_i2c_regs = {
279 .cnfg = 0x000,
280 .status = 0x01c,
281 .sl_cnfg = 0x020,
282 .sl_addr1 = 0x02c,
283 .sl_addr2 = 0x030,
284 .tx_fifo = 0x054,
285 .rx_fifo = 0x058,
286 .packet_transfer_status = 0x05c,
287 .fifo_control = 0x060,
288 .fifo_status = 0x064,
289 .int_mask = 0x068,
290 .int_status = 0x06c,
291 .clk_divisor = 0x070,
292 .bus_clear_cnfg = 0x088,
293 .bus_clear_status = 0x08c,
294 .config_load = 0x090,
295 .clken_override = 0x094,
296 .interface_timing_0 = 0x098,
297 .interface_timing_1 = 0x09c,
298 .hs_interface_timing_0 = 0x0a0,
299 .hs_interface_timing_1 = 0x0a4,
300 .master_reset_cntrl = 0x0ac,
301 .mst_fifo_control = 0x0b8,
302 .mst_fifo_status = 0x0bc,
303 .sw_mutex = 0x0f0,
304 };
305
306 /*
307 * msg_end_type: The bus control which needs to be sent at end of transfer.
308 * @MSG_END_STOP: Send stop pulse.
309 * @MSG_END_REPEAT_START: Send repeat-start.
310 * @MSG_END_CONTINUE: Don't send stop or repeat-start.
311 */
312 enum msg_end_type {
313 MSG_END_STOP,
314 MSG_END_REPEAT_START,
315 MSG_END_CONTINUE,
316 };
317
318 /*
319 * tegra_i2c_variant: Identifies the variant of I2C controller.
320 * @TEGRA_I2C_VARIANT_DEFAULT: Identifies the default I2C controller.
321 * @TEGRA_I2C_VARIANT_DVC: Identifies the DVC I2C controller, has a different register layout.
322 * @TEGRA_I2C_VARIANT_VI: Identifies the VI I2C controller, has a different register layout.
323 */
324 enum tegra_i2c_variant {
325 TEGRA_I2C_VARIANT_DEFAULT,
326 TEGRA_I2C_VARIANT_DVC,
327 TEGRA_I2C_VARIANT_VI,
328 };
329
330 /**
331 * struct tegra_i2c_hw_feature : per hardware generation features
332 * @has_continue_xfer_support: continue-transfer supported
333 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
334 * completion interrupt on per packet basis.
335 * @has_config_load_reg: Has the config load register to load the new
336 * configuration.
337 * @clk_divisor_hs_mode: Clock divisor in HS mode.
338 * @clk_divisor_std_mode: Clock divisor in standard mode. It is
339 * applicable if there is no fast clock source i.e. single clock
340 * source.
341 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
342 * applicable if there is no fast clock source i.e. single clock
343 * source.
344 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
345 * applicable if there is no fast clock source (i.e. single
346 * clock source).
347 * @has_multi_master_mode: The I2C controller supports running in single-master
348 * or multi-master mode.
349 * @has_slcg_override_reg: The I2C controller supports a register that
350 * overrides the second level clock gating.
351 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
352 * provides additional features and allows for longer messages to
353 * be transferred in one go.
354 * @has_mst_reset: The I2C controller contains MASTER_RESET_CTRL register which
355 * provides an alternative to controller reset when configured as
356 * I2C master
357 * @quirks: I2C adapter quirks for limiting write/read transfer size and not
358 * allowing 0 length transfers.
359 * @supports_bus_clear: Bus Clear support to recover from bus hang during
360 * SDA stuck low from device for some unknown reasons.
361 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
362 * @tlow_std_mode: Low period of the clock in standard mode.
363 * @thigh_std_mode: High period of the clock in standard mode.
364 * @tlow_fast_mode: Low period of the clock in fast mode.
365 * @thigh_fast_mode: High period of the clock in fast mode.
366 * @tlow_fastplus_mode: Low period of the clock in fast-plus mode.
367 * @thigh_fastplus_mode: High period of the clock in fast-plus mode.
368 * @tlow_hs_mode: Low period of the clock in HS mode.
369 * @thigh_hs_mode: High period of the clock in HS mode.
370 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
371 * in standard mode.
372 * @setup_hold_time_fast_mode: Setup and hold time for start and stop
373 * conditions in fast mode.
374 * @setup_hold_time_fastplus_mode: Setup and hold time for start and stop
375 * conditions in fast-plus mode.
376 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
377 * in HS mode.
378 * @has_interface_timing_reg: Has interface timing register to program the tuned
379 * timing settings.
380 * @enable_hs_mode_support: Enable support for high speed (HS) mode transfers.
381 * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs.
382 * @variant: This represents the I2C controller variant.
383 * @regs: Register offsets for the specific SoC variant.
384 */
385 struct tegra_i2c_hw_feature {
386 bool has_continue_xfer_support;
387 bool has_per_pkt_xfer_complete_irq;
388 bool has_config_load_reg;
389 u32 clk_divisor_hs_mode;
390 u32 clk_divisor_std_mode;
391 u32 clk_divisor_fast_mode;
392 u32 clk_divisor_fast_plus_mode;
393 bool has_multi_master_mode;
394 bool has_slcg_override_reg;
395 bool has_mst_fifo;
396 bool has_mst_reset;
397 const struct i2c_adapter_quirks *quirks;
398 bool supports_bus_clear;
399 bool has_apb_dma;
400 u32 tlow_std_mode;
401 u32 thigh_std_mode;
402 u32 tlow_fast_mode;
403 u32 thigh_fast_mode;
404 u32 tlow_fastplus_mode;
405 u32 thigh_fastplus_mode;
406 u32 tlow_hs_mode;
407 u32 thigh_hs_mode;
408 u32 setup_hold_time_std_mode;
409 u32 setup_hold_time_fast_mode;
410 u32 setup_hold_time_fastplus_mode;
411 u32 setup_hold_time_hs_mode;
412 bool has_interface_timing_reg;
413 bool enable_hs_mode_support;
414 bool has_mutex;
415 enum tegra_i2c_variant variant;
416 const struct tegra_i2c_regs *regs;
417 };
418
419 /**
420 * struct tegra_i2c_dev - per device I2C context
421 * @dev: device reference for power management
422 * @hw: Tegra I2C HW feature
423 * @adapter: core I2C layer adapter information
424 * @div_clk: clock reference for div clock of I2C controller
425 * @clocks: array of I2C controller clocks
426 * @nclocks: number of clocks in the array
427 * @base: ioremapped registers cookie
428 * @base_phys: physical base address of the I2C controller
429 * @cont_id: I2C controller ID, used for packet header
430 * @irq: IRQ number of transfer complete interrupt
431 * @msg_complete: transfer completion notifier
432 * @msg_buf_remaining: size of unsent data in the message buffer
433 * @msg_len: length of message in current transfer
434 * @msg_err: error code for completed message
435 * @msg_buf: pointer to current message data
436 * @msg_read: indicates that the transfer is a read access
437 * @timings: i2c timings information like bus frequency
438 * @multimaster_mode: indicates that I2C controller is in multi-master mode
439 * @dma_chan: DMA channel
440 * @dma_phys: handle to DMA resources
441 * @dma_buf: pointer to allocated DMA buffer
442 * @dma_buf_size: DMA buffer size
443 * @dma_dev: DMA device used for transfers
444 * @dma_mode: indicates active DMA transfer
445 * @dma_complete: DMA completion notifier
446 * @atomic_mode: indicates active atomic transfer
447 */
448 struct tegra_i2c_dev {
449 struct device *dev;
450 struct i2c_adapter adapter;
451
452 const struct tegra_i2c_hw_feature *hw;
453 unsigned int cont_id;
454 unsigned int irq;
455
456 phys_addr_t base_phys;
457 void __iomem *base;
458
459 struct clk_bulk_data clocks[2];
460 unsigned int nclocks;
461
462 struct clk *div_clk;
463 struct i2c_timings timings;
464
465 struct completion msg_complete;
466 size_t msg_buf_remaining;
467 unsigned int msg_len;
468 int msg_err;
469 u8 *msg_buf;
470
471 struct completion dma_complete;
472 struct dma_chan *dma_chan;
473 unsigned int dma_buf_size;
474 struct device *dma_dev;
475 dma_addr_t dma_phys;
476 void *dma_buf;
477
478 bool multimaster_mode;
479 bool atomic_mode;
480 bool dma_mode;
481 bool msg_read;
482 };
483
484 #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \
485 (dev)->hw->variant == TEGRA_I2C_VARIANT_DVC)
486 #define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \
487 (dev)->hw->variant == TEGRA_I2C_VARIANT_VI)
488
dvc_writel(struct tegra_i2c_dev * i2c_dev,u32 val,unsigned int reg)489 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
490 unsigned int reg)
491 {
492 writel_relaxed(val, i2c_dev->base + reg);
493 }
494
dvc_readl(struct tegra_i2c_dev * i2c_dev,unsigned int reg)495 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
496 {
497 return readl_relaxed(i2c_dev->base + reg);
498 }
499
i2c_writel(struct tegra_i2c_dev * i2c_dev,u32 val,unsigned int reg)500 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg)
501 {
502 writel_relaxed(val, i2c_dev->base + reg);
503
504 /* read back register to make sure that register writes completed */
505 if (reg != i2c_dev->hw->regs->tx_fifo)
506 readl_relaxed(i2c_dev->base + reg);
507 else if (IS_VI(i2c_dev))
508 readl_relaxed(i2c_dev->base + i2c_dev->hw->regs->int_status);
509 }
510
i2c_readl(struct tegra_i2c_dev * i2c_dev,unsigned int reg)511 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
512 {
513 return readl_relaxed(i2c_dev->base + reg);
514 }
515
i2c_writesl(struct tegra_i2c_dev * i2c_dev,void * data,unsigned int reg,unsigned int len)516 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
517 unsigned int reg, unsigned int len)
518 {
519 writesl(i2c_dev->base + reg, data, len);
520 }
521
i2c_writesl_vi(struct tegra_i2c_dev * i2c_dev,void * data,unsigned int reg,unsigned int len)522 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data,
523 unsigned int reg, unsigned int len)
524 {
525 u32 *data32 = data;
526
527 /*
528 * VI I2C controller has known hardware bug where writes get stuck
529 * when immediate multiple writes happen to TX_FIFO register.
530 * Recommended software work around is to read I2C register after
531 * each write to TX_FIFO register to flush out the data.
532 */
533 while (len--)
534 i2c_writel(i2c_dev, *data32++, reg);
535 }
536
i2c_readsl(struct tegra_i2c_dev * i2c_dev,void * data,unsigned int reg,unsigned int len)537 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
538 unsigned int reg, unsigned int len)
539 {
540 readsl(i2c_dev->base + reg, data, len);
541 }
542
tegra_i2c_mutex_acquired(struct tegra_i2c_dev * i2c_dev)543 static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev)
544 {
545 unsigned int reg = i2c_dev->hw->regs->sw_mutex;
546 u32 val, id;
547
548 val = readl(i2c_dev->base + reg);
549 id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
550
551 return id == I2C_SW_MUTEX_ID_CCPLEX;
552 }
553
tegra_i2c_mutex_trylock(struct tegra_i2c_dev * i2c_dev)554 static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev)
555 {
556 unsigned int reg = i2c_dev->hw->regs->sw_mutex;
557 u32 val, id;
558
559 val = readl(i2c_dev->base + reg);
560 id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
561 if (id != 0 && id != I2C_SW_MUTEX_ID_CCPLEX)
562 return false;
563
564 val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID_CCPLEX);
565 writel(val, i2c_dev->base + reg);
566
567 return tegra_i2c_mutex_acquired(i2c_dev);
568 }
569
tegra_i2c_mutex_lock(struct tegra_i2c_dev * i2c_dev)570 static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev)
571 {
572 bool locked;
573 int ret;
574
575 if (!i2c_dev->hw->has_mutex)
576 return 0;
577
578 if (i2c_dev->atomic_mode)
579 ret = read_poll_timeout_atomic(tegra_i2c_mutex_trylock, locked, locked,
580 USEC_PER_MSEC, I2C_SW_MUTEX_TIMEOUT_US,
581 false, i2c_dev);
582 else
583 ret = read_poll_timeout(tegra_i2c_mutex_trylock, locked, locked, USEC_PER_MSEC,
584 I2C_SW_MUTEX_TIMEOUT_US, false, i2c_dev);
585
586 if (ret)
587 dev_warn(i2c_dev->dev, "failed to acquire mutex\n");
588
589 return ret;
590 }
591
tegra_i2c_mutex_unlock(struct tegra_i2c_dev * i2c_dev)592 static void tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev)
593 {
594 unsigned int reg = i2c_dev->hw->regs->sw_mutex;
595 u32 val, id;
596
597 if (!i2c_dev->hw->has_mutex)
598 return;
599
600 val = readl(i2c_dev->base + reg);
601
602 id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
603 if (WARN(id && id != I2C_SW_MUTEX_ID_CCPLEX,
604 "unable to unlock mutex, mutex is owned by: %u\n", id))
605 return;
606
607 writel(0, i2c_dev->base + reg);
608 }
609
tegra_i2c_mask_irq(struct tegra_i2c_dev * i2c_dev,u32 mask)610 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
611 {
612 u32 int_mask;
613
614 int_mask = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask) & ~mask;
615 i2c_writel(i2c_dev, int_mask, i2c_dev->hw->regs->int_mask);
616 }
617
tegra_i2c_unmask_irq(struct tegra_i2c_dev * i2c_dev,u32 mask)618 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
619 {
620 u32 int_mask;
621
622 int_mask = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask) | mask;
623 i2c_writel(i2c_dev, int_mask, i2c_dev->hw->regs->int_mask);
624 }
625
tegra_i2c_dma_complete(void * args)626 static void tegra_i2c_dma_complete(void *args)
627 {
628 struct tegra_i2c_dev *i2c_dev = args;
629
630 complete(&i2c_dev->dma_complete);
631 }
632
tegra_i2c_dma_submit(struct tegra_i2c_dev * i2c_dev,size_t len)633 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
634 {
635 struct dma_async_tx_descriptor *dma_desc;
636 enum dma_transfer_direction dir;
637
638 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
639
640 reinit_completion(&i2c_dev->dma_complete);
641
642 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
643
644 dma_desc = dmaengine_prep_slave_single(i2c_dev->dma_chan, i2c_dev->dma_phys,
645 len, dir, DMA_PREP_INTERRUPT |
646 DMA_CTRL_ACK);
647 if (!dma_desc) {
648 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n",
649 i2c_dev->msg_read ? "RX" : "TX");
650 return -EINVAL;
651 }
652
653 dma_desc->callback = tegra_i2c_dma_complete;
654 dma_desc->callback_param = i2c_dev;
655
656 dmaengine_submit(dma_desc);
657 dma_async_issue_pending(i2c_dev->dma_chan);
658
659 return 0;
660 }
661
tegra_i2c_release_dma(struct tegra_i2c_dev * i2c_dev)662 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
663 {
664 if (i2c_dev->dma_buf) {
665 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
666 i2c_dev->dma_buf, i2c_dev->dma_phys);
667 i2c_dev->dma_buf = NULL;
668 }
669
670 if (i2c_dev->dma_chan) {
671 dma_release_channel(i2c_dev->dma_chan);
672 i2c_dev->dma_chan = NULL;
673 }
674 }
675
tegra_i2c_init_dma(struct tegra_i2c_dev * i2c_dev)676 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
677 {
678 dma_addr_t dma_phys;
679 u32 *dma_buf;
680 int err;
681
682 if (IS_VI(i2c_dev))
683 return 0;
684
685 if (!of_property_present(i2c_dev->dev->of_node, "dmas")) {
686 dev_dbg(i2c_dev->dev, "DMA not available, falling back to PIO\n");
687 return 0;
688 }
689
690 if (i2c_dev->hw->has_apb_dma) {
691 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
692 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n");
693 return 0;
694 }
695 } else if (!IS_ENABLED(CONFIG_TEGRA186_GPC_DMA)) {
696 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n");
697 return 0;
698 }
699
700 /*
701 * The same channel will be used for both RX and TX.
702 * Keeping the name as "tx" for backward compatibility
703 * with existing devicetrees.
704 */
705 i2c_dev->dma_chan = dma_request_chan(i2c_dev->dev, "tx");
706 if (IS_ERR(i2c_dev->dma_chan)) {
707 err = PTR_ERR(i2c_dev->dma_chan);
708 i2c_dev->dma_chan = NULL;
709 goto err_out;
710 }
711
712 i2c_dev->dma_dev = i2c_dev->dma_chan->device->dev;
713 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +
714 I2C_PACKET_HEADER_SIZE;
715
716 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
717 &dma_phys, GFP_KERNEL | __GFP_NOWARN);
718 if (!dma_buf) {
719 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n");
720 err = -ENOMEM;
721 goto err_out;
722 }
723
724 i2c_dev->dma_buf = dma_buf;
725 i2c_dev->dma_phys = dma_phys;
726
727 return 0;
728
729 err_out:
730 tegra_i2c_release_dma(i2c_dev);
731 if (err != -EPROBE_DEFER) {
732 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
733 dev_err(i2c_dev->dev, "falling back to PIO\n");
734 return 0;
735 }
736
737 return err;
738 }
739
740 /*
741 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
742 * block. This block is identical to the rest of the I2C blocks, except that
743 * it only supports master mode, it has registers moved around, and it needs
744 * some extra init to get it into I2C mode. The register moves are handled
745 * by i2c_readl() and i2c_writel().
746 */
tegra_dvc_init(struct tegra_i2c_dev * i2c_dev)747 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
748 {
749 u32 val;
750
751 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
752 val |= DVC_CTRL_REG3_SW_PROG;
753 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
754 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
755
756 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
757 val |= DVC_CTRL_REG1_INTR_EN;
758 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
759 }
760
tegra_i2c_vi_init(struct tegra_i2c_dev * i2c_dev)761 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
762 {
763 u32 value;
764
765 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
766 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
767 i2c_writel(i2c_dev, value, i2c_dev->hw->regs->interface_timing_0);
768
769 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
770 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
771 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
772 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
773 i2c_writel(i2c_dev, value, i2c_dev->hw->regs->interface_timing_1);
774
775 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
776 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
777 i2c_writel(i2c_dev, value, i2c_dev->hw->regs->hs_interface_timing_0);
778
779 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
780 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
781 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
782 i2c_writel(i2c_dev, value, i2c_dev->hw->regs->hs_interface_timing_1);
783
784 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
785 i2c_writel(i2c_dev, value, i2c_dev->hw->regs->bus_clear_cnfg);
786
787 i2c_writel(i2c_dev, 0x0, i2c_dev->hw->regs->tlow_sext);
788 }
789
tegra_i2c_poll_register(struct tegra_i2c_dev * i2c_dev,u32 reg,u32 mask,u32 delay_us,u32 timeout_us)790 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
791 u32 reg, u32 mask, u32 delay_us,
792 u32 timeout_us)
793 {
794 void __iomem *addr = i2c_dev->base + reg;
795 u32 val;
796
797 if (!i2c_dev->atomic_mode)
798 return readl_relaxed_poll_timeout(addr, val, !(val & mask),
799 delay_us, timeout_us);
800
801 return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask),
802 delay_us, timeout_us);
803 }
804
tegra_i2c_flush_fifos(struct tegra_i2c_dev * i2c_dev)805 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
806 {
807 u32 mask, val, offset;
808 int err;
809
810 if (i2c_dev->hw->has_mst_fifo) {
811 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
812 I2C_MST_FIFO_CONTROL_RX_FLUSH;
813 offset = i2c_dev->hw->regs->mst_fifo_control;
814 } else {
815 mask = I2C_FIFO_CONTROL_TX_FLUSH |
816 I2C_FIFO_CONTROL_RX_FLUSH;
817 offset = i2c_dev->hw->regs->fifo_control;
818 }
819
820 val = i2c_readl(i2c_dev, offset);
821 val |= mask;
822 i2c_writel(i2c_dev, val, offset);
823
824 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000);
825 if (err) {
826 dev_err(i2c_dev->dev, "failed to flush FIFO\n");
827 return err;
828 }
829
830 return 0;
831 }
832
tegra_i2c_wait_for_config_load(struct tegra_i2c_dev * i2c_dev)833 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
834 {
835 int err;
836
837 if (!i2c_dev->hw->has_config_load_reg)
838 return 0;
839
840 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, i2c_dev->hw->regs->config_load);
841
842 err = tegra_i2c_poll_register(i2c_dev, i2c_dev->hw->regs->config_load, 0xffffffff,
843 1000, I2C_CONFIG_LOAD_TIMEOUT);
844 if (err) {
845 dev_err(i2c_dev->dev, "failed to load config\n");
846 return err;
847 }
848
849 return 0;
850 }
851
tegra_i2c_master_reset(struct tegra_i2c_dev * i2c_dev)852 static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev)
853 {
854 if (!i2c_dev->hw->has_mst_reset)
855 return -EOPNOTSUPP;
856
857 /*
858 * Writing 1 to I2C_MASTER_RESET_CNTRL will reset all internal state of
859 * Master logic including FIFOs. Clear this bit to 0 for normal operation.
860 * SW needs to wait for 2us after assertion and de-assertion of this soft
861 * reset.
862 */
863 i2c_writel(i2c_dev, 0x1, i2c_dev->hw->regs->master_reset_cntrl);
864 fsleep(2);
865
866 i2c_writel(i2c_dev, 0x0, i2c_dev->hw->regs->master_reset_cntrl);
867 fsleep(2);
868
869 return 0;
870 }
871
tegra_i2c_init(struct tegra_i2c_dev * i2c_dev)872 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
873 {
874 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
875 u32 max_bus_freq_hz;
876 struct i2c_timings *t = &i2c_dev->timings;
877 int err;
878
879 /*
880 * Reset the controller before initializing it.
881 * In case if device_reset() returns -ENOENT, i.e. when the reset is
882 * not available, the internal software reset will be used if it is
883 * supported by the controller.
884 */
885 err = device_reset(i2c_dev->dev);
886 if (err == -ENOENT)
887 err = tegra_i2c_master_reset(i2c_dev);
888
889 /*
890 * The reset shouldn't ever fail in practice. The failure will be a
891 * sign of a severe problem that needs to be resolved. Still we don't
892 * want to fail the initialization completely because this may break
893 * kernel boot up since voltage regulators use I2C. Hence, we will
894 * emit a noisy warning on error, which won't stay unnoticed and
895 * won't hose machine entirely.
896 */
897 WARN_ON_ONCE(err);
898
899 if (IS_DVC(i2c_dev))
900 tegra_dvc_init(i2c_dev);
901
902 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
903 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
904
905 if (i2c_dev->hw->has_multi_master_mode)
906 val |= I2C_CNFG_MULTI_MASTER_MODE;
907
908 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->cnfg);
909 i2c_writel(i2c_dev, 0, i2c_dev->hw->regs->int_mask);
910
911 if (IS_VI(i2c_dev))
912 tegra_i2c_vi_init(i2c_dev);
913
914 if (i2c_dev->hw->enable_hs_mode_support)
915 max_bus_freq_hz = I2C_MAX_HIGH_SPEED_MODE_FREQ;
916 else
917 max_bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ;
918
919 if (WARN_ON(t->bus_freq_hz > max_bus_freq_hz))
920 t->bus_freq_hz = max_bus_freq_hz;
921
922 if (t->bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
923 tlow = i2c_dev->hw->tlow_std_mode;
924 thigh = i2c_dev->hw->thigh_std_mode;
925 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
926 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
927 } else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
928 tlow = i2c_dev->hw->tlow_fast_mode;
929 thigh = i2c_dev->hw->thigh_fast_mode;
930 tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode;
931 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
932 } else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
933 tlow = i2c_dev->hw->tlow_fastplus_mode;
934 thigh = i2c_dev->hw->thigh_fastplus_mode;
935 tsu_thd = i2c_dev->hw->setup_hold_time_fastplus_mode;
936 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
937 } else {
938 /*
939 * When using HS mode, i.e. when the bus frequency is greater than fast plus mode,
940 * the non-hs timing registers will be used for sending the master code byte for
941 * transition to HS mode. Configure the non-hs timing registers for Fast Mode to
942 * send the master code byte at 400kHz.
943 */
944 tlow = i2c_dev->hw->tlow_fast_mode;
945 thigh = i2c_dev->hw->thigh_fast_mode;
946 tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode;
947 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
948 }
949
950 /* make sure clock divisor programmed correctly */
951 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
952 i2c_dev->hw->clk_divisor_hs_mode) |
953 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
954 i2c_writel(i2c_dev, clk_divisor, i2c_dev->hw->regs->clk_divisor);
955
956 if (i2c_dev->hw->has_interface_timing_reg) {
957 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
958 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
959 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->interface_timing_0);
960 }
961
962 /*
963 * Configure setup and hold times only when tsu_thd is non-zero.
964 * Otherwise, preserve the chip default values.
965 */
966 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
967 i2c_writel(i2c_dev, tsu_thd, i2c_dev->hw->regs->interface_timing_1);
968
969 /* Write HS mode registers. These will get used only for HS mode*/
970 if (i2c_dev->hw->enable_hs_mode_support) {
971 tlow = i2c_dev->hw->tlow_hs_mode;
972 thigh = i2c_dev->hw->thigh_hs_mode;
973 tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode;
974
975 val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) |
976 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow);
977 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->hs_interface_timing_0);
978 i2c_writel(i2c_dev, tsu_thd, i2c_dev->hw->regs->hs_interface_timing_1);
979 }
980
981 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
982
983 err = clk_set_rate(i2c_dev->div_clk,
984 t->bus_freq_hz * clk_multiplier);
985 if (err) {
986 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
987 return err;
988 }
989
990 if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) {
991 u32 sl_cfg = i2c_readl(i2c_dev, i2c_dev->hw->regs->sl_cnfg);
992
993 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
994 i2c_writel(i2c_dev, sl_cfg, i2c_dev->hw->regs->sl_cnfg);
995 i2c_writel(i2c_dev, 0xfc, i2c_dev->hw->regs->sl_addr1);
996 i2c_writel(i2c_dev, 0x00, i2c_dev->hw->regs->sl_addr2);
997 }
998
999 err = tegra_i2c_flush_fifos(i2c_dev);
1000 if (err)
1001 return err;
1002
1003 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
1004 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, i2c_dev->hw->regs->clken_override);
1005
1006 err = tegra_i2c_wait_for_config_load(i2c_dev);
1007 if (err)
1008 return err;
1009
1010 return 0;
1011 }
1012
tegra_i2c_disable_packet_mode(struct tegra_i2c_dev * i2c_dev)1013 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
1014 {
1015 u32 cnfg;
1016
1017 /*
1018 * NACK interrupt is generated before the I2C controller generates
1019 * the STOP condition on the bus. So, wait for 2 clock periods
1020 * before disabling the controller so that the STOP condition has
1021 * been delivered properly.
1022 */
1023 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz));
1024
1025 cnfg = i2c_readl(i2c_dev, i2c_dev->hw->regs->cnfg);
1026 if (cnfg & I2C_CNFG_PACKET_MODE_EN)
1027 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, i2c_dev->hw->regs->cnfg);
1028
1029 return tegra_i2c_wait_for_config_load(i2c_dev);
1030 }
1031
tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev * i2c_dev)1032 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
1033 {
1034 size_t buf_remaining = i2c_dev->msg_buf_remaining;
1035 unsigned int words_to_transfer, rx_fifo_avail;
1036 u8 *buf = i2c_dev->msg_buf;
1037 u32 val;
1038
1039 /*
1040 * Catch overflow due to message fully sent before the check for
1041 * RX FIFO availability.
1042 */
1043 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
1044 return -EINVAL;
1045
1046 if (i2c_dev->hw->has_mst_fifo) {
1047 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->mst_fifo_status);
1048 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
1049 } else {
1050 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->fifo_status);
1051 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
1052 }
1053
1054 /* round down to exclude partial word at the end of buffer */
1055 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
1056 if (words_to_transfer > rx_fifo_avail)
1057 words_to_transfer = rx_fifo_avail;
1058
1059 i2c_readsl(i2c_dev, buf, i2c_dev->hw->regs->rx_fifo, words_to_transfer);
1060
1061 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
1062 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
1063 rx_fifo_avail -= words_to_transfer;
1064
1065 /*
1066 * If there is a partial word at the end of buffer, handle it
1067 * manually to prevent overwriting past the end of buffer.
1068 */
1069 if (rx_fifo_avail > 0 && buf_remaining > 0) {
1070 /*
1071 * buf_remaining > 3 check not needed as rx_fifo_avail == 0
1072 * when (words_to_transfer was > rx_fifo_avail) earlier
1073 * in this function.
1074 */
1075 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->rx_fifo);
1076 val = cpu_to_le32(val);
1077 memcpy(buf, &val, buf_remaining);
1078 buf_remaining = 0;
1079 rx_fifo_avail--;
1080 }
1081
1082 /* RX FIFO must be drained, otherwise it's an Overflow case. */
1083 if (WARN_ON_ONCE(rx_fifo_avail))
1084 return -EINVAL;
1085
1086 i2c_dev->msg_buf_remaining = buf_remaining;
1087 i2c_dev->msg_buf = buf;
1088
1089 return 0;
1090 }
1091
tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev * i2c_dev)1092 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
1093 {
1094 size_t buf_remaining = i2c_dev->msg_buf_remaining;
1095 unsigned int words_to_transfer, tx_fifo_avail;
1096 u8 *buf = i2c_dev->msg_buf;
1097 u32 val;
1098
1099 if (i2c_dev->hw->has_mst_fifo) {
1100 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->mst_fifo_status);
1101 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
1102 } else {
1103 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->fifo_status);
1104 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
1105 }
1106
1107 /* round down to exclude partial word at the end of buffer */
1108 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
1109
1110 /*
1111 * This hunk pushes 4 bytes at a time into the TX FIFO.
1112 *
1113 * It's very common to have < 4 bytes, hence there is no word
1114 * to push if we have less than 4 bytes to transfer.
1115 */
1116 if (words_to_transfer) {
1117 if (words_to_transfer > tx_fifo_avail)
1118 words_to_transfer = tx_fifo_avail;
1119
1120 /*
1121 * Update state before writing to FIFO. Note that this may
1122 * cause us to finish writing all bytes (AKA buf_remaining
1123 * goes to 0), hence we have a potential for an interrupt
1124 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt
1125 * is disabled at this point.
1126 */
1127 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
1128 tx_fifo_avail -= words_to_transfer;
1129
1130 i2c_dev->msg_buf_remaining = buf_remaining;
1131 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD;
1132
1133 if (IS_VI(i2c_dev))
1134 i2c_writesl_vi(i2c_dev, buf, i2c_dev->hw->regs->tx_fifo, words_to_transfer);
1135 else
1136 i2c_writesl(i2c_dev, buf, i2c_dev->hw->regs->tx_fifo, words_to_transfer);
1137
1138 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
1139 }
1140
1141 /*
1142 * If there is a partial word at the end of buffer, handle it manually
1143 * to prevent reading past the end of buffer, which could cross a page
1144 * boundary and fault.
1145 */
1146 if (tx_fifo_avail > 0 && buf_remaining > 0) {
1147 /*
1148 * buf_remaining > 3 check not needed as tx_fifo_avail == 0
1149 * when (words_to_transfer was > tx_fifo_avail) earlier
1150 * in this function for non-zero words_to_transfer.
1151 */
1152 memcpy(&val, buf, buf_remaining);
1153 val = le32_to_cpu(val);
1154
1155 i2c_dev->msg_buf_remaining = 0;
1156 i2c_dev->msg_buf = NULL;
1157
1158 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->tx_fifo);
1159 }
1160
1161 return 0;
1162 }
1163
tegra_i2c_isr(int irq,void * dev_id)1164 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
1165 {
1166 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1167 struct tegra_i2c_dev *i2c_dev = dev_id;
1168 u32 status;
1169
1170 status = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_status);
1171
1172 if (status == 0) {
1173 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n",
1174 i2c_readl(i2c_dev, i2c_dev->hw->regs->packet_transfer_status),
1175 i2c_readl(i2c_dev, i2c_dev->hw->regs->status),
1176 i2c_readl(i2c_dev, i2c_dev->hw->regs->cnfg));
1177 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
1178 goto err;
1179 }
1180
1181 if (status & status_err) {
1182 tegra_i2c_disable_packet_mode(i2c_dev);
1183 if (status & I2C_INT_NO_ACK)
1184 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
1185 if (status & I2C_INT_ARBITRATION_LOST)
1186 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
1187 goto err;
1188 }
1189
1190 /*
1191 * I2C transfer is terminated during the bus clear, so skip
1192 * processing the other interrupts.
1193 */
1194 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
1195 goto err;
1196
1197 if (!i2c_dev->dma_mode) {
1198 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
1199 if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
1200 /*
1201 * Overflow error condition: message fully sent,
1202 * with no XFER_COMPLETE interrupt but hardware
1203 * asks to transfer more.
1204 */
1205 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
1206 goto err;
1207 }
1208 }
1209
1210 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
1211 if (i2c_dev->msg_buf_remaining)
1212 tegra_i2c_fill_tx_fifo(i2c_dev);
1213 else
1214 tegra_i2c_mask_irq(i2c_dev,
1215 I2C_INT_TX_FIFO_DATA_REQ);
1216 }
1217 }
1218
1219 i2c_writel(i2c_dev, status, i2c_dev->hw->regs->int_status);
1220 if (IS_DVC(i2c_dev))
1221 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
1222
1223 /*
1224 * During message read XFER_COMPLETE interrupt is triggered prior to
1225 * DMA completion and during message write XFER_COMPLETE interrupt is
1226 * triggered after DMA completion.
1227 *
1228 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer,
1229 * so forcing msg_buf_remaining to 0 in DMA mode.
1230 */
1231 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
1232 if (i2c_dev->dma_mode)
1233 i2c_dev->msg_buf_remaining = 0;
1234 /*
1235 * Underflow error condition: XFER_COMPLETE before message
1236 * fully sent.
1237 */
1238 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
1239 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
1240 goto err;
1241 }
1242 complete(&i2c_dev->msg_complete);
1243 }
1244 goto done;
1245 err:
1246 /* mask all interrupts on error */
1247 tegra_i2c_mask_irq(i2c_dev,
1248 I2C_INT_NO_ACK |
1249 I2C_INT_ARBITRATION_LOST |
1250 I2C_INT_PACKET_XFER_COMPLETE |
1251 I2C_INT_TX_FIFO_DATA_REQ |
1252 I2C_INT_RX_FIFO_DATA_REQ);
1253
1254 if (i2c_dev->hw->supports_bus_clear)
1255 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1256
1257 i2c_writel(i2c_dev, status, i2c_dev->hw->regs->int_status);
1258
1259 if (IS_DVC(i2c_dev))
1260 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
1261
1262 if (i2c_dev->dma_mode) {
1263 dmaengine_terminate_async(i2c_dev->dma_chan);
1264 complete(&i2c_dev->dma_complete);
1265 }
1266
1267 complete(&i2c_dev->msg_complete);
1268 done:
1269 return IRQ_HANDLED;
1270 }
1271
tegra_i2c_config_fifo_trig(struct tegra_i2c_dev * i2c_dev,size_t len)1272 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
1273 size_t len)
1274 {
1275 struct dma_slave_config slv_config = {0};
1276 u32 val, reg, dma_burst, reg_offset;
1277 int err;
1278
1279 if (i2c_dev->hw->has_mst_fifo)
1280 reg = i2c_dev->hw->regs->mst_fifo_control;
1281 else
1282 reg = i2c_dev->hw->regs->fifo_control;
1283
1284 if (i2c_dev->dma_mode) {
1285 if (len & 0xF)
1286 dma_burst = 1;
1287 else if (len & 0x10)
1288 dma_burst = 4;
1289 else
1290 dma_burst = 8;
1291
1292 if (i2c_dev->msg_read) {
1293 reg_offset = i2c_dev->hw->regs->rx_fifo;
1294
1295 slv_config.src_addr = i2c_dev->base_phys + reg_offset;
1296 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1297 slv_config.src_maxburst = dma_burst;
1298
1299 if (i2c_dev->hw->has_mst_fifo)
1300 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
1301 else
1302 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
1303 } else {
1304 reg_offset = i2c_dev->hw->regs->tx_fifo;
1305
1306 slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
1307 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1308 slv_config.dst_maxburst = dma_burst;
1309
1310 if (i2c_dev->hw->has_mst_fifo)
1311 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
1312 else
1313 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
1314 }
1315
1316 slv_config.device_fc = true;
1317 err = dmaengine_slave_config(i2c_dev->dma_chan, &slv_config);
1318 if (err) {
1319 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err);
1320 dev_err(i2c_dev->dev, "falling back to PIO\n");
1321
1322 tegra_i2c_release_dma(i2c_dev);
1323 i2c_dev->dma_mode = false;
1324 } else {
1325 goto out;
1326 }
1327 }
1328
1329 if (i2c_dev->hw->has_mst_fifo)
1330 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
1331 I2C_MST_FIFO_CONTROL_RX_TRIG(1);
1332 else
1333 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
1334 I2C_FIFO_CONTROL_RX_TRIG(1);
1335 out:
1336 i2c_writel(i2c_dev, val, reg);
1337 }
1338
tegra_i2c_poll_completion(struct tegra_i2c_dev * i2c_dev,struct completion * complete,unsigned int timeout_ms)1339 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev,
1340 struct completion *complete,
1341 unsigned int timeout_ms)
1342 {
1343 ktime_t ktime = ktime_get();
1344 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
1345
1346 do {
1347 u32 status = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_status);
1348
1349 if (status)
1350 tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1351
1352 if (completion_done(complete)) {
1353 s64 delta = ktime_ms_delta(ktimeout, ktime);
1354
1355 return msecs_to_jiffies(delta) ?: 1;
1356 }
1357
1358 ktime = ktime_get();
1359
1360 } while (ktime_before(ktime, ktimeout));
1361
1362 return 0;
1363 }
1364
tegra_i2c_wait_completion(struct tegra_i2c_dev * i2c_dev,struct completion * complete,unsigned int timeout_ms)1365 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev,
1366 struct completion *complete,
1367 unsigned int timeout_ms)
1368 {
1369 unsigned long ret;
1370
1371 if (i2c_dev->atomic_mode) {
1372 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms);
1373 } else {
1374 enable_irq(i2c_dev->irq);
1375 ret = wait_for_completion_timeout(complete,
1376 msecs_to_jiffies(timeout_ms));
1377 disable_irq(i2c_dev->irq);
1378
1379 /*
1380 * Under some rare circumstances (like running KASAN +
1381 * NFS root) CPU, which handles interrupt, may stuck in
1382 * uninterruptible state for a significant time. In this
1383 * case we will get timeout if I2C transfer is running on
1384 * a sibling CPU, despite of IRQ being raised.
1385 *
1386 * In order to handle this rare condition, the IRQ status
1387 * needs to be checked after timeout.
1388 */
1389 if (ret == 0)
1390 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0);
1391 }
1392
1393 return ret;
1394 }
1395
tegra_i2c_issue_bus_clear(struct i2c_adapter * adap)1396 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1397 {
1398 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1399 u32 val, time_left;
1400 int err;
1401
1402 reinit_completion(&i2c_dev->msg_complete);
1403
1404 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
1405 I2C_BC_TERMINATE;
1406 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->bus_clear_cnfg);
1407
1408 err = tegra_i2c_wait_for_config_load(i2c_dev);
1409 if (err)
1410 return err;
1411
1412 val |= I2C_BC_ENABLE;
1413 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->bus_clear_cnfg);
1414 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1415
1416 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50);
1417 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1418
1419 if (time_left == 0) {
1420 dev_err(i2c_dev->dev, "failed to clear bus\n");
1421 return -ETIMEDOUT;
1422 }
1423
1424 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->bus_clear_status);
1425 if (!(val & I2C_BC_STATUS)) {
1426 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n");
1427 return -EIO;
1428 }
1429
1430 return -EAGAIN;
1431 }
1432
tegra_i2c_push_packet_header(struct tegra_i2c_dev * i2c_dev,struct i2c_msg * msg,enum msg_end_type end_state)1433 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
1434 struct i2c_msg *msg,
1435 enum msg_end_type end_state)
1436 {
1437 u32 *dma_buf = i2c_dev->dma_buf;
1438 u32 packet_header;
1439
1440 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) |
1441 FIELD_PREP(PACKET_HEADER0_PROTOCOL,
1442 PACKET_HEADER0_PROTOCOL_I2C) |
1443 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1444 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1);
1445
1446 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1447 *dma_buf++ = packet_header;
1448 else
1449 i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo);
1450
1451 packet_header = i2c_dev->msg_len - 1;
1452
1453 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1454 *dma_buf++ = packet_header;
1455 else
1456 i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo);
1457
1458 packet_header = I2C_HEADER_IE_ENABLE;
1459
1460 if (end_state == MSG_END_CONTINUE)
1461 packet_header |= I2C_HEADER_CONTINUE_XFER;
1462 else if (end_state == MSG_END_REPEAT_START)
1463 packet_header |= I2C_HEADER_REPEAT_START;
1464
1465 if (msg->flags & I2C_M_TEN) {
1466 packet_header |= msg->addr;
1467 packet_header |= I2C_HEADER_10BIT_ADDR;
1468 } else {
1469 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1470 }
1471
1472 if (msg->flags & I2C_M_IGNORE_NAK)
1473 packet_header |= I2C_HEADER_CONT_ON_NAK;
1474
1475 if (msg->flags & I2C_M_RD)
1476 packet_header |= I2C_HEADER_READ;
1477
1478 if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
1479 packet_header |= I2C_HEADER_HS_MODE;
1480
1481 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1482 *dma_buf++ = packet_header;
1483 else
1484 i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo);
1485 }
1486
tegra_i2c_error_recover(struct tegra_i2c_dev * i2c_dev,struct i2c_msg * msg)1487 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev,
1488 struct i2c_msg *msg)
1489 {
1490 if (i2c_dev->msg_err == I2C_ERR_NONE)
1491 return 0;
1492
1493 tegra_i2c_init(i2c_dev);
1494
1495 /* start recovery upon arbitration loss in single master mode */
1496 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1497 if (!i2c_dev->multimaster_mode)
1498 return i2c_recover_bus(&i2c_dev->adapter);
1499
1500 return -EAGAIN;
1501 }
1502
1503 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1504 if (msg->flags & I2C_M_IGNORE_NAK)
1505 return 0;
1506
1507 return -EREMOTEIO;
1508 }
1509
1510 return -EIO;
1511 }
1512
tegra_i2c_xfer_msg(struct tegra_i2c_dev * i2c_dev,struct i2c_msg * msg,enum msg_end_type end_state)1513 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1514 struct i2c_msg *msg,
1515 enum msg_end_type end_state)
1516 {
1517 unsigned long time_left, xfer_time = 100;
1518 size_t xfer_size;
1519 u32 int_mask;
1520 int err;
1521
1522 err = tegra_i2c_flush_fifos(i2c_dev);
1523 if (err)
1524 return err;
1525
1526 i2c_dev->msg_buf = msg->buf;
1527 i2c_dev->msg_len = msg->len;
1528
1529 i2c_dev->msg_err = I2C_ERR_NONE;
1530 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD);
1531 reinit_completion(&i2c_dev->msg_complete);
1532
1533 /*
1534 * For SMBUS block read command, read only 1 byte in the first transfer.
1535 * Adjust that 1 byte for the next transfer in the msg buffer and msg
1536 * length.
1537 */
1538 if (msg->flags & I2C_M_RECV_LEN) {
1539 if (end_state == MSG_END_CONTINUE) {
1540 i2c_dev->msg_len = 1;
1541 } else {
1542 i2c_dev->msg_buf += 1;
1543 i2c_dev->msg_len -= 1;
1544 }
1545 }
1546
1547 i2c_dev->msg_buf_remaining = i2c_dev->msg_len;
1548
1549 if (i2c_dev->msg_read)
1550 xfer_size = i2c_dev->msg_len;
1551 else
1552 xfer_size = i2c_dev->msg_len + I2C_PACKET_HEADER_SIZE;
1553
1554 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1555
1556 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN &&
1557 i2c_dev->dma_buf && !i2c_dev->atomic_mode;
1558
1559 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1560
1561 /*
1562 * Transfer time in mSec = Total bits / transfer rate
1563 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1564 */
1565 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1566 i2c_dev->timings.bus_freq_hz);
1567
1568 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1569 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1570
1571 if (i2c_dev->dma_mode) {
1572 if (i2c_dev->msg_read) {
1573 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1574 if (err)
1575 return err;
1576 }
1577 }
1578
1579 tegra_i2c_push_packet_header(i2c_dev, msg, end_state);
1580
1581 if (!i2c_dev->msg_read) {
1582 if (i2c_dev->dma_mode) {
1583 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
1584 msg->buf, i2c_dev->msg_len);
1585 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1586 if (err)
1587 return err;
1588 } else {
1589 tegra_i2c_fill_tx_fifo(i2c_dev);
1590 }
1591 }
1592
1593 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1594 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1595
1596 if (!i2c_dev->dma_mode) {
1597 if (msg->flags & I2C_M_RD)
1598 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1599 else if (i2c_dev->msg_buf_remaining)
1600 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1601 }
1602
1603 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1604 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n",
1605 i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask));
1606
1607 if (i2c_dev->dma_mode) {
1608 time_left = tegra_i2c_wait_completion(i2c_dev,
1609 &i2c_dev->dma_complete,
1610 xfer_time);
1611
1612 /*
1613 * Synchronize DMA first, since dmaengine_terminate_sync()
1614 * performs synchronization after the transfer's termination
1615 * and we want to get a completion if transfer succeeded.
1616 */
1617 dmaengine_synchronize(i2c_dev->dma_chan);
1618 dmaengine_terminate_sync(i2c_dev->dma_chan);
1619
1620 if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1621 tegra_i2c_init(i2c_dev);
1622 return -ETIMEDOUT;
1623 }
1624
1625 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE)
1626 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len);
1627 }
1628
1629 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,
1630 xfer_time);
1631
1632 tegra_i2c_mask_irq(i2c_dev, int_mask);
1633
1634 if (time_left == 0) {
1635 tegra_i2c_init(i2c_dev);
1636 return -ETIMEDOUT;
1637 }
1638
1639 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1640 time_left, completion_done(&i2c_dev->msg_complete),
1641 i2c_dev->msg_err);
1642
1643 i2c_dev->dma_mode = false;
1644
1645 err = tegra_i2c_error_recover(i2c_dev, msg);
1646 if (err)
1647 return err;
1648
1649 return 0;
1650 }
1651
tegra_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1652 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1653 int num)
1654 {
1655 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1656 int i, ret;
1657
1658 ret = pm_runtime_get_sync(i2c_dev->dev);
1659 if (ret < 0) {
1660 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1661 pm_runtime_put_noidle(i2c_dev->dev);
1662 return ret;
1663 }
1664
1665 ret = tegra_i2c_mutex_lock(i2c_dev);
1666 if (ret) {
1667 pm_runtime_put(i2c_dev->dev);
1668 return ret;
1669 }
1670
1671 for (i = 0; i < num; i++) {
1672 enum msg_end_type end_type = MSG_END_STOP;
1673
1674 if (i < (num - 1)) {
1675 /* check whether follow up message is coming */
1676 if (msgs[i + 1].flags & I2C_M_NOSTART)
1677 end_type = MSG_END_CONTINUE;
1678 else
1679 end_type = MSG_END_REPEAT_START;
1680 }
1681 /* If M_RECV_LEN use ContinueXfer to read the first byte */
1682 if (msgs[i].flags & I2C_M_RECV_LEN) {
1683 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE);
1684 if (ret)
1685 break;
1686
1687 /* Validate message length before proceeding */
1688 if (msgs[i].buf[0] == 0 || msgs[i].buf[0] > I2C_SMBUS_BLOCK_MAX)
1689 break;
1690
1691 /* Set the msg length from first byte */
1692 msgs[i].len += msgs[i].buf[0];
1693 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len);
1694 }
1695 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1696 if (ret)
1697 break;
1698 }
1699
1700 tegra_i2c_mutex_unlock(i2c_dev);
1701 pm_runtime_put(i2c_dev->dev);
1702
1703 return ret ?: i;
1704 }
1705
tegra_i2c_xfer_atomic(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1706 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap,
1707 struct i2c_msg msgs[], int num)
1708 {
1709 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1710 int ret;
1711
1712 i2c_dev->atomic_mode = true;
1713 ret = tegra_i2c_xfer(adap, msgs, num);
1714 i2c_dev->atomic_mode = false;
1715
1716 return ret;
1717 }
1718
tegra_i2c_func(struct i2c_adapter * adap)1719 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1720 {
1721 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1722 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1723 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1724
1725 if (i2c_dev->hw->has_continue_xfer_support)
1726 ret |= I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1727
1728 return ret;
1729 }
1730
1731 static const struct i2c_algorithm tegra_i2c_algo = {
1732 .xfer = tegra_i2c_xfer,
1733 .xfer_atomic = tegra_i2c_xfer_atomic,
1734 .functionality = tegra_i2c_func,
1735 };
1736
1737 /* payload size is only 12 bit */
1738 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1739 .flags = I2C_AQ_NO_ZERO_LEN,
1740 .max_read_len = SZ_4K,
1741 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1742 };
1743
1744 static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1745 .flags = I2C_AQ_NO_ZERO_LEN,
1746 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1747 };
1748
1749 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1750 .recover_bus = tegra_i2c_issue_bus_clear,
1751 };
1752
1753 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1754 .has_continue_xfer_support = false,
1755 .has_per_pkt_xfer_complete_irq = false,
1756 .clk_divisor_hs_mode = 3,
1757 .clk_divisor_std_mode = 0,
1758 .clk_divisor_fast_mode = 0,
1759 .clk_divisor_fast_plus_mode = 0,
1760 .has_config_load_reg = false,
1761 .has_multi_master_mode = false,
1762 .has_slcg_override_reg = false,
1763 .has_mst_fifo = false,
1764 .has_mst_reset = false,
1765 .quirks = &tegra_i2c_quirks,
1766 .supports_bus_clear = false,
1767 .has_apb_dma = true,
1768 .tlow_std_mode = 0x4,
1769 .thigh_std_mode = 0x2,
1770 .tlow_fast_mode = 0x4,
1771 .thigh_fast_mode = 0x2,
1772 .tlow_fastplus_mode = 0x4,
1773 .thigh_fastplus_mode = 0x2,
1774 .setup_hold_time_std_mode = 0x0,
1775 .setup_hold_time_fast_mode = 0x0,
1776 .setup_hold_time_fastplus_mode = 0x0,
1777 .setup_hold_time_hs_mode = 0x0,
1778 .has_interface_timing_reg = false,
1779 .enable_hs_mode_support = false,
1780 .has_mutex = false,
1781 .variant = TEGRA_I2C_VARIANT_DEFAULT,
1782 .regs = &tegra20_i2c_regs,
1783 };
1784
1785 #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
1786 static const struct tegra_i2c_hw_feature tegra20_dvc_i2c_hw = {
1787 .has_continue_xfer_support = false,
1788 .has_per_pkt_xfer_complete_irq = false,
1789 .clk_divisor_hs_mode = 3,
1790 .clk_divisor_std_mode = 0,
1791 .clk_divisor_fast_mode = 0,
1792 .clk_divisor_fast_plus_mode = 0,
1793 .has_config_load_reg = false,
1794 .has_multi_master_mode = false,
1795 .has_slcg_override_reg = false,
1796 .has_mst_fifo = false,
1797 .has_mst_reset = false,
1798 .quirks = &tegra_i2c_quirks,
1799 .supports_bus_clear = false,
1800 .has_apb_dma = true,
1801 .tlow_std_mode = 0x4,
1802 .thigh_std_mode = 0x2,
1803 .tlow_fast_mode = 0x4,
1804 .thigh_fast_mode = 0x2,
1805 .tlow_fastplus_mode = 0x4,
1806 .thigh_fastplus_mode = 0x2,
1807 .setup_hold_time_std_mode = 0x0,
1808 .setup_hold_time_fast_mode = 0x0,
1809 .setup_hold_time_fastplus_mode = 0x0,
1810 .setup_hold_time_hs_mode = 0x0,
1811 .has_interface_timing_reg = false,
1812 .enable_hs_mode_support = false,
1813 .has_mutex = false,
1814 .variant = TEGRA_I2C_VARIANT_DVC,
1815 .regs = &tegra20_dvc_i2c_regs,
1816 };
1817 #endif
1818
1819 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1820 .has_continue_xfer_support = true,
1821 .has_per_pkt_xfer_complete_irq = false,
1822 .clk_divisor_hs_mode = 3,
1823 .clk_divisor_std_mode = 0,
1824 .clk_divisor_fast_mode = 0,
1825 .clk_divisor_fast_plus_mode = 0,
1826 .has_config_load_reg = false,
1827 .has_multi_master_mode = false,
1828 .has_slcg_override_reg = false,
1829 .has_mst_fifo = false,
1830 .has_mst_reset = false,
1831 .quirks = &tegra_i2c_quirks,
1832 .supports_bus_clear = false,
1833 .has_apb_dma = true,
1834 .tlow_std_mode = 0x4,
1835 .thigh_std_mode = 0x2,
1836 .tlow_fast_mode = 0x4,
1837 .thigh_fast_mode = 0x2,
1838 .tlow_fastplus_mode = 0x4,
1839 .thigh_fastplus_mode = 0x2,
1840 .setup_hold_time_std_mode = 0x0,
1841 .setup_hold_time_fast_mode = 0x0,
1842 .setup_hold_time_fastplus_mode = 0x0,
1843 .setup_hold_time_hs_mode = 0x0,
1844 .has_interface_timing_reg = false,
1845 .enable_hs_mode_support = false,
1846 .has_mutex = false,
1847 .variant = TEGRA_I2C_VARIANT_DEFAULT,
1848 .regs = &tegra20_i2c_regs,
1849 };
1850
1851 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1852 .has_continue_xfer_support = true,
1853 .has_per_pkt_xfer_complete_irq = true,
1854 .clk_divisor_hs_mode = 1,
1855 .clk_divisor_std_mode = 0x19,
1856 .clk_divisor_fast_mode = 0x19,
1857 .clk_divisor_fast_plus_mode = 0x10,
1858 .has_config_load_reg = false,
1859 .has_multi_master_mode = false,
1860 .has_slcg_override_reg = false,
1861 .has_mst_fifo = false,
1862 .has_mst_reset = false,
1863 .quirks = &tegra_i2c_quirks,
1864 .supports_bus_clear = true,
1865 .has_apb_dma = true,
1866 .tlow_std_mode = 0x4,
1867 .thigh_std_mode = 0x2,
1868 .tlow_fast_mode = 0x4,
1869 .thigh_fast_mode = 0x2,
1870 .tlow_fastplus_mode = 0x4,
1871 .thigh_fastplus_mode = 0x2,
1872 .setup_hold_time_std_mode = 0x0,
1873 .setup_hold_time_fast_mode = 0x0,
1874 .setup_hold_time_fastplus_mode = 0x0,
1875 .setup_hold_time_hs_mode = 0x0,
1876 .has_interface_timing_reg = false,
1877 .enable_hs_mode_support = false,
1878 .has_mutex = false,
1879 .variant = TEGRA_I2C_VARIANT_DEFAULT,
1880 .regs = &tegra20_i2c_regs,
1881 };
1882
1883 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1884 .has_continue_xfer_support = true,
1885 .has_per_pkt_xfer_complete_irq = true,
1886 .clk_divisor_hs_mode = 1,
1887 .clk_divisor_std_mode = 0x19,
1888 .clk_divisor_fast_mode = 0x19,
1889 .clk_divisor_fast_plus_mode = 0x10,
1890 .has_config_load_reg = true,
1891 .has_multi_master_mode = false,
1892 .has_slcg_override_reg = true,
1893 .has_mst_fifo = false,
1894 .has_mst_reset = false,
1895 .quirks = &tegra_i2c_quirks,
1896 .supports_bus_clear = true,
1897 .has_apb_dma = true,
1898 .tlow_std_mode = 0x4,
1899 .thigh_std_mode = 0x2,
1900 .tlow_fast_mode = 0x4,
1901 .thigh_fast_mode = 0x2,
1902 .tlow_fastplus_mode = 0x4,
1903 .thigh_fastplus_mode = 0x2,
1904 .setup_hold_time_std_mode = 0x0,
1905 .setup_hold_time_fast_mode = 0x0,
1906 .setup_hold_time_fastplus_mode = 0x0,
1907 .setup_hold_time_hs_mode = 0x0,
1908 .has_interface_timing_reg = true,
1909 .enable_hs_mode_support = false,
1910 .has_mutex = false,
1911 .variant = TEGRA_I2C_VARIANT_DEFAULT,
1912 .regs = &tegra20_i2c_regs,
1913 };
1914
1915 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1916 .has_continue_xfer_support = true,
1917 .has_per_pkt_xfer_complete_irq = true,
1918 .clk_divisor_hs_mode = 1,
1919 .clk_divisor_std_mode = 0x19,
1920 .clk_divisor_fast_mode = 0x19,
1921 .clk_divisor_fast_plus_mode = 0x10,
1922 .has_config_load_reg = true,
1923 .has_multi_master_mode = false,
1924 .has_slcg_override_reg = true,
1925 .has_mst_fifo = false,
1926 .has_mst_reset = false,
1927 .quirks = &tegra_i2c_quirks,
1928 .supports_bus_clear = true,
1929 .has_apb_dma = true,
1930 .tlow_std_mode = 0x4,
1931 .thigh_std_mode = 0x2,
1932 .tlow_fast_mode = 0x4,
1933 .thigh_fast_mode = 0x2,
1934 .tlow_fastplus_mode = 0x4,
1935 .thigh_fastplus_mode = 0x2,
1936 .setup_hold_time_std_mode = 0,
1937 .setup_hold_time_fast_mode = 0,
1938 .setup_hold_time_fastplus_mode = 0,
1939 .setup_hold_time_hs_mode = 0,
1940 .has_interface_timing_reg = true,
1941 .enable_hs_mode_support = false,
1942 .has_mutex = false,
1943 .variant = TEGRA_I2C_VARIANT_DEFAULT,
1944 .regs = &tegra20_i2c_regs,
1945 };
1946
1947 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
1948 static const struct tegra_i2c_hw_feature tegra210_vi_i2c_hw = {
1949 .has_continue_xfer_support = true,
1950 .has_per_pkt_xfer_complete_irq = true,
1951 .clk_divisor_hs_mode = 1,
1952 .clk_divisor_std_mode = 0x19,
1953 .clk_divisor_fast_mode = 0x19,
1954 .clk_divisor_fast_plus_mode = 0x10,
1955 .has_config_load_reg = true,
1956 .has_multi_master_mode = false,
1957 .has_slcg_override_reg = true,
1958 .has_mst_fifo = false,
1959 .has_mst_reset = false,
1960 .quirks = &tegra_i2c_quirks,
1961 .supports_bus_clear = true,
1962 .has_apb_dma = true,
1963 .tlow_std_mode = 0x4,
1964 .thigh_std_mode = 0x2,
1965 .tlow_fast_mode = 0x4,
1966 .thigh_fast_mode = 0x2,
1967 .tlow_fastplus_mode = 0x4,
1968 .thigh_fastplus_mode = 0x2,
1969 .setup_hold_time_std_mode = 0,
1970 .setup_hold_time_fast_mode = 0,
1971 .setup_hold_time_fastplus_mode = 0,
1972 .setup_hold_time_hs_mode = 0,
1973 .has_interface_timing_reg = true,
1974 .enable_hs_mode_support = false,
1975 .has_mutex = false,
1976 .variant = TEGRA_I2C_VARIANT_VI,
1977 .regs = &tegra210_vi_i2c_regs,
1978 };
1979 #endif
1980
1981 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1982 .has_continue_xfer_support = true,
1983 .has_per_pkt_xfer_complete_irq = true,
1984 .clk_divisor_hs_mode = 1,
1985 .clk_divisor_std_mode = 0x16,
1986 .clk_divisor_fast_mode = 0x19,
1987 .clk_divisor_fast_plus_mode = 0x10,
1988 .has_config_load_reg = true,
1989 .has_multi_master_mode = false,
1990 .has_slcg_override_reg = true,
1991 .has_mst_fifo = false,
1992 .has_mst_reset = false,
1993 .quirks = &tegra_i2c_quirks,
1994 .supports_bus_clear = true,
1995 .has_apb_dma = false,
1996 .tlow_std_mode = 0x4,
1997 .thigh_std_mode = 0x3,
1998 .tlow_fast_mode = 0x4,
1999 .thigh_fast_mode = 0x2,
2000 .tlow_fastplus_mode = 0x4,
2001 .thigh_fastplus_mode = 0x2,
2002 .setup_hold_time_std_mode = 0,
2003 .setup_hold_time_fast_mode = 0,
2004 .setup_hold_time_fastplus_mode = 0,
2005 .setup_hold_time_hs_mode = 0,
2006 .has_interface_timing_reg = true,
2007 .enable_hs_mode_support = false,
2008 .has_mutex = false,
2009 .variant = TEGRA_I2C_VARIANT_DEFAULT,
2010 .regs = &tegra20_i2c_regs,
2011 };
2012
2013 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
2014 .has_continue_xfer_support = true,
2015 .has_per_pkt_xfer_complete_irq = true,
2016 .clk_divisor_hs_mode = 1,
2017 .clk_divisor_std_mode = 0x4f,
2018 .clk_divisor_fast_mode = 0x3c,
2019 .clk_divisor_fast_plus_mode = 0x16,
2020 .has_config_load_reg = true,
2021 .has_multi_master_mode = true,
2022 .has_slcg_override_reg = true,
2023 .has_mst_fifo = true,
2024 .has_mst_reset = true,
2025 .quirks = &tegra194_i2c_quirks,
2026 .supports_bus_clear = true,
2027 .has_apb_dma = false,
2028 .tlow_std_mode = 0x8,
2029 .thigh_std_mode = 0x7,
2030 .tlow_fast_mode = 0x2,
2031 .thigh_fast_mode = 0x2,
2032 .tlow_fastplus_mode = 0x2,
2033 .thigh_fastplus_mode = 0x2,
2034 .tlow_hs_mode = 0x8,
2035 .thigh_hs_mode = 0x3,
2036 .setup_hold_time_std_mode = 0x08080808,
2037 .setup_hold_time_fast_mode = 0x02020202,
2038 .setup_hold_time_fastplus_mode = 0x02020202,
2039 .setup_hold_time_hs_mode = 0x090909,
2040 .has_interface_timing_reg = true,
2041 .enable_hs_mode_support = true,
2042 .has_mutex = false,
2043 .variant = TEGRA_I2C_VARIANT_DEFAULT,
2044 .regs = &tegra20_i2c_regs,
2045 };
2046
2047 static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
2048 .has_continue_xfer_support = true,
2049 .has_per_pkt_xfer_complete_irq = true,
2050 .clk_divisor_hs_mode = 9,
2051 .clk_divisor_std_mode = 0x7a,
2052 .clk_divisor_fast_mode = 0x40,
2053 .clk_divisor_fast_plus_mode = 0x14,
2054 .has_config_load_reg = true,
2055 .has_multi_master_mode = true,
2056 .has_slcg_override_reg = true,
2057 .has_mst_fifo = true,
2058 .has_mst_reset = true,
2059 .quirks = &tegra194_i2c_quirks,
2060 .supports_bus_clear = true,
2061 .has_apb_dma = false,
2062 .tlow_std_mode = 0x8,
2063 .thigh_std_mode = 0x7,
2064 .tlow_fast_mode = 0x4,
2065 .thigh_fast_mode = 0x2,
2066 .tlow_fastplus_mode = 0x4,
2067 .thigh_fastplus_mode = 0x4,
2068 .tlow_hs_mode = 0x3,
2069 .thigh_hs_mode = 0x2,
2070 .setup_hold_time_std_mode = 0x08080808,
2071 .setup_hold_time_fast_mode = 0x04010101,
2072 .setup_hold_time_fastplus_mode = 0x04020202,
2073 .setup_hold_time_hs_mode = 0x030303,
2074 .has_interface_timing_reg = true,
2075 .enable_hs_mode_support = true,
2076 .has_mutex = true,
2077 .variant = TEGRA_I2C_VARIANT_DEFAULT,
2078 .regs = &tegra264_i2c_regs,
2079 };
2080
2081 static const struct tegra_i2c_hw_feature tegra264_i2c_hw = {
2082 .has_continue_xfer_support = true,
2083 .has_per_pkt_xfer_complete_irq = true,
2084 .clk_divisor_hs_mode = 1,
2085 .clk_divisor_std_mode = 0x1d,
2086 .clk_divisor_fast_mode = 0x15,
2087 .clk_divisor_fast_plus_mode = 0x8,
2088 .has_config_load_reg = true,
2089 .has_multi_master_mode = true,
2090 .has_slcg_override_reg = true,
2091 .has_mst_fifo = true,
2092 .has_mst_reset = true,
2093 .quirks = &tegra194_i2c_quirks,
2094 .supports_bus_clear = true,
2095 .has_apb_dma = false,
2096 .tlow_std_mode = 0x8,
2097 .thigh_std_mode = 0x7,
2098 .tlow_fast_mode = 0x2,
2099 .thigh_fast_mode = 0x2,
2100 .tlow_fastplus_mode = 0x2,
2101 .thigh_fastplus_mode = 0x2,
2102 .tlow_hs_mode = 0x4,
2103 .thigh_hs_mode = 0x2,
2104 .setup_hold_time_std_mode = 0x08080808,
2105 .setup_hold_time_fast_mode = 0x02020202,
2106 .setup_hold_time_fastplus_mode = 0x02020202,
2107 .setup_hold_time_hs_mode = 0x090909,
2108 .has_interface_timing_reg = true,
2109 .enable_hs_mode_support = true,
2110 .has_mutex = true,
2111 .variant = TEGRA_I2C_VARIANT_DEFAULT,
2112 .regs = &tegra264_i2c_regs,
2113 };
2114
2115 static const struct tegra_i2c_hw_feature tegra410_i2c_hw = {
2116 .has_continue_xfer_support = true,
2117 .has_per_pkt_xfer_complete_irq = true,
2118 .clk_divisor_hs_mode = 1,
2119 .clk_divisor_std_mode = 0x3f,
2120 .clk_divisor_fast_mode = 0x2c,
2121 .clk_divisor_fast_plus_mode = 0x11,
2122 .has_config_load_reg = true,
2123 .has_multi_master_mode = true,
2124 .has_slcg_override_reg = true,
2125 .has_mst_fifo = true,
2126 .has_mst_reset = true,
2127 .quirks = &tegra194_i2c_quirks,
2128 .supports_bus_clear = true,
2129 .has_apb_dma = false,
2130 .tlow_std_mode = 0x8,
2131 .thigh_std_mode = 0x7,
2132 .tlow_fast_mode = 0x2,
2133 .thigh_fast_mode = 0x2,
2134 .tlow_fastplus_mode = 0x2,
2135 .thigh_fastplus_mode = 0x2,
2136 .tlow_hs_mode = 0x8,
2137 .thigh_hs_mode = 0x6,
2138 .setup_hold_time_std_mode = 0x08080808,
2139 .setup_hold_time_fast_mode = 0x02020202,
2140 .setup_hold_time_fastplus_mode = 0x02020202,
2141 .setup_hold_time_hs_mode = 0x0b0b0b,
2142 .has_interface_timing_reg = true,
2143 .enable_hs_mode_support = true,
2144 .has_mutex = true,
2145 .variant = TEGRA_I2C_VARIANT_DEFAULT,
2146 .regs = &tegra410_i2c_regs,
2147 };
2148
2149 static const struct of_device_id tegra_i2c_of_match[] = {
2150 { .compatible = "nvidia,tegra264-i2c", .data = &tegra264_i2c_hw, },
2151 { .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, },
2152 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
2153 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
2154 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
2155 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_vi_i2c_hw, },
2156 #endif
2157 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
2158 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
2159 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
2160 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
2161 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
2162 #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
2163 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_dvc_i2c_hw, },
2164 #endif
2165 {},
2166 };
2167 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
2168
tegra_i2c_parse_dt(struct tegra_i2c_dev * i2c_dev)2169 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
2170 {
2171 bool multi_mode;
2172
2173 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true);
2174
2175 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master");
2176 i2c_dev->multimaster_mode = multi_mode;
2177 }
2178
tegra_i2c_init_clocks(struct tegra_i2c_dev * i2c_dev)2179 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)
2180 {
2181 int err;
2182
2183 if (ACPI_HANDLE(i2c_dev->dev))
2184 return 0;
2185
2186 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
2187
2188 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw)
2189 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk";
2190
2191 if (IS_VI(i2c_dev))
2192 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow";
2193
2194 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks,
2195 i2c_dev->clocks);
2196 if (err)
2197 return err;
2198
2199 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks);
2200 if (err)
2201 return err;
2202
2203 i2c_dev->div_clk = i2c_dev->clocks[0].clk;
2204
2205 if (!i2c_dev->multimaster_mode)
2206 return 0;
2207
2208 err = clk_enable(i2c_dev->div_clk);
2209 if (err) {
2210 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err);
2211 goto unprepare_clocks;
2212 }
2213
2214 return 0;
2215
2216 unprepare_clocks:
2217 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
2218
2219 return err;
2220 }
2221
tegra_i2c_release_clocks(struct tegra_i2c_dev * i2c_dev)2222 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev)
2223 {
2224 if (i2c_dev->multimaster_mode)
2225 clk_disable(i2c_dev->div_clk);
2226
2227 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
2228 }
2229
tegra_i2c_init_hardware(struct tegra_i2c_dev * i2c_dev)2230 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev)
2231 {
2232 int ret;
2233
2234 ret = pm_runtime_get_sync(i2c_dev->dev);
2235 if (ret < 0)
2236 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret);
2237 else
2238 ret = tegra_i2c_init(i2c_dev);
2239
2240 pm_runtime_put_sync(i2c_dev->dev);
2241
2242 return ret;
2243 }
2244
tegra_i2c_probe(struct platform_device * pdev)2245 static int tegra_i2c_probe(struct platform_device *pdev)
2246 {
2247 struct tegra_i2c_dev *i2c_dev;
2248 struct resource *res;
2249 int err;
2250
2251 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2252 if (!i2c_dev)
2253 return -ENOMEM;
2254
2255 platform_set_drvdata(pdev, i2c_dev);
2256
2257 init_completion(&i2c_dev->msg_complete);
2258 init_completion(&i2c_dev->dma_complete);
2259
2260 i2c_dev->hw = device_get_match_data(&pdev->dev);
2261 i2c_dev->cont_id = pdev->id;
2262 i2c_dev->dev = &pdev->dev;
2263
2264 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2265 if (IS_ERR(i2c_dev->base))
2266 return PTR_ERR(i2c_dev->base);
2267
2268 i2c_dev->base_phys = res->start;
2269
2270 err = platform_get_irq(pdev, 0);
2271 if (err < 0)
2272 return err;
2273
2274 i2c_dev->irq = err;
2275
2276 /* interrupt will be enabled during of transfer time */
2277 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
2278
2279 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq,
2280 NULL, tegra_i2c_isr,
2281 IRQF_NO_SUSPEND | IRQF_ONESHOT,
2282 dev_name(i2c_dev->dev), i2c_dev);
2283 if (err)
2284 return err;
2285
2286 tegra_i2c_parse_dt(i2c_dev);
2287
2288 err = tegra_i2c_init_clocks(i2c_dev);
2289 if (err)
2290 return err;
2291
2292 err = tegra_i2c_init_dma(i2c_dev);
2293 if (err)
2294 goto release_clocks;
2295
2296 /*
2297 * VI I2C is in VE power domain which is not always ON and not
2298 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a
2299 * non IRQ-safe domain because this prevents powering off the power
2300 * domain.
2301 *
2302 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't
2303 * be used for atomic transfers. ACPI device is not IRQ safe also.
2304 *
2305 * Devices with pinctrl states cannot be marked IRQ-safe as the pinctrl
2306 * state transitions during runtime PM require mutexes.
2307 */
2308 if (!IS_VI(i2c_dev) && !has_acpi_companion(i2c_dev->dev) && !i2c_dev->dev->pins)
2309 pm_runtime_irq_safe(i2c_dev->dev);
2310
2311 pm_runtime_enable(i2c_dev->dev);
2312
2313 err = tegra_i2c_init_hardware(i2c_dev);
2314 if (err)
2315 goto release_rpm;
2316
2317 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
2318 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node;
2319 i2c_dev->adapter.dev.parent = i2c_dev->dev;
2320 i2c_dev->adapter.retries = 1;
2321 i2c_dev->adapter.timeout = 6 * HZ;
2322 i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
2323 i2c_dev->adapter.owner = THIS_MODULE;
2324 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
2325 i2c_dev->adapter.algo = &tegra_i2c_algo;
2326 i2c_dev->adapter.nr = pdev->id;
2327 ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev));
2328
2329 if (i2c_dev->hw->supports_bus_clear)
2330 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
2331
2332 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
2333 sizeof(i2c_dev->adapter.name));
2334
2335 err = i2c_add_numbered_adapter(&i2c_dev->adapter);
2336 if (err)
2337 goto release_rpm;
2338
2339 return 0;
2340
2341 release_rpm:
2342 pm_runtime_disable(i2c_dev->dev);
2343
2344 tegra_i2c_release_dma(i2c_dev);
2345 release_clocks:
2346 tegra_i2c_release_clocks(i2c_dev);
2347
2348 return err;
2349 }
2350
tegra_i2c_remove(struct platform_device * pdev)2351 static void tegra_i2c_remove(struct platform_device *pdev)
2352 {
2353 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2354
2355 i2c_del_adapter(&i2c_dev->adapter);
2356 pm_runtime_force_suspend(i2c_dev->dev);
2357
2358 tegra_i2c_release_dma(i2c_dev);
2359 tegra_i2c_release_clocks(i2c_dev);
2360 }
2361
tegra_i2c_runtime_resume(struct device * dev)2362 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
2363 {
2364 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2365 int err;
2366
2367 err = pinctrl_pm_select_default_state(dev);
2368 if (err)
2369 return err;
2370
2371 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks);
2372 if (err)
2373 return err;
2374
2375 /*
2376 * VI I2C device is attached to VE power domain which goes through
2377 * power ON/OFF during runtime PM resume/suspend, meaning that
2378 * controller needs to be re-initialized after power ON.
2379 */
2380 if (IS_VI(i2c_dev)) {
2381 err = tegra_i2c_init(i2c_dev);
2382 if (err)
2383 goto disable_clocks;
2384 }
2385
2386 return 0;
2387
2388 disable_clocks:
2389 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
2390
2391 return err;
2392 }
2393
tegra_i2c_runtime_suspend(struct device * dev)2394 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
2395 {
2396 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2397
2398 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
2399
2400 return pinctrl_pm_select_idle_state(dev);
2401 }
2402
tegra_i2c_suspend(struct device * dev)2403 static int __maybe_unused tegra_i2c_suspend(struct device *dev)
2404 {
2405 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2406 int err;
2407
2408 i2c_mark_adapter_suspended(&i2c_dev->adapter);
2409
2410 if (!pm_runtime_status_suspended(dev)) {
2411 err = tegra_i2c_runtime_suspend(dev);
2412 if (err)
2413 return err;
2414 }
2415
2416 return 0;
2417 }
2418
tegra_i2c_resume(struct device * dev)2419 static int __maybe_unused tegra_i2c_resume(struct device *dev)
2420 {
2421 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2422 int err;
2423
2424 /*
2425 * We need to ensure that clocks are enabled so that registers can be
2426 * restored in tegra_i2c_init().
2427 */
2428 err = tegra_i2c_runtime_resume(dev);
2429 if (err)
2430 return err;
2431
2432 err = tegra_i2c_init(i2c_dev);
2433 if (err)
2434 return err;
2435
2436 /*
2437 * In case we are runtime suspended, disable clocks again so that we
2438 * don't unbalance the clock reference counts during the next runtime
2439 * resume transition.
2440 */
2441 if (pm_runtime_status_suspended(dev)) {
2442 err = tegra_i2c_runtime_suspend(dev);
2443 if (err)
2444 return err;
2445 }
2446
2447 i2c_mark_adapter_resumed(&i2c_dev->adapter);
2448
2449 return 0;
2450 }
2451
2452 static const struct dev_pm_ops tegra_i2c_pm = {
2453 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
2454 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
2455 NULL)
2456 };
2457
2458 static const struct acpi_device_id tegra_i2c_acpi_match[] = {
2459 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw},
2460 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw},
2461 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw},
2462 {.id = "NVDA2017", .driver_data = (kernel_ulong_t)&tegra410_i2c_hw},
2463 { }
2464 };
2465 MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match);
2466
2467 static struct platform_driver tegra_i2c_driver = {
2468 .probe = tegra_i2c_probe,
2469 .remove = tegra_i2c_remove,
2470 .driver = {
2471 .name = "tegra-i2c",
2472 .of_match_table = tegra_i2c_of_match,
2473 .acpi_match_table = tegra_i2c_acpi_match,
2474 .pm = &tegra_i2c_pm,
2475 },
2476 };
2477 module_platform_driver(tegra_i2c_driver);
2478
2479 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver");
2480 MODULE_AUTHOR("Colin Cross");
2481 MODULE_LICENSE("GPL v2");
2482