1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * NVIDIA Tegra Video decoder driver 4 * 5 * Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com> 6 * 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/dma-buf.h> 11 #include <linux/genalloc.h> 12 #include <linux/interrupt.h> 13 #include <linux/list.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 #include <linux/uaccess.h> 21 22 #include <soc/tegra/common.h> 23 #include <soc/tegra/pmc.h> 24 25 #include "vde.h" 26 27 #define CREATE_TRACE_POINTS 28 #include "trace.h" 29 30 void tegra_vde_writel(struct tegra_vde *vde, u32 value, 31 void __iomem *base, u32 offset) 32 { 33 trace_vde_writel(vde, base, offset, value); 34 35 writel_relaxed(value, base + offset); 36 } 37 38 u32 tegra_vde_readl(struct tegra_vde *vde, void __iomem *base, u32 offset) 39 { 40 u32 value = readl_relaxed(base + offset); 41 42 trace_vde_readl(vde, base, offset, value); 43 44 return value; 45 } 46 47 void tegra_vde_set_bits(struct tegra_vde *vde, u32 mask, 48 void __iomem *base, u32 offset) 49 { 50 u32 value = tegra_vde_readl(vde, base, offset); 51 52 tegra_vde_writel(vde, value | mask, base, offset); 53 } 54 55 int tegra_vde_alloc_bo(struct tegra_vde *vde, 56 struct tegra_vde_bo **ret_bo, 57 enum dma_data_direction dma_dir, 58 size_t size) 59 { 60 struct device *dev = vde->dev; 61 struct tegra_vde_bo *bo; 62 int err; 63 64 bo = kzalloc_obj(*bo); 65 if (!bo) 66 return -ENOMEM; 67 68 bo->vde = vde; 69 bo->size = size; 70 bo->dma_dir = dma_dir; 71 bo->dma_attrs = DMA_ATTR_WRITE_COMBINE | 72 DMA_ATTR_NO_KERNEL_MAPPING; 73 74 if (!vde->domain) 75 bo->dma_attrs |= DMA_ATTR_FORCE_CONTIGUOUS; 76 77 bo->dma_cookie = dma_alloc_attrs(dev, bo->size, &bo->dma_handle, 78 GFP_KERNEL, bo->dma_attrs); 79 if (!bo->dma_cookie) { 80 dev_err(dev, "Failed to allocate DMA buffer of size: %zu\n", 81 bo->size); 82 err = -ENOMEM; 83 goto free_bo; 84 } 85 86 err = dma_get_sgtable_attrs(dev, &bo->sgt, bo->dma_cookie, 87 bo->dma_handle, bo->size, bo->dma_attrs); 88 if (err) { 89 dev_err(dev, "Failed to get DMA buffer SG table: %d\n", err); 90 goto free_attrs; 91 } 92 93 err = dma_map_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs); 94 if (err) { 95 dev_err(dev, "Failed to map DMA buffer SG table: %d\n", err); 96 goto free_table; 97 } 98 99 if (vde->domain) { 100 err = tegra_vde_iommu_map(vde, &bo->sgt, &bo->iova, bo->size); 101 if (err) { 102 dev_err(dev, "Failed to map DMA buffer IOVA: %d\n", err); 103 goto unmap_sgtable; 104 } 105 106 bo->dma_addr = iova_dma_addr(&vde->iova, bo->iova); 107 } else { 108 bo->dma_addr = sg_dma_address(bo->sgt.sgl); 109 } 110 111 *ret_bo = bo; 112 113 return 0; 114 115 unmap_sgtable: 116 dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs); 117 free_table: 118 sg_free_table(&bo->sgt); 119 free_attrs: 120 dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle, 121 bo->dma_attrs); 122 free_bo: 123 kfree(bo); 124 125 return err; 126 } 127 128 void tegra_vde_free_bo(struct tegra_vde_bo *bo) 129 { 130 struct tegra_vde *vde = bo->vde; 131 struct device *dev = vde->dev; 132 133 if (vde->domain) 134 tegra_vde_iommu_unmap(vde, bo->iova); 135 136 dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs); 137 138 sg_free_table(&bo->sgt); 139 140 dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle, 141 bo->dma_attrs); 142 kfree(bo); 143 } 144 145 static irqreturn_t tegra_vde_isr(int irq, void *data) 146 { 147 struct tegra_vde *vde = data; 148 149 if (completion_done(&vde->decode_completion)) 150 return IRQ_NONE; 151 152 tegra_vde_set_bits(vde, 0, vde->frameid, 0x208); 153 complete(&vde->decode_completion); 154 155 return IRQ_HANDLED; 156 } 157 158 static __maybe_unused int tegra_vde_runtime_suspend(struct device *dev) 159 { 160 struct tegra_vde *vde = dev_get_drvdata(dev); 161 int err; 162 163 if (!dev->pm_domain) { 164 err = tegra_pmc_powergate_power_off(vde->pmc, 165 TEGRA_POWERGATE_VDEC); 166 if (err) { 167 dev_err(dev, "Failed to power down HW: %d\n", err); 168 return err; 169 } 170 } 171 172 clk_disable_unprepare(vde->clk); 173 reset_control_release(vde->rst); 174 reset_control_release(vde->rst_mc); 175 176 return 0; 177 } 178 179 static __maybe_unused int tegra_vde_runtime_resume(struct device *dev) 180 { 181 struct tegra_vde *vde = dev_get_drvdata(dev); 182 int err; 183 184 err = reset_control_acquire(vde->rst_mc); 185 if (err) { 186 dev_err(dev, "Failed to acquire mc reset: %d\n", err); 187 return err; 188 } 189 190 err = reset_control_acquire(vde->rst); 191 if (err) { 192 dev_err(dev, "Failed to acquire reset: %d\n", err); 193 goto release_mc_reset; 194 } 195 196 if (!dev->pm_domain) { 197 err = tegra_pmc_powergate_sequence_power_up(vde->pmc, 198 TEGRA_POWERGATE_VDEC, 199 vde->clk, vde->rst); 200 if (err) { 201 dev_err(dev, "Failed to power up HW : %d\n", err); 202 goto release_reset; 203 } 204 } else { 205 /* 206 * tegra_pmc_powergate_sequence_power_up() leaves clocks enabled, 207 * while GENPD not. 208 */ 209 err = clk_prepare_enable(vde->clk); 210 if (err) { 211 dev_err(dev, "Failed to enable clock: %d\n", err); 212 goto release_reset; 213 } 214 } 215 216 return 0; 217 218 release_reset: 219 reset_control_release(vde->rst); 220 release_mc_reset: 221 reset_control_release(vde->rst_mc); 222 223 return err; 224 } 225 226 static int tegra_vde_probe(struct platform_device *pdev) 227 { 228 struct device *dev = &pdev->dev; 229 struct tegra_vde *vde; 230 int irq, err; 231 232 vde = devm_kzalloc(dev, sizeof(*vde), GFP_KERNEL); 233 if (!vde) 234 return -ENOMEM; 235 236 platform_set_drvdata(pdev, vde); 237 238 vde->soc = of_device_get_match_data(&pdev->dev); 239 vde->dev = dev; 240 241 vde->sxe = devm_platform_ioremap_resource_byname(pdev, "sxe"); 242 if (IS_ERR(vde->sxe)) 243 return PTR_ERR(vde->sxe); 244 245 vde->bsev = devm_platform_ioremap_resource_byname(pdev, "bsev"); 246 if (IS_ERR(vde->bsev)) 247 return PTR_ERR(vde->bsev); 248 249 vde->mbe = devm_platform_ioremap_resource_byname(pdev, "mbe"); 250 if (IS_ERR(vde->mbe)) 251 return PTR_ERR(vde->mbe); 252 253 vde->ppe = devm_platform_ioremap_resource_byname(pdev, "ppe"); 254 if (IS_ERR(vde->ppe)) 255 return PTR_ERR(vde->ppe); 256 257 vde->mce = devm_platform_ioremap_resource_byname(pdev, "mce"); 258 if (IS_ERR(vde->mce)) 259 return PTR_ERR(vde->mce); 260 261 vde->tfe = devm_platform_ioremap_resource_byname(pdev, "tfe"); 262 if (IS_ERR(vde->tfe)) 263 return PTR_ERR(vde->tfe); 264 265 vde->ppb = devm_platform_ioremap_resource_byname(pdev, "ppb"); 266 if (IS_ERR(vde->ppb)) 267 return PTR_ERR(vde->ppb); 268 269 vde->vdma = devm_platform_ioremap_resource_byname(pdev, "vdma"); 270 if (IS_ERR(vde->vdma)) 271 return PTR_ERR(vde->vdma); 272 273 vde->frameid = devm_platform_ioremap_resource_byname(pdev, "frameid"); 274 if (IS_ERR(vde->frameid)) 275 return PTR_ERR(vde->frameid); 276 277 vde->clk = devm_clk_get(dev, NULL); 278 if (IS_ERR(vde->clk)) { 279 err = PTR_ERR(vde->clk); 280 dev_err(dev, "Could not get VDE clk %d\n", err); 281 return err; 282 } 283 284 vde->rst = devm_reset_control_get_exclusive_released(dev, NULL); 285 if (IS_ERR(vde->rst)) { 286 err = PTR_ERR(vde->rst); 287 dev_err(dev, "Could not get VDE reset %d\n", err); 288 return err; 289 } 290 291 vde->rst_mc = devm_reset_control_get_optional_exclusive_released(dev, "mc"); 292 if (IS_ERR(vde->rst_mc)) { 293 err = PTR_ERR(vde->rst_mc); 294 dev_err(dev, "Could not get MC reset %d\n", err); 295 return err; 296 } 297 298 vde->pmc = devm_tegra_pmc_get(dev); 299 if (IS_ERR(vde->pmc)) 300 return dev_err_probe(dev, PTR_ERR(vde->pmc), 301 "failed to get PMC\n"); 302 303 irq = platform_get_irq_byname(pdev, "sync-token"); 304 if (irq < 0) 305 return irq; 306 307 err = devm_request_irq(dev, irq, tegra_vde_isr, 0, 308 dev_name(dev), vde); 309 if (err) { 310 dev_err(dev, "Could not request IRQ %d\n", err); 311 return err; 312 } 313 314 err = devm_tegra_core_dev_init_opp_table_common(dev); 315 if (err) { 316 dev_err(dev, "Could initialize OPP table %d\n", err); 317 return err; 318 } 319 320 vde->iram_pool = of_gen_pool_get(dev->of_node, "iram", 0); 321 if (!vde->iram_pool) { 322 dev_err(dev, "Could not get IRAM pool\n"); 323 return -EPROBE_DEFER; 324 } 325 326 vde->iram = gen_pool_dma_alloc(vde->iram_pool, 327 gen_pool_size(vde->iram_pool), 328 &vde->iram_lists_addr); 329 if (!vde->iram) { 330 dev_err(dev, "Could not reserve IRAM\n"); 331 return -ENOMEM; 332 } 333 334 INIT_LIST_HEAD(&vde->map_list); 335 mutex_init(&vde->map_lock); 336 mutex_init(&vde->lock); 337 init_completion(&vde->decode_completion); 338 339 err = tegra_vde_iommu_init(vde); 340 if (err) { 341 dev_err(dev, "Failed to initialize IOMMU: %d\n", err); 342 goto err_gen_free; 343 } 344 345 pm_runtime_enable(dev); 346 pm_runtime_use_autosuspend(dev); 347 pm_runtime_set_autosuspend_delay(dev, 300); 348 349 /* 350 * VDE partition may be left ON after bootloader, hence let's 351 * power-cycle it in order to put hardware into a predictable lower 352 * power state. 353 */ 354 err = pm_runtime_resume_and_get(dev); 355 if (err) 356 goto err_pm_runtime; 357 358 pm_runtime_put(dev); 359 360 err = tegra_vde_alloc_bo(vde, &vde->secure_bo, DMA_FROM_DEVICE, 4096); 361 if (err) { 362 dev_err(dev, "Failed to allocate secure BO: %d\n", err); 363 goto err_pm_runtime; 364 } 365 366 err = tegra_vde_v4l2_init(vde); 367 if (err) { 368 dev_err(dev, "Failed to initialize V4L2: %d\n", err); 369 goto err_free_secure_bo; 370 } 371 372 return 0; 373 374 err_free_secure_bo: 375 tegra_vde_free_bo(vde->secure_bo); 376 err_pm_runtime: 377 pm_runtime_dont_use_autosuspend(dev); 378 pm_runtime_disable(dev); 379 380 tegra_vde_iommu_deinit(vde); 381 382 err_gen_free: 383 gen_pool_free(vde->iram_pool, (unsigned long)vde->iram, 384 gen_pool_size(vde->iram_pool)); 385 386 return err; 387 } 388 389 static void tegra_vde_remove(struct platform_device *pdev) 390 { 391 struct tegra_vde *vde = platform_get_drvdata(pdev); 392 struct device *dev = &pdev->dev; 393 394 tegra_vde_v4l2_deinit(vde); 395 tegra_vde_free_bo(vde->secure_bo); 396 397 /* 398 * As it increments RPM usage_count even on errors, we don't need to 399 * check the returned code here. 400 */ 401 pm_runtime_get_sync(dev); 402 403 pm_runtime_dont_use_autosuspend(dev); 404 pm_runtime_disable(dev); 405 406 /* 407 * Balance RPM state, the VDE power domain is left ON and hardware 408 * is clock-gated. It's safe to reboot machine now. 409 */ 410 pm_runtime_put_noidle(dev); 411 clk_disable_unprepare(vde->clk); 412 413 tegra_vde_dmabuf_cache_unmap_all(vde); 414 tegra_vde_iommu_deinit(vde); 415 416 gen_pool_free(vde->iram_pool, (unsigned long)vde->iram, 417 gen_pool_size(vde->iram_pool)); 418 } 419 420 static void tegra_vde_shutdown(struct platform_device *pdev) 421 { 422 /* 423 * On some devices bootloader isn't ready to a power-gated VDE on 424 * a warm-reboot, machine will hang in that case. 425 */ 426 pm_runtime_get_sync(&pdev->dev); 427 } 428 429 static __maybe_unused int tegra_vde_pm_suspend(struct device *dev) 430 { 431 struct tegra_vde *vde = dev_get_drvdata(dev); 432 int err; 433 434 mutex_lock(&vde->lock); 435 436 err = pm_runtime_force_suspend(dev); 437 if (err < 0) 438 return err; 439 440 return 0; 441 } 442 443 static __maybe_unused int tegra_vde_pm_resume(struct device *dev) 444 { 445 struct tegra_vde *vde = dev_get_drvdata(dev); 446 int err; 447 448 err = pm_runtime_force_resume(dev); 449 if (err < 0) 450 return err; 451 452 mutex_unlock(&vde->lock); 453 454 return 0; 455 } 456 457 static const struct dev_pm_ops tegra_vde_pm_ops = { 458 SET_RUNTIME_PM_OPS(tegra_vde_runtime_suspend, 459 tegra_vde_runtime_resume, 460 NULL) 461 SET_SYSTEM_SLEEP_PM_OPS(tegra_vde_pm_suspend, 462 tegra_vde_pm_resume) 463 }; 464 465 static const u32 tegra124_decoded_fmts[] = { 466 /* TBD: T124 supports only a non-standard Tegra tiled format */ 467 }; 468 469 static const struct tegra_coded_fmt_desc tegra124_coded_fmts[] = { 470 { 471 .fourcc = V4L2_PIX_FMT_H264_SLICE, 472 .frmsize = { 473 .min_width = 16, 474 .max_width = 1920, 475 .step_width = 16, 476 .min_height = 16, 477 .max_height = 2032, 478 .step_height = 16, 479 }, 480 .num_decoded_fmts = ARRAY_SIZE(tegra124_decoded_fmts), 481 .decoded_fmts = tegra124_decoded_fmts, 482 .decode_run = tegra_vde_h264_decode_run, 483 .decode_wait = tegra_vde_h264_decode_wait, 484 }, 485 }; 486 487 static const u32 tegra20_decoded_fmts[] = { 488 V4L2_PIX_FMT_YUV420M, 489 V4L2_PIX_FMT_YVU420M, 490 }; 491 492 static const struct tegra_coded_fmt_desc tegra20_coded_fmts[] = { 493 { 494 .fourcc = V4L2_PIX_FMT_H264_SLICE, 495 .frmsize = { 496 .min_width = 16, 497 .max_width = 1920, 498 .step_width = 16, 499 .min_height = 16, 500 .max_height = 2032, 501 .step_height = 16, 502 }, 503 .num_decoded_fmts = ARRAY_SIZE(tegra20_decoded_fmts), 504 .decoded_fmts = tegra20_decoded_fmts, 505 .decode_run = tegra_vde_h264_decode_run, 506 .decode_wait = tegra_vde_h264_decode_wait, 507 }, 508 }; 509 510 static const struct tegra_vde_soc tegra124_vde_soc = { 511 .supports_ref_pic_marking = true, 512 .coded_fmts = tegra124_coded_fmts, 513 .num_coded_fmts = ARRAY_SIZE(tegra124_coded_fmts), 514 }; 515 516 static const struct tegra_vde_soc tegra114_vde_soc = { 517 .supports_ref_pic_marking = true, 518 .coded_fmts = tegra20_coded_fmts, 519 .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts), 520 }; 521 522 static const struct tegra_vde_soc tegra30_vde_soc = { 523 .supports_ref_pic_marking = false, 524 .coded_fmts = tegra20_coded_fmts, 525 .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts), 526 }; 527 528 static const struct tegra_vde_soc tegra20_vde_soc = { 529 .supports_ref_pic_marking = false, 530 .coded_fmts = tegra20_coded_fmts, 531 .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts), 532 }; 533 534 static const struct of_device_id tegra_vde_of_match[] = { 535 { .compatible = "nvidia,tegra124-vde", .data = &tegra124_vde_soc }, 536 { .compatible = "nvidia,tegra114-vde", .data = &tegra114_vde_soc }, 537 { .compatible = "nvidia,tegra30-vde", .data = &tegra30_vde_soc }, 538 { .compatible = "nvidia,tegra20-vde", .data = &tegra20_vde_soc }, 539 { }, 540 }; 541 MODULE_DEVICE_TABLE(of, tegra_vde_of_match); 542 543 static struct platform_driver tegra_vde_driver = { 544 .probe = tegra_vde_probe, 545 .remove = tegra_vde_remove, 546 .shutdown = tegra_vde_shutdown, 547 .driver = { 548 .name = "tegra-vde", 549 .of_match_table = tegra_vde_of_match, 550 .pm = &tegra_vde_pm_ops, 551 }, 552 }; 553 module_platform_driver(tegra_vde_driver); 554 555 MODULE_DESCRIPTION("NVIDIA Tegra Video Decoder driver"); 556 MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>"); 557 MODULE_LICENSE("GPL"); 558