1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ADC driver for the Ingenic JZ47xx SoCs
4 * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
5 *
6 * based on drivers/mfd/jz4740-adc.c
7 */
8
9 #include <dt-bindings/iio/adc/ingenic,adc.h>
10
11 #include <linux/cleanup.h>
12 #include <linux/clk.h>
13 #include <linux/iio/buffer.h>
14 #include <linux/iio/iio.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/iopoll.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/of.h>
22 #include <linux/platform_device.h>
23 #include <linux/property.h>
24
25 #define JZ_ADC_REG_ENABLE 0x00
26 #define JZ_ADC_REG_CFG 0x04
27 #define JZ_ADC_REG_CTRL 0x08
28 #define JZ_ADC_REG_STATUS 0x0c
29 #define JZ_ADC_REG_ADSAME 0x10
30 #define JZ_ADC_REG_ADWAIT 0x14
31 #define JZ_ADC_REG_ADTCH 0x18
32 #define JZ_ADC_REG_ADBDAT 0x1c
33 #define JZ_ADC_REG_ADSDAT 0x20
34 #define JZ_ADC_REG_ADCMD 0x24
35 #define JZ_ADC_REG_ADCLK 0x28
36
37 #define JZ_ADC_REG_ENABLE_PD BIT(7)
38 #define JZ_ADC_REG_CFG_AUX_MD (BIT(0) | BIT(1))
39 #define JZ_ADC_REG_CFG_BAT_MD BIT(4)
40 #define JZ_ADC_REG_CFG_SAMPLE_NUM(n) ((n) << 10)
41 #define JZ_ADC_REG_CFG_PULL_UP(n) ((n) << 16)
42 #define JZ_ADC_REG_CFG_CMD_SEL BIT(22)
43 #define JZ_ADC_REG_CFG_VBAT_SEL BIT(30)
44 #define JZ_ADC_REG_CFG_TOUCH_OPS_MASK (BIT(31) | GENMASK(23, 10))
45 #define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0
46 #define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB 16
47 #define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB 8
48 #define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB 16
49
50 #define JZ_ADC_REG_ADCMD_YNADC BIT(7)
51 #define JZ_ADC_REG_ADCMD_YPADC BIT(8)
52 #define JZ_ADC_REG_ADCMD_XNADC BIT(9)
53 #define JZ_ADC_REG_ADCMD_XPADC BIT(10)
54 #define JZ_ADC_REG_ADCMD_VREFPYP BIT(11)
55 #define JZ_ADC_REG_ADCMD_VREFPXP BIT(12)
56 #define JZ_ADC_REG_ADCMD_VREFPXN BIT(13)
57 #define JZ_ADC_REG_ADCMD_VREFPAUX BIT(14)
58 #define JZ_ADC_REG_ADCMD_VREFPVDD33 BIT(15)
59 #define JZ_ADC_REG_ADCMD_VREFNYN BIT(16)
60 #define JZ_ADC_REG_ADCMD_VREFNXP BIT(17)
61 #define JZ_ADC_REG_ADCMD_VREFNXN BIT(18)
62 #define JZ_ADC_REG_ADCMD_VREFAUX BIT(19)
63 #define JZ_ADC_REG_ADCMD_YNGRU BIT(20)
64 #define JZ_ADC_REG_ADCMD_XNGRU BIT(21)
65 #define JZ_ADC_REG_ADCMD_XPGRU BIT(22)
66 #define JZ_ADC_REG_ADCMD_YPSUP BIT(23)
67 #define JZ_ADC_REG_ADCMD_XNSUP BIT(24)
68 #define JZ_ADC_REG_ADCMD_XPSUP BIT(25)
69
70 #define JZ_ADC_AUX_VREF 3300
71 #define JZ_ADC_AUX_VREF_BITS 12
72 #define JZ_ADC_BATTERY_LOW_VREF 2500
73 #define JZ_ADC_BATTERY_LOW_VREF_BITS 12
74 #define JZ4725B_ADC_BATTERY_HIGH_VREF 7500
75 #define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS 10
76 #define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986)
77 #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12
78 #define JZ4760_ADC_BATTERY_VREF 2500
79 #define JZ4770_ADC_BATTERY_VREF 1200
80 #define JZ4770_ADC_BATTERY_VREF_BITS 12
81
82 #define JZ_ADC_IRQ_AUX BIT(0)
83 #define JZ_ADC_IRQ_BATTERY BIT(1)
84 #define JZ_ADC_IRQ_TOUCH BIT(2)
85 #define JZ_ADC_IRQ_PEN_DOWN BIT(3)
86 #define JZ_ADC_IRQ_PEN_UP BIT(4)
87 #define JZ_ADC_IRQ_PEN_DOWN_SLEEP BIT(5)
88 #define JZ_ADC_IRQ_SLEEP BIT(7)
89
90 struct ingenic_adc;
91
92 struct ingenic_adc_soc_data {
93 unsigned int battery_high_vref;
94 unsigned int battery_high_vref_bits;
95 const int *battery_raw_avail;
96 size_t battery_raw_avail_size;
97 const int *battery_scale_avail;
98 size_t battery_scale_avail_size;
99 unsigned int battery_vref_mode: 1;
100 unsigned int has_aux_md: 1;
101 const struct iio_chan_spec *channels;
102 unsigned int num_channels;
103 int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
104 };
105
106 struct ingenic_adc {
107 void __iomem *base;
108 struct clk *clk;
109 struct mutex lock;
110 struct mutex aux_lock;
111 const struct ingenic_adc_soc_data *soc_data;
112 bool low_vref_mode;
113 };
114
ingenic_adc_set_adcmd(struct iio_dev * iio_dev,unsigned long mask)115 static void ingenic_adc_set_adcmd(struct iio_dev *iio_dev, unsigned long mask)
116 {
117 struct ingenic_adc *adc = iio_priv(iio_dev);
118
119 guard(mutex)(&adc->lock);
120
121 /* Init ADCMD */
122 readl(adc->base + JZ_ADC_REG_ADCMD);
123
124 if (mask & 0x3) {
125 /* Second channel (INGENIC_ADC_TOUCH_YP): sample YP vs. GND */
126 writel(JZ_ADC_REG_ADCMD_XNGRU
127 | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
128 | JZ_ADC_REG_ADCMD_YPADC,
129 adc->base + JZ_ADC_REG_ADCMD);
130
131 /* First channel (INGENIC_ADC_TOUCH_XP): sample XP vs. GND */
132 writel(JZ_ADC_REG_ADCMD_YNGRU
133 | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
134 | JZ_ADC_REG_ADCMD_XPADC,
135 adc->base + JZ_ADC_REG_ADCMD);
136 }
137
138 if (mask & 0xc) {
139 /* Fourth channel (INGENIC_ADC_TOUCH_YN): sample YN vs. GND */
140 writel(JZ_ADC_REG_ADCMD_XNGRU
141 | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
142 | JZ_ADC_REG_ADCMD_YNADC,
143 adc->base + JZ_ADC_REG_ADCMD);
144
145 /* Third channel (INGENIC_ADC_TOUCH_XN): sample XN vs. GND */
146 writel(JZ_ADC_REG_ADCMD_YNGRU
147 | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
148 | JZ_ADC_REG_ADCMD_XNADC,
149 adc->base + JZ_ADC_REG_ADCMD);
150 }
151
152 if (mask & 0x30) {
153 /* Sixth channel (INGENIC_ADC_TOUCH_YD): sample YP vs. YN */
154 writel(JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
155 | JZ_ADC_REG_ADCMD_YPADC,
156 adc->base + JZ_ADC_REG_ADCMD);
157
158 /* Fifth channel (INGENIC_ADC_TOUCH_XD): sample XP vs. XN */
159 writel(JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
160 | JZ_ADC_REG_ADCMD_XPADC,
161 adc->base + JZ_ADC_REG_ADCMD);
162 }
163
164 /* We're done */
165 writel(0, adc->base + JZ_ADC_REG_ADCMD);
166 }
167
ingenic_adc_set_config(struct ingenic_adc * adc,uint32_t mask,uint32_t val)168 static void ingenic_adc_set_config(struct ingenic_adc *adc,
169 uint32_t mask,
170 uint32_t val)
171 {
172 uint32_t cfg;
173
174 guard(mutex)(&adc->lock);
175
176 cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask;
177 cfg |= val;
178 writel(cfg, adc->base + JZ_ADC_REG_CFG);
179 }
180
__ingenic_adc_enable(struct ingenic_adc * adc,int engine,bool enabled)181 static void __ingenic_adc_enable(struct ingenic_adc *adc, int engine,
182 bool enabled)
183 {
184 u8 val;
185
186 val = readb(adc->base + JZ_ADC_REG_ENABLE);
187
188 if (enabled)
189 val |= BIT(engine);
190 else
191 val &= ~BIT(engine);
192
193 writeb(val, adc->base + JZ_ADC_REG_ENABLE);
194 }
195
ingenic_adc_enable(struct ingenic_adc * adc,int engine,bool enabled)196 static void ingenic_adc_enable(struct ingenic_adc *adc,
197 int engine,
198 bool enabled)
199 {
200 guard(mutex)(&adc->lock);
201 __ingenic_adc_enable(adc, engine, enabled);
202 }
203
ingenic_adc_capture(struct ingenic_adc * adc,int engine)204 static int ingenic_adc_capture(struct ingenic_adc *adc,
205 int engine)
206 {
207 u32 cfg;
208 u8 val;
209 int ret;
210
211 /*
212 * Disable CMD_SEL temporarily, because it causes wrong VBAT readings,
213 * probably due to the switch of VREF. We must keep the lock here to
214 * avoid races with the buffer enable/disable functions.
215 */
216 guard(mutex)(&adc->lock);
217 cfg = readl(adc->base + JZ_ADC_REG_CFG);
218 writel(cfg & ~JZ_ADC_REG_CFG_CMD_SEL, adc->base + JZ_ADC_REG_CFG);
219
220 __ingenic_adc_enable(adc, engine, true);
221 ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
222 !(val & BIT(engine)), 250, 1000);
223 if (ret)
224 __ingenic_adc_enable(adc, engine, false);
225
226 writel(cfg, adc->base + JZ_ADC_REG_CFG);
227
228 return ret;
229 }
230
ingenic_adc_write_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,int val,int val2,long m)231 static int ingenic_adc_write_raw(struct iio_dev *iio_dev,
232 struct iio_chan_spec const *chan,
233 int val,
234 int val2,
235 long m)
236 {
237 struct ingenic_adc *adc = iio_priv(iio_dev);
238 struct device *dev = iio_dev->dev.parent;
239 int ret;
240
241 switch (m) {
242 case IIO_CHAN_INFO_SCALE:
243 switch (chan->channel) {
244 case INGENIC_ADC_BATTERY:
245 if (!adc->soc_data->battery_vref_mode)
246 return -EINVAL;
247
248 ret = clk_enable(adc->clk);
249 if (ret) {
250 dev_err(dev, "Failed to enable clock: %d\n",
251 ret);
252 return ret;
253 }
254
255 if (val > JZ_ADC_BATTERY_LOW_VREF) {
256 ingenic_adc_set_config(adc,
257 JZ_ADC_REG_CFG_BAT_MD,
258 0);
259 adc->low_vref_mode = false;
260 } else {
261 ingenic_adc_set_config(adc,
262 JZ_ADC_REG_CFG_BAT_MD,
263 JZ_ADC_REG_CFG_BAT_MD);
264 adc->low_vref_mode = true;
265 }
266
267 clk_disable(adc->clk);
268
269 return 0;
270 default:
271 return -EINVAL;
272 }
273 default:
274 return -EINVAL;
275 }
276 }
277
278 static const int jz4725b_adc_battery_raw_avail[] = {
279 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
280 };
281
282 static const int jz4725b_adc_battery_scale_avail[] = {
283 JZ4725B_ADC_BATTERY_HIGH_VREF, JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
284 JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
285 };
286
287 static const int jz4740_adc_battery_raw_avail[] = {
288 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
289 };
290
291 static const int jz4740_adc_battery_scale_avail[] = {
292 JZ4740_ADC_BATTERY_HIGH_VREF, JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
293 JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
294 };
295
296 static const int jz4760_adc_battery_scale_avail[] = {
297 JZ4760_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS,
298 };
299
300 static const int jz4770_adc_battery_raw_avail[] = {
301 0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1,
302 };
303
304 static const int jz4770_adc_battery_scale_avail[] = {
305 JZ4770_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS,
306 };
307
jz4725b_adc_init_clk_div(struct device * dev,struct ingenic_adc * adc)308 static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
309 {
310 struct clk *parent_clk;
311 unsigned long parent_rate, rate;
312 unsigned int div_main, div_10us;
313
314 parent_clk = clk_get_parent(adc->clk);
315 if (!parent_clk) {
316 dev_err(dev, "ADC clock has no parent\n");
317 return -ENODEV;
318 }
319 parent_rate = clk_get_rate(parent_clk);
320
321 /*
322 * The JZ4725B ADC works at 500 kHz to 8 MHz.
323 * We pick the highest rate possible.
324 * In practice we typically get 6 MHz, half of the 12 MHz EXT clock.
325 */
326 div_main = DIV_ROUND_UP(parent_rate, 8000000);
327 div_main = clamp(div_main, 1u, 64u);
328 rate = parent_rate / div_main;
329 if (rate < 500000 || rate > 8000000) {
330 dev_err(dev, "No valid divider for ADC main clock\n");
331 return -EINVAL;
332 }
333
334 /* We also need a divider that produces a 10us clock. */
335 div_10us = DIV_ROUND_UP(rate, 100000);
336
337 writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) |
338 (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
339 adc->base + JZ_ADC_REG_ADCLK);
340
341 return 0;
342 }
343
jz4770_adc_init_clk_div(struct device * dev,struct ingenic_adc * adc)344 static int jz4770_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
345 {
346 struct clk *parent_clk;
347 unsigned long parent_rate, rate;
348 unsigned int div_main, div_ms, div_10us;
349
350 parent_clk = clk_get_parent(adc->clk);
351 if (!parent_clk) {
352 dev_err(dev, "ADC clock has no parent\n");
353 return -ENODEV;
354 }
355 parent_rate = clk_get_rate(parent_clk);
356
357 /*
358 * The JZ4770 ADC works at 20 kHz to 200 kHz.
359 * We pick the highest rate possible.
360 */
361 div_main = DIV_ROUND_UP(parent_rate, 200000);
362 div_main = clamp(div_main, 1u, 256u);
363 rate = parent_rate / div_main;
364 if (rate < 20000 || rate > 200000) {
365 dev_err(dev, "No valid divider for ADC main clock\n");
366 return -EINVAL;
367 }
368
369 /* We also need a divider that produces a 10us clock. */
370 div_10us = DIV_ROUND_UP(rate, 10000);
371 /* And another, which produces a 1ms clock. */
372 div_ms = DIV_ROUND_UP(rate, 1000);
373
374 writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) |
375 ((div_10us - 1) << JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB) |
376 (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
377 adc->base + JZ_ADC_REG_ADCLK);
378
379 return 0;
380 }
381
382 static const struct iio_chan_spec jz4740_channels[] = {
383 {
384 .extend_name = "aux",
385 .type = IIO_VOLTAGE,
386 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
387 BIT(IIO_CHAN_INFO_SCALE),
388 .indexed = 1,
389 .channel = INGENIC_ADC_AUX,
390 .scan_index = -1,
391 },
392 {
393 .extend_name = "battery",
394 .type = IIO_VOLTAGE,
395 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
396 BIT(IIO_CHAN_INFO_SCALE),
397 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
398 BIT(IIO_CHAN_INFO_SCALE),
399 .indexed = 1,
400 .channel = INGENIC_ADC_BATTERY,
401 .scan_index = -1,
402 },
403 };
404
405 static const struct iio_chan_spec jz4760_channels[] = {
406 {
407 .extend_name = "aux",
408 .type = IIO_VOLTAGE,
409 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
410 BIT(IIO_CHAN_INFO_SCALE),
411 .indexed = 1,
412 .channel = INGENIC_ADC_AUX0,
413 .scan_index = -1,
414 },
415 {
416 .extend_name = "aux1",
417 .type = IIO_VOLTAGE,
418 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
419 BIT(IIO_CHAN_INFO_SCALE),
420 .indexed = 1,
421 .channel = INGENIC_ADC_AUX,
422 .scan_index = -1,
423 },
424 {
425 .extend_name = "aux2",
426 .type = IIO_VOLTAGE,
427 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
428 BIT(IIO_CHAN_INFO_SCALE),
429 .indexed = 1,
430 .channel = INGENIC_ADC_AUX2,
431 .scan_index = -1,
432 },
433 {
434 .extend_name = "battery",
435 .type = IIO_VOLTAGE,
436 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
437 BIT(IIO_CHAN_INFO_SCALE),
438 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
439 BIT(IIO_CHAN_INFO_SCALE),
440 .indexed = 1,
441 .channel = INGENIC_ADC_BATTERY,
442 .scan_index = -1,
443 },
444 };
445
446 static const struct iio_chan_spec jz4770_channels[] = {
447 {
448 .type = IIO_VOLTAGE,
449 .indexed = 1,
450 .channel = INGENIC_ADC_TOUCH_XP,
451 .scan_index = 0,
452 .scan_type = {
453 .sign = 'u',
454 .realbits = 12,
455 .storagebits = 16,
456 },
457 },
458 {
459 .type = IIO_VOLTAGE,
460 .indexed = 1,
461 .channel = INGENIC_ADC_TOUCH_YP,
462 .scan_index = 1,
463 .scan_type = {
464 .sign = 'u',
465 .realbits = 12,
466 .storagebits = 16,
467 },
468 },
469 {
470 .type = IIO_VOLTAGE,
471 .indexed = 1,
472 .channel = INGENIC_ADC_TOUCH_XN,
473 .scan_index = 2,
474 .scan_type = {
475 .sign = 'u',
476 .realbits = 12,
477 .storagebits = 16,
478 },
479 },
480 {
481 .type = IIO_VOLTAGE,
482 .indexed = 1,
483 .channel = INGENIC_ADC_TOUCH_YN,
484 .scan_index = 3,
485 .scan_type = {
486 .sign = 'u',
487 .realbits = 12,
488 .storagebits = 16,
489 },
490 },
491 {
492 .type = IIO_VOLTAGE,
493 .indexed = 1,
494 .channel = INGENIC_ADC_TOUCH_XD,
495 .scan_index = 4,
496 .scan_type = {
497 .sign = 'u',
498 .realbits = 12,
499 .storagebits = 16,
500 },
501 },
502 {
503 .type = IIO_VOLTAGE,
504 .indexed = 1,
505 .channel = INGENIC_ADC_TOUCH_YD,
506 .scan_index = 5,
507 .scan_type = {
508 .sign = 'u',
509 .realbits = 12,
510 .storagebits = 16,
511 },
512 },
513 {
514 .extend_name = "aux",
515 .type = IIO_VOLTAGE,
516 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
517 BIT(IIO_CHAN_INFO_SCALE),
518 .indexed = 1,
519 .channel = INGENIC_ADC_AUX,
520 .scan_index = -1,
521 },
522 {
523 .extend_name = "battery",
524 .type = IIO_VOLTAGE,
525 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
526 BIT(IIO_CHAN_INFO_SCALE),
527 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
528 BIT(IIO_CHAN_INFO_SCALE),
529 .indexed = 1,
530 .channel = INGENIC_ADC_BATTERY,
531 .scan_index = -1,
532 },
533 {
534 .extend_name = "aux2",
535 .type = IIO_VOLTAGE,
536 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
537 BIT(IIO_CHAN_INFO_SCALE),
538 .indexed = 1,
539 .channel = INGENIC_ADC_AUX2,
540 .scan_index = -1,
541 },
542 };
543
544 static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
545 .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,
546 .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
547 .battery_raw_avail = jz4725b_adc_battery_raw_avail,
548 .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
549 .battery_scale_avail = jz4725b_adc_battery_scale_avail,
550 .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
551 .battery_vref_mode = true,
552 .has_aux_md = false,
553 .channels = jz4740_channels,
554 .num_channels = ARRAY_SIZE(jz4740_channels),
555 .init_clk_div = jz4725b_adc_init_clk_div,
556 };
557
558 static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
559 .battery_high_vref = JZ4740_ADC_BATTERY_HIGH_VREF,
560 .battery_high_vref_bits = JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
561 .battery_raw_avail = jz4740_adc_battery_raw_avail,
562 .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
563 .battery_scale_avail = jz4740_adc_battery_scale_avail,
564 .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
565 .battery_vref_mode = true,
566 .has_aux_md = false,
567 .channels = jz4740_channels,
568 .num_channels = ARRAY_SIZE(jz4740_channels),
569 .init_clk_div = NULL, /* no ADCLK register on JZ4740 */
570 };
571
572 static const struct ingenic_adc_soc_data jz4760_adc_soc_data = {
573 .battery_high_vref = JZ4760_ADC_BATTERY_VREF,
574 .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS,
575 .battery_raw_avail = jz4770_adc_battery_raw_avail,
576 .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail),
577 .battery_scale_avail = jz4760_adc_battery_scale_avail,
578 .battery_scale_avail_size = ARRAY_SIZE(jz4760_adc_battery_scale_avail),
579 .battery_vref_mode = false,
580 .has_aux_md = true,
581 .channels = jz4760_channels,
582 .num_channels = ARRAY_SIZE(jz4760_channels),
583 .init_clk_div = jz4770_adc_init_clk_div,
584 };
585
586 static const struct ingenic_adc_soc_data jz4770_adc_soc_data = {
587 .battery_high_vref = JZ4770_ADC_BATTERY_VREF,
588 .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS,
589 .battery_raw_avail = jz4770_adc_battery_raw_avail,
590 .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail),
591 .battery_scale_avail = jz4770_adc_battery_scale_avail,
592 .battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail),
593 .battery_vref_mode = false,
594 .has_aux_md = true,
595 .channels = jz4770_channels,
596 .num_channels = ARRAY_SIZE(jz4770_channels),
597 .init_clk_div = jz4770_adc_init_clk_div,
598 };
599
ingenic_adc_read_avail(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long m)600 static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
601 struct iio_chan_spec const *chan,
602 const int **vals,
603 int *type,
604 int *length,
605 long m)
606 {
607 struct ingenic_adc *adc = iio_priv(iio_dev);
608
609 switch (m) {
610 case IIO_CHAN_INFO_RAW:
611 *type = IIO_VAL_INT;
612 *length = adc->soc_data->battery_raw_avail_size;
613 *vals = adc->soc_data->battery_raw_avail;
614 return IIO_AVAIL_RANGE;
615 case IIO_CHAN_INFO_SCALE:
616 *type = IIO_VAL_FRACTIONAL_LOG2;
617 *length = adc->soc_data->battery_scale_avail_size;
618 *vals = adc->soc_data->battery_scale_avail;
619 return IIO_AVAIL_LIST;
620 default:
621 return -EINVAL;
622 }
623 }
624
__ingenic_adc_read_chan(struct ingenic_adc * adc,struct iio_chan_spec const * chan,int * val)625 static int __ingenic_adc_read_chan(struct ingenic_adc *adc,
626 struct iio_chan_spec const *chan,
627 int *val)
628 {
629 int cmd, ret, engine = (chan->channel == INGENIC_ADC_BATTERY);
630
631 if (adc->soc_data->has_aux_md && engine == 0) {
632 switch (chan->channel) {
633 case INGENIC_ADC_AUX0:
634 cmd = 0;
635 break;
636 case INGENIC_ADC_AUX:
637 cmd = 1;
638 break;
639 case INGENIC_ADC_AUX2:
640 cmd = 2;
641 break;
642 }
643
644 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, cmd);
645 }
646
647 ret = ingenic_adc_capture(adc, engine);
648 if (ret)
649 return ret;
650
651 switch (chan->channel) {
652 case INGENIC_ADC_AUX0:
653 case INGENIC_ADC_AUX:
654 case INGENIC_ADC_AUX2:
655 *val = readw(adc->base + JZ_ADC_REG_ADSDAT);
656 break;
657 case INGENIC_ADC_BATTERY:
658 *val = readw(adc->base + JZ_ADC_REG_ADBDAT);
659 break;
660 }
661
662 return IIO_VAL_INT;
663 }
664
ingenic_adc_read_chan_info_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,int * val)665 static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev,
666 struct iio_chan_spec const *chan,
667 int *val)
668 {
669 struct ingenic_adc *adc = iio_priv(iio_dev);
670 int ret;
671
672 ret = clk_enable(adc->clk);
673 if (ret) {
674 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n", ret);
675 return ret;
676 }
677
678 /* We cannot sample the aux channels in parallel. */
679 scoped_guard(mutex, &adc->aux_lock)
680 ret = __ingenic_adc_read_chan(adc, chan, val);
681
682 clk_disable(adc->clk);
683
684 return ret;
685 }
686
ingenic_adc_read_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)687 static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
688 struct iio_chan_spec const *chan,
689 int *val,
690 int *val2,
691 long m)
692 {
693 struct ingenic_adc *adc = iio_priv(iio_dev);
694
695 switch (m) {
696 case IIO_CHAN_INFO_RAW:
697 return ingenic_adc_read_chan_info_raw(iio_dev, chan, val);
698 case IIO_CHAN_INFO_SCALE:
699 switch (chan->channel) {
700 case INGENIC_ADC_AUX0:
701 case INGENIC_ADC_AUX:
702 case INGENIC_ADC_AUX2:
703 *val = JZ_ADC_AUX_VREF;
704 *val2 = JZ_ADC_AUX_VREF_BITS;
705 break;
706 case INGENIC_ADC_BATTERY:
707 if (adc->low_vref_mode) {
708 *val = JZ_ADC_BATTERY_LOW_VREF;
709 *val2 = JZ_ADC_BATTERY_LOW_VREF_BITS;
710 } else {
711 *val = adc->soc_data->battery_high_vref;
712 *val2 = adc->soc_data->battery_high_vref_bits;
713 }
714 break;
715 }
716
717 return IIO_VAL_FRACTIONAL_LOG2;
718 default:
719 return -EINVAL;
720 }
721 }
722
ingenic_adc_fwnode_xlate(struct iio_dev * iio_dev,const struct fwnode_reference_args * iiospec)723 static int ingenic_adc_fwnode_xlate(struct iio_dev *iio_dev,
724 const struct fwnode_reference_args *iiospec)
725 {
726 int i;
727
728 if (!iiospec->nargs)
729 return -EINVAL;
730
731 for (i = 0; i < iio_dev->num_channels; ++i)
732 if (iio_dev->channels[i].channel == iiospec->args[0])
733 return i;
734
735 return -EINVAL;
736 }
737
738 static const struct iio_info ingenic_adc_info = {
739 .write_raw = ingenic_adc_write_raw,
740 .read_raw = ingenic_adc_read_raw,
741 .read_avail = ingenic_adc_read_avail,
742 .fwnode_xlate = ingenic_adc_fwnode_xlate,
743 };
744
ingenic_adc_buffer_enable(struct iio_dev * iio_dev)745 static int ingenic_adc_buffer_enable(struct iio_dev *iio_dev)
746 {
747 struct ingenic_adc *adc = iio_priv(iio_dev);
748 int ret;
749
750 ret = clk_enable(adc->clk);
751 if (ret) {
752 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
753 ret);
754 return ret;
755 }
756
757 /* It takes significant time for the touchscreen hw to stabilize. */
758 msleep(50);
759 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK,
760 JZ_ADC_REG_CFG_SAMPLE_NUM(4) |
761 JZ_ADC_REG_CFG_PULL_UP(4));
762
763 writew(80, adc->base + JZ_ADC_REG_ADWAIT);
764 writew(2, adc->base + JZ_ADC_REG_ADSAME);
765 writeb((u8)~JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_CTRL);
766 writel(0, adc->base + JZ_ADC_REG_ADTCH);
767
768 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL,
769 JZ_ADC_REG_CFG_CMD_SEL);
770 ingenic_adc_set_adcmd(iio_dev, iio_dev->active_scan_mask[0]);
771
772 ingenic_adc_enable(adc, 2, true);
773
774 return 0;
775 }
776
ingenic_adc_buffer_disable(struct iio_dev * iio_dev)777 static int ingenic_adc_buffer_disable(struct iio_dev *iio_dev)
778 {
779 struct ingenic_adc *adc = iio_priv(iio_dev);
780
781 ingenic_adc_enable(adc, 2, false);
782
783 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL, 0);
784
785 writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
786 writeb(0xff, adc->base + JZ_ADC_REG_STATUS);
787 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK, 0);
788 writew(0, adc->base + JZ_ADC_REG_ADSAME);
789 writew(0, adc->base + JZ_ADC_REG_ADWAIT);
790 clk_disable(adc->clk);
791
792 return 0;
793 }
794
795 static const struct iio_buffer_setup_ops ingenic_buffer_setup_ops = {
796 .postenable = &ingenic_adc_buffer_enable,
797 .predisable = &ingenic_adc_buffer_disable
798 };
799
ingenic_adc_irq(int irq,void * data)800 static irqreturn_t ingenic_adc_irq(int irq, void *data)
801 {
802 struct iio_dev *iio_dev = data;
803 struct ingenic_adc *adc = iio_priv(iio_dev);
804 unsigned long mask = iio_dev->active_scan_mask[0];
805 unsigned int i;
806 u32 tdat[3];
807
808 for (i = 0; i < ARRAY_SIZE(tdat); mask >>= 2, i++) {
809 if (mask & 0x3)
810 tdat[i] = readl(adc->base + JZ_ADC_REG_ADTCH);
811 else
812 tdat[i] = 0;
813 }
814
815 iio_push_to_buffers(iio_dev, tdat);
816 writeb(JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_STATUS);
817
818 return IRQ_HANDLED;
819 }
820
ingenic_adc_probe(struct platform_device * pdev)821 static int ingenic_adc_probe(struct platform_device *pdev)
822 {
823 struct device *dev = &pdev->dev;
824 struct iio_dev *iio_dev;
825 struct ingenic_adc *adc;
826 const struct ingenic_adc_soc_data *soc_data;
827 int irq, ret;
828
829 soc_data = device_get_match_data(dev);
830 if (!soc_data)
831 return -EINVAL;
832
833 iio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
834 if (!iio_dev)
835 return -ENOMEM;
836
837 adc = iio_priv(iio_dev);
838 mutex_init(&adc->lock);
839 mutex_init(&adc->aux_lock);
840 adc->soc_data = soc_data;
841
842 irq = platform_get_irq(pdev, 0);
843 if (irq < 0)
844 return irq;
845
846 ret = devm_request_irq(dev, irq, ingenic_adc_irq, 0,
847 dev_name(dev), iio_dev);
848 if (ret < 0) {
849 dev_err(dev, "Failed to request irq: %d\n", ret);
850 return ret;
851 }
852
853 adc->base = devm_platform_ioremap_resource(pdev, 0);
854 if (IS_ERR(adc->base))
855 return PTR_ERR(adc->base);
856
857 adc->clk = devm_clk_get_prepared(dev, "adc");
858 if (IS_ERR(adc->clk)) {
859 dev_err(dev, "Unable to get clock\n");
860 return PTR_ERR(adc->clk);
861 }
862
863 ret = clk_enable(adc->clk);
864 if (ret) {
865 dev_err(dev, "Failed to enable clock\n");
866 return ret;
867 }
868
869 /* Set clock dividers. */
870 if (soc_data->init_clk_div) {
871 ret = soc_data->init_clk_div(dev, adc);
872 if (ret) {
873 clk_disable_unprepare(adc->clk);
874 return ret;
875 }
876 }
877
878 /* Put hardware in a known passive state. */
879 writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
880 writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
881
882 /* JZ4760B specific */
883 if (device_property_present(dev, "ingenic,use-internal-divider"))
884 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_VBAT_SEL,
885 JZ_ADC_REG_CFG_VBAT_SEL);
886 else
887 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_VBAT_SEL, 0);
888
889 usleep_range(2000, 3000); /* Must wait at least 2ms. */
890 clk_disable(adc->clk);
891
892 iio_dev->name = "jz-adc";
893 iio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
894 iio_dev->setup_ops = &ingenic_buffer_setup_ops;
895 iio_dev->channels = soc_data->channels;
896 iio_dev->num_channels = soc_data->num_channels;
897 iio_dev->info = &ingenic_adc_info;
898
899 ret = devm_iio_device_register(dev, iio_dev);
900 if (ret)
901 dev_err(dev, "Unable to register IIO device\n");
902
903 return ret;
904 }
905
906 static const struct of_device_id ingenic_adc_of_match[] = {
907 { .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
908 { .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
909 { .compatible = "ingenic,jz4760-adc", .data = &jz4760_adc_soc_data, },
910 { .compatible = "ingenic,jz4760b-adc", .data = &jz4760_adc_soc_data, },
911 { .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, },
912 { }
913 };
914 MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
915
916 static struct platform_driver ingenic_adc_driver = {
917 .driver = {
918 .name = "ingenic-adc",
919 .of_match_table = ingenic_adc_of_match,
920 },
921 .probe = ingenic_adc_probe,
922 };
923 module_platform_driver(ingenic_adc_driver);
924 MODULE_DESCRIPTION("ADC driver for the Ingenic JZ47xx SoCs");
925 MODULE_LICENSE("GPL v2");
926